CY29940 2.5 V or 3.3 V, 200 MHz, 1:18 Clock Distribution Buffer 2.5 V or 3.3 V, 200 MHz, 1:18 Clock Distribution Buffer Features Functional Description 200 MHz clock support The CY29940 is a low-voltage 200 MHz clock distribution buffer with the capability to select either a differential LVPECL or a LVCMOS/LVTTL compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible. The eighteen outputs are 2.5 V or 3.3 V LVCMOS/LVTTL compatible and can drive 50 series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:36. Low output-to-output skews make the CY29940 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. LVPECL or LVCMOS/LVTTL clock input LVCMOS/LVTTL compatible inputs 18 clock outputs: drive up to 36 clock lines 60 ps typical output-to-output skew Dual or single supply operation: 3.3 V core and 3.3 V outputs 3.3 V core and 2.5 V outputs 2.5 V core and 2.5 V outputs Pin compatible with MPC940L, MPC9109 Available in Commercial and Industrial temperature 32-pin TQFP package For a complete list of related documentation, click here. Block Diagram VDD PECL_CLK PECL_CLK# 0 TCLK 1 VDDC 18 Q0-Q17 TCLK_SEL Cypress Semiconductor Corporation Document Number: 38-07283 Rev. *J * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised November 22, 2017 CY29940 Q0 Q1 Q2 VDDC Q3 Q4 Q5 VSS 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 Q15 VSS Q14 Q13 Q12 VDDC CY29940 Q16 1 2 3 4 5 6 7 8 Q17 VSS VSS TCLK TCLK_SEL PECL_CLK PECL_CLK# VDD VDDC 32 Pin Configuration 24 23 22 21 20 19 18 17 Q6 Q7 Q8 VDD Q9 Q10 Q11 VSS Pin Description Pin Name PWR I/O [1] Description 5 PECL_CLK I, PU 6 PECL_CLK# I, PD PECL input clock 3 TCLK I, PD External reference/test clock input 9, 10, 11, 13, 14, 15, 18, 19, 20, 22, 23, 24, 26, 27, 28, 30, 31, 32 Q(17:0) 4 TCLK_SEL VDDC O I, PD PECL input clock Clock outputs Clock Select Input. When LOW, PECL clock is selected and when HIGH TCLK is selected. 8, 16, 29 VDDC 3.3 V or 2.5 V power supply for output clock buffers 7, 21 VDD 3.3 V or 2.5 V power supply 1, 2, 12, 17, 25 VSS Common ground Note 1. PD = Internal Pull-Down, PU = Internal Pull-up Document Number: 38-07283 Rev. *J Page 2 of 10 CY29940 Maximum Ratings Maximum power supply ................................................ 5.5 V Exceeding the maximum ratings[2] may impair the useful life of the device. User guidelines are not tested. Maximum input voltage relative to VSS .............. VSS - 0.3 V Maximum input voltage relative to VDD .............. VDD + 0.3 V Storage temperature ................................ -65 C to +150 C Operating temperature .............................. -40 C to +85 C Maximum ESD protection .............................................. 2 kV Maximum input current ............................................. 20 mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Parameters VDD = 3.3 V 5% or 2.5 V 5%, VDDC = 3.3 V 5% or 2.5 V 5%, TA = -40 C to +85 C Parameter [2] Description Conditions Min Typ Max Unit VIL Input low voltage VSS - 0.8 V VIH Input high voltage 2.0 - VDD V - - -200 A - - 200 A 500 - 1000 mV IIL Input low current[3] current[3] IIH Input high VPP Peak-to-peak input voltage PECL_CLK VCMR Common mode range[4] PECL_CLK VDD = 3.3 V VDD - 1.4 - VDD - 0.6 V VDD = 2.5 V VDD - 1.0 - VDD - 0.6 V VOL Output low voltage[5, 6, 7] IOL = 20 mA - - 0.5 V IOH = -20 mA, VDDC = 3.3 V 2.4 - - V IOH = -20 mA, VDDC = 2.5 V 1.8 - - V VOH Output high voltage[5, 6, 7] IDDQ Quiescent supply current IDD Dynamic supply current Zout Cin Output impedance - 5 7 mA VDD = 3.3 V, Outputs at 150 MHz, CL = 15 pF - 285 - mA VDD = 3.3 V, Outputs at 200 MHz, CL = 15 pF - 335 - VDD = 2.5 V, Outputs at 150 MHz, CL = 15 pF - 200 - VDD = 2.5 V, Outputs at 200 MHz, CL = 15 pF - 240 - VDD = 3.3 V 8 12 16 VDD = 2.5 V 10 15 20 - 4 - Input capacitance pF Thermal Resistance Parameter [8] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions 32-pin TQFP Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 67 C/W 28 C/W Notes 2. Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required. 3. Inputs have pull-up/pull-down resistors that effect input current. 4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the "High" input is within the VCMR range and the input lies within the VPP specification. Driving series or parallel terminated 50 (or 50 to VDD/2) transmission lines 5. Outputs driving 50 transmission lines. 6. See Figure 1 on page 5 and Figure 2 on page 5. 7. 50% input duty cycle. 8. These parameters are guaranteed by design and are not tested. Document Number: 38-07283 Rev. *J Page 3 of 10 CY29940 AC Parameters[9] VDD = 3.3 V 5% or 2.5 V 5%, VDDC = 3.3 V 5% or 2.5 V 5%, TA = -40 C to +85 C Parameter Fmax tPD Description Conditions Min Typ Max Unit - - 200 MHz tPHL 2.0 - 3.2 ns tPLH 2.1 - 3.4 tPHL 1.9 - 3.1 tPLH 2.0 - 3.2 tPHL 2.5 - 5.2 tPLH 2.6 - 5 tPHL 2.5 - 5 tPLH 2.6 - 5 tPHL 1.9 - 3 tPLH 2.0 - 3.2 tPHL 1.8 - 2.9 tPLH 1.8 - 3.1 tPHL 2.5 - 4 tPLH 2.5 - 4 tPHL 2.3 - 3.8 tPLH 2.3 - 3.8 VDD = 3.3 V @ 150 MHz - - 10 ps FCLK < 134 MHz - - 55 % FCLK > 134 MHz - - 60 VDD = 3.3 V - 60 150 VDD = 2.5 V - - 200 PECL, VDDC = 3.3 V - - 1.4 PECL, VDDC = 2.5 V - - 2.2 TCLK, VDDC = 3.3 V - - 1.2 TCLK, VDDC = 2.5 V - - 1.7 PECL_CLK - - 850 TCLK - - 750 0.7 V to 2.0 V, VDDC = 3.3 V 0.3 - 1.1 0.5 V to 1.8 V, VDDC = 2.5 V 0.3 - 1.2 Input frequency PECL_CLK to Q Delay - [10, 11, 12] 150 MHz VDD = 3.3 V, 85 C VDD = 3.3 V, 70 C VDD = 2.5 V, 85 C VDD = 2.5 V, 70 C tPD LVCMOS to Q Delay[10, 11, 12] 150 MHz VDD = 3.3 V, 85 C VDD = 3.3 V, 70 C VDD = 2.5 V, 85 C VDD = 2.5 V, 70 C tJ FoutDC Tskew Tskew(pp) Total jitter Output duty cycle[10, 11, 13] Output-to-output skew[10, 11] Part-to-part skew[14] Tskew(pp) Part-to-part skew[14] Tskew(pp) skew[15] tR/tF Part-to-part Output clocks rise/fall time[10, 11] ns ps ns ns ps ns Notes 9. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 10. Outputs driving 50 transmission lines. 11. See Figure 1 on page 5 and Figure 2 on page 5. 12. Parameters tested @ 150 MHz. 13. 50% input duty cycle. 14. Across temperature and voltage ranges, includes output skew. 15. For a specific temperature and voltage, includes output skew. Document Number: 38-07283 Rev. *J Page 4 of 10 CY29940 Figure 1. LVCMOS_CLK CY29940 Test Reference for VCC = 3.3 V and VCC = 2.5 V CY29940 DUT Zo = 50 ohm Pulse Generator Z = 50 ohm Zo = 50 ohm RT = 50 ohm RT = 50 ohm VTT VTT Figure 2. PECL_CLK CY29940 Test Reference for VCC = 3.3 V and VCC = 2.5 V CY29940 DUT Zo = 50 ohm Differential Pulse Generator Z = 50 ohm Zo = 50 ohm Zo = 50 ohm RT = 50 ohm VTT RT = 50 ohm VTT Figure 3. Propagation Delay (TPD) Test Reference PECL_CLK PECL_CLK VPP VCMR VCC Q VCC /2 tPD GND Figure 4. LVCMOS Propagation Delay (TPD) Test Reference VCC LVCMOS_CLK VCC /2 GND VCC Q VCC /2 tPD Document Number: 38-07283 Rev. *J GND Page 5 of 10 CY29940 Figure 5. Output Duty Cycle (FoutDC) VCC VCC /2 tP GND T0 DC = tP / T0 x 100% Figure 6. Output-to-Output Skew tsk(0) VCC VCC /2 GND VCC VCC /2 tSK(0) GND Ordering Information Part Number Package Type Production Flow Pb-free CY29940AXI 32-pin TQFP Industrial, -40 C to +85 C CY29940AXIT 32-pin TQFP - Tape and Reel Industrial, -40 C to +85 C CY29940AXC 32-pin TQFP Commercial, 0 C to 70 C CY29940AXCT 32-pin TQFP - Tape and Reel Commercial, 0C to 70 C Ordering Code Definitions CY 29940 A X X T T = Tape and Reel; blank = Tube Temperature Range: X = C or I C = Commercial; I = Industrial Pb-free Package: A = 32-pin TQFP Base part number Company ID: CY = Cypress Document Number: 38-07283 Rev. *J Page 6 of 10 CY29940 Package Drawing and Dimensions Figure 7. 32-pin TQFP 7 x 7 x 1.4 mm A32.14 51-85088 *E Document Number: 38-07283 Rev. *J Page 7 of 10 CY29940 Acronyms Acronym Document Conventions Description ESD electrostatic discharge I/O input/output Units of Measure Symbol C Unit of Measure degree Celsius TQFP thin quad flat package LVCMOS low voltage complementary metal oxide semiconductor LVPECL low-voltage positive emitter-coupled logic A micro Amperes LVTTL low-voltage transistor-transistor logic mA milli Amperes TQFP thin quad flat pack mm milli meter mV milli Volts ns nano seconds ohms Document Number: 38-07283 Rev. *J kV kilo Volts MHz Mega Hertz % percent pF pico Farad ps pico seconds V Volts W Watts Page 8 of 10 CY29940 Document History Page Document Title: CY29940, 2.5 V or 3.3 V, 200 MHz, 1:18 Clock Distribution Buffer Document Number: 38-07283 Rev. ECN No. Issue Date Orig. of Change ** 111094 02/01/02 BRK New data sheet *A 116776 08/15/02 HWT Incorporate results of final characterization using corporate methods, added output impedance on page 3 and added output duty cycle on page 4. Updated Ordering Information: Add commercial temperature range part numbers. Description of Change *B 122875 12/21/02 RBI Add power up requirements to maximum rating information *C 448379 See ECN RGL Add typical value for output-to-output skew Updated Ordering Information: Added Lead-free devices. *D 2899304 03/25/10 *E 3254185 05/11/2011 BASH / KVM Updated Ordering Information: Removed inactive parts. Updated Package Drawing and Dimensions. CXQ Added Ordering Code Definitions. Added Acronyms and Units of Measure. Updated to new template. *F 3548252 03/12/2012 PURU Changed LQFP to TQFP throughout document. *G 4586288 12/03/2014 PURU Updated Functional Description: Added "For a complete list of related documentation, click here." at the end. Updated Package Drawing and Dimensions: Updated Figure 7 (spec 51-85088 - Changed revision from *D to *E). *H 4787038 06/04/2015 TAVA Updated to new template. Completing Sunset Review. *I 5258862 05/04/2016 PSR Added Thermal Resistance. Updated to new template. Completing Sunset Review. *J 5973872 11/22/2017 Document Number: 38-07283 Rev. *J AESATMP8 Updated logo and Copyright. Page 9 of 10 CY29940 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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