Two-stage, dual-output, opto-coupled
gate driver evaluation board
Features:
- Suitable for driving Microsemi APTJC120AM13VCT1AG
- Isolated high-side and low-side outputs
- On-board derivation of isolated +/- 15 V supply voltages
- Two-stage driver - switching & conduction
- Peak gate current of +20/-10 A
- Switching frequency up to 100 kHz
- Duty cycle: 0 to 100%
Applications:
- Hard Switched Bridge Topologies
- Inverters/Converters
- Product Evaluation
- Research
- For operation principles and intended
use, refer to Application note AN-SS5.
MAXIMUM RATINGS
Insert Phot Here
Schematic Overview
Input current logic HIGH I
F(ON)
(high and low side inputs) 10
VPositive supply voltage V
CC
Not connected to the JFET,
output shorted to GND or pure
capacitive load
mA
Peak Output Current I
O
Symbol Conditions Value
+ 12
+ 100
to GND
Preliminary SGDR2500P2
Product Summary
Duty Cycle %0-100
The SGDR2500P2 is an opto-isolated, two-stage gate driver
optimized for high-speed hard switching of Microsemi's
APTJC120AM13VCT1AG SiC JFET half-bridge power module.
The SGDR2500P2 gate driver provides isolated high-side & low-
side drivers with peak output currents of +20/-10 A for fast turn-on
transients, yielding record-low switching energy losses.
V
DD
I
PK
+20/-10
Unit
T
ST
A
SGDR2500P2
100
+12
kHz
Operating temperature T
OP
+ 85 °C
Demo Board
- 27
+ 27
F
SW(MAX)
V
A
Parameter
Storage temperature °C
SGDR2500P2 Rev 1.3 1/4 September 2011
Preliminary SGDR2500P2
Demo Board
ELECTRICAL CHARACTERISTICS
Notes:
(1) I
PK
is limited by the JFET gate-source voltage (V
GS
) and gate resistor (R
G
). Pulse width is fixed at 100 ns. Connected to
APTJC120AM13VCT1AG.
o
C
+ 100
T
ST
Operating Conditions
Storage Temperature
Positive supply voltage V
CC
1.4
I
ODC
limited by R
GCOND
R
GOFF
= 0.17 Ω
C
in
-
-
o
C
+ 11.5
-
mA
0.8
-
Timing Characteristics
V
CC
= +12 V, f = 100 kHz, D = 50%
Input capacitance
I
F
= 5 mA, T
A
= 25
o
C
I
CC
500
-
Typ
Parameter Symbol
to GND
Value
Max
Conditions
Operating Temperature
-
-
+ 20
Max ∆V/∆t at ∆V = TBD
Output voltage rise time
Steady-state output current
Peak output current
(1)
pF
I
F(ON)
mA
45
V
t
d(OFF)
V
O
4.5
Peak positive voltage clamped by
JFET gate-source diode
Output voltage
-
- + 5V
ns
ns
Delay time input to output t
d(ON)
130
V
F(OFF)
V = 0V, f = 1 MHz, T
A
= 25
o
C
Positive supply current
-
1.701.60
- 10
-
130
-
I
O
Input forward voltage
Input voltage, OFF
Creep path input-output
+ 85
A
ns
7.6
-
-
t
ro
t
fo
20
0
0
- 15
Output
(characteristics same for both outputs)
Output voltage fall time -
-
1400
T
OP
-
- 10
R
GON
= 0.17 Ω
0 -
kV/µs
TBD
Electrical Isolation
ns20-
10 kV used at 1000 Vp-p
mm
without load
Min
mA
Unit
V
0.2
+12.5
Input current, ON
V
V
V
F
Input
(characteristics same for both inputs)
External Power Supplies
SGDR2500P2 Rev 1.3 2/4 September 2011
Preliminary SGDR2500P2
Demo Board
Package Pinout
J1
VCC
P1
S
L
J2
V
H
P2
G
L
J3
V
L
P3
G
H
Package Dimensions
in. mm
A2.70 68.58
B3.00 76.20
C2.85 72.39
D1.75 44.51
E0.15 3.81
F0.10 2.54
G2.36 59.94
H2.55 64.77
I0.98 24.82
J1 0.04 1.09
K0.15 3.81
J2 0.04 1.09
J3
Top View
L0.75 19.05
M1 0.12 2.95
V2.24
M2
3.81
56.78
1.70
P2 0.07 1.70
Q1.16 29.51
R1.54 39.07
S0.20 5.08
T0.10 2.54
U0.52 13.13
0.04 1.09
P3 0.07 1.70
P4 0.07
Pin Descriptions
Voltage supply
High side PWM (opto-coupler input)
Low side PWM (opto-coupler input)
Low side source connection
Low side gate connection
P4
S
H
High side gate connection
High side source connection
1.70
P1 0.07
0.12 2.95
N0.15
SGDR2500P2 Rev 1.3 3/4 September 2011
Preliminary SGDR2500P2
Demo Board
Published by
SemiSouth Laboratories, Inc.
201 Research Boulevard
Starkville, MS 39759 USA
© SemiSouth Laboratories, Inc. 2011
Unless expressly approved in writing by an authorized representative of SemiSouth, SemiSouth products are
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Information in this document supersedes and replaces all information previously supplied.
Information in this document is provided solely in connection with SemiSouth products. SemiSouth
Laboratories, Inc. reserves the right to make changes, corrections, modifications or improvements, to this
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No license, express or implied to any intellectual property rights is granted under this document.
SGDR2500P2 Rev 1.3 4/4 September 2011