SMJ320C6701-SP
www.ti.com
SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
RAD-TOLERANT CLASS-V FLOATING-POINT DIGITAL SIGNAL PROCESSOR
Check for Samples: SMJ320C6701-SP
1FEATURES – Bit Counting
– Normalization
23456• Rad-Tolerant: 100-kRad (Si) TID • 1M-Bit On-Chip SRAM
• SEL Immune at 89MeV-cm2/mg LET Ions – 512K-Bit Internal Program/Cache (16K 32-
• QML-V Qualified, SMD 5962-98661 Bit Instructions)
• Highest-Performance Floating-Point Digital – 512K-Bit Dual-Access Internal Data (64K
Signal Processor (DSP) SMJ320C6701 Bytes)
– 7-ns Instruction Cycle Time • 32-Bit External Memory Interface (EMIF)
– 140-MHz Clock Rate – Glueless Interface to Synchronous
– Eight 32-Bit Instructions/Cycle Memories: SDRAM and SBSRAM
– Up to One GFLOPS Performance – Glueless Interface to Asynchronous
– Pin Compatible With ’C6201 Fixed-Point Memories: SRAM and EPROM
DSP • Four-Channel Bootloading
• SMJ: QML Processing to MIL-PRF-38535 Direct Memory Access (DMA) Controller With
• SM: Standard Processing Auxiliary Channel
• Operating Temperature Ranges • 16-Bit Host-Port Interface (HPI)
– –55°C to 115°C – Access to Entire Memory Map
– –55°C to 125°C • Two Multichannel Buffered Serial Ports
• VelociTI™ Advanced Very Long Instruction (McBSPs)
Word (VLIW) ’C67x CPU Core – Direct Interface to T1/E1, MVIP, SCSA
– Eight Highly Independent Functional Units: Framers
– Four ALUs (Floating and Fixed Point) – ST Bus Switching Compatible
– Two ALUs (Fixed Point) – Up to 256 Channels Each
– Two Multipliers (Floating and Fixed – AC97 Compatible
Point) – Serial Peripheral Interface (SPI)
– Load-Store Architecture With 32 Compatible ( Motorola™)
32-Bit General-Purpose Registers • Two 32-Bit General-Purpose Timers
– Instruction Packing Reduces Code Size • Flexible Phase-Locked Loop (PLL) Clock
– All Instructions Conditional Generator
• Instruction Set Features • IEEE Std 1149.1 (JTAG (1) )
Boundary Scan Compatible
– Hardware Support for IEEE Single-
Precision Instructions • 429-Pin Ceramic Ball Grid Array (CBGA/GLP)
and Ceramic Land Grid Array (CLGA/ZMB)
– Hardware Support for IEEE Double- Package Types
Precision Instructions • 0.18-μm/5-Level Metal Process
– Byte Addressable (8-/16-/32-Bit Data) – CMOS Technology
– 32-Bit Address Range • 3.3-V I/Os, 1.9 V Internal
– 8-Bit Overflow Protection
– Saturation (1) IEEE Std 1149.1-1990 Test Access Port and Boundary Scan
– Bit-Field Extract, Set, Clear Architecture
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2VelociTI, XDS, XDS510, XDS510WS are trademarks of Texas Instruments.
3Windows, Win32, NT are trademarks of Microsoft Corporation.
4Motorola is a trademark of Motorola, Inc.
5SPARC is a trademark of SPARC International.
6Solaris is a trademark of Sun Microsystems, Inc..
PRODUCTION DATA information is current as of publication date. Copyright © 2000–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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SMJ320C6701-SP
SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
www.ti.com
• Engineering Evaluation (/EM) Samples are
Available (2)
(2) These units are intended for engineering evaluation only.
They are processed to a non-compliant flow (e.g. No Burn-In,
etc.) and are tested to a temperature rating of 25°C only.
These units are not suitable for qualification, production,
radiation testing or flight use. Parts are not warranted for
performance over the full MIL specified temperature range of
-55°C to 125°C or operating life.
DESCRIPTION
The SMJ320C67x DSPs are the floating-point DSP family in the SMJ320C6000 platform. The SMJ320C6701
(’C6701) device is based on the high-performance, advanced VelociTI™ very-long-instruction-word (VLIW)
architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and
multifunction applications. With performance of up to 1 giga floating-point operations per second (GFLOPS) at a
clock rate of 140 MHz, the ’C6701 offers cost-effective solutions to high-performance DSP programming
challenges. The ’C6701 DSP possesses the operational flexibility of high-speed controllers and the numerical
capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight
highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-
point ALUs, and two floating-/fixed-point multipliers. The ’C6701 can produce two multiply-accumulates (MACs)
per cycle for a total of 334 million MACs per second (MMACS). The ’C6701 DSP also has application-specific
hardware logic, on-chip memory, and additional on-chip peripherals.
The ’C6701 includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program
memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space.
Data memory consists of two 32K-byte blocks of RAM. The peripheral set includes two multichannel buffered
serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory
interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.
The ’C6701 has a complete set of development tools that includes a new C compiler, an assembly optimizer to
simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code
execution.
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Program
Control
Logic
Test
’C67x CPU
Data Path B
B Register File
Program
Access/Cache
Controller
Instruction Fetch
Instruction Dispatch
Instruction Decode
Data Path A
A Register File
Data
Access
Controller
Power-
Down
Logic
.L1(1) .S1(1) .M1(1) .D1 .D2 .M2(1) .S2(1) .L2(1)
32
ROM/FLASH
SRAM
I/O Devices
16
Timer 0
Timer 1
External Memory
Interface (EMIF)
Multichannel
Buffered Serial
Port 0
Multichannel
Buffered Serial
Port 1
Direct Memory
Access Controller
(DMA)
(4 Channels)
Host Port
Interface
(HPI)
Internal Program Memory
1 Block Program/Cache
(64K Bytes)
Control
Registers
Internal Data
Memory
(64K Bytes)
2 Blocks of 8 Banks
Each
In-Circuit
Emulation
Interrupt
Control
Framing Chips:
H.100, MVIP,
SCSA, T1, E1
AC97 Devices,
SPI Devices,
Codecs
DMA Buses
Data Bus
’C6701 Digital Signal Processor
PLL
(x1, x4)
Bus
SBSRAM
SDRAM
HOST CONNECTION
MC68360 Glueless
MPC860 Glueless
PCI9050 Bridge + Inverter
MC68302 + PAL
MPC750 + PAL
MPC960 (Jx/Rx) + PAL
SMJ320C6701-SP
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SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
Device Characteristics
Table 1 provides an overview of the ’C6701 DSP. The table shows significant features of each device, including
the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count.
Table 1. Characteristics of 'C6701 Processors
CHARACTERISTICS DESCRIPTION
Device Number SMJ320C6701
512K-bit Program Memory
On–Chip Memory 512K-bit Data Memory (organized as 2 blocks)
2 Mutichannel Buffered Serial Ports (McBSP)
2 General-Purpose Timers
Peripherals Host-Port Interface (HPI)
External Memory Interface (EMIF)
Cycle Time 7 ns at 140 MHz
Package Type 27 mm × 27 mm, 429–Pin BGA (GLP) and 429-Pin LGA (ZMB)
1.9 V Core
Nominal Voltage 3.3 V I/O
Functional and CPU Block Diagram
(1) These functional units execute floating-point instructions.
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CPU Description
The CPU fetches VelociTI advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-
bit instructions to the eight functional units during every clock cycle. The VelociTI VLIW architecture features
controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The
first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the
previous instruction, or whether it should be executed in the following clock as a part of the next execute packet.
Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length
execute packets are a key memory-saving feature, distinguishing the ’C67x CPU from other VLIW architectures.
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files
contain 16 32-bit registers each for the total of 32 general-purpose registers. The two sets of functional units,
along with two register files, compose sides A and B of the CPU (see the functional and CPU block diagram and
Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that
side. Additionally, each side features a single data bus connected to all registers on the other side, by which the
two sets of functional units can access data from the register files on opposite sides. While register access by
functional units on the same side of the CPU as the register file can service all the units in a single clock cycle,
register access using the register file across the CPU supports one read and one write per cycle.
The ’C67x CPU executes all ’C62x instructions. In addition to ’C62x fixed-point instructions, the six out of eight
functional units (.L1, .M1, .D1, .D2, .M2, and .L2) also execute floating-point instructions. The remaining two
functional units (.S1 and .S2) also execute the new LDDW instruction which loads 64 bits per CPU side for a
total of 128 bits per cycle.
Another key feature of the ’C67x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file. The
’C67x CPU supports a variety of indirect-addressing modes using either linear- or circular-addressing modes with
5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some
registers, however, are singled out to support specific addressing or to hold the condition for conditional
instructions (if the condition is not automatically "true"). The two .M functional units are dedicated for multiplies.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The
32-bit instructions destined for the individual functional units are "linked" together by "1" bits in the least
significant bit (LSB) position of the instructions. The instructions that are "chained" together for simultaneous
execution (up to eight in total) compose an execute packet. A "0" in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the
fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of
the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet
can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one
per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a
maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers,
they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are
byte, half-word, or word addressable.
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8
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long src
dst
src2
src1
src1
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src1
src1
long dst
long dst
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src2
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2X
1X
.L2(1)
.S2(1)
.M2(1)
.D2
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.M1(1)
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Control
Register File
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DA1
DA2
ST1
LD1 32 LSB
LD2 32 LSB
LD2 32 MSB
32
32
Data Path A
Data Path B
Register
File A
(A0−A15)
Register
File B
(B0−B15)
LD1 32 MSB
32
ST2 32
8
8
8
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SMJ320C6701-SP
www.ti.com
SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
(1) These functional units execute floating-point instructions.
Figure 1. SMJ320C67x CPU Data Paths
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HHWIL
HBE0
HBE1
HCNTL0
HCNTL1
TRST
EXT_INT7
CLOCK/PLL
IEEE Standard
1149.1
(JTAG)
Emulation
Reserved
Data
Register Select
Half-Word/Byte
Select
Boot Mode
Reset and
Interrupts
Little ENDIAN
Big ENDIAN
DMA Status
Power-Down
Status
Control
HPI
(Host-Port Interface)
16
Control/Status
TDI
TDO
TMS
TCK
CLKIN
CLKOUT2
CLKOUT1
CLKMODE1
CLKMODE0
PLLFREQ3
PLLFREQ2
PLLFREQ1
PLLV
PLLG
PLLF
EMU1
EMU0
RSV3
RSV2
RSV1
RSV0
HD[15:0]
BOOTMODE4
BOOTMODE3
BOOTMODE2
BOOTMODE1
BOOTMODE0
NMI
IACK
INUM3
INUM2
INUM1
INUM0
LENDIAN
DMAC3
DMAC2
DMAC1
DMAC0
PD
HAS
HR/W
HCS
HDS1
HDS2
HRDY
HINT
RSV7
RSV6
RSV5
RSV4
RSV8
EXT_INT6
EXT_INT5
EXT_INT4
RESET
RSV9
SMJ320C6701-SP
SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
www.ti.com
Signal Groups Description
Figure 2. CPU and Peripheral Signals
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CE3
ARE
ED[31:0]
CE2
CE1
CE0
EA[21:2]
BE3
BE2
BE1
BE0
HOLD
HOLDA
TOUT1
CLKX1
FSX1
DX1
CLKR1
FSR1
DR1
CLKS1
AOE
AWE
ARDY
SSADS
SSOE
SSWE
SSCLK
SDA10
SDRAS
SDCAS
SDWE
SDCLK
TOUT0
CLKX0
FSX0
DX0
CLKR0
FSR0
DR0
CLKS0
Data
Memory Map
Space Select
Word Address
Byte Enables
HOLD/
HOLDA
32
20
Asynchronous
Memory
Control
SBSRAM
Control
SDRAM
Control
EMIF
(External Memory Interface)
Timer 1
Receive Receive
Timer 0
Timers
McBSP1 McBSP0
Transmit Transmit
Clock Clock
McBSPs
(Multichannel Buffered Serial Ports)
TINP1 TINP0
SMJ320C6701-SP
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SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
Figure 3. Peripheral Signals
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Signal Descriptions
SIGNAL TYPE(1) DESCRIPTION
NAME NO.
CLOCK/PLL
CLKIN A14 I Clock Input
CLKOUT1 Y6 O Clock output at full device speed
CLKOUT2 V9 O Clock output at half of device speed
CLKMODE1 B17 Clock mode select
I
CLKMODE0 C17 • Selects whether the output clock frequency = input clock freq ×4
or ×1
PLLFREQ3 C13 PLL frequency range (3, 2, and 1)
PLLFREQ2 G11 I • The target range for CLKOUT1 frequency is determined by the
3–bit value of the PLLFREQ pins.
PLLFREQ1 F11
PLLV(2) D12 A(3) PLL analog VCC connection for the low-pass filter
PLLG(2) G10 A(3) PLL analog GND connection for the low-pass filter
PLLF C12 A(3) PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
TMS K19 I JTAG test port mode select (features an internal pull-up)
TDO R12 O/Z JTAG test port data out
TDI R13 I JTAG test port data in (features an internal pull-up)
TCK M20 I JTAG test port clock
TRST N18 I JTAG test port reset (features an internal pull-down)
EMU1 R20 I/O/Z Emulation pin 1, pullup with a dedicated 20-kΩresistor(4)
EMU0 T18 I/O/Z Emulation pin 0, pullup with a dedicated 20-kΩresistor(4)
RESET AND INTERRUPTS
RESET J20 I Device reset
Nonmaskable interrupt
NMI K21 I • Edge driven (rising edge)
EXT_INT7 R16 External interrupts
EXT_INT6 P20 I
EXT_INT5 R15 • Edge driven (rising edge)
EXT_INT4 R18
IACK R11 O Interrupt acknowledge for all active interrupts serviced by the CPU
INUM3 T19 Active interrupt identification number
INUM2 T20 • Valid during IACK for all active interrupts (not just external)
O
INUM1 T14 • Encoding order follows the interrupt service fetch packet
ordering.
INUM0 T16
LITTLE ENDIAN/BIG ENDIAN
If high, selects little-endian byte/half-word addressing order within a word.
LENDIAN G20 I If low, selects big-endian addressing.
POWER-DOWN STATUS
PD D19 O Power-down mode 2 or 3 (active if high)
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
(2) PLLV and PLLG signals are not part of external voltage supply or ground. See the CLOCK/PLL documentation for information on how to
connect those pins.
(3) A = Analog signal (PLL filter)
(4) For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩresistor. For boundary scan, pull down EMU1 and
EMU0 with a dedicated 20-kΩresistor.
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Signal Descriptions (continued)
SIGNAL TYPE(1) DESCRIPTION
NAME NO.
HOST-PORT INTERFACE (HPI)
HINT H2 O/Z Host interrupt (from DSP to host)
HCNTL1 J6 I Host control – selects between control, address or data registers
HCNTL0 H6 I Host control – selects between control, address or data registers
HHWIL E4 I Host halfword select – first or second halfword (not necessarily high or low order)
HBE1 G6 I Host byte select within word or half-word
HBE0 F6 I Host byte select within word or half-word
HR/W D4 I Host read or write select
HD15 D11
HD14 B11
HD13 A11
HD12 G9
HD11 D10
HD10 A10
HD9 C10
HD8 B9 I/O/Z Host-port data (used for transfer of data, address and control)
HD7 F9
HD6 C9
HD5 A9
HD4 B8
HD3 D9
HD2 D8
HD1 B7
HD0 C7
HAS L6 I Host address strobe
HCS C5 I Host chip select
HDS1 C4 I Host data strobe 1
HDS2 K6 I Host data strobe 2
HRDY H3 O Host ready (from DSP to host)
BOOT MODE
BOOTMODE4 B16
BOOTMODE3 G14
BOOTMODE2 F15 I Boot mode
BOOTMODE1 C18
BOOTMODE0 D17
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Signal Descriptions (continued)
SIGNAL TYPE(1) DESCRIPTION
NAME NO.
EMIF - CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
CE3 Y5 O/Z Memory space enables
CE2 V3 O/Z • Enabled by bits 24 and 25 of the word address
CE1 T6 O/Z • Only one asserted during any external data access
CE0 U2 O/Z
BE3 R8 O/Z Byte enable control
BE2 T3 O/Z • Decoded from the two lowest bits of the internal address
BE1 T2 O/Z • Byte write enables for most types of memory
• Can be directly connected to SDRAM read and write mask signal
BE0 R2 O/Z (SDQM)
EMIF - ADDRESS
EA21 L4
EA20 L3
EA19 J2
EA18 J1
EA17 K1
EA16 K2
EA15 L2
EA14 L1
EA13 M1
EA12 M2 O/Z External address (word address)
EA11 M6
EA10 N4
EA9 N1
EA8 N2
EA7 N6
EA6 P4
EA5 P3
EA4 P2
EA3 P1
EA2 P6
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Signal Descriptions (continued)
SIGNAL TYPE(1) DESCRIPTION
NAME NO.
EMIF - DATA
ED31 U18
ED30 U20
ED29 T15
ED28 V18
ED27 V17
ED26 V16
ED25 T12
ED24 W17
ED23 T13
ED22 Y17
ED21 T11
ED20 Y16
ED19 W15
ED18 V14
ED17 Y15
ED16 R9 I/O/Z External data
ED15 Y14
ED14 V13
ED13 AA13
ED12 T10
ED11 Y13
ED10 W12
ED9 Y12
ED8 Y11
ED7 V10
ED6 AA10
ED5 Y10
ED4 W10
ED3 Y9
ED2 AA9
ED1 Y8
ED0 W9
EMIF - ASYNCHRONOUS MEMORY CONTROL
ARE R7 O/Z Asynchronous memory read enable
AOE T7 O/Z Asynchronous memory output enable
AWE V5 O/Z Asynchronous memory write enable
ARDY R4 I Asynchronous memory ready input
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Signal Descriptions (continued)
SIGNAL TYPE(1) DESCRIPTION
NAME NO.
EMIF - SYNCHRONOUS BURST SRAM CONTROL
SSADS V8 O/Z SBSRAM address strobe
SSOE W7 O/Z SBSRAM output enable
SSWE Y7 O/Z SBSRAM write enable
SSCLK AA8 O/Z SBSRAM clock
EMIF - SYNCHRONOUS DRAM CONTROL
SDA10 V7 O/Z SDRAM address 10 (separate for deactivate command)
SDRAS V6 O/Z SDRAM row address strobe
SDCAS W5 O/Z SDRAM column address strobe
SDWE T8 O/Z SDRAM write enable
SDCLK T9 O/Z SDRAM clock
EMIF - BUS ARBITRATION
HOLD R6 I Hold request from the host
HOLDA B15 O Hold request acknowledge to the host
TIMERS
TOUT1 G2 O/Z Timer 1 or general-purpose output
TINP1 K3 I Timer 1 or general-purpose input
TOUT0 M18 O/Z Timer 0 or general-purpose output
TINP0 J18 I Timer 0 or general-purpose input
DMA ACTION COMPLETE
DMAC3 E18
DMAC2 F19 O DMA action complete
DMAC1 E20
DMAC0 G16
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKS1 F4 I External clock source (as opposed to internal)
CLKR1 H4 I/O/Z Receive clock
CLKX1 J4 I/O/Z Transmit clock
DR1 E2 I Receive data
DX1 G4 O/Z Transmit data
FSR1 F3 I/O/Z Receive frame sync
FSX1 F2 I/O/Z Transmit frame sync
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Signal Descriptions (continued)
SIGNAL TYPE(1) DESCRIPTION
NAME NO.
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKS0 K18 I Extended clock source (as opposed to internal)
CLKR0 L21 I/O/Z Receive clock
CLKX0 K20 I/O/Z Transmit clock
DR0 J21 I Receive data
DX0 M21 O/Z Transmit data
FSR0 P16 I/O/Z Receive frame sync
FSX0 N16 I/O/Z Transmit frame sync
RESERVED FOR TEST
RSV0 N21 I Reserved for testing, pullup with a dedicated 20-kΩresistor
RSV1 K16 I Reserved for testing, pullup with a dedicated 20-kΩresistor
RSV2 B13 I Reserved for testing, pullup with a dedicated 20-kΩresistor
RSV3 B14 I Reserved for testing, pullup with a dedicated 20-kΩresistor
RSV4 F13 I Reserved for testing, pulldown with a dedicated 20-kΩresistor
RSV5 C15 O Reserved (leave unconnected, do not connect to power or ground)
RSV6 F7 I Reserved for testing, pullup with a dedicated 20-kΩresistor
RSV7 D7 I Reserved for testing, pullup with a dedicated 20-kΩresistor
RSV8 B5 I Reserved for testing, pullup with a dedicated 20-kΩresistor
RSV9 F16 O Reserved (leave unconnected, do not connect to power or ground)
C14
C8
E19
E3
H11
H13
H9
J10
J12
J14
DVDD J19 S 3.3-V supply voltage
J3
J8
K11
K13
K15
K7
K9
L10
L12
L14
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Signal Descriptions (continued)
SIGNAL TYPE(1) DESCRIPTION
NAME NO.
SUPPLY VOLTAGE PINS (CONTINUED)
L8
M11
M13
M15
M7
M9
N10
N12
N14
DVDD N19 S 3.3-V supply voltage
N3
N8
P11
P13
P9
U19
U3
W14
W8
A12
A13
B10
B12
B6
D15
D16
F10
F14
F8
CVDD S 1.9-V supply voltage
G13
G7
G8
K4
M3
M4
A3
A5
A7
A16
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Signal Descriptions (continued)
SIGNAL TYPE(1) DESCRIPTION
NAME NO.
SUPPLY VOLTAGE PINS (CONTINUED)
A18
AA4
AA6
AA15
AA17
AA19
B2
B4
B19
C1
C3
C20
D2
D21
E1
E6
E8
CVDD S 1.9-V supply voltage
E10
E12
E14
E16
F5
F17
F21
G1
H5
H17
K5
K17
M5
M17
P5
P17
R21
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Signal Descriptions (continued)
SIGNAL TYPE(1) DESCRIPTION
NAME NO.
SUPPLY VOLTAGE PINS (CONTINUED)
T1
T5
T17
U6
U8
U10
U12
U14
U16
U21
V1
V20
W2
W19
W21
Y3
Y18
Y20
CVDD AA11 S 1.9-V supply voltage
AA12
F20
G18
H16
H18
L18
L19
L20
N20
P18
P19
R10
R14
U4
V11
V12
V15
W13
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Signal Descriptions (continued)
SIGNAL TYPE(1) DESCRIPTION
NAME NO.
GROUND PINS
C11
C16
C6
D5
G3
H10
H12
H14
H7
H8
J11
J13
J7
J9
K8
L7
L9
M8
N7
VSS R3 GND Ground
A4
A6
A8
A15
A17
A19
AA3
AA5
AA7
AA14
AA16
AA18
B3
B18
B20
C2
C19
C21
D1
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Signal Descriptions (continued)
SIGNAL TYPE(1) DESCRIPTION
NAME NO.
GROUND PINS (CONTINUED)
D20
E5
E7
E9
E11
E13
E15
E17
E21
F1
G5
G17
G21
H1
J5
J17
L5
VSS L17 GND Ground pins
N5
N17
P21
R1
R5
R17
T21
U1
U5
U7
U9
U11
U13
U15
U17
V2
V21
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Signal Descriptions (continued)
SIGNAL TYPE(1) DESCRIPTION
NAME NO.
GROUND PINS (CONTINUED)
W1
W3
W20
Y2
Y4
Y19
F18
G19
H15
J15
J16
K10
K12
K14
L11
L13
L15
VSS M10 GND Ground pins
M12
M14
N11
N13
N15
N9
P10
P12
P14
P15
P7
P8
R19
T4
W11
W16
W6
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Signal Descriptions (continued)
SIGNAL TYPE(1) DESCRIPTION
NAME NO.
REMAINING UNCONNECTED PINS
D13
D14
D18
D3
D6
F12
G12
G15
H19
NC Unconnected pins
H20
H21
L16
M16
M19
V19
V4
W18
W4
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SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
Development Support
Texas Instruments (TI) offers an extensive line of development tools for the ’C6x generation of DSPs, including
tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules.
The following products support development of ’C6x-based applications:
•Software-development tools
– Assembly optimizer
– Assembler/Linker
– Simulator
– Optimizing ANSI C compiler
– Application algorithms
– C/Assembly debugger and code profiler
•Hardware-development tools
– Extended development system ( XDS™) emulator (supports ’C6x multiprocessor system debug)
– EVM (Evaluation Module)
The TMS320 DSP Development Support Reference Guide (SPRU011) contains information about development-
support products for all TMS320 family member devices, including documentation. See this document for further
information on TMS320 documentation or any TMS320 support products from Texas Instruments. An additional
document, the TMS320 Third-Party Support Reference Guide (SPRU052), contains information about TMS320-
related products from other companies in the industry. To receive TMS320 literature, contact the Literature
Response Center at 800/477-8924.
See Table 2 for a complete listing of development-support tools for the ’C6x. For information on pricing and
availability, contact the nearest TI field sales office or authorized distributor.
Table 2. SMJ320C6x Development-Support Tools
DEVELOPMENT TOOL PLATFORM PART NUMBER
Software
AD0345AS8500RF – Single user
Ada 95 Compiler(1) Sun Solaris 2.3™(2) AD0345BS8500RF – Multi user
C Compiler/Assembler/Linker/Assembly Win32™ TMDX3246855-07
Optimizer
C Compiler/Assembler/Linker/Assembly SPARC™ Solaris™ TMDX3246555-07
Optimizer
Simulator Win32 TMDS3246851-07
Simulator SPARC Solaris TMDS3246551-07
XDS510™ Debugger/Emulation Software Win32, Windows NT™ TMDX324016X-07
Hardware
XDS510 Emulator(3) PC TMDS00510
XDS510WS™ Emulator(4) SCSI TMDS00510WS
Software/Hardware
EVM Evaluation Kit PC/Win95/Windows NT TMDX3260A6201
EVM Evaluation Kit (including TMDX3246855- PC/Win95/Windows NT TMDX326006201
07)
(1) Contact IRVINE Compiler Corporation (949) 250-1366 to order
(2) NT support estimated availability 1Q00
(3) Includes XDS510 board and JTAG emulation cable. TMDX324016X-07 C-source Debugger/Emulation software is not included.
(4) Includes XDS510WS box, SCSI cable, power supply, and JTAG emulation cable.
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Device and Development-Support Tool Nomenclature
To designate the stages in the product-development cycle, TI assigns prefixes to the part numbers of all SMJ320
devices and support tools. Each SMJ320 member has one of three prefixes: SMX, SM, or SMJ. Texas
Instruments recommends two of three possible prefix designators for support tools: TMDX and TMDS. These
prefixes represent evolutionary stages of product development from engineering prototypes (SMX/TMDX)
through fully qualified production devices/tools (SMJ/TMDS).
Device development evolutionary flow:
SMX Experimental device that is not necessarily representative of the final device’s electrical
specifications
SM Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification
SMJ Fully qualified production device processed to MIL-PRF-38535
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS Fully qualified development-support product
SMX devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
SMJ devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (SMX or SM) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, GLP), the temperature range, and the device speed range in megahertz (for example, 14 is 140
MHz). Figure 4 provides a legend for reading the complete device name for any SMJ320 family member.
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-SP
PREFIX
DEVICE SPEED RANGE
SMJ 320 C 6701 GLP 14
SMX= Experimental device
SMJ = MIL-PRF-38535, QML
SM = Commercial
processing
DEVICE FAMILY
320 = SMJ320 family
TECHNOLOGY
14 = 140 MHz
PACKAGE TYPE (1)
GLP =429-pin ceramic BGA
C = CMOS
DEVICE
’6x DSP:
6201B
6203
6701
TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)
W
W = -55 °C to 115°C, extended temperature
RAD-TOLERANT CLASS V
ZMB = 429-pin ceramic LGA
SMJ320C6701-SP
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SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
(1) BGA = Ball grid array
Figure 4. SMJ320 Device Nomenclature (Including SMJ320C6701-SP)
Documentation Support
Extensive documentation supports all SMJ320 family generations of devices from product announcement through
applications development. The types of documentation available include: data sheets, such as this document,
with design specifications; complete user’s reference guides for all devices; technical briefs; development-support
tools; and hardware and software applications. The following is a brief, descriptive list of support documentation
specific to the ’C6x devices:
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the
’C6000 CPU architecture, instruction set, pipeline, and associated interrupts.
The TMS320C6000 Peripherals Reference Guide (literature number SPRU190) describes the functionality of the
peripherals available on ’C6x devices, such as the external memory interface (EMIF), host-port interface (HPI),
multichannel buffered serial ports (McBSPs), direct-memory-access (DMA), enhanced direct-memory-access
(EDMA) controller, expansion bus (XB), clocking and phase-locked loop (PLL); and power-down modes. This
guide also includes information on internal data and program memories.
The TMS320C6000 Programmer’s Guide (literature number SPRU198) describes ways to optimize C and
assembly code for ’C6x devices and includes application program examples.
The TMS320C6x C Source Debugger User’s Guide (literature number SPRU188) describes how to invoke the
’C6x simulator and emulator versions of the C source debugger interface and discusses various aspects of the
debugger, including: command entry, code execution, data management, breakpoints, profiling, and analysis.
The TMS320C6x Peripheral Support Library Programmer’s Reference (literature number SPRU273) describes
the contents of the ’C6x peripheral support library of functions and macros. It lists functions and macros both by
header file and alphabetically, provides a complete description of each, and gives code examples to show how
they are used.
TMS320C6000 Assembly Language Tools User’s Guide (literature number SPRU186) describes the assembly
language tools (assembler, linker, and other tools used to develop assembly language code), assembler
directives, macros, common object file format, and symbolic debugging directives for the ’C6000 generation of
devices.
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The TMS320C6x Evaluation Module Reference Guide (literature number SPRU269) provides instructions for
installing and operating the ’C6x evaluation module. It also includes support software documentation, application
programming interfaces, and technical reference material.
TMS320C6000 DSP/BIOS User’s Guide (literature number SPRU303) describes how to use DSP/BIOS tools and
APIs to analyze embedded real-time DSP applications.
Code Composer User’s Guide (literature number SPRU296) explains how to use the Code Composer
development environment to build and debug embedded real-time DSP applications.
Code Composer Studio Tutorial (literature number SPRU301) introduces the Code Composer Studio integrated
development environment and software tools.
The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the ’C62x/C67x
devices, associated development tools, and third-party support.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support DSP research and
education. The TMS320 newsletter, Details on Signal Processing, is published quarterly and distributed to update
SMJ320 customers on product information. The TMS320 DSP bulletin board service (BBS) provides access to
information pertaining to the SMJ320 family, including documentation, source code, and object code for many
DSP algorithms and utilities. The BBS can be reached at 281/274-2323.
Information regarding TI DSP products is also available on the Worldwide Web at http://www.ti.com uniform
resource locator (URL).
Clock PLL
All of the internal ’C67x clocks are generated from a single source through the CLKIN pin. This source clock
either drives the PLL, which multiplies the source clock in frequency to generate the internal CPU clock, or
bypasses the PLL to become the internal CPU clock.
To use the PLL to generate the CPU clock, the external PLL filter circuit must be properly designed. Table 3,
Table 4, and Figure 5 show the external PLL circuitry for either x1 (PLL bypass) or x4 PLL multiply modes.
Table 3 and Figure 6 show the external PLL circuitry for a system with ONLY x1 (PLL bypass) mode.
To minimize the clock jitter, a single clean power supply should power both the ’C67x device and the external
clock oscillator circuit. Noise coupling into PLLF will directly impact PLL clock jitter. The minimum CLKIN rise and
fall times should also be observed. For the input clock timing requirements, see the input and output clocks
electricals section. Guidelines for EMI filter selection are as follows: maximum attenuation frequency = 20–30
MHz, maximum dB attenuation = 45–50 dB, and minimum dB attenuation above 30 MHz = 20 dB.
Table 3. CLKOUT1 Frequency Ranges(1)
PLLFREQ3 PLLFREQ2 PLLFREQ1 CLKOUT1 FREQUENCY RANGE
(C13) (G11) (F11) (MHz)
0 0 0 50-140
(1) Due to overlap of frequency ranges when choosing the PLLFREQ, more than one frequency range can contain the CLKOUT1
frequency. Choose the lowest frequency range that includes the desired frequency. For example, for CLKOUT1 = 133 MHz, choose
PLLFREQ value of 000b. PLLFREQ values other than 000b, 001b, and 010b are reserved.
Table 4. 'C6701 PLL Component Selection Table
CPU CLOCK
CLKIN TYPICAL
FREQUENCY CLKOUT2 RANGE R1 C1 C2
CLKMODE RANGE LOCK TIME
(CLKOUT1) (MHz) (W) (nF) (pF)
(MHz) (μs)(1)
RANGE (MHz)
x4 12.5 – 41.7 50-140 25 – 83.5 60.4 27 560 75
(1) Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For
example, if the typical lock time is specified as 100 μs, the maximum value may be as long as 250 μs.
AVAILABLE MULTIPLY FACTORS
CPU CLOCK FREQUENCY
CLKMODE1 CLKMODE0 PLL MULTIPLY FACTORS F(CPUCLOCK)
0 0 x1(BYPASS) 1 x f(CLKIN)
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CLKMODE0
CLKMODE1 PLL
PLLV
CLKIN LOOP FILTER
PLLCLK
PLLMULT
CLKIN
PLLG
Internal to ’C6701
CPU
CLOCK
PLLF
1
0
3.3V See Table 3
PLLFREQ1
PLLFREQ2
PLLFREQ3
CLKMODE0
CLKMODE1 PLL
PLLV
CLKIN LOOP FILTER
PLLCLK
PLLMULT
CLKIN
PLLG
C2
Internal to ’C6701
CPU
CLOCK
C1 R1
3.3V
10 mF0.1 mF
PLLF
EMI Filter
C3 C4
1
0
See Table 3
PLLFREQ1
PLLFREQ2
PLLFREQ3
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AVAILABLE MULTIPLY FACTORS
CPU CLOCK FREQUENCY
CLKMODE1 CLKMODE0 PLL MULTIPLY FACTORS F(CPUCLOCK)
0 1 Reserved Reserved
1 0 Reserved Reserved
1 1 x4 4 x f(CLKIN)
(1) Keep the lead length and the number of vias between the PLLF pin, the PLLG pin, and R1, C1, and C2 to a minimum.
In addition, place all PLL external components (R1, C1, C2, C3, C4, and the EMI filter) as close to the ’C6000 device
as possible. For the best performance, TI recommends that all the PLL external components be on a single side of
the board without jumpers, switches, or components other than the ones shown.
(2) For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (R1, C1,
C2, C3, C4, and the EMI filter).
(3) The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
Figure 5. External PLL Circuitry for Either PLL ×4 Mode or ×1 (Bypass) Mode
(1) For a system with ONLY PLL x1 (bypass) mode, short the PLLF terminal to the PLLG terminal.
(2) The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
Figure 6. External PLL Circuitry for ×1 (Bypass) Mode Only
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Power-Supply Sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time if the other
supply is below the proper operating voltage.
System-Level Design Considerations
System-level design considerations, such as bus contention, may require supply sequencing to be implemented.
In this case, the core supply should be powered up at the same time as, or prior to (and powered down after),
the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the output buffers
are powered up, thus, preventing bus contention with other chips on the board.
Power-Supply Design Considerations
For systems using the C6000™ DSP platform of devices, the core supply may be required to provide in excess
of 2 A per DSP until the I/O supply is powered up. This extra current condition is a result of uninitialized logic
within the DSP(s) and is corrected once the CPU sees an internal clock pulse. With the PLL enabled, as the I/O
supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. With the PLL
disabled, an external clock pulse may be required to stop this extra current draw. A normal current state returns
once the I/O power supply is turned on and the CPU sees a clock pulse. Decreasing the amount of time between
the core supply power up and the I/O supply power up can minimize the effects of this current draw.
A dual-power supply with simultaneous sequencing, such as available with TPS563xx controllers or PT69xx plug-
in power modules, can be used to eliminate the delay between core and I/O power up [see the Using the
TPS56300 to Power DSPs application report (literature number SLVA088)]. A Schottky diode can also be used to
tie the core rail to the I/O rail, effectively pulling up the I/O power supply to a level that can help initialize the logic
within the DSP.
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000™ platform of DSPs, the PC board should include separate power planes for
core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
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SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
CVDD Supply voltage range(2) –0.3 2.3 V
DVDD Supply voltage range(2) –0.3 4 V
Input voltage range –0.3 4 V
Output voltage range –0.3 4 V
S-suffix device –40 90
TCOperating case temperature range °C
W-suffix device –55 115
Tstg Storage temperature range –55 150 °C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS.
Recommended Operating Conditions
MIN NOM MAX UNIT
CVDD Supply voltage 1.81 1.9 1.99 V
DVDD Supply voltage 3.14 3.3 3.46 V
VSS Supply ground 0 0 0 V
VIH High-level input voltage 2 V
VIL Low-level input voltage 0.8 V
IOH High-level output current –12 mA
IOL Low-level output current 12 mA
S-suffix device –40 90
TCCase temperature °C
W-suffix device –55 115
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Electrical Characteristics
over recommended ranges of supply voltage and operating case temperature (unless otherwise noted) (unchanged after 100
kRad) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage DVDD = MIN, IOH = MAX 2.4 V
VOL Low-level output voltage DVDD = MIN, IOL = MAX 0.6 V
IIInput current(1) VI= VSS to DVDD ±10 μA
IOZ Off-state output current VO= DVDD or 0 V ±10 μA
Supply current, CPU + CPU memory
IDD2V CVDD = NOM, CPU clock = 150 MHz 470 mA
access(2)
IDD2V Supply current, peripherals(3) CVDD = NOM, CPU clock = 150 MHz 250 mA
IDD3V Supply current, I/O pins(4) DVDD = NOM, CPU clock = 150 MHz 85 mA
CiInput capacitance 15(5) pF
CoOutput capacitance 15(5) pF
(1) TMS and TDI are not included due to internal pullups.
TRST is not included due to internal pulldown.
(2) Measured with average CPU activity:
50% of time: 8 instructions per cycle, 32-bit DMEM access per cycle
50% of time: 2 instructions per cycle, 16-bit DMEM access per cycle
(3) Measured with average peripheral activity:
50% of time: Timers at max rate, McBSPs at E1 rate, and DMA burst transfer between DMEM and SDRAM
50% of time: Timers at max rate, McBSPs at E1 rate, and DMA servicing McBSPs
(4) Measured with average I/O activity (30-pF load, SDCLK on):
25% of time: Reads from external SDRAM
25% of time: Writes to external SDRAM
50% of time: No activity
(5) This parameter is not tested.
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Vref = 1.5 V
Tester Pin
Electronics
Vref
IOL
CT = 30 pF(1)
IOH
Output
Under
Test
50 Ω
SMJ320C6701-SP
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SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
PARAMETER MEASUREMENT INFORMATION
(1) Typical distributed load circuit capacitance.
Signal-Transition Levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
Figure 7. Input and Output Voltage Reference Levels for AC Timing Measurements
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CLKOUT1
1
3
4
4
2
CLKIN
1
2
3
4
4
SMJ320C6701-SP
SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
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INPUT AND OUTPUT CLOCKS
Timing Requirements for CLKIN(1)
(see Figure 8)CLKMODE = x4 CLKMODE = x1
NO. UNIT
MIN MAX MIN MAX
1 tc(CLKIN) Cycle time, CLKIN 28.4 7.1 ns
Pulse duration,
2 tw(CLKINH) 0.4C(2) (3) 0.45C(2) (3) ns
CLKIN high
Pulse duration,
3 tw(CLKINL) 0.4C(2) (3) 0.45C(2) (3) ns
CLKIN low
4 tt(CLKIN) Transition time, CLKIN 5(2) 0.6(2) ns
(1) The reference points for the rise and fall transitions ar measured at 20% and 80%, respectively, of VIH.
(2) This parameter is not tested.
(3) C = CLKIN cycle time in ns. For example, when CLKIN frequency is 10 MHz, use C = 100 ns.
Figure 8. CLKIN Timing
Switching Characteristics for CLKOUT1(1) (2)
(see Figure 9)CLKMODE = x4 CLKMODE = x1
NO. PARAMETER UNIT
MIN MAX MIN MAX
1 tc(CKO1) Cycle time, CLKOUT1 P – 0.7(3) P + 0.7(3) P – 0.7(3) P + 0.7(3) ns
2 tw(CKO1H) Pulse duration, CLKOUT1 high (P/2) – 0.5(3) (P/2) + 0.5(3) PH – 0.5(3) PH + 0.5(3) ns
3 tw(CKO1L) Pulse duration, CLKOUT1 low (P/2) – 0.5(3) (P/2) + 0.5(3) PL – 0.5(3) PL + 0.5(3) ns
4 tt(CKO1) Transition time, CLKOUT1 0.6(3) 0.6(3) ns
(1) P = 1/CPU clock frequency in nanoseconds (ns).
(2) PH is the high period of CLKIN in ns and PL is the low period of CLKIN in ns.
(3) This parameter is not tested.
Figure 9. CLKOUT1 Timing
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4
3
2
1
CLKOUT1
SSCLK
SSCLK (1/2rate)
CLKOUT2
SDCLK
CLKOUT2
1
2
3
4
4
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SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
Switching Characteristics for CLKOUT2(1)
(see Figure 10)
NO. PARAMETER MIN MAX UNIT
1 tc(CKO2) Cycle time, CLKOUT2 2P – 0.7(2) 2P + 0.7(2) ns
2 tw(CKO2H) Pulse duration, CLKOUT2 high P – 0.7(2) P + 0.7(2) ns
3 tw(CKO2L) Pulse duration, CLKOUT2 low P – 0.7(2) P + 0.7(2) ns
4 tt(CKO2) Transition time, CLKOUT2 0.6(2) ns
(1) P = 1/CPU clock frequency in ns.
(2) This parameter is not tested.
Figure 10. CLKOUT2 Timing
SDCLK, SSCLK Timing Parameter
SDCLK timing parameters are the same as CLKOUT2 parameters.
SSCLK timing parameters are the same as CLKOUT1 or CLKOUT2 parameters, depending on SSCLK
configuration.
Switching Characteristics for the Relation of SSCLK, SDCLK, and CLKOUT2 to CLKOUT1
(see Figure 11)
NO. PARAMETER MIN MAX UNIT
1 td(CKO1–SSCLK) Delay time, CLKOUT1 edge to SSCLK edge –0.8 3.4 ns
2 td(CKO1–SSCLK1/2) Delay time, CLKOUT1 edge to SSCLK edge (1/2 clock rate) –1 3 ns
3 td(CKO1–CKO2) Delay time, CLKOUT1 edge to CLKOUT2 edge –1.5 2.5 ns
4 td(CKO1–SDCLK) Delay time, CLKOUT1 edge to SDCLK edge –1.5 1.9 ns
Figure 11. Relation of CLKOUT2, SDCLK, and SSCLK to CLKOUT1
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1111
10 10
99
88
7
6
54
32
11
CLKOUT1
CEx
BE[3:0]
EA[21:2]
ED[31:0]
AOE
ARE
AWE
ARDY
Setup = 2 Strobe = 5 Not ready = 2 HOLD = 1
SMJ320C6701-SP
SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
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ASYNCHRONOUS MEMORY TIMING
Timing Requirements for Asynchronous Memory Cycles(1)
(see Figure 12 and Figure 13)
NO. MIN MAX UNIT
6 tsu(EDV–CKO1H) Setup time, read EDx valid before CLKOUT1 high 4.8 ns
7 th(CKO1H–EDV) Hold time, read EDx valid after CLKOUT1 high 1.5 ns
10 tsu(ARDY–CKO1H) Setup time, ARDY valid before CLKOUT1 high 3.5 ns
11 th(CKO1H–ARDY) Hold time, ARDY valid after CLKOUT1 high 1.5 ns
(1) To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. If ARDY does meet setup or
hold time, it may be recognized in the current cycle or the next cycle. Thus, ARDY can be an asynchronous input.
Switching Characteristics for Asynchronous Memory Cycles(1)
(see Figure 12 and Figure 13)
NO. PARAMETER MIN MAX UNIT
1 td(CKO1H–CEV) Delay time, CLKOUT1 high to CEx valid –1 4.5 ns
2 td(CKO1H–BEV) Delay time, CLKOUT1 high to BEx valid 4.5 ns
3 td(CKO1H–BEIV) Delay time, CLKOUT1 high to BEx invalid –1 ns
4 td(CKO1H–EAV) Delay time, CLKOUT1 high to EAx valid 4.5 ns
5 td(CKO1H–EAIV) Delay time, CLKOUT1 high to EAx invalid –1 ns
8 td(CKO1H–AOEV) Delay time, CLKOUT1 high to AOE valid –1 4.5 ns
9 td(CKO1H–AREV) Delay time, CLKOUT1 high to ARE valid –1 4.5 ns
12 td(CKO1H–EDV) Delay time, CLKOUT1 high to EDx valid 4.5 ns
13 td(CKO1H–EDIV) Delay time, CLKOUT1 high to EDx invalid –1 ns
14 td(CKO1H–AWEV) Delay time, CLKOUT1 high to AWE valid –1 4.5 ns
(1) The minimum delay is also the minimum output hold after CLKOUT1 high.
Figure 12. Asynchronous Memory Read Timing
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11
10
11
10
1414
13
12
54
32
11
CLKOUT1
CEx
BE[3:0]
EA[21:2]
ED[31:0]
AOE
ARE
AWE
ARDY
Setup = 2 Strobe = 5 Not ready = 2 HOLD = 1
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SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
Figure 13. Aysnchronous Memory Write Timing
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BE1 BE2 BE3 BE4
A1 A2 A3 A4
Q1 Q2 Q3 Q4
1211
109
8
7
65
43
21
SSCLK
CEx
BE[3:0]
EA[21:2]
ED[31:0]
SSADS
SSOE
SSWE
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SYNCHRONOUS-BURST MEMORY TIMING
Timing Requirements for Synchronous-Burst SRAM Cycles (Full-Rate SSCLK)
(see Figure 14)
NO. MIN MAX UNIT
7 tsu(EDV–SSCLKH) Setup time, read EDx valid before SSCLK high 2.6 ns
8 th(SSCLKH–EDV) Hold time, read EDx valid after SSCLK high 1.5 ns
Switching Characteristics for Synchronous-burst SRAM Cycles(1) (Full-Rate SSCLK)
(see Figure 14 and Figure 15)
NO. PARAMETER MIN MAX UNIT
1 tosu(CEV–SSCLKH) Output setup time, CEx valid before SSCLK high 0.5P – 1.5 ns
2 toh(SSCLKH–CEV) Output hold time, CEx valid after SSCLK high 0.5P – 2.5 ns
3 tosu(BEV–SSCLKH) Output setup time, BEx valid before SSCLK high 0.5P – 1.6 ns
4 toh(SSCLKH–BEIV) Output hold time, BEx invalid after SSCLK high 0.5P – 2.5 ns
5 tosu(EAV–SSCLKH) Output setup time, EAx valid before SSCLK high 0.5P – 1.7 ns
6 toh(SSCLKH–EAIV) Output hold time, EAx invalid after SSCLK high 0.5P – 2.5 ns
9 tosu(ADSV–SSCLKH) Output setup time, SSADS valid before SSCLK high 0.5P – 1.5 ns
10 toh(SSCLKH–ADSV) Output hold time, SSADS valid after SSCLK high 0.5P – 2.5 ns
11 tosu(OEV–SSCLKH) Output setup time, SSOE valid before SSCLK high 0.5P – 1.5 ns
12 toh(SSCLKH–OEV) Output hold time, SSOE valid after SSCLK high 0.5P – 2.5 ns
13 tosu(EDV–SSCLKH) Output setup time, EDx valid before SSCLK high 0.5P – 1.5 ns
14 toh(SSCLKH–EDIV) Output hold time, EDx invalid after SSCLK high 0.5P – 2.5 ns
15 tosu(WEV–SSCLKH) Output setup time, SSWE valid before SSCLK high 0.5P – 1.5 ns
16 toh(SSCLKH–WEV) Output hold time, SSWE valid after SSCLK high 0.5P – 2.5 ns
(1) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. When the PLL is
used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns. For CLKMODE x1,
0.5P is defined as PH (pulse duration of CLKIN high) for all output setup times; 0.5P is defined as PL (pulse duration of CLKIN low) for
all output hold times.
Figure 14. SBSRAM Read Timing (Full-Rate SSCLK)
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BE1 BE2 BE3 BE4
A1 A2 A3 A4
D1 D2 D3 D4
1615
109
14
13
65
43
21
SSCLK
CEx
BE[3:0]
EA[21:2]
ED[31:0]
SSADS
SSOE
SSWE
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SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
Figure 15. SBSRAM Write Timing (Full-Rate SSCLK)
Timing Requirements for Synchronous-Burst SRAM Cycles (Half-Rate SSCLK)
(seeFigure 16)
NO. MIN MAX UNIT
7 tsu(EDV–SSCLKH) Setup time, read EDx valid before SSCLK high 3.8 ns
8 th(SSCLKH–EDV) Hold time, read EDx valid after SSCLK high 1.5 ns
Switching Characteristics for Synchronous-Burst SRAM Cycles(1) (Half-Rate SSCLK)
(see Figure 16 and Figure 17)
NO. PARAMETER MIN MAX UNIT
1 tosu(CEV–SSCLKH) Output setup time, CEx valid before SSCLK high 1.5P – 5.5 ns
2 toh(SSCLKH–CEV) Output hold time, CEx valid after SSCLK high 0.5P – 2.3 ns
3 tosu(BEV–SSCLKH) Output setup time, BEx valid before SSCLK high 1.5P – 5.5 ns
4 toh(SSCLKH–BEIV) Output hold time, BEx invalid after SSCLK high 0.5P – 2.3 ns
5 tosu(EAV–SSCLKH) Output setup time, EAx valid before SSCLK high 1.5P – 5.5 ns
6 toh(SSCLKH–EAIV) Output hold time, EAx invalid after SSCLK high 0.5P – 2.3 ns
9 tosu(ADSV–SSCLKH) Output setup time, SSADS valid before SSCLK high 1.5P – 5.5 ns
10 toh(SSCLKH–ADSV) Output hold time, SSADS valid after SSCLK high 0.5P – 2.3 ns
11 tosu(OEV–SSCLKH) Output setup time, SSOE valid before SSCLK high 1.5P – 5.5 ns
12 toh(SSCLKH–OEV) Output hold time, SSOE valid after SSCLK high 0.5P – 2.3 ns
13 tosu(EDV–SSCLKH) Output setup time, EDx valid before SSCLK high 1.5P – 5.5 ns
14 toh(SSCLKH–EDIV) Output hold time, EDx invalid after SSCLK high 0.5P – 2.3 ns
15 tosu(WEV–SSCLKH) Output setup time, SSWE valid before SSCLK high 1.5P – 5.5 ns
16 toh(SSCLKH–WEV) Output hold time, SSWE valid after SSCLK high 0.5P – 2.3 ns
(1) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. When the PLL is
used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
For CLKMODE x1:
1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.
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SSCLK
CEx
BE[3:0]
EA[21:2]
ED[31:0]
SSADS
SSOE
SSWE
BE1 BE2 BE3 BE4
A1 A2 A3 A4
Q1 Q2 Q3 Q4
1615
109
1413
65
43
21
SSCLK
CEx
BE[3:0]
EA[21:2]
ED[31:0]
SSADS
SSOE
SDWE
BE1 BE2 BE3 BE4
A1 A2 A3 A4
Q1 Q2 Q3 Q4
1211
109
65
43
21
8
7
SMJ320C6701-SP
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Figure 16. SBSRAM Read Timing (Half-Rate SSCLK)
Figure 17. SBSRAM Write Timing (Half-Rate SSCLK)
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SYNCHRONOUS DRAM TIMING
Timing Requirements for Synchronous DRAM Cycles
(see Figure 18)
NO. MIN MAX UNIT
7 tsu(EDV–SDCLKH) Setup time, read EDx valid before SDCLK high 2 ns
8 th(SDCLKH–EDV) Hold time, read EDx valid after SDCLK high 3 ns
Switching Characteristics for Synchronous DRAM Cycles(1)
(see Figure 18 –Figure 23)
NO. PARAMETER MIN MAX UNIT
1 tosu(CEV–SDCLKH) Output setup time, CEx valid before SDCLK high 1.5P – 5 ns
2 toh(SDCLKH–CEV) Output hold time, CEx valid after SDCLK high 0.5P – 1.9 ns
3 tosu(BEV–SDCLKH) Output setup time, BEx valid before SDCLK high 1.5P – 5 ns
4 toh(SDCLKH–BEIV) Output hold time, BEx invalid after SDCLK high 0.5P – 1.9 ns
5 tosu(EAV–SDCLKH) Output setup time, EAx valid before SDCLK high 1.5P – 5 ns
6 toh(SDCLKH–EAIV) Output hold time, EAx invalid after SDCLK high 0.5P – 1.9 ns
9 tosu(SDCAS–SDCLKH) Output setup time, SDCAS valid before SDCLK high 1.5P – 5 ns
10 toh(SDCLKH–SDCAS) Output hold time, SDCAS valid after SDCLK high 0.5P – 1.9 ns
11 tosu(EDV–SDCLKH) Output setup time, EDx valid before SDCLK high 1.5P – 5 ns
12 toh(SDCLKH–EDIV) Output hold time, EDx invalid after SDCLK high 0.5P – 1.9 ns
13 tosu(SDWE–SDCLKH) Output setup time, SDWE valid before SDCLK high 1.5P – 5 ns
14 toh(SDCLKH–SDWE) Output hold time, SDWE valid after SDCLK high 0.5P – 1.9 ns
15 tosu(SDA10V–SDCLKH) Output setup time, SDA10 valid before SDCLK high 1.5P – 5 ns
16 toh(SDCLKH–SDA10IV) Output hold time, SDA10 invalid after SDCLK high 0.5P – 1.9 ns
17 tosu(SDRAS–SDCLKH) Output setup time, SDRAS valid before SDCLK high 1.5P – 5 ns
18 toh(SDCLKH–SDRAS) Output hold time, SDRAS valid after SDCLK high 0.5P – 1.9 ns
(1) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. When the PLL is
used (CLKMODE x4), P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
For CLKMODE x1:
1.5P = P + PH, where P = 1/CPU clock frequency, and PH = pulse duration of CLKIN high.
0.5P = PL, where PL = pulse duration of CLKIN low.
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SDCLK
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS
SDCAS
SDWE
BE1 BE2 BE3
CA1 CA2 CA3
D1 D2 D3
1413
109
1615
12
11
6
5
4
3
2
1
WRITE
WRITE
WRITE
SDCLK
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS
SDCAS
SDWE
BE1 BE2 BE3
CA1 CA2 CA3
D1 D2 D3
109
1615
6
5
4
3
21
8
7
READ
READ
READ
SMJ320C6701-SP
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Figure 18. Three SDRAM Read Commands
Figure 19. Three SDRAM Write Commands
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SDCLK
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS
SDCAS
SDWE
14
18
16
2
15
1
17
13
DCAB
SDCLK
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS
SDCAS
SDWE
Bank Activate/Row Address
Row Address
18
17
15
5
2
1
ACTV
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SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
Figure 20. SDRAM ACTV Command
Figure 21. SDRAM DCAB Command
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SDCLK
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS
SDCAS
SDWE
MRS Value
14
10
18
6
2
1
5
17
9
13
MRS
SDCLK
CEx
BE[3:0]
EA[15:2]
ED[31:0]
SDA10
SDRAS
SDCAS
SDWE
10
9
18
17
2
1
REFR
SMJ320C6701-SP
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Figure 22. SDRAM REFR Command
Figure 23. SDRAM MRS Command
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DSP Owns Bus External Requester DSP Owns Bus
’C6701 Ext Req ’C6701
8
7
34
6
6
12
CLKOUT1
HOLD
HOLDA
EMIF Bus(1)
1
5
9
2
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SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
HOLD/HOLDA TIMING
Timing Requirements for the Hold/Hold Acknowledge Cycles(1)
(see Figure 24)
NO. MIN MAX UNIT
1 tsu(HOLDH–CKO1H) Setup time, HOLD high before CLKOUT1 high 5 ns
2 th(CKO1H–HOLDL) Hold time, HOLD low after CLKOUT1 high 2 ns
(1) HOLD is synchronized internally. Therefore, if setup and hold times are not met, it will either be recognized in the current cycle or in the
next cycle. Thus, HOLD can be an asynchronous input.
Switching Characteristics for the Hold/Hold Acknowledge Cycles(1)
(seeFigure 24)
NO. PARAMETER MIN MAX UNIT
3 tR(HOLDL–EMHZ) Response time, HOLD low to EMIF high impedance 4P (2)ns
4 tR(EMHZ–HOLDAL) Response time, EMIF high impedance to HOLDA low 2P ns
5 tR(HOLDH–HOLDAH) Response time, HOLD high to HOLDA high 4P 7P ns
6 td(CKO1H–HOLDAL) Delay time, CLKOUT1 high to HOLDA valid 1 8 ns
7 td(CKO1H–BHZ) Delay time, CLKOUT1 high to EMIF Bus high impedance(3) 1(4) 8(4) ns
8 td(CKO1H–BLZ) Delay time, CLKOUT1 high to EMIF Bus low impedance(3) 1(4) 12(4) ns
9 tR(HOLDH–BLZ) Response time, HOLD high to EMIF Bus low impedance(3) 3P 6P ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
(2) All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst cases for this is an asynchronous read or
write with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are
occurring, then the minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting the NOHOLD = 1.
(3) EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, and
SDWE.
(4) This parameter is not tested.
(1) EMIF bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10,
SDRAS, SDCAS, and SDWE.
Figure 24. HOLD/HOLDA Timing
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RESET TIMING
Timing Requirements for Reset
(see Figure 25)
NO. MIN MAX UNIT
CLKOUT
Width of the RESET pulse (PLL stable)(1) 10(2) 1
1 tw(RESET) cycles
Width of the RESET pulse (PLL needs to sync up)(3) 250(2) μs
(1) This parameter applies to CLKMODE x1 when CLKIN is stable and applies to CLKMODE x4 when CLKIN and PLL are stable.
(2) This parameter is not tested.
(3) This parameter only applies to CLKMODE x4. The RESET signal is not connected internally to the clock PLL circuit. The PLL, however,
may need up to 250 μs to stabilize following device powerup or after PLL configuration has been changed. During that time, RESET
must be asserted to ensure proper device operation. See the clock PLL section for PLL lock times.
Switching Characteristics During Reset(1)
(see Figure 25)
NO. PARAMETER MIN MAX UNIT
CLKOUT1
2 tR(RESET) Response time to change of value in RESET signal 1(2) cycles
3 td(CKO1H–CKO2IV) Delay time, CLKOUT1 high to CLKOUT2 invalid –1(2) ns
4 td(CKO1H–CKO2V) Delay time, CLKOUT1 high to CLKOUT2 valid 10(2) ns
5 td(CKO1H–SDCLKIV) Delay time, CLKOUT1 high to SDCLK invalid –1(2) ns
6 td(CKO1H–SDCLKV) Delay time, CLKOUT1 high to SDCLK valid 10(2) ns
7 td(CKO1H–SSCKIV) Delay time, CLKOUT1 high to SSCLK invalid –1(2) ns
8 td(CKO1H–SSCKV) Delay time, CLKOUT1 high to SSCLK valid 10(2) ns
9 td(CKO1H–LOWIV) Delay time, CLKOUT1 high to low group invalid –1(2) ns
10 td(CKO1H–LOWV) Delay time, CLKOUT1 high to low group valid 10(2) ns
11 td(CKO1H–HIGHIV) Delay time, CLKOUT1 high to high group invalid –1(2) ns
12 td(CKO1H–HIGHV) Delay time, CLKOUT1 high to high group valid 10(2) ns
13 td(CKO1H–ZHZ) Delay time, CLKOUT1 high to Z group high impedance –1(2) ns
14 td(CKO1H–ZV) Delay time, CLKOUT1 high to Z group valid 10(2) ns
(1) Low group consists of: IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1.
High group consists of: HRDY and HINT.
Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE,
HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.
(2) This parameter is not tested
42 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated
Product Folder Links: SMJ320C6701-SP
122
1413
1211
109
87
65
43
CLKOUT1
RESET
CLKOUT2
SDCLK
SSCLK
LOW GROUP(1)
HIGH GROUP(1)
Z GROUP(1)
SMJ320C6701-SP
www.ti.com
SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
(1) Low group consists of IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1.
High group consists of HRDY and HINT.
Z group consists of EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SSADS, SSOE, SSWE, SDA10, SDRAS,
SDCAS, SDWE, HD[15:0], CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, and FSR1.
Figure 25. Reset Timing
Copyright © 2000–2013, Texas Instruments Incorporated Submit Documentation Feedback 43
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Interrupt Number
6
5
4
4
3
2
CLKOUT2
EXT_INTx, NMI
1
Intr Flag
IACK
INUMx
SMJ320C6701-SP
SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
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EXTERNAL INTERRUPT/RESET TIMING
Timing Requirements for Interrupt Response Cycles(1) (2)
(see Figure 26)
NO. MIN MAX UNIT
2 tw(ILOW) Width of the interrupt pulse low 2P(3) ns
3 tw(IHIGH) Width of the interrupt pulse high 2P(3) ns
(1) Interrupt signals are synchronized internally and are potentially recognized one cycle later if setup and hold times are violated. Thus,
they can be connected to asynchronous inputs.
(2) P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
(3) This parameter is not tested.
Switching Characteristics During Interrupt Response Cycles(1)
(see Figure 26)
NO. PARAMETER MIN MAX UNIT
1 tR(EINTH–IACKH) Response time, EXT_INTx high to IACK high 9P ns
4 td(CKO2L–IACKV) Delay time, CLKOUT2 low to IACK valid –0.5P 13 – 0.5P ns
5 td(CKO2L–INUMV) Delay time, CLKOUT2 low to INUMx valid 10 – 0.5P ns
6 td(CKO2L–INUMIV) Delay time, CLKOUT2 low to INUMx invalid –0.5P ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
When the PLL is used (CLKMODE x4), 0.5P = 1/(2 x CPU clock frequency).
For CLKMODE x1: 0.5P = PH, where PH is the high period of CLKIN.
Figure 26. Interrupt Timing
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SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
HOST-PORT INTERFACE TIMING
Timing Requirements for Host-Port Interface Cycles(1) (2)
(see Figure 27,Figure 28,Figure 29, and Figure 30)
NO. MIN MAX UNIT
1 tsu(SEL–HSTBL) Setup time, select signals(3) valid before HSTROBE low 4 ns
2 th(HSTBL–SEL) Hold time, select signals(3) valid after HSTROBE low 2 ns
3 tw(HSTBL) Pulse duration, HSTROBE low 2P(4) ns
4 tw(HSTBH) Pulse duration, HSTROBE high between consecutive accesses 2P(4) ns
10 tsu(SEL–HASL) Setup time, select signals(3) valid before HAS low 4 ns
11 th(HASL–SEL) Hold time, select signals(3) valid after HAS low 2 ns
12 tsu(HDV–HSTBH) Setup time, host data valid before HSTROBE high 3 ns
13 th(HSTBH–HDV) Hold time, host data valid after HSTROBE high 2 ns
Hold time, HSTROBE low after HRDY low. HSTROBE should
14 th(HRDYL–HSTBL) not be inactivated until HRDY is active (low); otherwise, HPI 1(4) ns
writes will not complete properly.
18 tsu(HASL–HSTBL) Setup time, HAS low before HSTROBE low 2(4) ns
19 th(HSTBL–HASL) Hold time, HAS low after HSTROBE low 2(4) ns
(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(2) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
(3) Select signals include: HCNTRL[1:0], HR/W, and HHWIL.
(4) This parameter is not tested.
Switching Characteristics During Host-Port Interface Cycles(1) (2)
(see Figure 27,Figure 28,Figure 29, and Figure 30)
NO. PARAMETER MIN MAX UNIT
5 td(HCS–HRDY) Delay time, HCS to HRDY (3) 1 12 ns
6 td(HSTBL–HRDYH) Delay time, HSTROBE low to HRDY high(4) 1 12 ns
Output hold time, HD low impedance after HSTROBE low for an
7 toh(HSTBL–HDLZ) 4(5) ns
HPI read
8 td(HDV–HRDYL) Delay time, HD valid to HRDY low P – 3(5) P + 3(5) ns
9 toh(HSTBH–HDV) Output hold time, HD valid after HSTROBE high 3 12 ns
15 td(HSTBH–HDHZ) Delay time, HSTROBE high to HD high impedance 3(5) 12(5) ns
16 td(HSTBL–HDV) Delay time, HSTROBE low to HD valid 3 12 ns
17 td(HSTBH–HRDYH) Delay time, HSTROBE high to HRDY high(6) 1 12 ns
(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
(2) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
(3) HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI
is busy completing a previous HPID write or READ with autoincrement.
(4) This parameter is used during an HPID read. At the beginning of the first half–word transfer on the falling edge of HSTROBE, the HPI
sends the request to the DMA auxiliary channel, and HRDY remains high until the DMA auxiliary channel loads the requested data into
HPID.
(5) This parameter is not tested.
(6) This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an
HPID write or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
Copyright © 2000–2013, Texas Instruments Incorporated Submit Documentation Feedback 45
Product Folder Links: SMJ320C6701-SP
HAS
HCNTL[1:0]
HR/W
HHWIL
HSTROBE(1)
HCS
HD[15:0] (output)
HRDY (case 1)
HRDY (case 2)
1st half-word 2nd half-word
51786
51785
15
916
15
97
4
3
11
10
11
10
11
10
11
10
11
1011
10 19 19
18
18
1st half-word 2nd half-word
5
17
86
5
17
85
15
916
15
97
4
3
2
1
2
1
2
1
2
1
2
1
2
1
HAS
HCNTL[1:0]
HR/W
HHWIL
HSTROBE(1)
HCS
HD[15:0] (output)
HRDY (case 1)
HRDY (case 2)
SMJ320C6701-SP
SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
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(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 27. HPI Read Timing (HAS Not Used, Tied High)
(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 28. HPI Read Timing (HAS Used)
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1st half-word 2nd half-word 5
17
5
13
12
13
12
4
14
3
11
10
11
10
11
10
11
10
11
10
11
10
13
12
13
12
HAS
HCNTL[1:0]
HR/W
HHWIL
HSTROBE(1)
HCS
HD[15:0] (input)
HRDY
HBE[1:0]
19
19
18 18
1st half-word 2nd half-word 5
17
5
13
12
13
12
4
14
3
2
1
2
1
2
1
2
1
13
12
13
12
2
1
2
1
HAS
HCNTL[1:0]
HR/W
HHWIL
HSTROBE(1)
HCS
HD[15:0] (input)
HRDY
HBE[1:0]
SMJ320C6701-SP
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SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 29. HPI Write Timing (HAS Not Used, Tied High)
(1) HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 30. HPI Write Timing (HAS Used)
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MULTICHANNEL BUFFERED SERIAL PORT TIMING
Timing Requirements for McBSP(1) (2)
(see Figure 31)
NO. MIN MAX UNIT
2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P(3) ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P – 1(3) ns
CLKR int 13(3)
5 tsu(FRH–CKRL) Setup time, external FSR high before CLKR low ns
CLKR ext 4
CLKR int 7(3)
6 th(CKRL–FRH) Hold time, external FSR high after CLKR low ns
CLKR ext 4
CLKR int 10
7 tsu(DRV–CKRL) Setup time, DR valid before CLKR low ns
CLKR ext 1
CLKR int 4
8 th(CKRL–DRV) Hold time, DR valid after CLKR low ns
CLKR ext 4
CLKX int 13(3)
10 tsu(FXH–CKXL) Setup time, external FSX high before CLKX low ns
CLKX ext 4
CLKX int 7(3)
11 th(CKXL–FXH) Hold time, external FSX high after CLKX low ns
CLKX ext 3
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
(2) CLKRP = CLKXP = FSRP = FSXP = 0 in the pin control register (PCR). If polarity of any of the signals is inverted, then the timing
references of that signal are also inverted.
(3) This parameter is not tested.
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SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
Switching Characteristics for McBSP(1) (2) (3)
(see Figure 31)
NO. PARAMETER MIN MAX UNIT
Delay time, CLKS high to CLKR/X high for internal
1 td(CKSH–CKRXH) 3 15 ns
CLKR/X generated from CLKS input CLKR/X
2 tc(CKRX) Cycle time, CLKR/X 2P ns
int
CLKR/X
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low C – 1(4) C + 1(4) ns
int
4 td(CKRH–FRV) Delay time, CLKR high to internal FSR valid CLKR int –4 4 ns
CLKX int –4 5
9 td(CKXH–FXV) Delay time, CLKX high to internal FSX valid ns
CLKX ext 3(5) 16(5)
CLKX int –3(5) 2(5)
Disable time, DX high impedance following last data bit
12 tdis(CKXH–DXHZ) ns
from CLKX high CLKX ext 2(5) 9(5)
CLKX int –2 4
13 td(CKXH–DXV) Delay time, CLKX high to DX valid. ns
CLKX ext 3 16
Delay time, FSX high to DX valid. FSX int –2(5) 4(5)
14 td(FXH–DXV) ONLY applies when in data delay 0 (XDATDLY = 00b) ns
FSX ext 2(5) 10(5)
mode.
(1) CLKRP = CLKXP = FSRP = FSXP = 0 in the pin control register (PCR). If polarity of any of the signals is inverted, then the timing
references of that signal are also inverted.
(2) Minimum delay times also represent minimum output hold times.
(3) P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
(4) C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
(5) This parameter is not tested.
Copyright © 2000–2013, Texas Instruments Incorporated Submit Documentation Feedback 49
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2
1
CLKS
FSR external
CLKR/X (no need to resync)
CLKR/X(needs resync)
Bit(n-1) (n-2) (n-3)
Bit 0 Bit(n-1) (n-2) (n-3)
14
1312
11
10
9
3
32
8
7
6
5
4
4
3
1
32
CLKS
CLKR
FSR (int)
FSR (ext)
DR
CLKX
FSX (int)
FSX (ext)
FSX (XDATDLY=00b)
DX
13
SMJ320C6701-SP
SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
www.ti.com
Figure 31. McBSP Timing
Timing Requirements for FSR When GSYNC = 1
(see Figure 32)
NO. MIN MAX UNIT
1 tsu(FRH–CKSH) Setup time, FSR high before CLKS high 4(1) ns
2 th(CKSH–FRH) Hold time, FSR high after CLKS high 4(1) ns
(1) This parameter is not tested.
Figure 32. FSR Timing When GSYNC = 1
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Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
3
8
7
6
21
CLKX
FSX
DX
DR
SMJ320C6701-SP
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SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0(1) (2)
(seeFigure 33)MASTER SLAVE
NO. UNIT
MIN MAX MIN MAX
4 tsu(DRV–CKXL) Setup time, DR valid before CLKX low 12 2 – 3P ns
5 th(CKXL–DRV) Hold time, DR valid after CLKX low 4 5 + 6P ns
(1) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
(2) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP=0(1) (2)
(see Figure 33)MASTER(3) SLAVE
NO. PARAMETER UNIT
MIN MAX MIN MAX
1 th(CKXL–FXL) Hold time, FSX low after CLKX low(4) T – 4 T + 4 ns
2 td(FXL–CKXH) Delay time, FSX low to CLKX high(5) L – 4 L + 4 ns
3 td(CKXH–DXV) Delay time, CLKX high to DX valid –4 4 3P + 1 5P + 17 ns
Disable time, DX high impedance following last
6 tdis(CKXL–DXHZ) L–2(6) L + 3(6) ns
data�bit from CLKX low
Disable time, DX high impedance following last
7 tdis(FXH–DXHZ) P + 4(6) 3P + 17(6) ns
data�bit from FSX high
8 td(FXL–DXV) Delay time, FSX low to DX valid 2P + 1 4P + 13 ns
(1) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
(2) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(3) S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
(4) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on
FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
(5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
(6) This parameter is not tested.
Figure 33. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
Timing Requirements SPI Master or Slave: CLKSTP = 11b, CLKXP = 0(1) (1)
(see Figure 34)
(1) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
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Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
4
376
21
CLKX
FSX
DX
DR 5
SMJ320C6701-SP
SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
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Timing Requirements SPI Master or Slave: CLKSTP = 11b, CLKXP = 0(1) (1) (continued)
(see Figure 34)MASTER SLAVE
NO. UNIT
MIN MAX MIN MAX
4 tsu(DRV–CKXH) Setup time, DR valid before CLKX high 12 2 – 3P ns
5 th(CKXH–DRV) Hold time, DR valid after CLKX high 4 5 + 6P ns
Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0(1) (2)
(see Figure 34)MASTER(3) SLAVE
NO. PARAMETER UNIT
MIN MAX MIN MAX
1 th(CKXL–FXL) Hold time, FSX low after CLKX low(4) L – 4 L + 4 ns
2 td(FXL–CKXH) Delay time, FSX low to CLKX high(5) T – 4 T + 4 ns
3 td(CKXL–DXV) Delay time, CLKX low to DX valid –4 4 3P + 1 5P + 17 ns
Disable time, DX high impedance following last
6 tdis(CKXL–DXHZ) –2(6) 4(6) 3P + 4(6) 5P + 17(6) ns
data bit from CLKX low
7 td(FXL–DXV) Delay time, FSX low to DX valid H – 2(6) H + 3(6) 2P + 1 4P + 13 ns
(1) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
(2) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(3) S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
(4) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on
FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
(5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
(6) This parameter is not tested.
Figure 34. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
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Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
38
7
6
21
CLKX
FSX
DX
DR
SMJ320C6701-SP
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SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
Timing Requirements for MCBSP as SPI Master or Slave: CLKSTOP = 10b, CLKXP = 1(1) (2)
(see Figure 35)MASTER SLAVE
NO. UNIT
MIN MAX MIN MAX
4 tsu(DRV–CKXH) Setup time, DR valid before CLKX high 12 2 – 3P ns
5 th(CKXH–DRV) Hold time, DR valid after CLKX high 4 5 + 6P ns
(1) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
(2) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1(1) (2)
(see Figure 35)MASTER(3) SLAVE
NO. PARAMETER UNIT
MIN MAX MIN MAX
1 th(CKXH–FXL) Hold time, FSX low after CLKX high(4) T – 4 T + 4 ns
2 td(FXL–CKXL) Delay time, FSX low to CLKX low(5) H – 4 H + 4 ns
3 td(CKXL–DXV) Delay time, CLKX low to DX valid –4 4 3P + 1 5P + 17 ns
Disable time, DX high impedance following last
6 tdis(CKXH–DXHZ) H – 2(6) H + 3(6) ns
data bit from CLKX high
Disable time, DX high impedance following last
7 tdis(FXH–DXHZ) P + 4(6) 3P + 17(6) ns
data bit from FSX high
8 td(FXL–DXV) Delay time, FSX low to DX valid 2P + 1 4P + 13 ns
(1) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
(2) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(3) S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
(4) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on
FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
(5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
(6) This parameter is not tested.
Figure 35. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
Timing Requirements for McBSP as SPI Master or Slave: CLKSTOP = 11b, CLKXP = 1(1) (2)
(see Figure 36)
(1) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
(2) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
Copyright © 2000–2013, Texas Instruments Incorporated Submit Documentation Feedback 53
Product Folder Links: SMJ320C6701-SP
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
3
7
6
21
CLKX
FSX
DX
DR
SMJ320C6701-SP
SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
www.ti.com
Timing Requirements for McBSP as SPI Master or Slave: CLKSTOP = 11b, CLKXP = 1(1) (2)
(continued)
(see Figure 36)MASTER SLAVE
NO. UNIT
MIN MAX MIN MAX
4 tsu(DRV–CKXL) Setup time, DR valid before CLKX low 12 2 - 3P ns
5 th(CKXL–DRV) Hold time, DR valid after CLKX low 4 5 + 6P ns
Switching Characteristics for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1(1) (2)
(see Figure 36)MASTER(3) SLAVE
NO. PARAMETER UNIT
MIN MAX MIN MAX
1 th(CKXH–FXL) Hold time, FSX low after CLKX high(4) H – 4 H + 4 ns
2 td(FXL–CKXL) Delay time, FSX low to CLKX low(5) T – 4 T + 4 ns
3 td(CKXH–DXV) Delay time, CLKX high to DX valid –4 4 3P + 1 5P + 17 ns
Disable time, DX high impedance following last
6 tdis(CKXH–DXHZ) –2(6) 4(6) 3P + 4(6) 5P + 17(6) ns
data bit from CLKX high
7 td(FXL–DXV) Delay time, FSX low to DX valid L – 2(6) L + 3(6) 2P + 1 4P + 13 ns
(1) The effects of internal clock jitter are included at test. There is no need to adjust timing numbers for internal clock jitter. P = 1/CPU clock
frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
(2) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(3) S = sample rate generator input clock = P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
(4) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on
FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
(5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
(6) This parameter is not tested.
Figure 36. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
54 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated
Product Folder Links: SMJ320C6701-SP
11
CLKOUT1
PD
2
1
CLKOUT1
TINP
TOUT 2
11
CLKOUT1
DMAC[0:3]
SMJ320C6701-SP
www.ti.com
SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
DMAC, TIMER, POWER-DOWN TIMING
Switching Characteristics for DMAC Outputs
(see Figure 37)
NO. PARAMETER MIN MAX UNIT
1 td(CKO1H–DMACV) Delay time, CLKOUT1 high to DMAC valid 2 11 ns
Figure 37. DMAC Timing
Timing Requirements for Timer Inputs(1)
(see Figure 38)
NO. MIN MAX UNIT
1 tw(TINPH) Pulse duration, TINP high 2P ns
(1) P = 1/CPU clock frequency in ns. For example, when running parts at 140 MHz, use P = 7 ns.
Switching Characteristics for Timer Outputs
(see Figure 38)
NO. PARAMETER MIN MAX UNIT
2 td(CKO1H–TOUTV) Delay time, CLKOUT1 high to TOUT valid 1 10 ns
Figure 38. Timer Timing
Switching Characteristics for Power-Down Outputs
(seeFigure 39)
NO. PARAMETER MIN MAX UNIT
1 td(CKO1H–PDV) Delay time, CLKOUT1 high to PD valid 1 9 ns
Figure 39. Power-Down Timing
JTAG TEST-PORT TIMING
Timing Requirements for JTAG Test Port
(see Figure 40)
Copyright © 2000–2013, Texas Instruments Incorporated Submit Documentation Feedback 55
Product Folder Links: SMJ320C6701-SP
TCK
TDO
TDI/TMS/TRST
1
2
34
2
SMJ320C6701-SP
SGUS030F –APRIL 2000–REVISED SEPTEMBER 2013
www.ti.com
Timing Requirements for JTAG Test Port (continued)
(see Figure 40)
NO. MIN MAX UNIT
1 tc(TCK) Cycle time, TCK 35 ns
3 tsu(TDIV–TCKH) Setup time, TDI/TMS/TRST valid before TCK high 10 ns
4 th(TCKH–TDIV) Hold time, TDI/TMS/TRST valid after TCK high 9 ns
Switching Characteristics for JTAG Test Port
(see Figure 40)
NO. PARAMETER MIN MAX UNIT
2 td(TCKL–TDOV) Delay time, TCK low to TDO valid –3(1) 15(1) ns
(1) This parameter is not tested.
Figure 40. JTAG Test-Port Timing
56 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated
Product Folder Links: SMJ320C6701-SP
PACKAGE OPTION ADDENDUM
www.ti.com 7-Nov-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
5962-9866101VXA ACTIVE CFCBGA GLP 429 1 TBD Call TI N / A for Pkg Type -55 to 115 5962-9866101VX
A
SMV320C6701GLP
W14
5962-9866102VXA ACTIVE CFCBGA GLP 429 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9866102VX
A
SMV320C6701GLP
M14
5962-9866102VYC ACTIVE FCLGA ZMB 429 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9866102VY
C
SMV320C6701ZMB
M14
SMV320C6701GLP/EM PREVIEW CFCBGA GLP 429 1 TBD Call TI N / A for Pkg Type 25 Only SMV320C6701GLP/EM
EVAL ONLY
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
PACKAGE OPTION ADDENDUM
www.ti.com 7-Nov-2013
Addendum-Page 2
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SMJ320C6701-SP :
•Catalog: SMJ320C6701
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
MECHANICAL DATA
MCBG004A – SEPTEMBER 1998 – REVISED JANUAR Y 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
GLP (S-CBGA-N429) CERAMIC BALL GRID ARRAY
0,15
1,27
M
∅0,10
2021
25,40 TYP
19
18
16
15 17
1311
10 12 14
Y
V
W
AA
U
R
T
N
M
P
8
7
64 5
K
H
J
F
E
G
3
2
C
A
B
1
D
L
9
Seating Plane
4164732/B 1 1/01
SQ
27,20
26,80
0,50
0,70
0,60
0,90
1,00
1,22 3,30 MAX
1,27
A1 Corner
Bottom View
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-156
D. Flip chip application only
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