ICS950201
IDTTM Programmable Timing Control HubTM for P4TM 460J—01/25/10
Programmable Timing Control HubTM for P4TM
1
DATASHEET
Pin Configuration
Recommended Application:
CK-408 clock for Intel® 845 chipset with P4 processor.
Output Features:
• 3 Differential CPU Clock Pairs @ 3.3V
• 7 PCI (3.3V) @ 33.3MHz
• 3 PCI_F (3.3V) @ 33.3MHz
• 1 USB (3.3V) @ 48MHz
• 1 DOT (3.3V) @ 48MHz
• 1 REF (3.3V) @ 14.318MHz
• 5 3V66 (3.3V) @ 66.6MHz
• 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
Features:
• Supports spread spectrum modulation,
down spread 0 to -0.5%.
• Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
• Uses external 14.318MHz crystal
• Stop clocks and functional control available through
I2C interface.
Key Specifications:
•CPU Output Jitter <150ps
• 3V66 Output Jitter <250ps
• CPU Output Skew <100ps, programmable over 800 ps
with groups CPU0,1 and CPU2.
56-Pin SSOP & TSSOP
* These inputs have 150K internal pull-up resistor to VDD.
Frequency Table
2SF1SF0SF UPC
)zHM(
66V3
)zHM(
]0:2[ffuB66
]2:4[66V3
)zHM(
F_ICP
ICP
)zHM(
000 66.6666.6666.6633.33
001 00.00166.6666.6633.33
010 00.0
0266.6666.6633.33
011 33.33166.6666.6633.33
diM00 etatsirTetatsirTetatsirTetatsirT
diM01 2/KLCT4/KLCT4/KLCT8/KLCT
diM10 devreseRdevres
eRdevreseRdevreseR
diM11 devreseRdevreseRdevreseRdevreseR
IDTTM Programmable Timing Control HubTM for P4TM 460J—01/25/10
ICS950201
Programmable Timing Control HubTM for P4TM
2
Block Diagram
IDTTM Programmable Timing Control HubTM for P4TM 460J—01/25/10
ICS950201
Programmable Timing Control HubTM for P4TM
3
Pin Description
REBMUNNIPEMANNIPEPYTNOITPIRCSED
,62,91,41,8,1
05,64,73,23 DDVRWPylppusrewopV3.3
21XlatsyrC2X
tupnI tupnilatsyrCzHM813.41
32XlatsyrC1X
tuptuO tupt
uolatsyrCzHM813.41
5,6,7
)0:2(F_KLCICPTUO #POTS_ICPybdetceffatonkcolcICPgninnureerF
.tnemeganamrewoprof
,72,02,51,9,4
74,14,63,13 DNGRWPylppusV3.3rofsnipdnuorG
,31,61,71,81
01,11,21 )0:6(KLCICPTUOstuptuokcolcICP
12,
22,32,42)2:5(66V3TUOOCVlanretnimorf,skcolcecnereferzHM66
425_66V3TUOOCVlanretnimorf,kcolcecnereferzHM66
52#DPNI.
woLevitcA.edomnwod-rewopsekovnI
82#DGRWP_ttV
NI
otdesuebortsevitisneslevelasitupniLTTVLV3.3sihT
dilaverastupni0LESITLUMdna)0:2(SFnehwenimreted
delpma
sebotydaereradna
)wolevitca(
92ATADS
O/IIrofnipataD
2
tnarelotV5yrtiucricC
03KLCS
NIIfonipkcolC
2
tnarelotV5yrtiucricC
330_66V3TUOOCVlanretnimorf,skcolcecnereferzHM66
43#POTS_ICPNItpecxewoltupninehw,level0cigoltaskcolcKLCICPst
laH
gninnureerferahcihwF_KLCICP
53KLC_HCV/1_66V3TUO
hguorhtelbatcelestuptuoV3.3
I
2
C
OCVlanretnimorfzHM66ebot
ro
)CSS-non(zHM84
83TOD_zHM84TUOTODrofkcolctuptuozHM84
93BSU_zHM84TUOBSUrofkcolctuptuo
zHM84
042SFNI1cigolebtonnac,noitcelesedoMroftupniV3.3laicepS
24,FERITUO
.sriapKLCUPCehtroftnerrucecnerefereht
sehsilbatsenipsihT
otredronidnuorgotdeitrotsisernoisicerpdexifaseriuqernipsihT
.tnerrucetairporppaehths
ilbatse
340LESTLUMNI stuptuoUPCrofreilpitlumtnerrucehtgnitcelesroftupniLTTVLV3.3
15,84,44)0:2(CKLCUPCTUO erae
sehT.stuptuoUPCriaplaitnereffidfoskcolc"yrotnemelpmoC"
.saibegatlovrofderiuqererasrotsiserlanretxednas
tuptuotnerruc
25,94,54)0:2(TKLCUPCTUO tnerruceraesehT.stuptuoUPCriaplaitnereffidfoskcolc"eurT"
.saibegatlo
vrofderiuqererasrotsiserlanretxednastuptuo
35#POTS_UPCNIwoltupninehw,level0cigoltaskcolcKLCUPCstlaH
45,55)0
:1(SFNIsniptcelesycneuqerF
65FERTUO.kcolcecnereferzHM813.41
Power Groups
(Analog) (Digital)
VDDA = Analog Core PLL1 VDDPCI
VDDREF = REF, Xtal VDD3V66
VDD48 = 48MHz, PLL VDDCPU
IDTTM Programmable Timing Control HubTM for P4TM 460J—01/25/10
ICS950201
Programmable Timing Control HubTM for P4TM
4
Host Swing Select Functions
Maximum Allowed Current
Truth Table
noitidnoC
noitpmusnocylppusV3.3xaM
,sdaolpacetercsidxaM
V564.3=ddV
DNGroddV=stupnicitatsllA
evitcAlluF Am06
3
2SF1SF0SF UPC
)zHM(
)0:5(66V3
)zHM(
F_ICP
ICP
)zHM(
0FER
)zHM(
TOD/BSU
)zHM(
000 66.6666.6633.33813.4100.84
001 00.00166.6633.33813
.4100.84
010 00.00266.6633.33813.4100.84
011 33.33166.6633.33813.4100.84
diM00 etatsirTetatsirTetatsirTetatsirTetatsirT
diM01 2/KLCT4/K
LCT8/KLCTKLCT2/KLCT
diM10 devreseRdevreseRdevreseRdevreseRdevreseR
diM11 devreseRdevreseRdevreseRdevreseRdevreseR
0LESITLUM tegraTdraoB
ZmreT/ecarT
,RecnerefeR
=ferI
V
DD
)rR*3(/
tuptuO
tnerruC Z@hoV
1smho05 ,%1574=rR
Am23.2=ferI FERI*6=hoI05@V7.0
IDTTM Programmable Timing Control HubTM for P4TM 460J—01/25/10
ICS950201
Programmable Timing Control HubTM for P4TM
5
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact IDT for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will
acknowledge
• Controller (host) sends a dummy command code
• ICS clock will
acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will
acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will
acknowledge
each byte
one at a
time
.
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will
acknowledge
• ICS clock will send the
byte count
• Controller (host) acknowledges
• ICS clock sends first byte
(Byte 0) through byte 6
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
Controller (Host) ICS (Slave/Receiver)
St art Bit
Address
D2(H )
AC
K
Dummy Command Code
AC
K
Dummy Byte Count
AC
K
Byte 0
AC
K
Byte 1
AC
K
Byte 2
AC
K
Byte 3
AC
K
B
y
te 4
AC
K
B
y
te 5
AC
K
B
y
te 6
ACK
Stop Bit
How to Write:
Controller (Host) ICS (Slave/Receiver)
St art Bit
Address
D3(H )
AC
K
Byte Coun
t
ACK
Byte
0
ACK
Byte 1
ACK
Byte
2
ACK
Byte
3
ACK
Byte
4
ACK
Byte
5
ACK
Byte
6
ACK
Stop Bit
How to Read:
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has
been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two
bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
Notes:
IDTTM Programmable Timing Control HubTM for P4TM 460J—01/25/10
ICS950201
Programmable Timing Control HubTM for P4TM
6
Byte 0: Control Register
Byte 1: Control Register
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways. Wither the
system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert PCI_STOP
functionality via I2C Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the I2C Byte 0 Bit3. In Software mode it is not allowed to pull the external
PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped PCI_STOP conditions.
The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it is not allowed to mix these
modes.
In Hardware mode the I2C byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip is in
PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I2C Byte 0 Bit 3 = 0)].
4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high, CPUCLKC
off, and external resistor termination will bring CPUCLKC low.
tiB#niPemaNDWP
2
epyT
1
noitpircseD
0tiB450SFXR nodelpmasnip0SFfoeulavehtstcelfeR
purewop
1tiB551SFXR nodelpmasnip1SFfoeulavehtstcelfeR
pur
ewop
2tiB042SFXR nodelpmasnip2SFfoeulavehtstcelfeR
purewop
3tiB43#POTS_ICP
3
XR foeulavehtstcelfeR:edomerawdraH
DWPnodelpmasnip#POTS_ICP
1WR
:edomerawtfoS
deppotsKLCICP=0
deppotstonKLCIC
P=1
4tiB35#POTS_UPCXR lanretxeehtfoeulavtnerrucehtstcelfeR
nip#POTS_UPC
5tiB53HCV/1_66V30WRzHM84/zHM66tceleSHCV
zH
M84=1,zHM66=0
6tiB- 0 )devreseR(
7tiB- daerpS
delbanE 0WRnOdaerpS=1,ffOdaerpS=0
tiB#niPemaNDWP
2
epyT
1
noitpircseD
0tiB15,25 0TKLCUPC
0CKLCUPC 1WRdelbanE=1delbasiD=0
4
1tiB84,94 1TKLCUPC
1CKLCUPC 1WRdelbanE=1delbasiD=0
4
2tiB44,54 2TKLCUPC
2CKLCUPC 1WRdelbanE=1delbasiD=0
4
3tiB15,25 0TKLCUPC
0CKLCUPC 0WR
noitressahtiw0C/0TKLCUPCfolortnocwollA
eerF=1gninnureerftoN=0#POTS_UPCfo
gnin
nur
4tiB84,94 1TKLCUPC
1CKLCUPC 0WR
noitressahtiw1C/1TKLCUPCfolortnocwollA
eerF=1gninnureerftoN=0#POTS_UPCfo
g
ninnur
5tiB44,54 2TKLCUPC
2CKLCUPC 0WR
noitressahtiw2C/2TKLCUPCfolortnocwollA
eerF=1gninnureerftoN=0#POTS_UPC
fo
gninnur
6tiB- - 0 - )devreseR(
7tiB340LESTLUMXR 0LESTLUMfoeulavtnerrucehtstcelfeR
IDTTM Programmable Timing Control HubTM for P4TM 460J—01/25/10
ICS950201
Programmable Timing Control HubTM for P4TM
7
Byte 2: Control Register
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
Byte 3: Control Register
Byte 4: Control Register
tiB#niPemaNDWPepyTnoitpircseD
0tiB010KLCICP1WRdelbanE=1delbasiD=0
1tiB111KLCICP1WRdelbanE=1delbasiD=0
2tiB212KLCICP1WRdelban
E=1delbasiD=0
3tiB313KLCICP1WRdelbanE=1delbasiD=0
4tiB614KLCICP1WRdelbanE=1delbasiD=0
5tiB715KLCICP1WRdelbanE=1delbasiD
=0
6tiB816KLCICP1WRdelbanE=1delbasiD=0
7tiB- - 0 - )devreseR(
tiB#niPemaNDWPepyTnoitpircseD
0tiB5 0F_KLCICP1WRdelbanE=1delbasiD=0
1tiB6 1F_KLCICP1WRdelbanE=1delbasiD=0
2tiB7 2F_KLCICP1WRdel
banE=1delbasiD=0
3tiB5 0F_KLCICP0WR
fonoitressahtiw0F_KLCICPfolortnocwollA
eerftoN=1,gninnuReerF=0.#POTS_ICP
g
ninnur
4tiB6 1F_KLCICP0WR
fonoitressahtiw1F_KLCICPfolortnocwollA
eerftoN=1,gninnuReerF=0.#POTS_ICP
gninnur
5tiB7 2
F_KLCICP0WR
fonoitressahtiw2F_KLCICPfolortnocwollA
eerftoN=1,gninnuReerF=0.#POTS_ICP
gninnur
6tiB93BSU_zHM841WRd
elbanE=1delbasiD=0
7tiB83TOD_zHM841WRdelbanE=1delbasiD=0
tiB#niPemaNDWPepyTnoitpircseD
0tiB122-66V31WRdelbanE=1delbasiD=0
1tiB223-66V31WRdelbanE=1delbasiD=0
2tiB324-66V31WRdelbanE=1
delbasiD=0
3tiB425_66V31WRdelbanE=1delbasiD=0
4tiB53KLC_HCV/1_66V31WRdelbanE=1delbasiD=0
5tiB330_66V31WRdelbanE=1delbas
iD=0
6tiB- - 0 R )devreseR(
7tiB- - 0 R )devreseR(
IDTTM Programmable Timing Control HubTM for P4TM 460J—01/25/10
ICS950201
Programmable Timing Control HubTM for P4TM
8
Absolute Maximum Ratings
Supply Voltage 5.5 V
Logic Inputs GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature 0°C to +70°C
Case Temperature 115°C
Storage Temperature –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX
UNITS
Input High Voltage V
IH
2V
DD
+ 0.3
V
Input Low Voltage V
IL
V
SS
- 0.3 0.8
V
Input High Current I
IH
V
IN
= V
DD
-5 5
µ
A
I
IL1
V
IN
= 0 V; Inputs with no pull-up resistors -5
µ
A
I
IL2
V
IN
= 0 V; Inputs with pull-up resistors
-200
I
DD3.3OP
C
L
= Full load; Select @ 100 MHz 229 240 360
mA
I
DD3.3OP
C
L
=Full load; Select @ 133 MHz 220 236 360
mA
I
DD3.3OP
C
L
= Full load; Select @ 200 MHz 234 245 360
mA
Powerdown Current I
DD3.3PD
45
mA
Input Frequency F
i
V
DD
= 3.3 V 14.318
MHz
Pin Inductance L
pin
7
nH
C
IN
Logic Inputs 5
pF
C
OUT
Output pin capacitance 6
pF
C
INX
X1 & X2 pins 27 45
pF
Transition time
1
T
trans
To 1st crossing of target frequency 3
ms
Settlin
g
time
1
T
s
From 1st crossing to 1% target frequency 3
ms
Clk Stabilization
1
T
STAB
From V
DD
= 3.3 V to 1% target frequency 3
ms
t
PZH
,t
PZL
Output enable delay (all outputs) 110
ns
t
PHZ
,t
PLZ
Output disable delay (all outputs) 1 10
ns
1
Guaranteed by design, not 100% tested in production.
Delay
1
Input Capacitance
1
Input Low Current
Operating Supply
Current
IDTTM Programmable Timing Control HubTM for P4TM 460J—01/25/10
ICS950201
Programmable Timing Control HubTM for P4TM
9
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Current Source Output
Impedance Zo1 VO = Vx3000 Ω1
Voltage High VHigh 660 770 850 1
Voltage Low VLow -150 5 150 1
Max Volta
e Vovs 756 1150 1
Min Volta
g
e Vuds -300 -7 1
Crossin
g
Volta
g
e (abs) Vcross(abs) 250 350 550 mV 1
Crossing Voltage (var) d-Vcross Variation of crossing over all
ed
g
es 12 140 mV 1
Lon
g
Accurac
y
ppm see Tperiod min-max values -300 300 ppm 1,2
200MHz nominal 4.9985 5.0015 ns 2
200MHz spread 4.9985 5.0266 ns 2
166.66MHz nominal 5.9982 6.0018 ns 2
166.66MHz spread 5.9982 6.0320 ns 2
133.33MHz nominal 7.4978 7.5023 ns 2
133.33MHz spread 7.4978 5.4000 ns 2
100.00MHz nominal 9.9970 10.0030 ns 2
100.00MHz spread 9.9970 10.0533 ns 2
200MHz nominal 4.8735 ns 1,2
166.66MHz nominal/spread 5.8732 ns 1,2
133.33MHz nominal/spread 7.3728 ns 1,2
100.00MHz nominal/spread 9.8720 ns 1,2
Rise Time trVOL = 0.175V, VOH = 0.525V 175 332 700 ps 1
Fall Time tfVOH = 0.525V VOL = 0.175V 175 344 700 ps 1
Rise Time Variation d-tr30 125 ps 1
Fall Time Variation d-tf30 125 ps 1
Duty Cycle dt3
Measurement from differential
wavefrom 45 49 55 % 1
Skew tsk3 V
T
= 50% 8 100 ps 1
Jitter, Cycle to cycle tjcyc-cyc
Measurement from differential
wavefrom 60 150 ps 1
1Guaranteed b
y
desi
g
n, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
TperiodAverage period
Absolute min period Tabsmin
Statistical measurement on
single ended signal using
oscilloscope math function.
mV
Measurement on single ended
si
g
nal usin
g
absolute value. mV
IDTTM Programmable Timing Control HubTM for P4TM 460J—01/25/10
ICS950201
Programmable Timing Control HubTM for P4TM
10
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Frequency FO1 33.33 MHz
Output Impedance RDSP1
1VO = VDD*(0.5) 12 33 55 Ω
Output High Voltage VOH
1IOH = -1 mA 2.4 V
Output Low Voltage VO
L
1IOL = 1 mA 0.55 V
Output High Current IOH
1V OH@MIN = 1.0 V, V OH@MA
X
= 3.135 V -33 -33 mA
Output Low Current IOL
1VOL @MIN = 1.95 V, VOL @MA
X
= 0.4 V 30 38 mA
Rise Time tr1
1VOL = 0.4 V, VOH = 2.4 V 0.5 1.29 2 ns
Fall Time tf1
1VOH = 2.4 V, VOL = 0.4 V 0.5 1.45 2 ns
Duty Cycle dt1
1VT = 1.5 V 45 51 55 %
Skew tsk1
1VT = 1.5 V 190 500 ps
Jitter,cycle to cyc tjcyc-cyc
1VT = 1.5 V 124 250 ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Frequency FO1 66.67 MHz
Output Impedance RDSP1
1VO = VDD*(0.5) 12 33 55 Ω
Output High Voltage VOH
1IOH = -1 mA 2.4 V
Output Low Voltage VO
L
1IOL = 1 mA 0.55 V
Output High Current IOH
1V OH@MIN = 1.0 V, V OH@MA
X
= 3.135 V -33 -33 mA
Output Low Current IOL
1VOL @MIN = 1.95 V, VOL @MA
X
= 0.4 V 30 38 mA
Rise Time tr1
1VO
L
= 0.4 V, VOH = 2.4 V 0.5 1.28 2 ns
Fall Time tf1
1VOH = 2.4 V, VO
L
= 0.4 V 0.5 1.36 2 ns
Duty Cycle dt1
1VT = 1.5 V 45 53.1 55 %
Skew tsk1
1VT = 1.5 V 90 250 ps
Jitter tjcyc-cyc
1VT = 1.5 V 3V66 128 250 ps
1Guaranteed by design, not 100% tested in production.
IDTTM Programmable Timing Control HubTM for P4TM 460J—01/25/10
ICS950201
Programmable Timing Control HubTM for P4TM
11
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no
defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard
skew described below as Tpci.
Un-Buffered Mode 3V66 & PCI Phase Relationship
3V66 (1:0)
3V66 (4:2)
3V66_5
PCICLK_F (2:0) PCICLK (6:0) Tpci
Group Skews at Common Transition Edges: (Un-Buffered Mode)
GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS
3V66 3V66 3V66 pin to pin skew 0 500 ps
PCI PCI PCI_F and PCI pin to pin skew 0 500 ps
3V66 to PCI S3V66-PCI 3V66 leads 33MHz PCI 1.5 3.5 ns
1Guaranteed by design, not 100% tested in production.
PD# Functionality
#POTS_UPCTUPCCUPC66V3TUO_zHM66 F_KLCICP
KLCICP KLCICP TOD/BSU
zHM84
1lamroNlamroNzHM66NI_zHM66NI_zHM66NI_zHM66zHM84
0tlu
M*feritaolFwoLwoLwoLwoLwoL
IDTTM Programmable Timing Control HubTM for P4TM 460J—01/25/10
ICS950201
Programmable Timing Control HubTM for P4TM
12
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low
in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising
edge.
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
tsu
Assertion of PCI_STOP# Waveforms
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
CPU_STOP#
CPUT
CPUC
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.
The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current
values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
Assertion of CPU_STOP# Waveforms
CPU_STOP# Functionality
#POTS_UPCTUPCCUPC
1lamroNlamroN
0tluM*feritaolF
IDTTM Programmable Timing Control HubTM for P4TM 460J—01/25/10
ICS950201
Programmable Timing Control HubTM for P4TM
13
Ordering Information
950201yFLF-T
INDEX
AREA
INDEX
AREA
12
1 2
N
D
h x 45°
h x 45°
E1 E
a
SEATING
PLANE
SEATING
PLANE
A1
A
e
-C-
- C -
b
.10 (.004) C
.10 (.004) C
c
L
300 mil SSOP Package
MIN MAX MIN MAX
A 2.41 2.80 .095 .110
A1 0.20 0.40 .008 .016
b 0.20 0.34 .008 .0135
c 0.13 0.25 .005 .010
D
E 10.03 10.68 .395 .420
E1 7.40 7.60 .291 .299
e
h 0.38 0.64 .015 .025
L 0.50 1.02 .020 .040
N
α0° 8° 0° 8°
MIN MAX MIN MAX
56 18.31 18.55 .720 .730
10-0034
Reference Doc.: JEDEC Publication 95, MO-118
VARIATIONS
SEE VARIATIONS SEE VARIATIONS
ND mm. D (inch)
SEE VARIATIONS SEE VARIATIONS
0.635 BASIC 0.025 BASIC
SYMBOL
In Millimeters In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
Example:
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
XXXX y F LF- T
IDTTM Programmable Timing Control HubTM for P4TM 460J—01/25/10
ICS950201
Programmable Timing Control HubTM for P4TM
14
Ordering Information
950201yGLF-T
INDEX
AREA
INDEX
AREA
12
1 2
N
D
E1 E
a
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
-C-
- C -
b
c
L
aaa
C
6.10 mm. Body , 0.50 mm. pitch TSSOP
(240 mil) (0.020 mil)
MIN MAX MIN MAX
A -- 1.20 -- .047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.17 0.27 .007 .011
c 0.09 0.20 .0035 .008
D
E
E1 6.00 6.20 .236 .244
e
L 0.45 0.75 .018 .030
N
α0° 8° 0° 8°
aaa -- 0.10 -- .004
V
ARIATIONS
MIN MAX MIN MAX
56 13.90 14.10 .547 .555
10-0039
SYMBOL In Millimeters In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
SEE VARIATIONS SEE VARIATIONS
8.10 BASIC 0.319 BASIC
0.50 BASIC 0.020 BASIC
SEE VARIATIONS SEE VARIATIONS
ND mm. D (inch)
Reference Doc.: JEDEC Publication 95, MO-153
Example:
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
XXXX y G LF- T
ICS950201
Programmable Timing Control HubTM for P4TM
15
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
408-284-6578
pcclockhelp@idt.com
Corporate Headquarters
Integrated Device Technology , Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United S t ates
800 345 7015
+408 284 8200 (outside U.S.)
Asia Pacific and Jap an
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
Europe
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
© 2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, ICS, and the IDT logo are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks
are or may be trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
TM
Revision History
Rev. Issue Date Description Page #
J 1/25/2010 Updated document template