ADC10080
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ADC10080 10-Bit, 80 MSPS, 3V, 78.6 mW A/D Converter
Check for Samples: ADC10080
1FEATURES DESCRIPTION
The ADC10080 is a monolithic CMOS analog-to-
2• Single +3.0V Operation digital converter capable of converting analog input
• Selectable Full-Scale Input Swing signals into 10-bit digital words at 80 Megasamples
• 400 MHz −3 dB Input Bandwidth(1) per second (MSPS). This converter uses a
differential, pipeline architecture with digital error
• Low Power Consumption correction and an on-chip sample-and-hold circuit to
• Standby Mode provide a complete conversion solution and to
• On-Chip Reference and Sample-and-Hold minimize power consumption, while providing
Amplifier excellent dynamic performance. A unique sample-
and-hold stage yields a full-power bandwidth of 400
• Offset Binary or Two’s Complement Data MHz. Operating on a single 3.0V power supply, this
Format device consumes just 78.6 mW at 80 MSPS,
• Separate Adjustable Output Driver Supply including the reference current. The Standby feature
reduces power consumption to just 15 mW.
KEY SPECIFICATIONS The differential inputs provide a full scale selectable
• Resolution: 10 Bits input swing of 2.0 VP-P, 1.5 VP-P, 1.0 VP-P, with the
possibility of a single-ended input. Full use of the
• Conversion Rate: 80 MSPS differential input is recommended for optimum
• Full Power Bandwidth: 400 MHz performance. An internal +1.2V precision bandgap
• DNL: ±0.25 LSB (typ) reference is used to set the ADC full-scale range, and
• SNR (fIN = 10 MHz): 59.5 dB (typ) also allows the user to supply a buffered referenced
voltage for those applications requiring increased
• SFDR (fIN = 10 MHz): −78.7 dB (typ) accuracy. The output data format is user choice of
• Power Consumption, 80 Msps: 78.6 mW offset binary or two’s complement.
This device is available in the 28-lead TSSOP
APPLICATIONS package and will operate over the industrial
• Ultrasound and Imaging temperature range of −40°C to +85°C.
• Instrumentation
• Cellular Base Stations/Communications
Receivers
• Sonar/Radar
• xDSL
• Wireless Local Loops
• Data Acquisition Systems
• DSP Front Ends
(1) The input bandwidth is limited using a 10 pF capacitor
between VIN−and VIN+.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2003–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADC10080
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Table 1. PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS
Pin No. Symbol Equivalent Circuit Description
ANALOG I/O
Inverting analog input signal. With a 1.2V reference the full-scale
12 VIN−input signal level is a differential 1.0 VP-P. This pin may be tied to
VCOM (pin 4) for single-ended operation.
Non-inverting analog input signal. With a 1.2V reference the full-
13 VIN+scale input signal level is a differential 1.0 VP-P.
Reference input. This pin should be bypassed to VSSA with a 0.1 µF
6 VREF monolithic capacitor. VREF is 1.20V nominal. This pin may be driven
by a 1.20V external reference if desired. Do not load this pin.
7 VREFT
4 VCOM
These pins are high impedance reference bypass pins only.
Connect a 0.1 µF capacitor from each of these pins to VSSA. These
pins should not be loaded. VCOM may be used to set the input
common input voltage, VCM.
8 VREFB
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Table 1. PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS (continued)
Pin No. Symbol Equivalent Circuit Description
DIGITAL I/O
Digital clock input. The range of frequencies for this input is 20 MHz
1 CLK to 80 MHz. The input is sampled on the rising edge of this input.
DF = “1” Two’s Complement
15 DF DF = “0” Offset Binary
This is the standby pin. When high, this pin sets the converter into
28 STBY standby mode. When this pin is low, the converter is in active mode.
IRS = “VDDA” 2.0 VP-P differential input range
IRS = “VSSA” 1.5 VP-P differential input range
IRS (Input Range
5 IRS = “Floating” 1.0 VP-P differential input range
Select) If using both VIN+ and VIN- pins, (or differential mode), then the
peak-to-peak voltage refers to the differential voltage (VIN+ - VIN-).
16–20, Digital output data. D0 is the LSB and D9 is the MSB of the binary
D0–D9
23–27 output word.
ANALOG POWER
Positive analog supply pins. These pins should be connected to a
quiet 3.0V source and bypassed to analog ground with a 0.1 µF
2, 9, 10 VDDA monolithic capacitor located within 1 cm of these pins. A 4.7 µF
capacitor should also be used in parallel.
3, 11, 14 VSSA Ground return for the analog supply.
DIGITAL POWER
Positive digital supply pins for the ADC10080's output drivers. This
pin should be bypassed to digital ground with a 0.1 µF monolithic
22 VDDIO capacitor located within 1 cm of this pin. A 4.7 µF capacitor should
also be used in parallel. The voltage on this pin should never exceed
the voltage on VDDA by more than 300 mV.
The ground return for the digital supply for the output drivers. This
21 VSSIO pin should be connected to the ground plane, but not near the
analog circuitry.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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ABSOLUTE MAXIMUM RATINGS(1)(2)(3)
VDDA, VDDIO 3.9V
Voltage on Any Pin to GND −0.3V to VDDA or VDDIO
+0.3V
Input Current on Any Pin ±25 mA
Package Input Current(4) ±50 mA
Package Dissipation at T = 25°C See(5)
ESD Susceptibility(6) Human Body Model 2500V
Machine Model 250V
Soldering Temperature Infrared, 10 sec.(7) 235°C
Storage Temperature −65°C to +150°C
(1) All voltages are measured with respect to GND = VSSA = VSSIO = 0V, unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications
(4) When the voltage at any pin exceeds the power supplies (VIN < VSSA or VIN > VDDA), the current at that pin should be limited to 25 mA.
The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input
current of 25 mA to two.
(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax −TA)/θJA. In the 28-pin TSSOP, θJA is 96°C/W, so PDMAX = 1,302 mW at 25°C and 677 mW at the maximum
operating ambient temperature of 85°C. Note that the power dissipation of this device under normal operation will typically be about 78.6
mW. The values for maximum power dissipation listed above will be reached only when the ADC10080 is operated in a severe fault
condition.
(6) Human body model is 100 pF capacitor discharged through a 1.5 kΩresistor. Machine model is 220 pF discharged through 0Ω.
(7) The 235°C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR) the following conditions apply: Maintain the
temperature at the top of the package body above 183°C for a minimum of 60 seconds. The temperature measured on the package
body must not exceed 220°C. Only one excursion above 183°C is allowed per reflow cycle. The analog inputs are protected as shown
below. Input voltage magnitude up to 500 mV beyond the supply rails will not damage this device. However, input errors will be
generated if the input goes above VDDA or VDDIO and below VSSA or VSSIO.
OPERATING RATINGS(1)(2)
Operating Temperature Range −40°C ≤TA≤+85°C
VDDA (Supply Voltage) +2.7V to +3.6V
VDDIO (Output Driver Supply Voltage) +2.5V to VDDA
VREF 1.20V
|VSSA–VSSIO|≤100 mV
Clock Duty Cycle 30 to 70 %
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = VSSA = VSSIO = 0V, unless otherwise specified.
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CONVERTER ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V(1)(1)(2), VDDA = +3.0V, VDDIO = +2.5V, VIN =
2 VP-P, STBY = 0V, VREF = 1.20V (External), fCLK = 80 MHz, 50% Duty Cycle, CL= 10 pF/pin. Boldface limits apply for TA=
TMIN to TMAX:all other limits TA= 25°C.(3)(1)(2)
Symbol Parameter Conditions Min Typ Max Units
STATIC CONVERTER CHARACTERISTICS
No Missing Codes ensured 10 Bits
INL Integral Non-Linearity(4) FIN = 500 kHz, 0 dB Full Scale −1.4 ±0.5 +1.6 LSB
DNL Differential Non-Linearity FIN = 500 kHz, 0 dB Full Scale −0.9 ±0.25 +1.0 LSB
Positive Error −1.6 +0.5% +2.0 % FS
GE Gain Error Negative Error −1.6 −0.07% +2.0 % FS
OE Offset Error (VIN+=VIN−)−1.4 0.11 1.7 % FS
Under Range Output Code 0
Over Range Output Code 1023
FPBW Full Power Bandwidth 400 MHz
REFERENCE AND INPUT CHARACTERISTICS
VCM Common Mode Input Voltage 0.5 1.5 V
Output Voltage for use as an input
VCOM 1.45 V
common mode voltage(5)
VREF Internal Reference Voltage 1.2 V
External Reverence Voltage 1.0 1.2 1.5 V
Internal Reference Voltage
VREFTC ±80 ppm/°C
Temperature Coefficient
CIN VIN Input Capacitance (each pin to 4 pF
VSSA)
POWER SUPPLY CHARACTERISTICS
STBY = 1 5 6.3 mA
IVDDA Analog Supply Current STBY 0 25 32 mA
STBY = 1, fIN= 0 Hz 0 mA
IVDDIO Digital Supply Current(6) STBY 0, fIN = 0 Hz 1.2 1.4 mA
STBY = 1 15 18.9 mW
PWR Power Consumption(7) STBY = 0 78.6 100.2 mW
(1) With the test condition for 2 VP-P differential input, the 10-bit LSB is 1.95 mV.
(2) Typical figures are at TA= TJ= 25°C and represent most likely parametric norms. Test limits are ensured to AOQL (Average Outgoing
Quality Level).
(3) To ensure accuracy, it is required that |VDDA–VDDIO|≤100 mV and separate bypass capacitors are used at each power supply pin.
(4) Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge, and VIH = 2.4V for a rising edge.
(5) VCOM is typical value, measured at room temperature. It is not ensured by test. This pin should not be loaded.
(6) IVDDIO is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins,
the supply voltage, VDDIO, and the rate at which the outputs are switching (which is signal dependent). IDR = VDR x (C0x f0+ C1x f1+
C2+ f2+....C11 x f11) where VDR is the output driver supply voltage, Cnis the total load capacitance on the output pin, and fnis the
average frequency at which the pin is toggling.
(7) Power consumption includes output driver power. (fIN = 0 MHz).
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DC AND LOGIC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P,
STBY = 0V, VREF = 1.20V (External), fCLK = 80 MHz, 50% Duty Cycle, CL= 10 pF/pin. Boldface limits apply for TA= TMIN to
TMAX:all other limits TA= 25°C(1)(2)(3)
Symbol Parameter Conditions Min Typ Max Units
CLK, DF, STBY, SENSE
Logical “1” Input Voltage 2V
Logical “0” Input Voltage 0.8 V
Logical “1” Input Current +10 µA
Logical “0” Input Current −10 µA
D0–D9 OUTPUT CHARACTERISTICS
Logical “1” Output Voltage IOUT =−0.5 mA VDDIO−0.2 V
Logical “0” Output Voltage IOUT = 1.6 mA 0.4 V
DYNAMIC CONVERTER CHARACTERISTICS(4)
9.3 9.5 Bits
fIN = 10.0 MHz 9.1
ENOB Effective Number of Bits 9.3 9.5 Bits
fIN = 39 MHz 8.9
58.5 59.5 dB
fIN = 10.0 MHz 57.7
SNR Signal-to-Noise Ratio 58.0 59.2 dB
fIN = 39 MHz 57.0
58.0 dB
fIN = 10.0 MHz 59.2
56.3
SINAD Signal-to-Noise Ratio + Distortion 57.6 dB
fIN = 39 MHz 59.0
55.6
−74.1
fIN = 10.0 MHz −87.0 dBc
−68.7
2nd HD 2nd Harmonic −69.5
fIN = 39 MHz −82 dBc
−62.7
−65
fIN = 10.0 MHz −72.3 dBc
−58.6
3rd HD 3rd Harmonic −64.7
fIN = 39 MHz −74.5 dBc
−57.6
−65
fIN = 10.0 MHz −72.3 dB
−58.6
Total Harmonic Distortion (First 6
THD Harmonics) −64.7
fIN = 39 MHz −74.5 dB
−57.6
−70.8
fIN = 10.0 MHz −78.7 dBc
−68.2
Spurious Free Dynamic Range
SFDR (Excluding 2nd and 3rd Harmonic) −72
fIN = 39 MHz −78.8 dBc
−68
(1) To ensure accuracy, it is required that |VDDA–VDDIO|≤100 mV and separate bypass capacitors are used at each power supply pin.
(2) With the test condition for 2 VP-P differential input, the 10-bit LSB is 1.95 mV.
(3) Typical figures are at TA= TJ= 25°C and represent most likely parametric norms. Test limits are ensured to AOQL (Average Outgoing
Quality Level).
(4) Optimum dynamic performance will be obtained by keeping the reference input at +1.2V.
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AC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following specifications apply for VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P,
STBY = 0V, VREF = 1.20V, (Externally Supplied) fCLK = 80 MHz, 50% Duty Cycle, CL= 10 pF/pin. Boldface limits apply for
TA= TMIN to TMAX:all other limits TA= 25°C(1)(2) (3)(4)
Min Typ Max
Symbol Parameter Conditions Units
(4) (4) (4)
CLK, DF, STBY, SENSE
fCLK1 Maximum Clock Frequency 80 MHz (min)
fCLK2 Minimum Clock Frequency 20 MHz
tCH Clock High Time 6.25 ns
tCL Clock Low Time 6.25 ns
Conversion Latency 6Cycles
T = 25°C 2 3.5 5 ns
Data Output Delay after a Rising Clock
tOD Edge 1 6 ns
tAD Aperture Delay 1 ns
tAJ Aperture Jitter 2 ps (RMS)
Differential VIN step from ±3V
Over Range Recovery Time to 0V to get accurate 1 Clock Cycle
conversion
tSTBY Standby Mode Exit Cycle 20 Cycles
(1) To ensure accuracy, it is required that |VDDA–VDDIO|≤100 mV and separate bypass capacitors are used at each power supply pin.
(2) With the test condition for 2 VP-P differential input, the 10-bit LSB is 1.95 mV.
(3) Typical figures are at TA= TJ= 25°C and represent most likely parametric norms. Test limits are ensured to AOQL (Average Outgoing
Quality Level).
(4) Timing specifications are tested at TTL logic levels, VIL = 0.4V for a falling edge, and VIH = 2.4V for a rising edge.
Specification Definitions
APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for
conversion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.
Aperture jitter manifests itself as noise in the output.
COMMON MODE VOLTAGE (VCM)is the d.c. potential present at both signal inputs to the ADC.
CONVERSION LATENCY See PIPELINE DELAY.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The
specification here refers to the ADC clock input signal.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and states that the converter is
equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated as:
Gain Error = Positive Full-Scale Error −Negative Full-Scale Error (1)
INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
negative full scale through positive full scale. The deviation of any given code from this straight line is
measured from the center of that code value.
MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC10080 is ensured
not to have any missing codes.
NEGATIVE FULL SCALE ERROR is the difference between the input voltage (VIN+−VIN−) just causing a
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transition from negative full scale to the first code and its ideal value of 0.5 LSB.
OFFSET ERROR is the input voltage that will cause a transition from a code of 01 1111 1111 to a code of 10
0000 0000.
OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the
output pins.
PIPELINE DELAY (LATENCY) is the number of clock cycles between initiation of conversion and when that
data is presented to the output driver stage. Data for any given sample is available at the output pins the
Pipeline Delay plus the Output Delay after the sample is taken. New data is available at every clock cycle,
but the data lags the conversion by the pipeline delay.
POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of
1½ LSB below positive full scale.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not including
harmonics or DC.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of
the input signal to the rms value of all of the other spectral components below half the clock frequency,
including harmonics but excluding DC.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the
input signal and the peak spurious signal, where a spurious signal is any signal present in the output
spectrum that is not present at the input.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first six harmonic
levels at the output to the level of the fundamental at the output. THD is calculated as:
where
• f1is the RMS power of the fundamental (output) frequency and f2through f6are the RMS power in the
first 6 harmonic frequencies. (2)
Second Harmonic Distortion (2nd Harm) is the difference expressed in dB, between the RMS power in the
input frequency at the output and the power in its 2nd harmonic level at the output.
Third Harmonic Distortion (3rd Harm) is the difference, expressed in dB, between the RMS power in the input
frequency at the output and the power in its 3rd harmonic level at the output.
Timing Diagram
Figure 2. Clock and Data Timing Diagram
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TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P,
STBY = 0V, VREF = 1.2V (External), fCLK = 80 MHz, fIN , 39 MHz, 50% Duty Cycle.
DNL DNL vs. fCLK
Figure 4. Figure 5.
DNL vs. Clock Duty Cycle (DC input) DNL vs. Temperature
Figure 6. Figure 7.
INL INL vs. fCLK
Figure 8. Figure 9.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P,
STBY = 0V, VREF = 1.2V (External), fCLK = 80 MHz, fIN , 39 MHz, 50% Duty Cycle.
INL vs. Clock Duty Cycle SNR vs. VDDIO
Figure 10. Figure 11.
SNR vs. VDDA SNR vs. fCLK
Figure 12. Figure 13.
INL vs. Temperature SNR vs. Clock Duty Cycle
Figure 14. Figure 15.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P,
STBY = 0V, VREF = 1.2V (External), fCLK = 80 MHz, fIN , 39 MHz, 50% Duty Cycle.
SNR vs. Temperature THD vs. VDDA
Figure 16. Figure 17.
THD vs. VDDIO THD vs. fCLK
Figure 18. Figure 19.
SNR vs. IRS THD vs. IRS
Figure 20. Figure 21.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P,
STBY = 0V, VREF = 1.2V (External), fCLK = 80 MHz, fIN , 39 MHz, 50% Duty Cycle.
SINAD vs. VDDA SINAD vs. VDDIO
Figure 22. Figure 23.
THD vs. Clock Duty Cycle SINAD vs. Clock Duty Cycle
Figure 24. Figure 25.
THD vs. Temperature SINAD vs. Temperature
Figure 26. Figure 27.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P,
STBY = 0V, VREF = 1.2V (External), fCLK = 80 MHz, fIN , 39 MHz, 50% Duty Cycle.
SINAD vs. fCLK SFDR vs. VDDIO
Figure 28. Figure 29.
SINAD vs. IRS SFDR vs. fCLK
Figure 30. Figure 31.
SFDR vs. VDDA SFDR vs. IRS
Figure 32. Figure 33.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, the following specifications apply: VSSA = VSSIO = 0V, VDDA = +3.0V, VDDIO = +2.5V, VIN = 2 VP-P,
STBY = 0V, VREF = 1.2V (External), fCLK = 80 MHz, fIN , 39 MHz, 50% Duty Cycle.
SFDR vs. Clock Duty Cycle Spectral Response @ 10 MHz Input
Figure 34. Figure 35.
SFDR vs. Temperature Spectral Response @ 39 MHz Input
Figure 36. Figure 37.
Power Consumption vs. fCLK
Figure 38.
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2.5V Max
VCM + 1V
VCM
VCM - 1V
0V Min
2.5V Max
VCM + 0.5V
VCM
VCM - 0.5V
0V Min
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FUNCTIONAL DESCRIPTION
The ADC10080 uses a pipeline architecture and has error correction circuitry to help ensure maximum
performance. Differential analog input signals are digitized to 10 bits. In differential mode each analog input
signal should have a peak-to-peak voltage equal to 1.0V, 0.75V or 0.5V, depending on the state of the IRS pin
(pin 5), and be centered around VCM and be 180° out of phase with each other. If single ended operation is
desired, VIN- may be tied to the VCOM pin (pin 4). A single ended input signal may then be applied to VIN+, and
should have a mid range value of VCOM. The signal amplitude should be 2.0V, 1.5V or 1.0V peak-to-peak,
depending on the state or the IRS pin (pin 5).
APPLICATION INFORMATION
ANALOG INPUTS
The ADC10080 has two analog signal inputs, VIN+ and VIN−. These two pins form a differential input pair. There
is one common mode pin VCOM that may be used to set the common mode input voltage.
VCOM PIN
This pin supplies a voltage for possible use to set the common mode input voltage. This pin may also be
connected to VIN-, so that VIN+ may be used as a single ended input. This pin should be bypassed with at least a
0.1 uF capacitor. Do not load this pin.
SIGNAL INPUTS
The signal inputs are VIN+ and VIN−. The input signal amplitude is defined as VIN+−VIN−and is represented in
Figure 39:
Figure 39. Input Voltage Waveforms for a 2VP-P Differential Input
A single ended input signal is shown in Figure 40.
Figure 40. Input Voltage Waveform for a 2VP-P Single Ended Input
The internal switching action at the analog inputs causes energy to be output from the input pins. As the driving
source tries to compensate for this, it adds noise to the signal. To prevent this, use 18Ωseries resistors at each
of the signal input pins with a 25 pF capacitor across the inputs, as shown in Figure 41. These components
should be placed close to the ADC because the input pins of the ADC is the most sensitive part of the system
and this is the last opportunity to filter the input. The two 18Ωresistors and the 25 pF capacitor form a low-pass
filter with a -3 dB frequency of 177 MHz.
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CLK PIN
The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock
signal in the frequency range indicated in the AC Electrical Characteristics Table with rise and fall times of less
than 2 ns. The trace carrying the clock signal should be as short as possible and should not cross any other
signal line, analog or digital, not even at 90°. The CLK signal also drives an internal state machine. If the CLK is
interrupted, or its frequency is too low, the charge on internal capacitors can dissipate to the point where the
accuracy of the output data will degrade. This is what limits the lowest sample rate. The duty cycle of the clock
signal can affect the performance of any A/D Converter. Because achieving a precise duty cycle is difficult, the
ADC10080 is designed to maintain performance over a range of duty cycles. While it is specified and
performance is ensured with a 50% clock duty cycle, performance is typically maintained with minimum clock low
and high times indicated in the AC Electrical Characteristics Table. Both minimum high and low times may not be
held simultaneously.
STBY PIN
The STBY pin, when high, holds the ADC10080 in a power-down mode to conserve power when the converter is
not being used. The power consumption in this state is 15 mW. The output data pins are undefined in this mode.
Power consumption during power-down is not affected by the clock frequency, or by whether there is a clock
signal present. The data in the pipeline is corrupted while in power down.
DF PIN
The DF (Data Format) pin, when high, forces the ADC10080 to output the 2’s complement data format. When DF
is tied low, the output format is offset binary.
IRS PIN
The IRS (Input Range Select) pin defines the input signal amplitude that will produce a full scale output. The
table below describes the function of the IRS pin.
Table 2. IRS Pin Functions
IRS Pin Full-Scale Input
VDDA 2.0VP-P
VSSA 1.5VP-P
Floating 1.0VP-P
OUTPUT PINS
The ADC10080 has 10 TTL/CMOS compatible Data Output pins. The offset binary data is present at these
outputs while the DF and STBY pins are low. Be very careful when driving a high capacitance bus. The more
capacitance the output drivers must charge for each conversion, the more instantaneous digital current flows
through VDDIO and VSSIO. These large charging current spikes can cause on-chip noise and couple into the
analog circuitry, degrading dynamic performance. Adequate bypassing, limiting output capacitance and careful
attention to the ground plane will reduce this problem. Additionally, bus capacitance beyond the specified 10
pF/pin will cause tOD to increase, making it difficult to properly latch the ADC output data. The result could be an
apparent reduction in dynamic performance. To minimize noise due to output switching, minimize the load
currents at the digital outputs. This can be done by minimizing load capacitance and by connecting buffers
between the ADC outputs and any other circuitry, which will isolate the outputs from trace and other circuit
capacitances and limit the output currents, which could otherwise result in performance degradation. Only one
driven input should be connected to the ADC output pins.
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APPLICATION SCHEMATICS
The following figures show simple examples of using the ADC10080. Figure 41 shows a typical differentially
driven input. Figure 42 shows a single ended application circuit.
Figure 41. A Simple Application Using a Differential Driving Source
Figure 42. A Simple Application Using a Single Ended Driving Source
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REVISION HISTORY
Changes from Revision G (March 2013) to Revision H Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 19
20 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
ADC10080CIMT/NOPB ACTIVE TSSOP PW 28 48 RoHS & Green SN Level-3-260C-168 HR -40 to 85 ADC10080
CIMT
ADC10080CIMTX/NOPB ACTIVE TSSOP PW 28 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 85 ADC10080
CIMT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADC10080CIMTX/NOPB TSSOP PW 28 2500 330.0 16.4 6.8 10.2 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADC10080CIMTX/NOPB TSSOP PW 28 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 2
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