ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 1 -
GENERAL DESCRIPTION
The AK4704 offers the ideal features for digital set-top-box systems. Using AKM's mul ti-bit architecture
for its modulator, the AK4704 delivers a wide dynamic range while preserving linearity for improved
THD+N performance. The AK4704 integrat es a combination of SCF and CTF filters, removing the need
for high cost external filters and increasing performance for systems with excessive clock jitter. The
AK4704 also including the audio switches, volumes, vide o switches, video filters, etc. designed primarily
for digital set-top-box systems. The AK4704 is offered in a space s avin g 48-pi n LQFP package.
FEATURES
DAC
Sampling Rates Ranging from 8kHz to 50kHz
64dB High Attenuation 8x FIR Digital Filter
2nd order Analog LPF
On chip Buffer with Single-ended Output
Digital de- em phas is for 32k, 44.1k and 48 kHz sa mpling
I/F format: 24bit MSB justified, I2S, 18/16bit LSB justified
Master clock : 256fs, 384f s
High Tolerance to Clock Jitter
Analog switches for SCART
Audio section
THD+N: -86dB (@2V rms)
Dynamic Range: 96dB (@2Vrms)
Stereo Analog Volume with Zero-cross Detection Circuit
(+6dB to –60dB & Mute)
Six Analog Inputs
Two Stereo Input (TV&VCR SCART)
One Stereo Input (changeo ver to intern al DAC)
Five Analog Outputs
Two Stereo Outputs (TV, VCR SCART)
One Mono Output (Modulator)
Pop Noise Free Circuit for Power on/off
Video section
Integrated LPF: -40dB@27MHz
75ohm driver
6dB Gain for Outputs
Adjustable gain
Four CVBS/Y inputs (ENCx2, TV, VCR),
Three CVBS/Y output (RF, TV, VCR)
Three R/C inputs (ENCx2, VCR), Two R/C output (TV, VCR)
Bi-directional control for VCR-Chroma/Red
Two G and B inputs (ENC, VCR), One G and B outputs (TV)
Y/C Mixer for RF output
VCR input monitor
Loop-through Mode for standby
Auto-Startup Mode for power saving
SCART pin#16(Fast Blanking), pin#8(Slow Blanking) Control
Power supply
5V+/-5% and 12V+/-5 %
Low Power Dissipation / Low Power Standby Mode
Package
Small 48pin LQFP
2ch 24bit DAC with AV SCART switch
AK4704
= Target Spec =
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 2 -
TVOUTL
MONOOUT
TVOUTR
VCROUTL
VCROUTR
+6 to -60dB
(2dB/step)
-6dB/0dB/
+2.44/+4dB
TVINL
TVINR
VCRINL
VCRINR
DAC
MCLK
BICK
LRCK
SDTI
Bias (Mute)
Volume #0 Volume #1
TV1/0
VOL
MONO
SCK
SDA
Register
Control
PDN
DVCOM
PVCOM
VCR1/0
VD
VP
VSS
VMONO
Audio Block(DAPD =“0”)
TVOUTL
MONOOUT
TVOUTR
VCROUTL
VCROUTR
+6 to -60dB
(2dB/step)
TVINL
TVINR
VCRINL
VCRINR
(NC)
DACL
DACR
(NC)
Bias (Mute)
Volume #1
TV1/0
VOL
MONO
SCK
SDA
Register
Control
PDN
DVCOM
PVCOM
VCR1/0
VD
VP
VSS
VMONO
0dB/+6dB
Volume #2
Audio Block(DAPD =“1”)
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 3 -
ENC C TVRC
ENC G/CVBS
VCR G TVG
ENC B
VCR B TVB
ENC Y TVVOUT
RFV
6dB
6dB
6dB
6dB
0, 1, 2, 3 dB
ENC R/C
VCRVO U T
VCRC
6dB
6dB
VCR CVBS/
Y
TV CV B S
VCR R/C
ENC CVBS/Y
ENCC
ENCG
VCRG
ENCB
VCRB
ENCY
ENCRC
VCRVIN
TVVIN
VCRRC
ENCV
( T ypical connection )
RF Mod
TV SCART
VCR SCART
( Typical connection )
VVD2
VVSS
VVD1
6dB
Monitor
FILT
Video Block
Monitor
VCR FB TVFB
6dB
0V
2V
TVSB
VCRSB
0/ 6/ 12V
0/ 6/ 12V
VCRFB
( Typica l connect ion )
TV SCART
VCR SCART
( Typical connection )
INT
Video Blanking Block
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 4 -
Ordering Guide
AK4704 -10
∼ +70°C 48pin LQFP (0.5mm pitch)
Pin Layout
VCRC
TVFB
1
VVD1
48
2 VVSS
3
TVVOUT
4 VVD2
5 TVRC
6
7
TVG
8
TVB
9
ENCB
10
ENCG
11
VCRVOUT 47
RFV 46
PDN 45
SDA
44
SCL
43
LRCK 42
SDTI
41
BICK 40
MCLK 39
VD 38
ENCV 13
ENCY 14
TVVIN 15
VCRVIN 16
VCRFB 17
VCRRC 18
VCRG 19
VCRB 20
INT 21
VCRSB 22
TVSB 23
35
34
33
32
31
30
29
28
27
26
25
DVCOM
VP
VCROUTL
VCROUTR
FILT
TVINL
MONOOUT
TVOUT L
TVOUT R
TVINR
VCRINL
Top View
ENCRC
12
VCRINR 24
36 PVCOM
VSS 37
ENCC
Main differen ce between AK4702 and AK4704
Items AK4702 AK4704
Audio Audio bits 18bit 24bit
Digital filter attenuation level 54dB 64dB
+4dB gain at DAC volume#0 (total: +10dB max) - X
DAC power-down/analog input mode - X
Volume#1 output for VCROUTL/R switch m atrix - X
MONO mixing for VCROUTL/R - X
MONO input X -
Video Video filter - X
150ohm video driver for modulator - X
Y/C mixer for modulator - X
VCR video input monitor - X
VCR Slow Blanki ng monitor in output mode. enabled disabled TV/VCR CVBS input detection & Power Save Mode - X
I2C speed (max) 100kHz 400kHz Others Mask bits for INT function (09H) - X
-: NOT available. X: Available
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 5 -
PIN/FUNCTION
No. Pin Name I/O Function
1 VCRC O Chrominance Output Pin for VCR
2 VVSS - Video Ground Pin. 0V.
3 TVVOUT O Composite/Luminance Output Pi n for TV
4 VVD2 - Video Power Supply Pin #2. 5V.
Normally connected to VVSS with a 0.1µF ceramic capacitor in paralle l with
a 10µF electrolytic cap.
5 TVRC O Red/Chrominance Output Pin for TV
6 TVG O Green Output Pin for TV
7 TVB O Blue Output Pin for TV
8 VVD1 - Video Power Supply Pin #1. 5V.
Normally connected to VVSS with a 0.1µF ceramic ca pacitor in parallel with
a 10µF electrolytic cap.
9 ENCB I Blue Input Pin for Encoder
10 ENCG I Green Input Pin for Encoder
11 ENCRC I Red/Chrominance Input Pin1 for Encoder
12 ENCC I Chrominance Input Pin2 for Encoder
13 ENCV I Composite/Luminance Input Pin1 for Encoder
14 ENCY I Composite/Luminance Input Pin2 for Encoder
15 TVVIN I Composite/Luminance Input Pin for TV
16 VCRVIN I Composite/Luminance Input Pin for VCR
17 VCRFB I Fast Blanking Input Pin for VCR
18 VCRRC I Red/Chrominance Input Pin for VCR
19 VCRG I Green Input Pin for VCR
20 VCRB I Blue Input Pin for VCR
21 INT O Interrupt Pin for Video Blanking
22 VCRSB I/O Slow Blanking Input/Output Pin for VCR
23 TVSB O Slow Blanking Output Pin for TV
24 VCRINR I Rch VCR Audio Input Pin
25 VCRINL I Lch VCR Audio Input Pin
26 TVINR I Rch TV Audio Input Pin
27 TVINL I Lch TV Audio Input Pin
28 FILT O Filter Pin
Normally connected to VVSS with a 0.1µF ceramic capacitor.
29 VCROUTR O Rch Analog Output Pin1
30 VCROUTL O Lch Analog Output Pin1
31 TVOUTR O Rch Analog Output Pin2
32 TVOUTL O Lch Analog Output Pin2
33 MONOOUT O MONO Analog Output Pin
34 VP - Power Supply Pin. 12V.
Normally connected to VSS with a 0.1µF ceramic capacitor in parallel with a
10µF electrolytic cap.
35 DVCOM O DAC Common Voltage Pin
Normally connec te d to VSS wi th a 0.1µF ceramic capacitor in parallel with a
10µF electrolytic cap.
36 PVCOM O Audio Common Voltage Pin
Normally connec te d to VSS wi th a 0.1µF ceramic capacitor in parallel with a
10µF electrolytic cap. The caps affect the settling time of audio bias level.
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 6 -
PIN/FUNCTION (Continued)
37 VSS - Ground Pin. 0V.
38 VD - DAC Power Supply Pin. 5V.
Normally connected to VSS with a 0.1µF ceramic capacitor in parallel with a
10µF electrolytic cap.
39 MCLK
(NC) I
- Master Clock Input Pin at DAPD=”0”.
NC (No Connection) pin at DAPD=”1”.
40 BICK
DACR I
- Audio Serial Dat a Clock Pin at DAPD=”0”.
Rch Analog Audio Input Pin at DAPD=”1”.
41 SDTI
(NC) I
I Audio Serial Dat a Input Pin at DAPD=”0”.
NC (No Connection) pin at DAPD=”1”.
42 LRCK
DACL I
I L/R Clock Pin at DAPD=”0”.
Lch Analog Audio Input Pin at DAPD=”1”.
43 SCL I Control Data Clock Pin
44 SDA I/O Control Data Pin
45 PDN I Power-Down Mode Pin
When at “L”, t he AK4704 is in the power-down m ode and is held in reset. The
AK4704 should always be reset upon power-up.
46 RFV O Composite Output Pin for RF modulator
47 VCRVOUT O Composite/Luminance Output Pin for VCR
48 TVFB O Fast Blanking Output Pin for TV
Note: All input pins should not be left floating.
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 7 -
Internal Equivalent Circuits
Pin No. Pin Name Type Equivalent Circuit Description
39
40
41
42
43
45
MCLK
BICK
SDTI
LRCK
SCL
PDN
Digital I N
(DAPD="0")
Analog IN
(DAPD="1")
VD
200
VSS
(60k)
The 60kohm is attached
only for BICK and
LRCK.
44 SDA Digital I/O
VD
VSS
200
I2C Bus v oltage must
not exceed VD.
21 INT Digital OUT
V
SS
VP
Normally connected to
VD(5V) through
10kohm resistor
externally.
46
47
48
1
3
5
6
7
RFV
VCROUT
TVFB
VCRC
TVVOUT
TVRC
TVG
TVB
Video OUT
VVD1
VVSS
VVD2
VVSS
28 FILT Filter OUT
VP
VSS
VSS
200
1k
VD
68k
Normally connected to
VVSS (0V) through
0.1µF capacitor
externally.
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 8 -
Pin No. Pin Name Type Equivalent Circuit Description
9
10
11
12
13
14
15
16
17
18
19
20
ENCB
ENCG
ENCRC
ENCC
ENCV
ENCY
TVVIN
VCRVIN
VCRFB
VCRRC
VCRG
VCRB
Video IN
VVD1
200
VVSS
22
23 VCRSB
TVSB Video SB
VP
VSS
VP
VSS VSS
200
(120k)
The 120kohm is not
attached for TVSB.
24
25
26
27
VCRINR
VCRINL
TVINR
TVINL
Audio IN
VP
200
VSS
29
30
31
32
33
VCROUTR
VCROUTL
TVOUTR
TVOUTL
MONOOU
T
Audio OUT
VP
VSS
VP
VSS
100
35
36 DVCOM
PVCOM VCOM OUT
VD
VSS
VD
VSS
100
VD
VSS
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 9 -
ABSOLUTE MAXIMUM RATINGS
(VSS=VVSS=0V;Note: 1)
Parameter Symbol min max Units
Power Supply VD
VVD1
VVD2
VP
|VSS-VVSS| (Note: 2)
-0.3
-0.3
-0.3
-0.3
-
6.0
6.0
6.0
14
0.3
V
V
V
V
V
Input Current (any pins except for supplies) IIN - ±10 mA
Input Voltage VIND -0.3 VD+0.3 V
Video Input Voltage VINV -0.3 VVD1+0.3 V
Audio Input Voltage (except DAC L/R pins) VINA -0.3 VP+0.3 V
Audio Input Voltage (DACL/R pins) VINA -0.3 VD+0.3 V
Ambient Operat ing Temperature Ta -10 70 °C
Storage Tempe rature Tstg -65 150 °C
Note: 1. All voltages with respect to ground.
Note: 2. VSS and VVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITI ONS
(VSS=V VSS=0V; N ote: 1)
Parameter Symbol min typ max Units
Power Supply VD
VVD1=VVD2
VP
4.75
4.75
11.4
5.0
5.0
12
5.25
5.25
12.6
V
V
V
Note: 3. Analog output voltage scales with the voltage of VD.
AOUT (typ@0dB) = 2Vrms × VD/5.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
ELECTRICAL CHARACTERISTI CS
(Ta = 25°C; VP=12V, VD = 5V; VVD1=VVD2 = 5V; fs = 48kHz; BICK = 64fs)
Power Supplies
Power Supply Current
Normal Operation (PDN = “H”; Note: 4)
VD
VVD1+VVD2
VP
Power-Down Mode (PDN = “ L”; Note: 5)
VD
VVD1+VVD2
VP
TBD
TBD
TBD
10
10
10
TBD
TBD
TBD
100
100
100
mA
mA
mA
µA
µA
µA
Note: 4. STBY bit ="L", All video outputs active.
No signal, no load for A/V switches. fs=48kHz “0”data input for DAC.
Note: 5. All digital inputs including clock pins (MCLK, BICK and LRCK) are held at VD or VSS.
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 10 -
DIGITAL CHARACTERISTICS
(Ta = 25°C; VD = 4.75 ∼ 5.25V)
Parameter Symbol min typ max Units
High-Level Input Voltage
Low-Leve l Input Volt ag e VIH
VIL 2.0
- -
- -
0.8 V
V
Low-Level Output Voltage
(SDA pin: Iout= 3mA, INT pin: Iout= 1mA) VOL - - 0.4 V
Input Leakage Current Iin - - ± 100 µA
ANALOG CH AR AC TE RI S T I C S (AUDI O )
(Ta = 25°C; VP=12V, VD = 5V; VVD1=VVD2 = 5V; fs = 48kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input
Data; Measure ment frequency = 20Hz ∼ 20kHz; RL ≥4.5kΩ; Volume #0=Volume #1=0dB, 0dB=2Vrms output; unless
otherwise specified)
Parameter min typ max Units
DAC Resolution 24 bit
Analog Input: (TVINL/TVINR/VC RINL/VCRINR pins)
Analog Input Ch aracte ristics
Input Voltage 2 Vrms
Input Resist ance 100 150 - kΩ
Analog Input: (DACL/DACR pin)
Analog Input Ch aracte ristics
Input Voltage 1 Vrms
Input Resistance TBD TBD - kΩ
Stereo/Mono Output: (TVOUTL/TVOUTR/VCROUTL/VCROUTR/MONOOUT pins; Note : 6)
Analog Output C har acteristics
Volume#0 Gain (DVOL1-0 = “00”)
(DVOL1-0 = “01”)
(DVOL1-0 = “10”)
(DVOL1-0 = “11”. Note: 7)
0
-6
+2.44
+4
dB
dB
dB
dB
Volume#1 Step Width (+6dB to –12dB)
(-12dB to –40dB)
(-40dB to –60dB)
1.6
0.5
0.1
2
2
2
2.4
3.5
3.9
dB
dB
dB
THD+N (at 2Vrms output. Note: 8)
(at 3Vrms output. Note: 8, Note: 9) -86
-60 -80
- dB
dB
Dynamic Range (-60dB Output, A-weighted. Note: 8) 92 96 dB
S/N (A-weighted. Note: 8) 92 96 dB
Interchannel Isolation (Note: 8, Note: 10) 80 90 dB
Interchannel Gain Mismatch (Note: 8, Note: 10) - 0.3 - dB
Gain Drift - 200 - ppm/°C
Load Resistance (AC-Lord; Note: 11)
TVOUTL/R, VCROUTL/ R, MONOOUT
4.5
kΩ
Output Voltage (Note: 11, Note: 12) 1.85 2 2.15 Vrms
Power Supply Rejection (PSR. Note: 13) - 50 dB
Note: 6. Measured by Audio Precision System Two Cascade.
Note: 7. Output clips over –2.5dBFS digital input.
Note: 8. DAC to TVOUT
Note: 9. Except VCROUTL/VCROUTL pins.
Note: 10. Between TVOUTL and TVOUTR with digital inputs 1kHz/0dBFS.
Note: 11. THD+N : -80dB(min. at 2Vrns), -60dB(typ. at 3Vrms).
Note: 12. Full-scale output voltage by DAC (0dBFS). Output voltage of DAC scales with the voltage of VD,
Stereo output (typ@0dBFS) = 2Vrm s × VD/5 when volume#0=volume#1=0dB. Do not output signals over 3Vrms.
Note: 13. The PSR is applied to VD with 1kHz, 100mV.
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 11 -
FILTER CHARACTERISTICS
(Ta = 25°C; VP=11.4∼12.6V, V D = 4.75∼5.25V, VVD1=VVD2 = 4.75∼5.25V; fs = 48kHz ; DEM 0 = “1”, DEM 1 = “ 0”)
Parameter Symbol min typ max Units
Digital filter
Passband ±0.05dB (Note: 14)
-6.0dB PB 0
-
24.0 21.77
- kHz
kHz
Stopband (Note: 14) SB 26.23 kHz
Passband Ripple PR ± 0.01 dB
Stopband Attenuation SA 64 dB
Group Delay (Note: 15) GD - 24 - 1/fs
Digital Filter + LPF
Frequency Response 0 ∼ 20.0kHz FR -
± 0.5 - dB
Note: 14. The passband and stopband frequencies scale with fs (system sampling rate).
e.g.) PB=0.4535×fs (@±0.05dB), SB=0.546×fs.
Note: 15. The ca lcula ti ng de l ay t ime which occurred by di git al filtering. This t ime is from setting the 16/18/24bit data of
both channels to input register to the output of analog signal.
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 12 -
ANALOG CHARACTERISTICS (VIDEO)
(Ta = 25°C; VP=12V, VD = 5V; VVD1=VVD2 = 5V; VVOL1/0= “00”, YC=“0” unless specified.)
Parameter Conditions min typ max Units
Sync Tip Clamp Voltage at output pin. 0.7 V
Chrominance Bias Voltage at output pin. 2.2 V
Gain Input=0.3Vp-p, 100kHz 5.5 6 6.5 dB
VVOL1/0= “00” 5.5 6 6.5 dB
VVOL1/0= “01” 6.7 7.2 7.7 dB
VVOL1/0= “10” 7.7 8.2 8.7 dB
RGB Gain Input=0.3Vp-p,
100kHz
VVOL1/0= “11” 8.6 9.1 9.6 dB
Interchannel Gain Mismatch TVRC, TVG, TVB. Input=0.3Vp-p, 100kHz. -0.3 - 0.3 dB
Frequency Response Input=0.3Vp-p, C1=C2=0pF. 100kHz to 6MHz.
at 12MHz.
at 27MHz.
-1.0
-3
-40
0.5
-35
dB
dB
dB
Group Delay Distortion At 4.43MHz with respect to 1MHz. 15 ns
Input Impedance Chrominance input (i nternally biased) 40 60 - kohm
Input Signal f=100kHz, maximum with distortion < 1.0%,
gain=6dB. - - 1.5 Vpp
Load Resistance (Note: 16) 150 - - ohm
Load Capacitance C1 (Note: 16)
C2 (Note: 16) 400
15 pF
pF
Dynamic Output Signal f=100kHz, maximum with distortion < 1.0% - - 3 Vpp
Y/C Crosstalk f=4.43MHz, 1Vp-p input. Among TVVOUT,
TVRC, VCRVOUT and VCRC outputs. - -50 - dB
S/N Reference Level = 0.7Vp-p, CCIR 567 weighting.
BW= 15kHz to 5MHz. - 74 - dB
Differential Gain 0.7Vpp 5steps modulated staircase.
chrominance &burst are 280mVpp, 4.43MHz. - TBD - %
Differential Phase 0.7Vpp 5steps modulated staircase.
chrominance &burst are 280mVpp, 4.43MHz. - TBD - Degree
Note: 16. Refer the Figure 1.
Video Signa l Output 75 ohm
75 oh
m
max: 400pF
C1
R1
R2
max: 15pF
C2
Figure 1. Load Resistance R1+R2 and Load Capacitance C1/C2.
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 13 -
SWITCHING CHARACTERISTICS
(Ta = 25°C; VP=11.4 ∼ 12.6V, VD = 4.75 ∼ 5.25V, VVD1=VVD2 = 4.75 ∼ 5.25V; CL = 20pF)
Parameter Symbol Min typ max Units
Master Clock Frequency 256fs:
Duty Cycle
384fs:
Duty Cycle
fCLK
dCLK
fCLK
dCLK
2.048
40
3.072
40
12.8
60
19.2
60
MHz
%
MHz
%
LRCK Frequency
Duty Cycle fs
Duty 8
45 50
55 kHz
%
Audio Inte rface Timing
BICK Period
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge (Note: 17)
LRCK Edge to BICK “↑” (Note: 17)
SDTI Hold Time
SDTI Setup Time
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
312.5
100
100
50
50
50
50
ns
ns
ns
ns
ns
ns
ns
Control Interf ace Timing (I2C Bus):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note: 18)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise
Suppressed by Input Filter
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
-
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
0.6
0
400
-
-
-
-
-
-
-
0.3
0.3
-
50
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
Reset Timing
PDN Pulse Width (Note: 19)
tPD
150
ns
Note: 17. BICK rising edge must not occur at the same time as LRCK edge.
Note: 18. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note: 19. The AK4704 should be reset by PDN= “L” upon power up.
Note: 2 0 . I2C is a registered trademark of Philips Sem iconductors.
Purchase of Asahi Kasei Microsys tems Co., Ltd I2C components conveys a lice nse under the Phi l ips I2C patent
to use the components in the I2C system, provided the system conform to the I2C specifications defined by
Philips.
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 14 -
Timing Diagram
1/fCLK
tCLKL
VIH
tCLKH
MCLK VIL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK VIL
tBCK
tBCKL
VIH
tBCKH
BICK VIL
Clock Timing
tLRB
LRCK
VIH
BICK VIL
tSDS
VIH
SDTI VIL
tSDH
VIH
VIL
tBLR
Serial Interface Timing
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 15 -
tPD
VIL
PDN
Power-down Timi ng
tHIGH
SCL
SDA VIH
tLOW
tBUF
tHD:STA
tR tF
tHD:DAT tSU:DAT tSU:STA
Stop Start Start Stop
tSU:STO
VIL
VIH
VIL
tSP
I2C Bus mode Timing
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 16 -
OPERATION OVERVIEW
1. System Reset and Power-down options
The AK4704 should be reset onc e by bringing PDN pin = “ L” upon power-up. The AK4704 has several operati on modes.
The PDN pin, AUTO bi t, DAPD bit , MUTE bi t and STB Y bit control operati on modes as shown in Table 1 and Table 2.
Mode PDN
pin AUTO
bit STBY
bit MUTE
bit DAPD
bit Mode
0 “L” * * * * Full Power-down
1 “H” 1 * * * Auto Startup mode
(power-on default)
2 “H” 0 1 1 * Standby & mute
3 “H” 0 1 0 * Standby
4 “H” 0 0 1 1 Mute
(DAC power down)
5 “H” 0 0 1 0 Mute
(DAC operation)
6 “H” 0 0 0 1 Normal operation
(DAC power down
& Analog input)
7 “H” 0 0 0 0 Normal operation
(DAC operation)
*: Don’t Care
Table 1. Operation Mode Settings
Mode
Register
Control
MCLK,
BICK,
LRCK
Audio Bias
Level Video
Output TVFB,
TVSB VCRSB
0 Full Power-down NOT
available Not
needed Power
down Hi-Z Hi-Z Pull-
Down
(**)
1 Auto Startup mode
(power-on default) No video
input Available
Video
input (***) Active
Active
(****) Active Active
2 Standby & mute Power
down Hi-Z/
Active
3 Standby Active
4 Mute
(DAC power down)
Power
down
5 Mute
(DAC operation) Needed
6 Normal operation
(DAC power down
& Analog input)
Not
needed Acti ve (*)
7 Normal operation
(DAC operation) Needed
(*): TVOUTL/R are muted by VMUTE bit in the default state.
(**): Internally pulled down by 120kohm(typ) resister.
(***): Video input to TVVIN or VCRVIN.
(****): VCRC outputs 0V for termi nation.
Table 2. Status of each operation modes
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
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Full Power-down Mode
The AK4704 should be reset once by bringing PDN= ”L” upon power-up.
PDN pin: Power down pin
“H”: Normal operation
“L”: Device power down.
Auto Startup Mode
After when the PDN pin is set to “H”, the AK4704 is in the aut o startup mode. In this m ode, all blocks except for the video
detection circuit are powered down. Once the video detection circuit detects video signal from TVVIN pin or VCRVIN
pin, the AK4704 goes to t he stand-by mode automatic ally and sends “H” pulse via INT pin. To exit the aut o startup mode,
set the AUTO bit to “0”.
AUTO bit (00H D3): Auto start up bit
“1”: Auto startup enable (default).
“0”: Auto startup disable (Manual startup).
DAC Power-down Mode
The internal DAC block can be powered-down and switched to 1Vrms analog input mode. When DAPD bit =“1”, the
zero-cross detection and offset calibration does not work.
DAPD bit (00H D2): DAC power-down bit.
“1”: DAC power-down. Analog-input mode.
#39 pin: MCLK -> (NC)
#40 pin: BICK -> DACR. Rch analog input.
#41 pin: SDTI -> (NC)
#42 pin: LRCK -> DACL. Lch analog input.
“0”: DAC operation. (default)
Standby Mode
When the AUTO bit = M UTE bit = “0” and the STBY bit = “1”, the AK4704 is forced int o TV-VCR loop through mode.
In this mode, the sources of TVOUTL/R and MONOOUT pins a re fixed to VCRINL/R pins; the sources of VCROUTL/R
are fixed to TVINL/R pins respectively. The gain of volume#1 is fixed to 0dB. All register values themselves are NOT
changed by STBY bit = “1”.
STBY bit (00H D0): Sta ndby bit.
“1”: Standby mode. (default)
“0”: Normal operation.
Mute Mode (Bias-off Mode. 00H: D1)
When the MUTE bit = “1”, the bias voltage on the audio output goes to GND level. Bringing MUTE bit to “0” changes
this bias vol tage sm oothly from GND to V P/2 by 2sec(ty p.). This rem oves the huge clic k noise related the sudden change
of bias voltage at power-on. The change of MUT E bit from “ 1” to “0” also m akes smooth transient from VP/2 to GND by
2sec(typ). This removes the huge click noise related the sudden change of bias voltage at power-off.
MUTE bit: Bias-off bit.
“1”: Set the audio bias to GND. (default)
“0”: Normal operation
Normal Operation Mode
To use the DAC or change analog switches, set the AUTO bit, DAPD bit, MUTE bi t and STBY bit to “0”. The DAC is in
power-down mode until MCLK and LRCK are input. The AK4704 is in power-down mode until MCLK and LRCK are
input. The Figure 2 shows an example of the system timing at the power-down and power-up by PDN pi n.
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
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Typical Operation Sequence (auto setup mode)
The Figure 2 shows an example of the system timing at auto setup m ode.
PDN pi n
A
udi o out (DC)
don’t care
Clo ck, Data in
TVVOUT,
VCRVOUT
Active (l oop-through)
TVVIN Sign al in No Signal
don’t care Signal in No Signal don’t care
VCRVIN Signal in No Sign al don’t care don’t care
Active (l oop-through) Hi-Z Hi-Z Active (loop-through)
(GND) Active (loop-throu gh)
No Sign al
No Signal
Hi-Z
Low Power Mode Low Power Mode Low Power Mode
Figure 2. Typical operating sequence (auto setup mode)
Typical Operation Sequence (ex cept auto setup mode )
The Figure 3 shows an example of the system timing at auto setup m ode.
PDN
p
in
GD
D/A Out
(internal)
(1)
TV o u t
“1” (default)
STBY bit “0” “1”
don’t care (2)
Cl ock in normal operation don’t care (2)
don’t care
Data in don’t care
“0”
GD (1)
“0”
DAC
TV-Source
select
VCR in
VCR in
“1” (default)
MUTE bit “0”
“Stand-by“
VCR in
(3)
VCR in
fixed to VCR in (Loop-throu gh)
“1” “0”
“Stand-by“ “Mute”
Audio data
“1”
(defau lt)
offset calibration
(4)
“1” (de fault)
A
UTO bit “0”
Notes:
(1) The analog output corresponding to the digital input has a group dela y, GD.
(2) The external clocks (MCLK, BICK and LRCK) can be stopped in standby mode.
(3) Mute the analog outputs externally if click noise(3) adversely affects the system.
(4) In case of the CAL bit = “1”, the offset calibration is always executed when the source of TVOUTL/R pins are
switched to DAC after the STBY bit is changed to “0”. To disable this function, set the CAL bit = “0”.
Figure 3. Typical operating sequence (except auto setup mode)
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 19 -
2. Audio Block
System Clock
The external clocks required to operate the DAC section of AK4704 are MCLK, LRCK and BICK. The master clock
(MCLK) corresponds to 256fs or 384fs. MCLK frequency is automatically detected, and the internal master clock
becomes 256fs. The MCLK should be synchronized with LRC K but the phase is not critical. Table 3 illustrates
corresponding clock frequenci es. All external cloc ks (M CLK, B ICK a nd LR CK) should al way s be present whenever t he
DAC section of AK4704 is in the normal operating mode (STBY bit = “0” and DAPD bit = “0”). If these clocks are not
provided, the AK4704 may draw excess current because the device utilizes dynamically refreshed logic internally. The
DAC section of AK4704 should be reset by STB Y bit = “0” aft er threse clocks are provided. If the e xternal clocks are not
present, place the AK4704 in power-down mode (STBY bit = “1”). After exiting reset at power-up etc., the AK4704
remains in power-down mode until MCLK and LRCK are input.
LRCK MCLK BICK
fs 256fs 384fs 64fs
32.0kHz 8.1920MHz 12.2880MHz 2.0480MHz
44.1kHz 11.2896MHz 16.9344MHz 2.8224MHz
48.0kHz 12.2880MHz 18.4320MHz 3.0720MHz
Table 3. System clock example
Audio Serial Interface F ormat (00H: D5-D4)
Data is shifted i n via the SDTI pin using BIC K and LRCK inputs. The DIF0 and DIF1 bits ca n select four formats in serial
mode as shown in Table 4. In all modes, the serial data is MSB-first, 2’s compliment format and is latched on the rising
edge of BICK. Mode 2 can also be used for 16 MSB justified formats by zeroing the unused two LSBs.
Mode DIF1 DIF0 SDTI Format BICK Figure
0 0 0 16bit LSB Justified
≥32fs Figure 4
1 0 1 18bit LSB Justified
≥36fs Figure 4
2 1 0 24bit MSB Justified ≥48fs Figure 5
3 1 1 24bit I2S Compatib le ≥48fs or
32fs Figure 6 Default
Table 4. Audio Data Formats
SDTI
LRCK
BICK
14 0 14 0
Mode 0 D on’t ca re D on ’ t c are
15:MSB, 0:LSB
SDTI
Mode 1 1 7:MSB, 0:LSB
15 14 0 15 14 0
Don’t care Don’t care
17 16 17 16
Lch Data Rch Data
1515
Figure 4. Mode 0,1 Timing
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 20 -
LRCK
BICK
SDTI
23:MSB, 0:LSB
22 1 0 Don’t care 23
Lch Data Rch Data
22 1 0Don’t care
23 1617
Figure 5. Mode 2 Timing
LRCK
BICK
SDTI
23:MSB, 0:LSB
22 1 0Don’t care
23
Lch Data Rch Data
22 1 0Don’t care 23 17
Figure 6. Mode 3 Timing
De-emphasis filter (00H: D7-D6)
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and is controlled by the
DEM0 and DEM1 bits.
DEM1 DEM0 Mode
0 0 44.1kHz
0 1 OFF Default
1 0 48kHz
1 1 32kHz
Table 5. De-emphasis filter control
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 21 -
Volume/Switch Control
The AK4704 has analog volume controls and switch matrixes designed primarily for SCART routing. Those are
controlled via t he control re gister as shown in, Tabl e 6, Table 8, Table 10 and Tabl e 11 (Ple ase refer to t he block diagra m
in figure 1).
(03H: D4-D3)
DVOL1 DVOL0 Volume #0 Gain Output Level
0 0 0dB 2Vrms (with 0dBFS input & volume #1=0dB.)
0 1 -6dB 1Vrms (with 0dBFS input & volume #1=0dB.)
1 0 +2.44dB 2.65Vrms (with 0dBFS input & volume #1=0dB.)
1 1 +4dB
2Vrms (with –10dBFS input & volume #1=+6dB.
Clips over –2.5dBFS digital input.)
Table 6. Volume #0 (at DAPD bit =”0”. DAC mode)
(03H: D4-D3)
DVOL1 DVOL0 Volume #2 Gain Output Level
0 0 +6dB 2Vrms (with 1Vrms input & volume #1=0dB.)
0 1 0dB 1Vrms (with 1Vrms input & volume #1=0dB.)
1 0 (reserved) -
1 1 (reserved) -
Table 7. Volume #2 (at DAPD bit =”1”. analog input mode.)
(02H: D5-D0)
L5 L4 L3 L2 L1 L0 Gain
1 0 0 0 1 0 +6dB
1 0 0 0 0 1 +4dB
1 0 0 0 0 0 +2dB
0 1 1 1 1 1 0dB (default)
… … … … … … …
0 0 0 0 0 1 -60dB
0 0 0 0 0 0 Mute
Note: Do not exceed 3Vrms at analog output.
Table 8. Volume #1 (Analog Volume)
(01H: D1-D0)
TV1 TV0 Source of TVOUTL/R
0 0 DAC
0 1 VCRIN (default)
1 0 Mute
1 1 (Reserved)
Table 9. TVOUT Switch Configuration
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
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(01H: D2-D0)
VOL TV1 TV0 Source of MONOOUT
0 0 0 DAC (L+R)/2
0 0 1 DAC (L+R)/2
0 1 0 DAC (L+R)/2
Bypass the
volume #1
0 1 1 (Reserved)
1 0 0 DAC (L+R)/2
1 0 1 VCRIN (L+R)/2
Through the
volume #1
1 1 0 Mute
1 1 1 (Reserved)
Table 10. MONOOUT Switch Configuration
(01H: D5-D4)
VCR1 VCR0 Source of VCROUTL/R
0 0 DAC
0 1 TVIN (default)
1 0 Mute
1 1 Output of volume #1
Table 11. VCROUT Switch Configuration
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
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Zero-cross Detection and Offset Calibration
To minimize the click noise at changing the gain of volume #1, the AK4704 has a zero-cross detection and an offset
calibration function. When DAPD bit =”1”, the zero-cross detection and offset calibration does not work.
1. Zero-cross detection function (03H: D2-D0)
When the ZERO bit = “1”, the zero-cross detection function is enabled. The gain of volume #1 changes at the first
zero-cross point from the ac knowledgement of a volume changing com mand or when the zero-c ross is not detected within
the time set by ZTM1-0 bits (256/fs to 2048/fs). The zero-cross counter is initialized whenever a gain is issued. The
zero-cross is detected on L/R channels independently . To disable this function, se t the ZERO bit to “0”.
ZERO: Zero-cross detection enable for volume #1
0 : Disable. The volume value changes immediately without zero-cross.
1 : Enable (de fault). The volum e value changes at a zero-crossing point or whe n tim eout (ZTM1-0 bit
setting) occurs.
The internal comparator for zero-cross detection has a sm all offset. Therefore, the gain of volume #1 may change due to
a zero-cross timeout before the comparator-based zero-cross detection occurs.
When the new gain value 1EH(-2dB) is written while the gain of both Lch and Rch are 1FH(0dB), if the Lch detects the
zero-cross prior to Rch, only the ga in of Lch changes to 1EH(-2dB) while Rch waits for a zero-cross. After that, if the gain
is set to 1DH(-4dB) before eit her a zero-cross or zero-cross t imeout, the Rch keeps the sam e value and cha nges from 1FH
to 1DH at next zero-cross or timeout.
1FH
Lch Gain
Rch Gain
Gain Regi st ers
Zero-cross
1FH 1EH 1DH
1DH
1EH1FH 1DH
WR[Gain=1EH] WR[Gain=1DH]
zer o - cro ss ti mer initia li z ed Timeout;
(may have click noise)
Timer (256/fs to2048/fs)
Figure 7. Zero-cross Operation (ZERO= “1”)
2. Offset calibration function (03H: D5)
Offset ca libra tion i s enable d when the C AL bit = “ 1”. This function begins when the TVOUT source is swi tched t o DAC
after the STB Y bit i s cha nged to “0”. It takes 1664/fs to exec ute the offse t calibra tion cy cle. During the offset calibra tion
cycle, the analog outputs are muted. Onc e the offset cal ibration is execute d, the cal ibration m em ory i s held until PDN pin
= “L” or the new calibration is executed. When the switch is changed from DAC to VCR during calibration, the
calibration is discontinued, and resumed when TVOUT is switched back to DAC. If volume #1 gain is changed during
calibration, the change takes place after calibration is complete.
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
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3. Video Block
Video Sw itch Control
The AK4704 has switc hes for TV, VC R and RF modulator. Each sw it che s ca n be control le d via regi sters inde pendent l y.
When AUTO bit = “1” or STBY bit = “1”, these switch setting are ignored and set to fixed configuration (loop-through
mode). Please refer the auto setup mode and standby mode.
(04H: D2-D0)
Mode VTV2-0 bit
Source of
TVVOUT pin Source of
TVRC pin Source of
TVG pin Source of
TVB pin
Shutdown 000 (Hi-Z) (Hi-Z) (Hi-Z) (Hi-Z)
Encoder CVBS /RGB 001 ENCV pin ENCRC pin ENCG pin ENCB pin
Encoder Y/C 1 010 ENCV pin ENCRC pin Hi-Z (Hi-Z)
Encoder Y/C 2 011 ENCY pin ENCC pin Hi-Z (Hi-Z)
VCR (default) 100 VCRVIN pin VCRRC pin VCRG pin VCRB pin
TV CVBS 101 TVVIN pin (Hi-Z) (Hi-Z) (Hi-Z)
(reserved) 110 - - - -
(reserved) 111 - - - -
(please refer notes)
Table 12. TV video output
(04H: D5-D3)
Mode VVCR2-0 bit Source of
VCRVOUT pin Source of
VCRC pin
Shutdown 000 (Hi-Z) (Hi-Z)
Encoder CVBS or Y/C 1 001 ENCV pin ENCRC pin
Encoder CVBS or Y/C 2 010 ENCY pin ENCC pin
TV CVBS (default) 011 TVVIN pin (Hi-Z)
VCR 100 VCRVIN pin VCRRC pin
(reserved) 101 - -
(reserved) 110 - -
(reserved) 111 - -
(please refer notes)
Table 13. VCR video output
(04H: D7-D6)
Mode VRF1-0
bit Source of
RFV pin
Encoder CVBS1 00 ENCV pin
Encoder CVBS2 01 ENCG pin
(Note: 22)
VCR (default) 10 VCRVIN pin
Shutdown 11 (Hi-Z)
(when YC bit=0. please refer notes)
Table 14. RF video output
Note: 21: When input the video signal via ENCRC pin or VCRRC pin, set CLAMP1-0 bits respectively.
Note: 22 When VTV2-0 bit =“001”, TVG bit =“1” and VRF1-0 bit =“01”, RFV pin output is same
as TVG pin output (Encoder G).
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
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Video Output Control (05H: D6-D0)
Each video outputs can be set to Hi-Z individually via control registers. These setting are ignored when the AUTO bit =
“1”. When the CIO bit = “1”, the VCRC pin outputs 0V even if the VCRC bit = “0”. When the CIO bit = “0”, the VCRC
pin follows the setting of VCRC bit. Please refer the “Red/Chroma Bi-directional Control for VCR SCART”
TVV: TVVOUT output control
TVR: TVRCOUT output control
TVG: TVGOUT output control
TVB: TVBOUT output control
VCRV: VCRVOUT output control
VCRC: VCRC output control
TVFB: TVFB output control
0: Hi-Z (default)
1: Active.
Red/Chroma Bi-directional Control for VCR SCART (05H: D7, D5)
The 4704 supports the bi-directional Red/Chroma signal on the VCR SCART.
(AK4704)
VCRRC
pin
VCRC
pin
VCR SCART
75
0.1u
(CIO bit &
VCRC bit) #15 pin
Figure 8. Red/Chroma Bi-directional Control
CIO VCRC State of VCR C pin
0 0 Hi-z (default)
0 1 Active
1 0 Connected to GND
1 1 Connected to GND
Table 15 Red/Chroma Bi-directional Control
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
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RGB Video Gain Control (06H: D1-D0)
VVOL1-0 bits set the RGB video gain.
VVOL1 VVOL0 Gain Ou tput level (Typ. @Input=0.7Vpp)
0 0 +6dB 1.4Vpp (default)
0 1 +7.2dB 1.6Vpp
1 0 +8.2dB 1.8Vpp
1 1 +9.1dB 2.0Vpp
Table 16. RGB video gain control
Clamp and DC-restore circuit control (06H: D6-D5, D3-D2)
Each CVBS and Y input has the sy nc tip c lamp circuit. The sy nc tip volta ge at each output is 0.7V(ty p). This corresponds
0.35V(typ) at the SCA RT connector when m atched by 75ohm resiste rs. The CLAMP1 and CLAM P0 bits select the input
circuit for ENCRC pin (Encoder Red/Chroma) and VCRRC pin (VCR Red/Chroma) respectively. VCLP1-0 bits select
the source of DC- restore circuit.
CLAMP1 : Encoder Red/Chroma (ENCRC pin)input clamp control
0 : DC restore clamp active (for RED signal. default)
1 : Biased (for Chroma signal.)
CLAMP0 : VCR R/C (VCRRC pin)input clamp control
0 : DC restore clamp active (for RED signal)
1 : Biased (for Chroma signal. default.)
VCLP1-0 : DC restore source control
VCLP1 VCLP0 Sync Source of DC Restore
0 0 ENCV (default)
0 1 ENCY
1 0 VCRVIN
1 1 (Reserved)
When the AUTO bit = “1”, the source is fixed to VCRVIN.
Table 17. DC restore source control
Y/C Mixer for RF modulator (06H: D4)
When the YC bit = “1”, the RFV pin outputs Y/C mixed si gnal from TVVOUT pin and TVRC pin.
YC : Y/C m ixing output control for RFV pin
0 : Follow VRF1-0 bits (default)
1 : Y/C mixing from TVVOUT and TVRC.
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
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4. Blanking Control
The AK4704 supports Fast Blanking signals and Slow Blanking (Function Switching) signals for TV/VCR SCART.
Input/Output Control for Fast/Slow Blanking
FB1-0: TV Fast Blanking output control (07H: D1-D0)
FB1 FB0 TVFB pin Output Level
0 0 0V (default)
0 1 4V
1 0 Same a s VCR FB input (4V/0V)
1 1 (Reserved)
(note: minimum load is 150ohm)
Table 18. TV Fast Blanking output
SBT1-0: TV Slow Blanking output control (07H: D3-D2)
SBT1 SBT0 TVSB pin Output Level
0 0 <2V (default)
0 1 5V<, <7V
1 0 (Reserved)
1 1 10V<
(note: minimum load is 10kohm)
Table 19. TV Slow Blanking output
SBV1-0: VCR Slow Bl anking output control (07H: D5-D4)
SBV1 SBV0 VCRSB pin Output Level
0 0 <2V (default)
0 1 5V<, <7V
1 0 (Reserved)
1 1 10V<
(note: minimum load is 10kohm)
Table 20. VCR Slow Bla nking output
SBIO1-0: TV/VCR Sl ow Blanking I/O control (07H: D7-D6)
SBIO1 SBIO0 VCRSB pin Directi on TVSB pin Direction
0 0 Output
(Controlled by SBV1,0) Output
(Controlled by SBT1,0) (default)
0 1 (Reserved) (Reserved)
1 0 Input
(Stored in SVCR1,0) Output
(Controlled by SBT1,0)
1 1 Input
(Stored in SVCR1,0) Output
(Same output as VCR SB)
Table 21. TV/VCR Slow Blanking I/ O control
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
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5. Monitor Options and INT function
Monitor Options (08H: D3-D0)
The AK4704 has several m onitors for the input DC level of VCR slow blanking, the input DC level of VCR fast blanking
and signals input to TVVIN or VCRVIN pins. SVCR 1-0 bits, FVCR bit and VMON bit are reflected to these val ues.
SVCR1-0: VCR Slow blanking status monitor
SVCR1-0 reflect the voltage at VCRSB pin only when the VCRSB is in the input mode.
When the VCRSB is in the output mode, SVCR1-0 hold previous value.
VCRSB pin input level SVCR1 SVCR0
< 2V 0 0
4.5 to 7V 0 1
(Reserved) 1 0
9.5< 1 1
Table 22. VCR Slow Blanking monitor
FVCR: VCR Fast blanking input level monitor
This bit is en a b le d when TVFB bit = “1”.
VCRFB pin input level FVCR
<0.4V 0
1 V< 1
Table 23. VCR Fast Bl anking monitor (Typi cal threshold is 0.7V)
VMON : Video input monitor
0 : No video signal detected via TVVIN pin and VCRVIN pin.
1 : Detects video signa l via TVVIN pin OR VCRVIN pin.
INT Function and Mask Options (09H: D3-D1)
Changes of the 08H status can be monitored via the INT pin. The INT pin is the open drain output and goes “L” for
2usec(typ.) when the status of 08H is changed. This pin should be connected to VD (typ. 5V) through 10kohm resister.
MVMON bit, MFVCR bi t a nd MSVC R bi t cont rol t he refle ct ion of t he sta tus change of these m oni tors onto the INT pin
from report to prevent to masks each monitor
MVMON: Video input monitor mask.
AUTO MVMON Reflection of the change of VMON bit to INT pin
0 0 Reflect
0 1 NOT reflect (e. g . masked)
1 0 Reflect
1 1 Reflect (default)
Table 24. Reflec tion of VMON change
MFVCR: FVCR Mon it o r mask.
0 : Change of MFVCR is reflected to INT pin. (default)
1 : Change of MFVCR is NOT reflect ed to INT pin.
MSVCR: SVCR1-0 Monitor mask.
0 : Change of SVCR1-0 is reflected to INT pin. (default)
1 : Change of SVCR1-0 is NOT reflected to INT pin.
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
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6. Control Interface
I2C-bus Control Mode
1. WRITE Operations
Figure 9 shows the data transfer sequence i n I2C-bus mode. Al l comm ands are prec eded by a START condition. A HIGH
to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 15). After the START
condition, a slave address is sent. Thi s address is 7 bits l ong followed by an ei ghth bit which is a data direct ion bit (R/W).
The most significant seven bits of the slave address are fixed as “0010001”. If the slave address match that of the
AK4704, the AK4704 generates the acknowledge and the operation is executed. The master must generate the
acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 16). A
“1” for R/W bit indicates that the read operation is to be executed. A “0” indicates that the write operation is to be
executed. The sec ond byte consi sts of the address for control re gisters of the AK4704. The form at is M SB first, and t hose
most significant 3-bits are fixed to zeros (Figure 11). The data after the second byte contain control data. The format is
MSB first, 8bits (Figure 12). The AK4704 ge nerates an acknowl edge after each byt e has been received. A data transfer is
always te rminate d by a STOP condi tion generat ed by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 15).
The AK4704 can execute multiple one byte write operations in a sequence. After receipt of the third byte, the AK4704
generates an acknowledge, and awaits the next data again. The master can transmit more than one byte instead of
terminatin g the write cycle af te r th e f ir s t da ta byte is transf e rred. Aft er the receip t of each data , th e internal address
counter is increm ented by one, and the next dat a is taken into next addre ss automati cally. If the addre ss exceeds 09H prior
to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line m ust be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 17) except for the START and the STOP
condition.
SDA
S
T
A
R
T
A
C
K
A
C
K
SSlave
A
ddress
A
C
K
Sub
A
ddress(n) Data(n) P
S
T
O
P
Data(n+x)
A
C
K
Data(n+1)
A
C
K
R/W= “0”
A
C
K
Figure 9. Data transfer sequence at the I2C-bus mode
0 0 1 0 0 0 1 R/W
Figure 10. The first byte
0 0 0 A4 A3 A2 A1 A0
Figure 11. The second byte
D7 D6 D5 D4 D3 D2 D1 D0
Figure 12. Byte structure after the second byte
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 30 -
2. READ Operations
Set R/W bit = “1” for READ operations. After transmission of data, the master can read the next address’s data by
generating an acknowl edge i nstead of t erm inat ing t he write cycle after t he re cei pt the fi rst dat a word. Afte r t he rec ei pt of
each data, t he internal address counte r is increment ed by one, and the next data is take n into next address automatica lly. If
the address exceeds 09H prior to generating the stop condition, the address count er will “roll over” to 00H and the
previous data will be overwritten.
The AK4704 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ.
2-1. CURRENT ADDRESS READ
The AK4704 contains an inte rnal address counter that maintains the address of the last word accessed, incremented by
one. Ther e f o re, if the last ac ce ss (either a read or write) was to address n, the next CURRENT READ operation would
access data from the address n+1. After receipt of the slave address with R/W bit set to “1”, the AK4704 generates an
acknowledge, transmi ts 1byte data which address is set by the i nternal address counter and increments the int ernal address
counter by 1. If the master does not generate an acknowledge to the data but generate the stop condition, the AK4704
discontinue s transmission
SDA
S
T
A
R
T
A
C
K
A
C
K
SSlave
A
ddress
A
C
K
Data(n+1) P
S
T
O
P
Data(n+x)
A
C
K
Data(n+2)
A
C
K
R/W= “1”
A
C
K
Data(n)
Figure 13. CURRENT ADDRESS REA D
2-2. RANDOM READ
Random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bi t set to “1”, t he m aster m ust first pe rform a “dum my ” writ e operati on. The m aster issues a start c ondition,
slave address(R/W=“0”) and then the register address to read. After the register’s address is acknowledge, the master
imm ediatel y reissues the start c ondition and the slave a ddress with the R /W bit set t o “1”. Then the AK4704 generate s an
acknowledge, 1-byte data and increments the internal address counter by 1. If the ma ster does not generate an
acknowledge to the data but generate the stop condition, the AK4704 discontinues transmission.
SDA
S
T
A
R
T
A
C
K
A
C
K
SSlave
A
ddress
A
C
K
Data(n) P
S
T
O
P
Data(n+x)
A
C
K
Data(n+1)
A
C
K
R/W= “0”
A
C
K
Sub
A
ddress(n)
S
T
A
R
T
A
C
K
SSlave
A
ddress
R/W= “1”
Figure 14. RANDOM ADDRESS READ
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 31 -
SCL
SDA
stop co nditionstart condition
SP
Figure 15. START and STOP conditions
SCL FROM
MASTER
acknowledge
DATA
OUTPUT BY
TRANSMITTER
DATA
OUTPUT BY
RECEIVER
1 98
START
CONDITION
not acknowledge
clock pulse for
acknowledgement
S
2
Figure 16. Acknowledge on the I2C-bus
SCL
SDA
data line
stable;
data valid
change
of data
allowed
Figure 17. Bit transfer on the I2C-bus
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 32 -
Register Map
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control DEM1 DEM0 DIF1 DIF0 AUTO DAPD MUTE STBY
01H Switch VMUTE 0 VCR1 VCR0 MONO VOL TV1 TV0
02H Main volume 0 0 L5 L4 L3 L2 L1 L0
03H Zerocross 0 VMONO CAL DVOL1 DVOL0 ZERO ZTM1 ZTM0
04H Video switch VRF1 VRF0 VVCR2 VVCR1 VVCR0 VTV2 VTV1 VTV0
05H Video output enab le CIO TVFB VCRC VCRV TVB TVG TVR TVV
06H Video volume/clamp 0 VCLP1 VCLP0 YC CLAMP1 CLAMP0 VVOL1 VVOL0
07H S/F Blanking control SBIO1 SBIO0 SBV1 SBV0 SBT1 SBT0 FB1 FB0
08H S/F Blanking monitor 0 0 0 0 VMON FVCR SVCR1 SVCR0
09H Monitor mask 0 0 0 0 MVMON MFVCR MSVCR 0
When the PDN pin goes “L”, the registers are initialized to their default values.
While the PDN pin =“H”, al l registers can be accessed.
Do not write any data to the register over 09H.
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 33 -
Register Definitions
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control DEM1 DEM0 DIF1 DIF0 AUTO DAPD MUTE STBY
R/W R/W
default 0 1 1 1 1 0 1 1
STBY: Standby control
0 : Normal Operation
1 : Standby Mode(default). All registers are not initialized.
DAC : powered down and timings are reset.
Gain of Volume#1 : fixed to 0dB,
Source of TVOUT : fixed to VCRIN,
Source of VCROUT : fixed to TVIN,
Source of MONOOUT : fixed to VCRIN,
Source of TVVOUT : fixed to VCRVIN(or Hi-Z),
Source of TVRC : fixed to VCRRC(or Hi-Z),
Source of TVG : fixed to VCRG(or Hi-Z),
Source of TVB : fixed to VCRB(or Hi-Z),
Source of VCRVOUT : fixed to TVVIN(or Hi-Z),
Source of VCRC : fixed to Hi-Z or VSS(controlled by CIO bit).
MUTE: Audio output control
0 : Normal operation
1 : ALL Audio outputs to GND (default)
DAPD: DAC power down control
0 : Normal operation (default).
1 : DAC power down.
When DAPD bit = “1”, the zero-cross detection and offset calibration does not work.
AUTO: Auto startup bit
0 : Auto startup disable (Manual startup).
1 : Auto startup enable(default).
Note: When the SBIO1bit = “1”(default= “ 0”), the change of AUTO bit may cause a “L ” pulse on INT pin.
DIF1-0: Audio data inte rface format control
00 : 16bit LSB Justified
01 : 18bit LSB Justified
10 : 24bit MSB Justified
11 : 24bit I2S Compatible (Default)
DEM1-0: De-em phasis Response Control
00 : 44.1kHz
01 : off (Default)
10 : 48kHz
11 : 32kHz
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 34 -
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
01H Switch VMUTE 0 VCR1 VCR0 MONO VOL TV1 TV0
R/W R/W
default 1 0 0 1 0 1 0 1
TV1-0: TVOUTL/R pins source switch
00 : DAC
01 : VCRINL/R pins (Default)
10 : MUTE
11 : (Reserved)
VOL: MONOOUT pin source swit ch
0 : Bypass the volume (fixed to DAC out)
1 : Through the volume (Default)
MONO: Mono select for TVOUTL/R pins
0 : Stereo. (Default)
1 : Mono. (L+R)/2
VCR1-0: VCROUTL/R pins source switch
00 : DAC
01 : TVINL/R pins (Default)
10 : MUTE
11 : Volume #1 output
VMUTE: Mute switch for volume #1
0 : Normal operation
1 : Mute the volume #1 (Default)
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
02H Main volume 0 0 L5 L4 L3 L2 L1 L0
R/W R/W
default 0 0 0 1 1 1 1 1
L5-0: Volume #1 control
Those registers control both Lch and Rch of Volume #1.
111111 to
100011 : (Reserved)
100010 : Volume gain = +6dB
100001 : Volume gain = +4dB
100000 : Volume gain = +2dB
011111 : Volume gain = +0dB (default)
011110 : Volume gain = -2dB
...
000011 : Volume gain = -56dB
000010 : Volume gain = -58dB
000001 : Volume gain = -60dB
000000 : Volume gain = Mute
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 35 -
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
03H Zerocross 0 VMONO CAL DVOL1 DVOL0 ZERO ZTM1 ZTM0
R/W R/W
default 0
0 1 0 0 1 1 1
ZTM1-0: The time length control of zero-cross timeout
00 : typ. 256/fs
01 : 512/fs
10 : 1024/fs
11 : 2048/fs (default)
ZERO: Zero-cross detection enable for volume #1 control
0 : Disable
The volume value changes immediately without zero-cross.
1 : Enable (d efault)
The volume value changes when timeout or zero-cross before timeout.
This function is disabled when STBY bit = “1”.
DVOL1-0: Volume #0/Volume #2 control.
Please refer the Table 6 and Table 7
CAL: Offs e t ca lib ration Enable
0 : Offset calibration disable.
1 : Offset calibratio n enable(default)
VMONO: Mono selec t for VCROUTL/R pins
0 : Stereo. (Default)
1 : Mono. (L+R)/2
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 36 -
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
04H Video switch VRF1 VRF0 VVCR2 VVCR1 VVCR0 VTV2 VTV1 VTV0
R/W R/W
default 1 0 0 1 1 1 0 0
VTV0-2: Selector for TV video output
Please refer the Table 12.
VVCR0-2: Selector for VCR video output
Please refer the Table 13
RF0-1: Selector for RFV pin output (when YC bit=0).
Please refer the Table 14.
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
05H output enable CIO TVFB VCRC VCRV TVB TVG TVR TVV
R/W R/W
default 0
0 0 0 0 0 0 0
TVV: TVVOUT output control
TVR: TVRCOUT output control
TVG: TVGOUT output control
TVB: TVBOUT output control
VCRV: VCRVOUT output control
VCRC: VCRC output control (please refer the Table 15)
TVFB: TVFB output control
0 : Hi-Z (d efault)
1 : Active.
When the CIO pin = “1”, the VCRC pin is connected to GND even if VCRC= “0”.
When the CIO pin = “0”, the VCRC pin follows the setting of VCRC bit.
CIO: VCRC pin I/O control
Please refer the Table 15.
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 37 -
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
06H Video volume 0 VCLP1 VCLP0 YC CLAMP1 CLAMP0 VVOL1 VVOL0
R/W R/W
default 0
0 0 0 0 1 0 0
VVOL1-0: RGB video gain control
00: +6dB (default)
01: +7.2dB
10: +8.2dB
11: +9.1dB
CLAMP1 : Encoder R/Chroma (ENCRC pin) input clamp control
0 : DC restore clamp active (for RED signal. default)
1 : Biased (for Chroma signal.)
CLAMP0 : VCR R/C (VCRC pin) input clamp control
0 : DC restore clamp active (for RED signal)
1 : Biased (for Chroma signal. default.)
YC : Y/C m ixing output control for RFV pin
0 : Follow VRF1-0 bits (default)
1 : Y/C mixing from TVVOUT and TVRC.
VCLP1-0 : DC restore source control
00: ENCV pin (default)
01: ENCY pin
10: VCRVIN pin
11: (Reserved)
When the AUTO bit = “ 1”, the source is fixed to VCRVIN pin.
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
07H S/F Blanking SBIO1 SBIO0 SBV1 SBV0 SBT1 SBT0 FB1 FB0
R/W R/W
default 0
0 0 0 0 0 0 0
FB1-0: TV Fast Blanking output control (for TVFB pin)
00: 0V (default)
01: 4V
10: follow VCR FB input (4V/0V)
11: (Reserved)
SBT1-0: TV Slow Blanking output control (for TVSB pin. minimum load is 10kohm.)
00: <2V (default)
01: 5V<, <7V
10: (Reserved)
11: 10V<
SBV1-0: VCR Slow Blanking output control (for VCRSB pin. minimum load is 10kohm)
00: <2V (default)
01: 5V<, <7V
10: (Reserved)
11: 10V<
SBIO1-0: TV/VCR Sl ow Blanking I/O control (please re fer the Table 21)
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 38 -
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
08H SB/FB monitor 0 0 0 0 VMON FVCR SVCR1 SVCR0
R/W READ
default 0
0 0 0 0 0 0 0
SVCR1-0: VCR Slow blanking status monitor
SVCR1-0 reflect the voltage at VCRSB pin only when the VCRSB is in the input mode.
When the VCRSB is in the output mode, SVCR1-0 hold previous value.
VCRSB pin input level SVCR1 SVCR0
< 2V 0 0
4.5 to 7V 0 1
(Reserved) 1 0
9.5< 1 1
Table 25. VCR Slow Blanking monitor
FVCR: VCR Fast blanking input level monitor
This bit is en a b le d when TVFB bit = “1”.
VCRFB pin input level FVCR
<0.4V 0
1 V< 1
Table 26. VCR Fast Bl anking monitor (Typi cal threshold is 0.7V)
VMON : Video input monitor
0 : No video signal detected via TVVIN pin and VCRVIN pin.
1 : Detects video signa l via TVVIN pin OR VCRVIN pin.
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
09H Monitor mask 0 0 0 0 MVMON MFVCR MSVCR 0
R/W R/W
default 0
0 0 0 1 0 0 0
MVMON: Video input monitor mask.
Please refer the Table 24.
MFVCR: FVCR Mon it o r mask.
0 : The INT pin reflects the change of MFVCR bit. (default)
1 : The INT pin does not reflect the change of MFVCR bit.
MSVCR: SVCR1-0 Monitor mask.
0 : The INT pin reflects the change of SVCR1-0 bit. (default)
1 : The INT pin does not reflect the change of SVCR1-0 bit.
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 39 -
SYSTEM DESIGN
TV SCART
Y/CVBS
R/C
G
B
Audio L
Audio R
Y/CVBS
Audio L
Audio R
Fast Blank
Slow Blank
Encoder
Y
R/C
G/CVBS
B
CVBS/Y
C
VCR SCART
Y/CVBS
R/C
G
B
Audio L
Audio R
Y/CVBS
Audio L
Audio R
Fast Blank
Slow Blank
Audio MONO
CVBS RF Mod
MPEG
Decoder
BICK
LRCK
SDATA
MCLK
Micro
Processor SDA
SCK
PDN
Phono
ENCV
ENCY
VCRVIN
TVVOUT
ENCC
ENCRC
ENCGV
ENCB
SCK
SDA
PDN
BICK
LRCK
SDTI
MCLK VCRRC
VCRC
VCRG
VCRB
VCRINL
VCRINR
VCRVOUT
VCROUTL
VCROUTR
VCRSB
VCRFB
TVFB
TVOUTL
TVOUTR
TVVIN
TVRC
TVG
TVB
TVINL
TVINR
TVSB
RFV
MONOOUT
Interrupt INT
Figure 18. Typical Connect ion Diagram
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 40 -
Grounding and Power Supply Decoupling
VD, VP, VVD1, VVD2, VSS and VVSS should be supplied from analog supply unit with low impedance and be
separated from system digital supply. An electrolytic capacitor 10µF parallel with a 0.1µF ceramic capacitor should be
attached to these pins to eliminate the effects of high frequency noise. The 0.1µF ceramic capacitor should be placed as
near to VD (VP, VVD1, VVD2) as possible.
Voltage Reference
Each DVCOM/PVCOM are signal ground of this chip. An electrolytic capacitor 10µF parallel with a 0.1µF ceram ic
capacitor shoul d be attached t o these VCOM pins to el iminate the effects of high frequency noise . No load current may be
drawn from these VCOM pins. All signal s , especially clocks, should be kept away from these VCOM pins in order to
avoid unwanted coupling into the AK4704.
Analog Audio Outputs
The analog outputs are also single-ended and centered on 5.6V(typ.). The output signal range is typically 2Vrms
(typ@VD=5V). The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the
delta-sigm a modulator beyond t he audio pass band. Therefore, any external filters are not re quired for typical appl ication.
The output voltage is a positive full scale for 7FFFFFH (@24bit) and a negative full scale for 800000H (@24bit). The
ideal output is 5.6V(typ.) for 000000H (@24bit). The DC voltage on analog outputs are eliminated by AC coupling.
FILT pin
The C (0.1 µF) should be attached as shown in the Figure 19.
AK4704
C=0.1uF
FILT
VVSS
Figure 19. FILT pin
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 41 -
External Circuit Example
Analog Audio Input pin
MONOIN
TVINL/R
VCRINL/
R
DACL/R
0.47µF
300ohm
(Cable)
Analog Audio Output pin
MONOOUT
TVOUTL/R
VCROUTL/R 10µF 300ohm
Total > 4.5kohm
(Cable)
Analog Video Input pin
ENCV, ENCY, VCRVIN,
TVVIN, ENCRC, ENCC,
VCRRC, ENCG, VCRG,
ENCB, VCRB
0.1µF
75ohm
(Cable)
75ohm
Analog Video Output pin
TVVOUT, TVRC
TVG, TV R, RFV
VCRVOUT, VCRC
max
400pF
75ohm
75ohm
max
15pF
(Cable)
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 42 -
Slow Blanking pin
TVSB
VCRSB
max 3nF
(with 400ohm)
400ohm
(ma x 500o hm) min: 10k ohm
(Cable)
Fast Blanking Input pin
VCRFB
75ohm
(Cable)
75ohm
Fast Blanking Output pin
TVFB
75ohm
75ohm
(Cable)
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 43 -
PACKAGE
112
48 13
7.0
9.0 ± 0.2
7.0
9.0 ± 0.2
0.22
±
0.08
48pin LQFP(Unit:mm)
0.10
37 24
25
36
0.145 ± 0.05
1.40
±
0.05
0.13 ± 0.13
1.70Max
0° ∼ 10°
0.10 M
0.5
±
0.2
0.5
Package & Lead frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
ASAHI KASEI AKM CONFIDENTIAL [AK4704]
Rev. 0.5 2004/1
- 44 -
MARKING
AK4704VQ
XXXXXXX
1
XXXXXXXX: Date code identifier
IMPORTANT NOTICE
• These products and their specifications ar e subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Micros ystems Co., Ltd. (AKM) sales office or
authorized distributor conc erning their current status.
• AKM assumes no liability for infringement of any patent, intellectual pr operty, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic ma terials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or s ystem, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Repr esentative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expec ted to
result, whether directly or indirectly, in the loss of the sa fety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of perfor mance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM pr oduct who distributes, disposes of, or
otherwise places the produc t with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all respo nsibility and liability
for and hold AKM harmless fr om any and all claims arising from the use of said product in the
absence of such notificatio n.
