M48T212Y-85MH6 - STMicroelectronics

1/23April 2000

M48T212Y

M48T212V

5V/3.3V TIMEKEEPERCONTROLLER

■CONVERTS LOW POWER SRAM into

NVRAMs

■YEAR 2000 COMPLIANT (4-Digit Year)

■BATTERY LOW FLAG

■INTEGRATED REAL TIME CLOCK,

POWER-FAIL CONTROL CIRCUIT, BATTERY

and CRYSTAL

■AUTOMATIC POWER-FAIL CHIP DESELECT

and WRITE PROTECTION

■WATCHDOG TIMER

■CHOICE of WRITE PROTECT VOLTAGES

(VPFD = Power-fail Deselect Voltage):

– M48T212Y: 4.2V ≤ VPFD ≤ 4.5V

– M48T212V: 2.7V ≤ VPFD ≤ 3.0V

■MICROPROCESSOR POWER-ON RESET

■PROGRAMMABLE ALARM OUTPUT ACTIVE

in the BATTERY BACKED-UP MODE

■PACKAGING INCLUDESa44-LEADSOIC and

SNAPHATTOP (to be Ordered Separately)

DESCRIPTION

The M48T212Y/V are self-contained devices that

include a real time clock (RTC), programmable

alarms, a watchdog timer, and two external chip

enable outputs which provide control of up to four

(two in parallel) external low-power static RAMs.

Access to all TIMEKEEPERfunctions and the

external RAM is the same as conventional byte-

wide SRAM. The16TIMEKEEPER Registersoffer

Century, Year, Month, Date, Day, Hour, Minute,

Second, Calibration, Alarm, Watchdog, and Flags.

Externally attached static RAMs are controlled by

the M48T212Y/V via the E1CON and E2CON sig-

nals (see Table 4).

The 44 pin 330mil SOIC provides sockets with

gold plated contacts at both ends for direct con-

nection to a separate SNAPHAT housing contain-

ing the battery and crystal. The unique design

allows the SNAPHAT battery package to be

mounted on top of the SOIC package after the

completion of the surface mount process.

Figure 1. Logic Diagram

AI03019

A0-A3

DQ0-DQ7

VCC

M48T212Y

M48T212V

VSS

E2CON

E1CON

RSTIN2

RSTIN1

RST

IRQ/FT

VOUT

WDI

VCCSW

SOH44 (MH)

SNAPHAT (SH)

Battery

M48T212Y, M48T212V

2/23

Insertion of the SNAPHAT housing after reflow

prevents potential battery and crystal damage due

to the high temperatures required for device sur-

face-mounting. The SNAPHAT housing is keyed

to prevent reverse insertion.

The SOIC and battery/crystal packages are

shipped separately in plastic anti-static tubesor in

Tape & Reel form. For the 44 lead SOIC, the bat-

tery/crystal package (i.e. SNAPHAT) part number

is ”M4TXX-BR12SH” (see Table 15).

Caution: Donot place theSNAPHAT battery/crys-

tal topin conductive foam, asthis will drain the lith-

ium button-cell battery.

Automatic backup and write protection for an ex-

ternal SRAM is provided through VOUT,E1

CON

and E2CON pins. (Users are urged to insure that

voltage specifications, for both the controller chip

and external SRAM chosen, are similar). The

SNAPHAT containing the lithium energy source

used to permanently power the real time clock is

also used to retain RAM data in the absence of

VCC power through the VOUT pin.

The chip enable outputs to RAM (E1CON and

E2CON) are controlled during power transients to

prevent data corruption. The date is automatically

adjusted for months with less than 31 days and

corrects for leapyears. The internal watchdog tim-

er provides programmable alarm windows.

The nine clock bytes (Fh - 9h and 1h) are not the

actual clock counters, they are memory locations

consisting of BiPORTTM read/write memory cells

within the static RAM array. Clock circuitry up-

dates the clock bytes with current information once

per second. The information can be accessed by

the user in the same manner asany other location

in the static memory array.

Byte 8h is the clock control register. This byte con-

trols user access to the clock information and also

stores the clock calibration setting. Byte 7h con-

tains the watchdog timer setting. The watchdog

timer can generate either a reset or an interrupt,

depending on the state of the Watchdog Steering

bit (WDS).Bytes 6h-2hinclude bits that,when pro-

grammed, provide for clock alarm functionality.

Alarms are activated when the register content

matches the month, date, hours, minutes, and

seconds of the clock registers. Byte 1h contains

century information. Byte 0h contains additional

flag information pertaining to the watchdog timer,

alarm and battery status.

Table 1. Signal Names

A0-A3 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

RSTIN1 Reset 1 Input

RSTIN2 Reset 2 Input

RST Reset Output (Open Drain)

WDI Watchdog Input

A Bank Select Input

E Chip Enable Input

EX External Chip Enable Input

G Output Enable Input

W Write Enable Input

E1CON RAM Chip Enable 1 Output

E2CON RAM Chip Enable 2 Output

IRQ/FT Int/Freq Test Output (Open Drain)

Vccsw VCC Switch Output

VOUT Supply Voltage Output

VCC Supply Voltage

VSS Ground

NC Not Connected internally

Figure 2. SOIC Connections

AI03020

VSS

E1CON

VOUT

VCC

M48T212Y

M48T212V

NC EX

VCCSW

WDI

E2CON DQ7

DQ5DQ0

DQ1 DQ3

DQ4

DQ6

RSTIN2

RST

RSTIN1

DQ2

IRQ/FT

3/23

M48T212Y, M48T212V

Table 2. Absolute Maximum Ratings (1)

Note: 1. Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to thedevice. This is a stress

rating only and functional operation of the device at these or any other conditions above those indicated in the operational section

of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect

reliability.

2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.

CAUTION: Do NOT wave solder SOIC to avoiddamaging SNAPHATsockets.

Table 3. Operating Modes (1)

Note: 1. X = VIH or VIL.

2. VSO = Battery Back-up Switchover Voltage. (See Tables 7A and 7B for details).

Table 4. Truth Table for SRAM Bank Select (1)

Note: 1. X = VIH or VIL.

2. VSO = Battery Back-up Switchover Voltage. (See Tables 7A and 7B for details).

Symbol Parameter Value Unit

TAAmbient Operating Temperature 0 to 70 °C

TSTG Storage Temperature (VCC Off, Oscillator Off) SNAPHAT

SOIC –40 to 85

–55 to 125 °C

TSLD (2) Lead Solder Temperature for 10 sec 260 °C

VIO Input or Output Voltages –0.3 to VCC +0.3 V

VCC Supply Voltage M48T212Y

M48T212V –0.3 to 7

–0.3 to 4.6 V

IOOutput Current 20 mA

PDPower Dissipation 1 W

Mode VCC E G W DQ7-DQ0 Power

Deselect

4.5V to 5.5V

3.0V to 3.6V

VIH X X High-Z Standby

Write VIL XVIL DIN Active

Read VIL VIL VIH DOUT Active

Read VIL VIH VIH High-Z Active

Deselect VSO to VPFD (min) (2) X X X High-Z CMOS Standby

Deselect ≤VSO (2) X X X High-Z Battery Back-Up

Mode VCC EX A E1CON E2CON Power

Select 4.5V to 5.5V

3.0V to 3.6V

Low Low Low High Active

Low High High Low Active

Deselect High X High High Standby

Deselect VSO to VPFD (min) (2) X X High High CMOS Standby

Deselect ≤VSO (2) X X High High Battery Back-Up

M48T212Y, M48T212V

4/23

Figure 3. Hardware Hookup

Note: 1. See description in Power Supply Decoupling and Undershoot Protection.

2. Traces connecting E1CON and E2CON to external SRAM should be as short as possible.

AI03046

A0-A3

DQ0-DQ7

VCC

WDI

RSTIN1

RSTIN2

VSS

VCC

A0-Axx

0.1µF

5V/3.3V

E2CON

RST

IRQ/FT

M48T212Y/V

CMOS

SRAM

VOUT

VCC

CMOS

SRAM

E1CON Note 2

MOTOROLA

MTD20P06HDL

VCCSW

1N5817 (1)

A0-A18

A0-Axx

Figure 4. AC Testing Load Circuit

Note: 1. DQ0-DQ7

2. E1CON and E2CON

AI03239

CL= 100pF or 5pF(1)

CL=30pF(2)

645Ω

DEVICE

UNDER

TEST

1.75V

CLincludes JIG capacitance

Table 5. AC Measurement Conditions

Note that Output Hi-Z is defined as the point where data

is no longer driven.

Input Rise and Fall Times ≤5ns

Input Pulse Voltages 0 to 3V

Input and Output Timing Ref. Voltages 1.5V

5/23

M48T212Y, M48T212V

Table 6. Capacitance (1)

(TA=25°C, f = 1 MHz)

Note: 1. Sampled only, not 100% tested.

2. Outputs deselected.

Table 7A. DC Characteristics for M48T212V

(TA= 0 to 70°C; VCC = 3V to 3.6V)

Note: 1. Outputs deselected.

2. RSTIN1 andRSTIN2 internally pulled-upto VCC through 100KΩresistor. WDI internally pulled-down to VSS through 100KΩresistor.

3. For IRQ/FT & RST pins (Open Drain).

4. Conditioned outputs (E1CON -E2

CON) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage cur-

rents will reduce battery life.

5. External SRAM must match TIMEKEEPER Controller chip VCC specification.

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN =0V 10 pF

COUT (2) Input/Output Capacitance VOUT =0V 10 pF

Symbol Parameter Test Condition Min Typ Max Unit

ILI (1,2) Input Leakage Current 0V ≤VIN ≤VCC ±1µA

ILO (1) Output Leakage Current 0V ≤VOUT ≤VCC ±1µA

ICC Supply Current Outputs open 4 10 mA

ICC1 Supply Current (Standby) TTL E=V

IH 3mA

CC2 Supply Current (Standby) CMOS E=V

CC –0.2 2mA

BAT Battery Current OSC ON 575 800 nA

Battery Current OSC OFF 100 nA

VIL Input Low Voltage –0.3 0.8 V

VIH Input High Voltage 2.0 VCC + 0.3 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

Output Low Voltage (open drain) (3) IOL = 10mA 0.4 V

VOH Output High Voltage IOH = –1.0mA 2.4 V

VOHB (4) VOH Battery Back-up IOUT2 = –1.0µA2.0 3.6 V

IOUT1 (5) VOUT Current (Active) VOUT1 >V

CC –0.3 70 mA

IOUT2 VOUT Current (Battery Back-up) VOUT2 >V

BAT –0.3 100 µA

VPFD Power-fail Deselect Voltage 2.7 2.9 3.0 V

VSO Battery Back-up Switchover Voltage VPFD –100mV V

VBAT Battery Voltage 3.0 V

M48T212Y, M48T212V

6/23

Table 7B. DC Characteristics for M48T212Y

(TA= 0 to 70°C; VCC = 4.5V to 5.5V)

Note: 1. Outputs deselected.

2. RSTIN1 andRSTIN2 internally pulled-upto VCC through 100KΩresistor. WDI internally pulled-down to VSS through 100KΩresistor.

3. For IRQ/FT & RST pins (Open Drain).

4. Conditioned outputs (E1CON -E2

CON) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage cur-

rents will reduce battery life.

5. External SRAM must match TIMEKEEPER Controller chip VCC specification.

Symbol Parameter Test Condition Min Typ Max Unit

ILI (1,2) Input Leakage Current 0V ≤VIN ≤VCC ±1µA

ILO (1) Output Leakage Current 0V ≤VOUT ≤VCC ±1µA

ICC Supply Current Outputs open 8 15 mA

ICC1 Supply Current (Standby) TTL E=V

IH 5mA

CC2 Supply Current (Standby) CMOS E=V

CC –0.2 3mA

BAT Battery Current OSC ON 575 800 nA

Battery Current OSC OFF 100 nA

VIL Input Low Voltage –0.3 0.8 V

VIH Input High Voltage 2.2 VCC + 0.3 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

Output Low Voltage (open drain) (3) IOL = 10mA 0.4 V

VOH Output High Voltage IOH = –1.0mA 2.4 V

VOHB (4) VOH Battery Back-up IOUT2 = –1.0µA 2.0 3.6 V

IOUT1 (5) VOUT Current (Active) VOUT1 >V

CC –0.3 100 mA

IOUT2 VOUT Current (Battery Back-up) VOUT2 >V

BAT –0.3 100 µA

VPFD Power-fail Deselect Voltage 4.2 4.35 4.5 V

VSO Battery Back-up Switchover Voltage 3.0 V

VBAT Battery Voltage 3.0 V

The M48T212Y/V also has its own Power-Fail De-

tect circuit. This control circuitry constantly moni-

tors the supply voltage for an out of tolerance

condition. When VCC is out of tolerance, the circuit

write protects the TIMEKEEPER register data and

external SRAM, providing data security in the

midst of unpredictable system operation. As VCC

falls, the control circuitry automatically switchesto

the battery, maintaining data and clock operation

until valid power is restored.

Address Decoding

The M48T212Y/V accommodates 4 address lines

(A3-A0) which allowaccess to thesixteen bytes of

the TIMEKEEPER clock registers. All TIMEKEEP-

ER registers reside in the controller chip itself. All

TIMEKEEPER registers are accessed by enabling

E (Chip Enable).

7/23

M48T212Y, M48T212V

Table 8. Power Down/Up AC Characteristics

(TA= 0 to 70°C)

Symbol Parameter Min Max Unit

tFVPFD (max) to VPFD (min) VCC Fall Time 300 µs

tFB VPFD (min) to VSS VCC FallTime M48T212Y 10 µs

M48T212V 150 µs

tRVPFD (min) to VPFD (max) VCC Rise Time 10 µs

tREC VPFD (max) to RST High 40 200 ms

tRB VSS to VPFD (min) VCC Rise Time 1µs

Figure 5. Power Down/Up AC Waveform

AI02638

VCC

INPUTS

RST

OUTPUTS

DON’T CARE

HIGH-Z

tFB

tRECtRB

VALID VALID

VPFD (max)

VPFD (min)

VSO

VALID VALID

VCCSW

M48T212Y, M48T212V

8/23

Figure 6. Chip Enable Control and Bank Select Timing

AI02639

tEXPD tAPD

tEXPD

E1CON

E2CON

Table 9. Chip Enable Control and Bank Select Characteristics

(TA= 0 to 70°C)

Symbol Parameter

M48T212Y M48T212V

Unit-70 -85

Min Max Min Max

tEXPD EX to E1CON or E2CON (Low or High) 10 15 ns

tAPD AtoE1

CON or E2CON (Low or High) 10 15 ns

9/23

M48T212Y, M48T212V

Figure 7. Read Cycle Timing: RTC Control Signals

AI02640

DQ7-DQ0

DATA OUT

VALID

ADDRESS

tAVAV

tELQV

tAVAV tAVAV

READ READ WRITE

DATA IN

VALID

DATA OUT

VALID

tAVQV tWHAXtAVWL

tELQX

tGLQV

tGHQZ

tWLWH

tAXQXtGLQX

Table 10. Read Mode Characteristics

(TA= 0 to 70°C)

Note: 1. CL= 5pF

Symbol Parameter

M48T212Y M48T212V

Unit-70 -85

Min Max Min Max

tAVAV Read Cycle Time 70 85 ns

tAVQV Address Valid to Output Valid 70 85 ns

tELQV Chip Enable Low to Output Valid 70 85 ns

tGLQV Output Enable Low to Output Valid 25 35 ns

tELQX (1) Chip Enable Low to Output Transition 5 5 ns

tGLQX (1) Output Enable Low to Output Transition 0 0 ns

tEHQZ(1) Chip Enable High to Output Hi-Z 20 25 ns

tGHQZ (1) Output Enable High to Output Hi-Z 20 25 ns

tAXQX Address Transition to Output Transition 5 5 ns

READ MODE

The M48T212Y/V executes a read cycle whenev-

er W (WriteEnable) is high and E (Chip Enable) is

low. The unique address specified by the address

inputs (A3-A0) defines which one of the on-chip

TIMEKEEPER registers is to be accessed. When

the address presented to the M48T212Y/V is in

the range of 0h-Fh, one of the on-board TIME-

KEEPER registers is accessed and valid data will

be available to the eight data output drivers within

tAVQV after the address input signal is stable, pro-

viding that the E and G access times are also sat-

isfied.If they are not, then data access must be

measured from the latter occurring signal (E or G)

and the limiting parameter is either tELQV for E or

tGLQV for G rather than the address access time.

When EX input is low, an external SRAM location

will be selected.

Note: Care should be taken to avoid takingboth E

and EX low simultaneously to avoid bus conten-

tion.

M48T212Y, M48T212V

10/23

Figure 8. Write Cycle Timing: RTC Control Signals

AI02641

DQ0-DQ7

DATA IN

VALID

ADDRESS

tAVAV

tAVEH

tAVAV tAVAV

WRITE WRITE READ

DATA OUT

VALID

DATA OUT

VALID

tAVWH

tAVQV

tWLWH

tWHDX

tWHAX

tWHQX tWLQZ

tDVWH

tGLQV

tEHQZ tDVEH

DATA IN

VALID

tELEH tEHAX

tAVEL

tEHDX

tAVWL

WRITE MODE

The M48T212Y/V is in the Write Mode whenever

W (Write Enable) and E (Chip Enable) are in a low

state afterthe address inputs are stable. The start

of a write is referenced from the latter occurring

falling edge of W orE. A write is terminated by the

earlier rising edge of W or E. The addresses must

be heldvalid throughout the cycle. E or W must re-

turn high for a minimum of tEHAX from Chip Enable

or tWHAX from Write Enable prior to the initiation of

another read or write cycle. Data-in must be valid

tDVWH priorto the end of write and remain valid for

tWHDX afterward.

G should be kept high during write cycles to avoid

bus contention; although, if the output bus has

been activatedby a low on Eand G alow onW will

disable the outputs tWLQZ after W falls.

When E is low during the write, one of the on-

board TIMEKEEPER registers will be selected and

data will be written into the device. When EXis low

(and E is high) an external SRAM location is se-

lected.

Note: Care should be taken to avoid takingboth E

and EX low simultaneously to avoid bus conten-

tion.

11/23

M48T212Y, M48T212V

Table 11. Write Mode AC Characteristics

(TA= 0 to 70°C)

Note: 1. CL= 5pF.

2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.

Symbol Parameter

M48T212Y M48T212V

Unit-70 -85

Min Max Min Max

tAVAV Write Cycle Time 70 85 ns

tAVWL Address Valid to Write Enable Low 0 0 ns

tAVEL Address Valid to Chip Enable Low 0 0 ns

tWLWH Write Enable Pulse Width 45 55 ns

tELEH Chip Enable Low to Chip Enable High 50 60 ns

tWHAX Write Enable High to Address Transition 0 0 ns

tEHAX Chip Enable High to Address Transition 0 0 ns

tDVWH Input Valid to Write Enable High 25 30 ns

tDVEH Input Valid to Chip Enable High 25 30 ns

tWHDX Write Enable High to Input Transition 0 0 ns

tEHDX Chip Enable High to Input Transition 0 0 ns

tWLQZ (1,2) Write Enable Low to Output High-Z 20 25 ns

tAVWH Address Valid to Write Enable High 55 65 ns

tAVEH Address Valid to Chip Enable High 55 65 ns

tWHQX (1,2) Write Enable High to Output Transition 5 5 ns

DATA RETENTION MODE

With valid VCC applied, the M48T212Y/V can be

accessed as described above with read or write

cycles. Should the supply voltage decay, the

M48T212Y/V will automatically deselect, write

protecting itself (and any external SRAM) when

VCC falls between VPFD (max) and VPFD (min).

This is accomplished by internally inhibiting ac-

cess to the clock registers via the E signal. At this

time, the Reset pin (RST) is driven active and will

remain active until VCC returns to nominal levels.

External RAM access is inhibited in a similar man-

ner by forcing E1CON and E2CON to a high level.

This level is within 0.2 volts of the VBAT.E1

CON

and E2CON will remain atthis level as long asVCC

remains at an out-of tolerance condition.

When VCC falls below the level of the battery

(VBAT), power input is switched from the VCC pin

to the SNAPHAT battery and the clock registers

and external SRAM are maintained from the at-

tached batterysupply. All outputs become high im-

pedance. The VOUT pin is capable of supplying

100µA of current to the attached memory with less

than 0.3V drop under this condition. On power up,

when VCC returns to anominal value, write protec-

tion continues for 200ms (max) by inhibiting

E1CON or E2CON.

The RST signal also remains active during this

time (see Figure 5).

Note: Most low power SRAMs on the market to-

day can be used with the M48T212Y/V TIME-

KEEPER Controller. There are, however some

criteria which should be used in making the final

choice of anSRAM to use.The SRAM mustbe de-

signed in a way where the chip enable input dis-

ables all other inputs to the SRAM. This allows

inputs to the M48T212Y/V andSRAMs to be Don’t

Care once VCC falls below VPFD(min). The SRAM

should also guarantee data retention down to

VCC = 2.0V. The chip enable access time must be

sufficient to meet the system needs with the chip

enable output propagation delays included.

M48T212Y, M48T212V

12/23

If the SRAM includes a second chip enable pin

(E2), this pin should be tied to VOUT.

If data retention lifetime is a critical parameter for

the system, it is important to review the data reten-

tion current specifications for the particular

SRAMs being evaluated. Most SRAMs specify a

data retention current at 3.0V. Manufacturers gen-

erally specify a typical condition for room temper-

ature along with a worst case condition (generally

at elevated temperatures). The system level re-

quirements will determine the choice of which val-

ue to use.

Thedata retentioncurrent value oftheSRAMs can

then be added tothe IBAT valueof the M48T212Y/

V to determine the total current requirements for

data retention. The available battery capacity for

the SNAPHAT of your choice can then be divided

by this current to determine theamount of data re-

tention available (see Table 15).

For afurther more detailed review oflifetime calcu-

lations, please see Application Note AN1012.

Figure 9. Alarm Interrupt Reset Waveforms

AI03021

A0-A3

ACTIVE FLAG BIT

ADDRESS 0h

IRQ/FT

HIGH-Z

1h Fh

Table 12. Alarm Repeat Modes

RPT5 RPT4 RPT3 RPT2 RPT1 Alarm Setting

1 1 1 1 1 Once per Second

1 1 1 1 0 Once per Minute

1 1 1 0 0 Once per Hour

1 1 0 0 0 Once per Day

1 0 0 0 0 Once per Month

0 0 0 0 0 Once per Year

13/23

M48T212Y, M48T212V

TIMEKEEPER REGISTERS

The M48T212Y/V offers 16 internal registers

which contain TIMEKEEPER, Alarm, Watchdog,

Flag, and Control data. These registers are mem-

ory locationswhich contain external (user accessi-

ble) and internal copies of the data (usually

referred to as BiPORTTM TIMEKEEPER cells).

The external copies are independent of internal

functions except that they are updated periodically

by the simultaneous transfer of the incremented

internal copy. TIMEKEEPER and Alarm Registers

store data in BCD. Control, Watchdog and Flags

Registers store data in Binary Format.

CLOCK OPERATIONS

Reading the Clock

Updates to the TIMEKEEPER registers should be

halted beforeclock data is read to prevent reading

data in transition. Because the BiPORT TIME-

KEEPER cellsin the RAM array are only data reg-

isters, and not the actual clock counters, updating

the registers can be halted without disturbing the

clock itself.

Updating is halted when a ‘1’ is written to the

READ bit, D6 in the Control Register (8h). As long

as a ‘1’ remains inthat position,updating is halted.

After a halt is issued, the registers reflect the

count; that is, the day, date, and time that were

current at the moment the halt command was is-

sued.

All of the TIMEKEEPER registers are updated si-

multaneously. A halt will not interrupt an update in

progress. Updating occurs 1 second after the

READ bit is reset to a ‘0’.

Setting the Clock

Bit D7 of the Control Register (8h) is the WRITE

bit. Setting the WRITE bit to a ‘1’, like the READ

bit, halts updates to the TIMEKEEPER registers.

The user can then load them with the correct day,

date, and time data in 24 hour BCD format (see

Table 13).

Resetting the WRITE bit to a ‘0’ then transfers the

values of all time registers (Fh-9h, 1h) to theactual

TIMEKEEPER counters andallows normal opera-

tion to resume. After the WRITE bit is reset, the

next clock update will occur one second later.

Note: Upon power-up following a power failure,

the READ bit will automatically be set to a ‘1’. This

will prevent the clock from updating the TIME-

KEEPER registers, and will allow the user to read

the exact time of the power-down event.

Resetting theREAD Bitto a ‘0’ will allow the clock

to update these registers with the current time.

The WRITE Bit will be reset to a ‘0’ upon power-

up.

Figure 10. Back-Up Mode Alarm Waveforms

AI03622

VCC

IRQ/FT

HIGH-Z

VPFD (max)

VPFD (min)

AFE bit/ABE bit

AF bit in Flags Register

HIGH-Z

tREC

M48T212Y, M48T212V

14/23

Stopping and Starting the Oscillator

The oscillator may be stopped at any time. If the

device is going to spend a significant amount of

time on the shelf, the oscillator can be turned off to

minimize current drain on the battery. The STOP

bit is located at Bit D7 within the Seconds Register

(9h). Setting it toa ‘1’ stopsthe oscillator. Whenre-

set toa ‘0’, theM48T212Y/V oscillator starts within

one second.

Note: It is not necessary to set the WRITE bit

when setting or resetting the FREQUENCY TEST

bit (FT) or the STOP bit (ST).

SETTING ALARM CLOCK

Address locations 6h-2h contain the alarm set-

tings. The alarm can be configured to go off at a

prescribed time on a specific month, date, hour,

minute, or second or repeat every year, month,

day, hour, minute, or second. It can also be pro-

grammed to go off while the M48T212Y/V isin the

battery back-upto serve asa system wake-upcall.

Bits RPT5-RPT1 putthe alarm in the repeat mode

of operation. Table 12 shows the possible config-

urations. Codesnot listed in the tabledefault to the

once per second mode to quickly alert the user of

an incorrect alarm setting.

Note: User must transition address (or toggle chip

enable) to see Flag bit change.

When the clock information matches the alarm

clock settings based on the match criteria defined

by RPT5-RPT1, the AF (Alarm Flag) is set.

If AFE (Alarm Flag Enable) is also set, the alarm

condition activates the IRQ/FT pin. To disable

alarm, write ’0’ to the Alarm Date registers and

RPT1-4. The IRQ/FT output is cleared by a read to

the Flags register as shown in Figure 9. A subse-

quent read of the Flags register will reset the

Alarm Flag (D6; Register 0h).

The IRQ/FT pin can also be activated in the bat-

tery back-up mode. The IRQ/FT will go low if an

alarm occurs and both ABE (Alarm in Battery

Back-up Mode Enable) and AFE are set. The ABE

and AFE bits are reset during power-up, therefore

an alarm generated during power-up will only set

AF. Theuser can read the Flag Register at system

boot-up to determine if an alarm was generated

while the M48T212Y/V was in the deselect mode

during power-up. Figure 10 illustrates the back-up

mode alarm timing.

WATCHDOG TIMER

The watchdog timer can be used to detect an out-

of-control microprocessor. The user programs the

watchdog timer by setting the desired amount of

time-out into the Watchdog Register, address 7h.

Bits BMB4-BMB0 store a binary multiplier and the

two lower order bits RB1-RB0 select the resolu-

tion, where00=1/16 second,01=1/4 second,10=1

second, and 11=4 seconds. The amount of time-

out is then determined to be the multiplication of

the five bit multiplier value with the resolution. (For

example: writing 00001110 in the Watchdog Reg-

ister = 3*1 or 3 seconds).

Note: Accuracy of timer is within ±the selected

resolution.

If theprocessor does not reset the timer within the

specified period, the M48T212Y/V sets the WDF

(Watchdog Flag) and generates a watchdog inter-

rupt or a microprocessor reset. WDF is reset by

reading the Flags Register (Address 0h).

The most significant bit of the Watchdog Register

is the Watchdog Steering Bit (WDS). When set to

a ‘0’, the watchdog will activate the IRQ/FT pin

when timed-out. When WDS is set to a ‘1’, the

watchdog will output a negative pulse on the RST

pin for 40 to 200 ms. The Watchdog register and

the FT bit will reset to a ‘0’ at the end of a Watch-

dog time-out when the WDS bit is set to a ‘1’.

The watchdog timer can be reset by two methods:

1. a transition (high-to-low or low-to-high) can be

applied to the Watchdog Input pin (WDI) or

2. the microprocessor can perform a write of the

Watchdog Register.

The time-out period then starts over. The WDI pin

should be tied to VSS if not used. The watchdog

will be reset on each transition (edge) seen by the

WDI pin. In the order to perform a software reset

of the watchdog timer, the original time-out period

can be written into the Watchdog Register, effec-

tively restarting the count-down cycle.

Should the watchdog timer time-out,and theWDS

bit is programmed to output an interrupt, a value of

00h needs to be written to the Watchdog Register

in order to clear the IRQ/FT pin. This will also dis-

able the watchdog function until it is again pro-

grammed correctly. A read of the Flags Register

will reset theWatchdog Flag (Bit D7; Register 0h).

The watchdog function is automatically disabled

upon power-down and the Watchdog Register is

cleared. If the watchdog function is set to output to

the IRQ/FT pin and the frequency test function is

activated, the watchdog or alarm function prevails

and the frequency test function is denied.

15/23

M48T212Y, M48T212V

VCC SWITCH OUTPUT

Vccsw output goes low when VOUT switches to

VCC turning on a customer supplied P-Channel

MOSFET (see Figure 3). The Motorola

MTD20P06HDL is recommended. This MOSFET

in turn connects VOUT to a separate supply when

the current requirement is greater than IOUT1 (see

Tables 7A and 7B). This output may also be used

simply to indicate the status of the internal battery

switchover comparator, which controls the source

(VCC or battery) of the VOUT output.

POWER-ON RESET

The M48T212Y/V continuously monitors VCC.

When VCC falls to the power fail detect trip point,

the RSTpulls low (open drain) andremains lowon

power-up for 40 to 200ms after VCC passes VPFD.

The RST pin is an open drain output and an appro-

priate pull-up resistor to VCC should be chosen to

control rise time.

Note: If the RST output is fed back into either of

the RSTIN inputs (for a microprocessor with a bi-

directional reset) then a 1kΩ(max) pull-up resistor

is recommended.

Reset Inputs (RSTIN1 & RSTIN2)

The M48T212Y/V provides two independent in-

puts which can generate an output reset. The du-

ration and function of these resets is identical to a

reset generated by a power cycle. Table 14 and

Figure 12 illustrate the AC reset characteristics of

this function. During the time RST is enabled

(tR1HRH &t

R2HRH), the ResetInputs are ignored.

Note: RSTIN1 and RSTIN2 are each internally

pulled up to VCC through a 100KΩresistor.

Table 13. TIMEKEEPER Register Map

Address Function/Range

BCD Format

D7 D6 D5 D4 D3 D2 D1 D0

Fh 10 Years Year Year 00-99

Eh 0 0 0 10M Month Month 01-12

Dh 0 0 10 Date Date: Day of Month Date 01-31

Ch 0 FT 0 0 0 Day of Week Day 01-7

Bh 0 0 10 Hours Hours (24 Hour Format) Hour 00-23

Ah 0 10 Minutes Minutes Min 00-59

9h ST 10 Seconds Seconds Sec 00-59

8h W R S Calibration Control

7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog

6h AFE 0 ABE Al 10M Alarm Month A Month 01-12

5h RPT4 RPT5 AI 10 Date Alarm Date A Date 01-31

4h RPT3 0 AI 10 Hour Alarm Hour A Hour 00-23

3h RPT2 Alarm 10 Minutes Alarm Minutes A Min 00-59

2h RPT1 Alarm 10 Seconds Alarm Seconds A Sec 00-59

1h 1000 Year 100 Year Century 00-99

0h WDF AF Y BL Y Y Y Y Flag

Keys: S = Sign Bit

FT = Frequency Test Bit

R = Read Bit

W = Write Bit

ST = Stop Bit

0 = Must be set to zero

BL = Battery Low Flag

BMB0-BMB4 = Watchdog Multiplier Bits

AFE = Alarm Flag Enable Flag

RB0-RB1 = Watchdog Resolution Bits

WDS = Watchdog Steering Bit

ABE = Alarm in Battery Back-Up Mode Enable Bit

RPT1-RPT5 = Alarm Repeat Mode Bits

WDF = Watchdog flag

AF = Alarm flag

Y = ‘1’ or ‘0’

M48T212Y, M48T212V

16/23

Calibrating the Clock

The M48T212Y/V is driven by a quartz controlled

oscillator with a nominal frequency of 32,768 Hz.

The devices are tested not to exceed ±35 PPM

(parts per million) oscillator frequency error at

25°C, which equates to about ±1.53 minutes per

month. Whenthe Calibration circuit is properly em-

ployed, accuracy improves to better than +1/–2

PPM at 25°C.

The oscillation rate of crystals changes with tem-

perature. The M48T212Y/V design employs peri-

odic counter correction. The calibration circuit

adds or subtracts counts from the oscillator divider

circuit at the divide by 256 stage, as shown in Fig-

ure 11. The number of times pulses which are

blanked (subtracted, negative calibration) or split

(added, positive calibration) depends upon the

value loaded into the five Calibration bits found in

the Control Register. Adding counts speeds the

clock up, subtracting counts slows the clock down.

The Calibration bits occupy the five lower order

bits (D4-D0) in the Control Register 8h. These bits

can be set to represent any value between 0 and

31 in binary form. Bit D5 is a Sign bit; ‘1’ indicates

positive calibration, ‘0’ indicates negative calibra-

tion. Calibration occurs within a 64 minute cycle.

The first 62 minutes in the cycle may, once per

minute, have one second either shortened by 128

or lengthened by 256 oscillator cycles.

If a binary ‘1’ is loaded into the register, only the

first 2 minutes in the 64 minute cycle will be modi-

fied; if a binary 6 is loaded, the first 12 will be af-

fected, and so on.

Therefore, each calibration step has the effect of

adding 512 or subtracting 256 oscillator cycles for

every 125,829,120 actual oscillator cycles, that is

+4.068 or –2.034 PPM of adjustment per calibra-

tion step in the calibration register. Assuming that

the oscillator is running at exactly 32,768 Hz, each

of the 31 increments in the Calibration byte would

Figure 11. Calibration Waveform

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

represent +10.7 or –5.35 seconds per month

which correspondsto a total range of+5.5 or –2.75

minutes per month.

Two methods are available for ascertaining how

much calibration a given M48T212Y/V may re-

quire. The first involves setting the clock, letting it

run for a month and comparing it to a known accu-

rate reference and recording deviation over a fixed

period of time. Calibration values, including the

number of seconds lost or gained in a given peri-

od, can be found in Application Note AN934:

TIMEKEEPER Calibration.

This allows the designer to give the end user the

ability to calibrate the clock as the environment re-

quires, even if the final product is packaged in a

non-user serviceable enclosure. The designer

could provide a simple utility that accesses the

Calibration byte.

The second approach is better suited to a manu-

facturing environment, and involves the use of the

IRQ/FT pin. The pinwill toggleat 512Hz, when the

Stop bit (ST, D7of 9h) is ‘0’,the Frequency Testbit

(FT, D6 of Ch) is ‘1’, the Alarm Flag Enable bit

(AFE, D7 of 6h) is ‘0’, and the Watchdog Steering

bit (WDS, D7 of 7h) is‘1’ or the Watchdog Register

(7h=0) is reset.

Any deviation from 512 Hz indicates the degree

and direction of oscillatorfrequency shift atthe test

temperature. For example, a reading of

512.010124 Hz would indicate a +20 PPM oscilla-

tor frequency error, requiring a –10 (WR001010)

to be loaded into the Calibration Byte for correc-

tion. Note that setting or changing the Calibration

Byte does not affect the Frequency testoutput fre-

quency.

The IRQ/FT pin is an open drain output which re-

quires a pull-up resistor to VCC for proper opera-

tion. A500-10kΩresistor is recommended in order

to control the rise time. The FT bit is cleared on

power-up.

17/23

M48T212Y, M48T212V

BATTERY LOW WARNING

The M48T212Y/V automatically performs battery

voltage monitoring upon power-up and at factory-

programmed time intervals of approximately 24

hours. The Battery Low (BL) bit, Bit D4 of Flags

is found to be less than approximately 2.5V. The

BL bit will remain asserted until completion of bat-

tery replacement and subsequent battery low

monitoring tests, either during the next power-up

sequence or the next scheduled 24-hour interval.

If a battery lowis generated during a power-up se-

quence, this indicates that the batteryis belowap-

proximately 2.5 volts and may not be able to

maintain data integrity in the SRAM. Data should

be considered suspect and verified as correct. A

fresh battery should be installed.

If a battery low indication is generated during the

24-hour interval check, this indicates that the bat-

tery is near end of life. However, data is not com-

promised due to the fact that a nominal Vcc is

supplied. In order to insure data integrity during

subsequent periods of battery back-up mode, the

battery should be replaced. The SNAPHAT bat-

tery/crystal top should be replaced with VCC pow-

ering the device to avoid data loss.

Note: this will cause the clock to lose time during

the time interval the battery crystal is removed.

The M48T212Y/V only monitors the battery when

a nominal Vcc is applied to the device. Thus appli-

cations which require extensive durations in the

battery back-up mode should be powered-up peri-

odically (at least once every few months) in order

for this technique to be beneficial.

Additionally, if a battery low is indicated, data in-

tegrity should be verified upon power-up via a

checksum or other technique.

Table 14. Reset AC Characteristics

(TA= 0 to 70°C; VCC = 3V to 3.6V or VCC = 4.5V to 5.5V)

Note: 1. Pulse width less than 50ns will result in no RESET(for noise immunity).

2. Pulse width less than 20ms will result in no RESET (for noise immunity).

3. CL= 5pF (see Figure 4).

Table 15. SNAPHAT Battery Table

Symbol Parameter Min Max Unit

tR1 (1) RSTIN1 Low to RSTIN1 High 200 ns

tR2 (2) RSTIN2 Low to RSTIN2 High 100 ms

tR1HRH (3) RSTIN1 High to RST High 40 200 ms

tR2HRH (3) RSTIN2 High to RST High 40 200 ms

Part Number Description Package

M4T28-BR12SH Lithium Battery (48mAh) SNAPHAT SH

M4T32-BR12SH Lithium Battery (120mAh) SNAPHAT SH

Figure 12. RSTIN1 & RSTIN2 Timing Waveforms

AI02642

RSTIN1

RST (1)

RSTIN2

tR1

tR1HRH

tR2

tR2HRH

M48T212Y, M48T212V

18/23

INITIAL POWER-ON DEFAULTS

Upon application of power to the device, the fol-

lowing register bits are set to a ‘0’ state: WDS,

BMB0-BMB4, RB0-RB1, AFE, ABE, W and FT.

(See Table 16)

POWER SUPPLY DECOUPLING

AND UNDERSHOOT PROTECTION

Note: ICC transients, including those produced by

output switching, can produce voltage fluctua-

tions, resulting in spikes on the VCC bus. These

transients canbe reduced if capacitors are used to

store energy, which stabilizes the VCC bus. The

energy stored in the bypass capacitors will be re-

leased as low going spikes are generated or ener-

gy will be absorbed when overshoots occur.

A ceramic bypass capacitor value of 0.1µF is rec-

ommended in order to providethe neededfiltering.

In addition to transients that are caused bynormal

SRAM operation,power cycling cangenerate neg-

ative voltage spikes on VCC that drive it to values

below VSS byas much as onevolt. These negative

spikes can cause data corruption in the SRAM

while in battery backup mode.

To protect from these voltage spikes, ST recom-

mends connecting a schottky diode from VCC to

Figure 13. Supply Voltage Protection

AI02169

VCC

0.1µF DEVICE

VCC

VSS

VSS (cathode connected to VCC, anode to VSS).

(Schottky diode 1N5817 is recommended for

through hole and MBRS120T3 is recommended

for surface mount).

Table 16. Default Values

Note: 1. WDS, BMB0-BMB4, RB0, RB1.

2. State of other control bits undefined.

3. State of other control bits remains unchanged.

4. Assuming these bits set to ‘1’ prior to power-down.

Condition W R FT AFE ABE WATCHDOG

Initial Power-up

(Battery Attach for SNAPHAT) (2) 00000 0

Subsequent Power-up / RESET (3) 00000 0

Power-down (4) 00011 0

19/23

M48T212Y, M48T212V

Table 17. Ordering Information Scheme

Note: 1. The SOIC package (SOH44) requires the battery package (SNAPHAT) which is ordered separately under the part number

“M4Txx-BR12SH1” in plastic tube or ”M4Txx-BR12SH1TR” in Tape & Reel form.

Caution: Donot place the SNAPHATbattery package ”M4Txx-BR12SH1” in conductive foam since willdrain the lithium button-cell battery.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-

vice, please contact the STMicroelectronics Sales Office nearest to you.

Example: M48T212Y -70 MH 1 TR

Device Type

M48T

Supply Voltage and Write Protect Voltage

212Y = VCC = 4.5V to 5.5V; VPFD = 4.2V to 4.5V

212V = VCC = 3.0V to 3.6V; VPFD = 2.7V to 3.0V

Speed

-70 = 70ns (for M48T212Y)

-85 = 85ns (for M48T212V)

Package

MH (1) = SOH44

Temperature Range

1=0to70°C

6=–40to85°C

Shipping Method for SOIC

blank = Tubes

TR = Tape & Reel

Table 18. Revision History

Date Revision Details

October 1999 First Issue

03/01/00 Document Layout changed

Default Values table added (Table 16)

04/21/00 From Preliminary Data to Data Sheet

M48T212Y, M48T212V

20/23

Table 19. SOH44 - 44 lead Plastic Small Outline, SNAPHAT, Package Mechanical Data

Symb mm inches

Typ Min Max Typ Min Max

A 3.05 0.120

A1 0.05 0.36 0.002 0.014

A2 2.34 2.69 0.092 0.106

B 0.36 0.46 0.014 0.018

C 0.15 0.32 0.006 0.012

D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e 0.81 – – 0.032 – –

eB 3.20 3.61 0.126 0.142

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050

α0°8°0°8°

N44 44

CP 0.10 0.004

Figure 14. SOH44 - 44 lead Plastic Small Outline, SNAPHAT, Package Outline

Drawing is not to scale.

SOH-A

LA1 α

21/23

M48T212Y, M48T212V

Table 20. M4T28-BR12SH SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mechanical Data

Symb mm inches

Typ Min Max Typ Min Max

A 9.78 0.385

A1 6.73 7.24 0.265 0.285

A2 6.48 6.99 0.255 0.275

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 14.22 14.99 0.560 0.590

eA 15.55 15.95 0.612 0.628

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

Figure 15. M4T28-BR12SH SNAPHAT Housing for 48 mAhBattery & Crystal, Package Outline

Drawing is not to scale.

SHTK-A

A1 A

M48T212Y, M48T212V

22/23

Table 21. M4T32-BR12SH SNAPHAT Housingfor 120 mAh Battery & Crystal, Package Mechanical Data

Symb mm inches

Typ Min Max Typ Min Max

A 10.54 0.415

A1 8.00 8.51 0.315 .0335

A2 7.24 8.00 0.285 0.315

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 17.27 18.03 0.680 .0710

eA 15.55 15.95 0.612 0.628

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

Figure 16. M4T32-BR12SH SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline

Drawing is not to scale.

SHTK-A

A1 A

23/23

M48T212Y, M48T212V

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