T89C51001CA-RLTIM - Atmel Corporation

Rev. D – 17-Dec-01

1. Features

• 80C51 core architecture:

– 256 bytes of on-chip RAM

– 1 Kbytes of on-chip ERAM

– 32 Kbytes of on-chip Flash memory

Data Retention: 10 years at 85°C

Read/Write cycle: 10k

– 2 Kbytes of on-chip Flash for Bootloader

– 2 Kbytes of on-chip EEPROM

Read/Write cycle: 100k

– 14-sources 4-level interrupts

– Three 16-bit timers/counters

– Full duplex UART compatible 80C51

– Maximum crystal frequency 40 MHz. In X2 mode, 20 MHz (CPU core, 40 MHz)

– Five ports: 32 + 2 digital I/O lines

– Five-channel 16-bit PCA with:

PWM (8-bit)

High-speed output

Timer and edge capture

– Double Data Pointer

– 21-bit watchdog timer (7 programmable bits)

• A 10-bit resolution analog to digital converter (ADC) with 8 multiplexed inputs

• Full CAN controller:

– Fully compliant with CAN rev2.0A and 2.0B

– Optimized structure for communication management (via SFR)

– 15 independent message objects:

Each message object programmable on transmission or reception

individual tag and mask filters up to 29-bit identifier/channel

8-byte cyclic data register (FIFO)/message object

16-bit status & control register/message object

16-bit Time-Stamping register/message object

CAN specification 2.0 part A or 2.0 part B programmable for each message

object

Access to message object control and data registers via SFR

Programmable reception buffer length up to 15 message objects

Priority management of reception of hits on several message objects at the

same time (Basic CAN Feature)

Priority management for transmission

message object overrun interrupt

– Supports

Time Triggered Communication

Autobaud and Listening mode

Programmable Automatic reply mode

– 1 Mbit/s maximum transfer rate at 8MHz* Crystal frequency in X2 mode.

– Readable error counters

– Programmable link to on-chip Timer for Time Stamping and Network

synchronization

– Independent baud rate prescaler

– Data, Remote, Error and overload frame handling

• On-chip emulation Logic (enhanced Hook system)

• Power saving modes:

– Idle mode

– Power down mode

• Power supply: 5V +/- 10% (or 3V** +/- 10%)

• Temperature range: Industrial (-40°to +85°C)

• Packages: TQFP44, PLCC44, CA-BGA64

Note: * At BRP = 1 sampling point will be fixed.

** Ask for availability

Enhanced 8-bit

MCU with CAN

controller and

Flash

T89C51CC01

2T89C51CC01 Rev. D – 17-Dec-01

2. Description The T89C51CC01 is the first member of the CANaryTM family of 8-bit microcontrollers

dedicated to CAN network applications.

In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.

Besides the full CAN controller T89C51CC01 provides 32 Kbytes of Flash memory

including In-System Programming (ISP), 2Kbytes Boot Flash Memory, 2 Kbytes

EEPROM and 1.2 Kbyte RAM.

Primary attention is paid to the reduction of the electro-magnetic emission of

T89C51CC01.

3. Block Diagram

Timer 0 INT

RAM

256x8

T1 RxD

TxD

PSEN

ALE

XTAL2

XTAL1

UART

CPU

Timer 1

INT1

Ctrl

INT0

C51

CORE

Port 0

Port 1 Port 2Port 3

Parallel I/O Ports & Ext. Bus

P1(1)

ERAM

1kx8

IB-bus

PCA

RESET

Watch

Dog

PCA

ECI

Vss

Vcc

(1): 8 analog Inputs / 8 Digital I/O

Timer2

T2EX

Port 4

P4(2)

Emul

Unit 10 bit

ADC

Flash

32kx

Boot

loader

2kx8

PROM

2kx8 CAN

CONTROLLER

TxDC

RxDC

(2): 2-Bit I/O Port

T89C51CC01

Rev. D – 17-Dec-01

4. Pin Configuration

PLCC44

P1.3 / AN3 / CEX0

P1.2 / AN2 / ECI

P1.1 / AN1 / T2EX

P1.0 / AN 0 / T2

VAREF

VAGND

RESET

VSS

VCC

XTAL1

XTAL2

P3.7 / RD

P4.0/ TxDC

P4.1 / RxDC

P2.7 / A15

P2.6 / A14

P2.5 / A13

P2.4 / A12

P2.3 / A11

P2.2 / A10

P2.1 / A9

P3.6 / WR

ALE

PSEN

P0.7 / AD7

P0.6 / AD6

P0.5 / AD5

P0.2 / AD2

P0.3 / AD3

P0.4 / AD4

P0.1 / AD1

P0.0 / AD0

P2.0 / A8

P1.4 / AN4 / CEX1

P1.5 / AN5 / CEX2

P1.6 / AN6 / CEX3

P1.7 / AN7 / CEX4

P3.0 / RxD

P3.1 / TxD

P3.2 / INT0

P3.3 / INT1

P3.4 / T0

P3.5 / T1

43 42 41 40 3944 38 37 36 35 34

12 13 17161514 201918 21 22

TQFP44

P1.4 / AN4 / CEX1

P1.5 / AN5 / CEX2

P1.6 / AN6 / CEX3

P1.7 / AN7 / CEX4

P3.0 / RxD

P3.1 / TxD

P3.2 / INT0

P3.3 / INT1

P3.4 / T0

P3.5 / T1

ALE

PSEN

P0.7 / AD7

P0.6 / AD6

P0.5 / AD5

P0.2 /AD2

P0.3 /AD3

P0.4 /AD4

P0.1 /AD1

P0.0 /AD0

P2.0 / A8

P1.3 / AN3 / CEX0

P1.2 / AN2 / ECI

P1.1 / AN1 / T2EX

P1.0 / AN 0 / T2

VAREF

VAGND

RESET

VSS

VCC

XTAL1

XTAL2

P3.7 / RD

P4.0 / TxDC

P4.1 / RxDC

P2.7 / A15

P2.6 / A14

P2.5 / A13

P2.4 / A12

P2.3 / A11

P2.2 / A10

P2.1 / A9

P3.6 / WR

4T89C51CC01 Rev. D – 17-Dec-01

P1.2/AN2P1.4/AN4 P1.0/AN0

P1.3/AN3P1.5/AN5 P1.1/AN1

P1.6/AN6 NCP1.7/AN7

EA NC NC NC RESET NC P0.6 P0.5

P0.7

PSENNC

VDD

VSS

VAGND

VAREF VDD

VSS XTAL1

NC ALE

XTAL2

P3.0

P3.2

P3.4 P3.5

P3.1

P3.3 NC

P4.0

P2.7P3.7

P3.6 P2.6

P4.1

NC NC

P2.4

P2.5 P2.3 P2.1 P2.0

P2.2 NC P0.0

NC P0.1 P0.3

NC P0.2 P0.4

CA-BGA64 Top View

21 345678

T89C51CC01

Rev. D – 17-Dec-01

Table 1. Pin Description

Pin Name Type Description

VSS GND Circuit ground.

VCC Supply Voltage.

VAREF Reference Voltage for ADC

VAGND Reference Ground for ADC

P0.0:7 I/O

Port 0:

Is an 8-bit open drain bi-directional I/O port. Port 0 pins that have 1’s written to them float, and in this state can be used as

high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program

and Data Memory. In this application it uses strong internal pull-ups when emitting 1’s.

Port 0 also outputs the code bytes during program validation. External pull-ups are required during program verification.

P1.0:7 I/O

Port 1:

Is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins can be used for digital input/output or as analog inputs for

the Analog Digital Converter (ADC). Port 1 pins that have 1’s written to them are pulled high by the internal pull-up transistors

and can be used as inputs in this state. As inputs, Port 1 pins that are being pulled low externally will be the source of current

(IIL, see section "Electrical Characteristic") because of the internal pull-ups. Port 1 pins are assigned to be used as analog

inputs via the ADCCF register (in this case the internal pull-ups are disconnected).

As a secondary digital function, port 1 contains the Timer 2 external trigger and clock input; the PCA external clock input and

the PCA module I/O.

P1.0 / AN0 / T2

Analog input channel 0,

External clock input for Timer/counter2.

P1.1 / AN1 / T2EX

Analog input channel 1,

Trigger input for Timer/counter2.

P1.2 / AN2 / ECI

Analog input channel 2,

PCA external clock input.

P1.3 / AN3 / CEX0

Analog input channel 3,

PCA module 0 Entry of input/PWM output.

P1.4 / AN4 / CEX1

Analog input channel 4,

PCA module 1 Entry of input/PWM output.

P1.5 / AN5 / CEX2

Analog input channel 5,

PCA module 2 Entry of input/PWM output.

P1.6 / AN6 / CEX3

Analog input channel 6,

PCA module 3 Entry of input/PWM output.

P1.7 / AN7 / CEX4

Analog input channel 7,

PCA module 4 Entry ot input/PWM output.

Port 1 receives the low-order address byte during EPROM programming and program verification.

It can drive CMOS inputs without external pull-ups.

P2.0:7 I/O

Port 2:

Is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1’s written to them are pulled high by the internal

pull-ups and can be used as inputs in this state. As inputs, Port 2 pins that are being pulled low externally will be a source of

current (IIL, see section "Electrical Characteristic") because of the internal pull-ups. Port 2 emits the high-order address byte

during accesses to the external Program Memory and during accesses to external Data Memory that uses 16-bit addresses

(MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1’s. During accesses to external Data

Memory that use 8 bit addresses (MOVX @Ri), Port 2 transmits the contents of the P2 special function register.

It also receives high-order addresses and control signals during program validation.

It can drive CMOS inputs without external pull-ups.

6T89C51CC01 Rev. D – 17-Dec-01

P3.0:7 I/O

Port 3:

Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled high by the internal

pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that are being pulled low externally will be a

source of current (IIL, see section "Electrical Characteristic") because of the internal pull-ups.

The output latch corresponding to a secondary function must be programmed to one for that function to operate (except for

TxD and WR). The secondary functions are assigned to the pins of port 3 as follows:

P3.0 / RxD:

Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface

P3.1 / TxD:

Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface

P3.2 / INT0:

External interrupt 0 input / timer 0 gate control input

P3.3 / INT1:

External interrupt 1 input / timer 1 gate control input

P3.4 / T0:

Timer0counterinput

P3.5 / T1:

Timer1counterinput

P3.6 / WR:

External Data Memory write strobe; latches the data byte from port 0 into the external data memory

P3.7 / RD:

External Data Memory read strobe; Enables the external data memory.

It can drive CMOS inputs without external pull-ups.

P4.0:1 I/O

Port 4:

Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s written to them are pulled high by the internal

pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are being pulled low externally will be a source of

current (IIL, on the datasheet) because of the internal pull-up transistor.

The output latch corresponding to a secondary function RxDC must be programmed to one for that function to operate. The

secondary functions are assigned to the two pins of port 4 as follows:

P4.0 / TxDC:

Transmitter output of CAN controller

P4.1 / RxDC:

Receiver input of CAN controller.

It can drive CMOS inputs without external pull-ups.

Pin Name Type Description

T89C51CC01

Rev. D – 17-Dec-01

4.2 I/O Configurations Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A

CPU "write to latch" signal initiates transfer of internal bus data into the type-D latch. A

CPU "read latch" signal transfers the latched Q output onto the internal bus. Similarly, a

"read pin" signal transfers the logical level of the Port pin. Some Port data instructions

activate the "read latch" signal while others activate the "read pin" signal. Latch instruc-

tions are referred to as Read-Modify-Write instructions. Each I/O line may be

independently programmed as input or output.

4.3 Port 1, Port 3 and

Port 4 Figure 1 shows the structure of Ports 1 and 3, which have internal pull-ups. An external

source can pull the pin low. Each Port pin can be configured either for general purpose

I/O or for its alternate input output function.

To use a pin for general purpose output, set or clear the corresponding bit in the Px reg-

ister (x=1,3 or 4). To use a pin for general purpose input, set the bit in the Px register.

This turns off the output FET drive.

To configure a pin for its alternate function, set the bit in the Px register. When the latch

is set, the "alternate output function" signal controls the output level (see Figure 1). The

operation of Ports 1, 3 and 4 is discussed further in "quasi-Bidirectional Port Operation"

paragraph.

RESET I/O Reset:

A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull-down

resistor to VSS permits power-on reset using only an external capacitor to VCC.

ALE O

ALE:

An Address Latch Enable output for latching the low byte of the address during accesses to the external memory. The ALE is

activated every 1/6 oscillator periods (1/3 in X2 mode) except during an external data memory access. When instructions are

executed from an internal FLASH (EA = 1), ALE generation can be disabled by the software.

PSEN O

PSEN:

The Program Store Enable output is a control signal that enables the external program memory of the bus during external

fetch operations. It is activated twice each machine cycle during fetches from the external program memory. However, when

executing from of the external program memory two activations ofPSEN are skipped during each access to the external Data

memory. The PSEN is not activated for internal fetches.

EA I EA:

When External Access is held at the high level, instructions are fetched from the internal FLASH when the program counter is

less then 8000H. When held at the low level,T89C51CC01 fetches all instructions from the external program memory.

XTAL1 I

XTAL1:

Input of the inverting oscillator amplifier and input of the internal clock generator circuits.

To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate

above a frequency of 16 MHz, a duty cycle of 50% should be maintained.

XTAL2 O XTAL2:

Output from the inverting oscillator amplifier.

Pin Name Type Description

8T89C51CC01 Rev. D – 17-Dec-01

Figure 1. Port 1, Port 3 and Port 4 Structure

Note: The internal pull-up can be disabled on P1 when analog function is selected.

4.4 Port 0 and Port2 Ports 0 and 2 are used for general-purpose I/O or as the external address/data bus. Port

0, shown in Figure 3, differs from the other Ports in not having internal pull-ups. Figure 3

shows the structure of Port 2. An external source can pull a Port 2 pin low.

To use a pin for general-purpose output, set or clear the corresponding bit in the Px reg-

ister (x=0 or 2). To use a pin for general purpose input, set the bit in the Px register to

turn off the output driver FET.

Figure 2. Port 0 Structure

Notes: 1. Port 0 is precluded from use as general purpose I/O Ports when used as

address/data bus drivers.

2. Port 0 internal strong pull-ups assist the logic-one output for memory bus cycles only.

Except for these bus cycles, the pull-up FET is off, Port 0 outputs are open-drain.

QP1.X

LATCH

INTERNAL

WRITE

LATCH

READ

LATCH P1.x

P3.X

P4.X

ALTERNATE

OUTPUT

FUNCTION

VCC

INTERNAL

PULL-UP (1)

ALTERNATE

INPUT

FUNCTION

P3.x

P4.x

BUS

P0.X

LATCH

INTERNAL

WRITE

LATCH

READ

LATCH

1P0.x (1)

ADDRESS LOW/

DATA CONTROL VDD

BUS

(2)

T89C51CC01

Rev. D – 17-Dec-01

Figure 3. Port 2 Structure

Notes: 1. Port 2 is precluded from use as general purpose I/O Ports when as address/data bus

drivers.

2. Port 2 internal strong pull-ups FET (P1 in FiGURE) assist the logic-one output for

memory bus cycle.

When Port 0 and Port 2 are used for an external memory cycle, an internal control signal

switches the output-driver input from the latch output to the internal address/data line.

4.5 Read-Modify-Write

Instructions Some instructions read the latch data rather than the pin data. The latch based instruc-

tions read the data, modify the data and then rewrite the latch. These are called "Read-

Modify-Write" instructions. Below is a complete list of these special instructions (see

Table 1). When the destination operand is a Port or a Port bit, these instructions read

the latch rather than the pin:

Table 1. Read-Modify-Write Instructions

P2.X

LATCH

INTERNAL

WRITE

LATCH

READ

LATCH

1P2.x (1)

ADDRESS HIGH/ CONTROL

BUS

VDD

INTERNAL

PULL-UP (2)

Instruction Description Example

ANL logical AND ANL P1, A

ORL logical OR ORL P2, A

XRL logical EX-OR XRL P3, A

JBC jump if bit = 1 and clear bit JBC P1.1, LABEL

CPL complement bit CPL P3.0

INC increment INC P2

DEC decrement DEC P2

DJNZ decrement and jump if not zero DJNZ P3, LABEL

MOV Px.y, C move carry bit to bit y of Port x MOV P1.5, C

CLR Px.y clear bit y of Port x CLR P2.4

SET Px.y set bit y of Port x SET P3.3

10 T89C51CC01 Rev. D – 17-Dec-01

It is not obvious the last three instructions in this list are Read-Modify-Write instructions.

These instructions read the port (all 8 bits), modify the specifically addressed bit and

write the new byte back to the latch. These Read-Modify-Write instructions are directed

to the latch rather than the pin in order to avoid possible misinterpretation of voltage

(and therefore, logic) levels at the pin. For example, a Port bit used to drive the base of

an external bipolar transistor can not rise above the transistor’s base-emitter junction

voltage (a value lower than VIL). With a logic one written to the bit, attempts by the CPU

to read the Port at the pin are misinterpreted as logic zero. A read of the latch rather

than the pins returns the correct logic-one value.

4.6 Quasi-Bidirectional

Port Operation Port 1, Port 2, Port 3 and Port 4 have fixed internal pull-ups and are referred to as

"quasi-bidirectional" Ports. When configured as an input, the pin impedance appears as

logic one and sources current in response to an external logic zero condition. Port 0 is a

"true bidirectional" pin. The pins float when configured as input. Resets write logic one to

all Port latches. If logical zero is subsequently written to a Port latch, it can be returned

to input conditions by a logical one written to the latch.

Note: Port latch values change near the end of Read-Modify-Write instruction cycles. Output

buffers (and therefore the pin state) update early in the instruction after Read-Modify-

Write instruction cycle.

Logical zero-to-one transitions in Port 1, Port 2, Port 3 and Port 4 use an additional pull-

up (p1) to aid this logic transition (see Figure 4.). This increases switch speed. This

extra pull-up sources 100 times normal internal circuit current during 2 oscillator clock

periods. The internal pull-ups are field-effect transistors rather than linear resistors. Pull-

ups consist of three p-channel FET (pFET) devices. A pFET is on when the gate senses

logical zero and off when the gate senses logical one. pFET #1 is turned on for two

oscillator periods immediately after a zero-to-one transition in the Port latch. A logical

one at the Port pin turns on pFET #3 (a weak pull-up) through the inverter. This inverter

and pFET pair form a latch to drive logical one. pFET #2 is a very weak pull-up switched

on whenever the associated nFET is switched off. This is traditional CMOS switch con-

vention. Current strengths are 1/10 that of pFET #3.

Figure 4. Internal Pull-Up Configurations

Note: Port 2 p1 assists the logic-one output for memory bus cycles.

READ PIN

INPUT DATA

P1.x

OUTPUT DATA

2 Osc. PERIODS

p1(1) p2 p3

VCCVCCVCC

P2.x

P3.x

P4.x

T89C51CC01

Rev. D – 17-Dec-01

5. SFR Mapping The Special Function Registers (SFRs) of the T89C51CC01 fall into the following

categories:

Table 2. C51CoreSFRs

Table 3. I/O Port SFRs

Table 4. Timers SFRs

MnemonicAddName 76543210

ACC E0h Accumulator

BF0hBRegister

PSW D0h Program Status Word CY AC F0 RS1 RS0 OV F1 P

SP 81h Stack Pointer

DPL 82h Data Pointer Low

byte

LSB of DPTR

DPH 83h Data Pointer High

byte

MSB of DPTR

MnemonicAddName 76543210

P0 80h Port 0

P1 90h Port 1

P2 A0h Port 2

P3 B0h Port 3

P4 C0h Port 4 (x2) ------

MnemonicAddName 76543210

TH0 8Ch Timer/Counter 0High

byte

TL0 8Ah Timer/Counter 0 Low

byte

TH1 8Dh Timer/Counter 1High

byte

TL1 8Bh Timer/Counter 1 Low

byte

TH2 CDh Timer/Counter 2High

byte

TL2 CCh Timer/Counter 2 Low

byte

TCON 88h Timer/Counter 0 and

1 control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

TMOD 89h Timer/Counter 0 and

1 Modes GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00

12 T89C51CC01 Rev. D – 17-Dec-01

Table 5. Serial I/O Port SFRs

Table 6. PCA SFRs

T2CON C8h Timer/Counter 2

control TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#

T2MOD C9h Timer/Counter 2

Mode ------T2OEDCEN

RCAP2H CBh Timer/Counter 2

Reload/Capture High

byte

RCAP2L CAh Timer/Counter 2

Reload/Capture Low

byte

WDTRST A6h WatchDog Timer

Reset

WDTPRG A7h WatchDog Timer

Program -----S2S1S0

MnemonicAddName 76543210

SCON 98h Serial Control FE/SM0 SM1 SM2 REN TB8 RB8 TI RI

SBUF 99h Serial Data Buffer

SADEN B9h Slave Address Mask

SADDR A9h Slave Address

MnemonicAddName 76543210

CCON D8h PCA Timer/Counter

Control CF CR - CCF4 CCF3 CCF2 CCF1 CCF0

CMOD D9h PCA Timer/Counter

Mode CIDL WDTE - - - CPS1 CPS0 ECF

CL E9h PCA Timer/Counter

Low byte

CH F9h PCA Timer/Counter

High byte

CCAPM0

CCAPM1

CCAPM2

CCAPM3

CCAPM4

DAh

DBh

DCh

DDh

DEh

PCA Timer/Counter

Mode 0

PCA Timer/Counter

Mode 1

PCA Timer/Counter

Mode 2

PCA Timer/Counter

Mode 3

PCA Timer/Counter

Mode 4

ECOM0

ECOM1

ECOM2

ECOM3

ECOM4

CAPP0

CAPP1

CAPP2

CAPP3

CAPP4

CAPN0

CAPN1

CAPN2

CAPN3

CAPN4

MAT0

MAT1

MAT2

MAT3

MAT4

TOG0

TOG1

TOG2

TOG3

TOG4

PWM0

PWM1

PWM2

PWM3

PWM4

ECCF0

ECCF1

ECCF2

ECCF3

ECCF4

T89C51CC01

Rev. D – 17-Dec-01

Table 7. Interrupt SFRs

Table 8. ADC SFRs

CCAP0H

CCAP1H

CCAP2H

CCAP3H

CCAP4H

FAh

FBh

FCh

FDh

FEh

PCA Compare

Capture Module 0 H

PCA Compare

Capture Module 1 H

PCA Compare

Capture Module 2 H

PCA Compare

Capture Module 3 H

PCA Compare

Capture Module 4 H

CCAP0H7

CCAP1H7

CCAP2H7

CCAP3H7

CCAP4H7

CCAP0H6

CCAP1H6

CCAP2H6

CCAP3H6

CCAP4H6

CCAP0H5

CCAP1H5

CCAP2H5

CCAP3H5

CCAP4H5

CCAP0H4

CCAP1H4

CCAP2H4

CCAP3H4

CCAP4H4

CCAP0H3

CCAP1H3

CCAP2H3

CCAP3H3

CCAP4H3

CCAP0H2

CCAP1H2

CCAP2H2

CCAP3H2

CCAP4H2

CCAP0H1

CCAP1H1

CCAP2H1

CCAP3H1

CCAP4H1

CCAP0H0

CCAP1H0

CCAP2H0

CCAP3H0

CCAP4H0

CCAP0L

CCAP1L

CCAP2L

CCAP3L

CCAP4L

EAh

EBh

ECh

EDh

EEh

PCA Compare

Capture Module 0 L

PCA Compare

Capture Module 1 L

PCA Compare

Capture Module 2 L

PCA Compare

Capture Module 3 L

PCA Compare

Capture Module 4 L

CCAP0L7

CCAP1L7

CCAP2L7

CCAP3L7

CCAP4L7

CCAP0L6

CCAP1L6

CCAP2L6

CCAP3L6

CCAP4L6

CCAP0L5

CCAP1L5

CCAP2L5

CCAP3L5

CCAP4L5

CCAP0L4

CCAP1L4

CCAP2L4

CCAP3L4

CCAP4L4

CCAP0L3

CCAP1L3

CCAP2L3

CCAP3L3

CCAP4L3

CCAP0L2

CCAP1L2

CCAP2L2

CCAP3L2

CCAP4L2

CCAP0L1

CCAP1L1

CCAP2L1

CCAP3L1

CCAP4L1

CCAP0L0

CCAP1L0

CCAP2L0

CCAP3L0

CCAP4L0

MnemonicAddName 76543210

IEN0 A8h Interrupt Enable

Control 0 EA EC ET2 ES ET1 EX1 ET0 EX0

IEN1 E8h Interrupt Enable

Control 1 -----ETIMEADCECAN

IPL0 B8h Interrupt Priority

Control Low 0 - PPC PT2 PS PT1 PX1 PT0 PX0

IPH0 B7h Interrupt Priority

Control High 0 - PPCH PT2H PSH PT1H PX1H PT0H PX0H

IPL1 F8h Interrupt Priority

Control Low 1 -----POVRLPADCLPCANL

IPH1 F7h Interrupt Priority

Control High1 -----POVRHPADCHPCANH

MnemonicAddName 76543210

ADCON F3h ADC Control - PSIDLE ADEN ADEOC ADSST SCH2 SCH1 SCH0

ADCF F6h ADC Configuration CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0

ADCLK F2h ADC Clock - - - PRS4 PRS3 PRS2 PRS1 PRS0

ADDH F5h ADC Data High byte ADAT9 ADAT8 ADAT7 ADAT6 ADAT5 ADAT4 ADAT3 ADAT2

ADDLF4hADCDataLowbyte------ADAT1ADAT0

14 T89C51CC01 Rev. D – 17-Dec-01

Table 9. CAN SFRs

MnemonicAddName 76543210

CANGCON ABh CAN General Control ABRQ OVRQ TTC SYNCTTC AUT-

BAUD TEST ENA GRES

CANGSTA AAh CAN General Status - OVFG - TBSY RBSY ENFG BOFF ERRP

CANGIT 9Bh CAN General

Interrupt CANIT - OVRTIM OVRBUF SERG CERG FERG AERG

CANBT1 B4h CAN Bit Timing 1 - BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 -

CANBT2 B5h CAN Bit Timing 2 - SJW1 SJW0 - PRS2 PRS1 PRS0 -

CANBT3 B6h CAN Bit Timing 3 - PHS22 PHS21 PHS20 PHS12 PHS11 PHS10 SMP

CANEN1 CEh CAN Enable Channel

byte 1 - ENCH14 ENCH13 ENCH12 ENCH11 ENCH10 ENCH9 ENCH8

CANEN2 CFh CAN Enable Channel

byte 2 ENCH7 ENCH6 ENCH5 ENCH4 ENCH3 ENCH2 ENCH1 ENCH0

CANGIE C1h CAN General

Interrupt Enable - - ENRX ENTX ENERCH ENBUF ENERG -

CANIE1 C2h CAN Interrupt Enable

Channel byte 1 - IECH14 IECH13 IECH12 IECH11 IECH10 IECH9 IECH8

CANIE2 C3h CAN Interrupt Enable

Channel byte 2 IECH7 IECH6 IECH5 IECH4 IECH3 IECH2 IECH1 IECH0

CANSIT1 BAh CAN Status Interrupt

Channel byte1 - SIT14 SIT13 SIT12 SIT11 SIT10 SIT9 SIT8

CANSIT2 BBh CAN Status Interrupt

Channel byte2 SIT7 SIT6 SIT5 SIT4 SIT3 SIT2 SIT1 SIT0

CANTCON A1h CAN Timer Control TPRESC

7TPRESC

6TPRESC

5TPRESC

4TPRESC

3TPRESC

2TPRESC

1TPRESC

CANTIMH ADh CAN Timer high CANTIM

15 CANTIM

14 CANTIM

13 CANTIM

12 CANTIM

11 CANTIM

10 CANTIM 9 CANTIM 8

CANTIML ACh CAN Timer low CANTIM 7 CANTIM 6 CANTIM 5 CANTIM 4 CANTIM 3 CANTIM 2 CANTIM 1 CANTIM 0

CANSTMH AFh CAN Timer Stamp

high TIMSTMP

15 TIMSTMP

14 TIMSTMP

13 TIMSTMP

12 TIMSTMP

11 TIMSTMP

10 TIMSTMP

9TIMSTMP

CANSTML AEh CAN Timer Stamp

low TIMSTMP

7TIMSTMP

6TIMSTMP

5TIMSTMP

4TIMSTMP

3TIMSTMP

2TIMSTMP

1TIMSTMP

CANTTCH A5h CAN Timer TTC high TIMTTC

15 TIMTTC

14 TIMTTC

13 TIMTTC

12 TIMTTC

11 TIMTTC

10 TIMTTC

9TIMTTC

CANTTCL A4h CAN Timer TTC low TIMTTC

7TIMTTC

6TIMTTC

5TIMTTC

4TIMTTC

3TIMTTC

2TIMTTC

1TIMTTC

CANTEC 9Ch CAN Transmit Error

Counter TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0

CANREC 9Dh CAN Receive Error

Counter REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0

CANPAGE B1h CAN Page CHNB3 CHNB2 CHNB1 CHNB0 AINC INDX2 INDX1 INDX0

CANSTCH B2h CAN Status Channel DLCW TXOK RXOK BERR SERR CERR FERR AERR

T89C51CC01

Rev. D – 17-Dec-01

Table 10. Other SFRs

CANCONH B3h CAN Control Channel CONCH1 CONCH0 RPLV IDE DLC3 DLC2 DLC1 DLC0

CANMSG A3h CAN Message Data MSG7 MSG6 MSG5 MSG4 MSG3 MSG2 MSG1 MSG0

CANIDT1 BCh

CAN Identifier Tag

byte 1(Part A)

CAN Identifier Tag

byte 1(PartB)

IDT10

IDT28 IDT9

IDT27 IDT8

IDT26 IDT7

IDT25 IDT6

IDT24 IDT5

IDT23 IDT4

IDT22 IDT3

IDT21

CANIDT2 BDh

CAN Identifier Tag

byte 2 (PartA)

CAN Identifier Tag

byte 2 (PartB)

IDT2

IDT20 IDT1

IDT19 IDT0

IDT18 -

IDT17 -

IDT16 -

IDT15 -

IDT14 -

IDT13

CANIDT3 BEh

CAN Identifier Tag

byte 3(PartA)

CAN Identifier Tag

byte 3(PartB)

IDT12 -

IDT11 -

IDT10 -

IDT9 -

IDT8 -

IDT7 -

IDT6 -

IDT5

CANIDT4 BFh

CAN Identifier Tag

byte 4(PartA)

CAN Identifier Tag

byte 4(PartB)

IDT4 -

IDT3 -

IDT2 -

IDT1 -

IDT0 RTRTAG -

RB1TAG RB0TAF

CANIDM1 C4h

CAN Identifier Mask

byte 1(PartA)

CAN Identifier Mask

byte 1(PartB)

IDMSK10

IDMSK28 IDMSK9

IDMSK27 IDMSK8

IDMSK26 IDMSK7

IDMSK25 IDMSK6

IDMSK24 IDMSK5

IDMSK23 IDMSK4

IDMSK22 IDMSK3

IDMSK21

CANIDM2 C5h

CAN Identifier Mask

byte 2(PartA)

CAN Identifier Mask

byte 2(PartB)

IDMSK2

IDMSK20 IDMSK1

IDMSK19 IDMSK0

IDMSK18 -

IDMSK17 -

IDMSK16 -

IDMSK15 -

IDMSK14 -

IDMSK13

CANIDM3 C6h

CAN Identifier Mask

byte 3(PartA)

CAN Identifier Mask

byte 3(PartB)

IDMSK12 -

IDMSK11 -

IDMSK10 -

IDMSK9 -

IDMSK8 -

IDMSK7 -

IDMSK6 -

IDMSK5

CANIDM4 C7h

CAN Identifier Mask

byte 4(PartA)

CAN Identifier Mask

byte 4(PartB)

IDMSK4 -

IDMSK3 -

IDMSK2 -

IDMSK1 -

IDMSK0 RTRMSK - IDEMSK

MnemonicAddName 76543210

PCON 87h Power Control SMOD1 SMOD0 - POF GF1 GF0 PD IDL

AUXR 8Eh Auxiliary Register 0 - - M0 - XRS1 XRS2 EXTRAM A0

AUXR1 A2h Auxiliary Register 1 - - ENBOOT - GF3 0 - DPS

CKCON 8Fh Clock Control CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2

FCON D1h FLASH Control FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY

EECON D2h EEPROM Contol EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY

16 T89C51CC01 Rev. D – 17-Dec-01

Table 11. SFR’s mapping

Reserved

Notes: 1. These registers are bit-addressable.

Sixteen addresses in the SFR space are both byte-addressable and bit-addressable.

The bit-addressable SFR’s are those whose address ends in 0 and 8. The bit

addresses, in this area, are 0x80 through to 0xFF.

0/8(1) 1/9 2/A 3/B 4/C 5/D 6/E 7/F

F8h IPL1

xxxx x000 CH

0000 0000 CCAP0H

0000 0000 CCAP1H

0000 0000 CCAP2H

0000 0000 CCAP3H

0000 0000 CCAP4H

0000 0000 FFh

F0h B

0000 0000 ADCLK

xxx0 0000 ADCON

x000 0000 ADDL

0000 0000 ADDH

0000 0000 ADCF

0000 0000 IPH1

xxxx x000 F7h

E8h IEN1

xxxx x000 CL

0000 0000 CCAP0L

0000 0000 CCAP1L

0000 0000 CCAP2L

0000 0000 CCAP3L

0000 0000 CCAP4L

0000 0000 EFh

E0h ACC

0000 0000 E7h

D8h CCON

0000 0000 CMOD

00xx x000 CCAPM0

x000 0000 CCAPM1

x000 0000 CCAPM2

x000 0000 CCAPM3

x000 0000 CCAPM4

x000 0000 DF

D0h PSW

0000 0000 FCON

0000 0000 EECON

xxxx xx00 D7h

C8h T2CON

0000 0000 T2MOD

xxxx xx00 RCAP2L

0000 0000 RCAP2H

0000 0000 TL2

0000 0000 TH2

0000 0000 CANEN1

x000 0000 CANEN2

0000 0000 CF

C0h P4

xxxx xx11 CANGIE

xx00 000x CANIE1

x000 0000 CANIE2

0000 0000 CANIDM1

xxxx xxxx CANIDM2

xxxx xxxx CANIDM3

xxxx xxxx CANIDM4

xxxx xxxx C7h

B8h IPL0

x000 0000 SADEN

0000 0000 CANSIT1

0000 0000 CANSIT2

0000 0000 CANIDT1

xxxx xxxx CANIDT2

xxxx xxxx CANIDT3

xxxx xxxx CANIDT4

xxxx xxxx BFh

B0h P3

1111 1111 CANPAGE

0000 0000 CANSTCH

xxxx xxxx CANCONCH

xxxx xxxx CANBT1

xxxx xxxx CANBT2

xxxx xxxx CANBT3

xxxx xxxx IPH0

x000 0000 B7h

A8h IEN0

0000 0000 SADDR

0000 0000 CANGSTA

x0x0 0000 CANGCON

0000 0x00 CANTIML

0000 0000 CANTIMH

0000 0000 CANSTMPL

0000 0000 CANSTMPH

0000 0000 AFh

A0h P2

1111 1111 CANTCON

0000 0000 AUXR1

xxxx 00x0 CANMSG

xxxx xxxx CANTTCL

0000 0000 CANTTCH

0000 0000 WDTRST

1111 1111 WDTPRG

xxxx x000 A7h

98h SCON

0000 0000 SBUF

0000 0000 CANGIT

0x00 0000 CANTEC

0000 0000 CANREC

0000 0000 9Fh

90h P1

1111 1111 97h

88h TCON

0000 0000 TMOD

0000 0000 TL0

0000 0000 TL1

0000 0000 TH0

0000 0000 TH1

0000 0000 AUXR

x00x 1100 CKCON

0000 0000 8Fh

80h P0

1111 1111 SP

0000 0111 DPL

0000 0000 DPH

0000 0000 PCON

00x1 0000 87h

0/8(1) 1/9 2/A 3/B 4/C 5/D 6/E 7/F

T89C51CC01

Rev. D – 17-Dec-01

6. Clock The T89C51CC01 core needs only 6 clock periods per machine cycle. This feature,

called”X2”, provides the following advantages:

• Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU

power.

• Saves power consumption while keeping the same CPU power (oscillator power

saving).

• Saves power consumption by dividing dynamic operating frequency by 2 in

operating and idle modes.

• Increases CPU power by 2 while keeping the same crystal frequency.

In order to keep the original C51 compatibility, a divider-by-2 is inserted between the

XTAL1 signal and the main clock input of the core (phase generator). This divider may

be disabled by the software.

An extra feature is available to start after Reset in the X2 mode. This feature can be

enabled by a bit X2B in the Hardware Security Byte. This bit is described in the section

"In-System Programming".

6.1 Description The X2 bit in the CKCON register (see Table 12) allows switching from 12 clock cycles

per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated

(STD mode).

Setting this bit activates the X2 feature (X2 mode) for the CPU Clock only (see Figure

5.).

The Timers 0, 1 and 2, Uart, PCA, watchdog or CAN switch in X2 mode only if the corre-

sponding bit is cleared in the CKCON register.

The clock for the whole circuit and peripheral is first divided by two before being used by

the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1

input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic

ratio between 40 to 60%. Figure 5. shows the clock generation block diagram. The X2

bit is validated on the XTAL1÷2 rising edge to avoid glitches when switching from the X2

to the STD mode. Figure 6 shows the mode switching waveforms.

18 T89C51CC01 Rev. D – 17-Dec-01

Figure 5. Clock CPU Generation Diagram

XTAL1

XTAL2

PCON.1

CPU Core

÷2

PERIPH

CLOCK

Clock

Peripheral Clock Symbol

CPU

CLOCK

CPU Core Clock Symbol

CKCON.0

X2B

Hardware byte

CANX2

CKCON.7 WDX2

CKCON.6 PCAX2

CKCON.5 SIX2

CKCON.4 T2X2

CKCON.3 T1X2

CKCON.2 T0X2

CKCON.1

IDL

PCON.0

÷2

CKCON.0

FCan Clock

FWd Clock

FPca Clock

FUart Clock

FT2 Clock

FT1 Clock

FT0 Clock

and ADC

On RESET

T89C51CC01

Rev. D – 17-Dec-01

Figure 6. Mode Switching Waveforms

Note: In order to prevent any incorrectoperation while operating in the X2 mode, users must be

aware that all peripherals using the clock frequency as a time reference (UART, timers...)

will have their time reference divided by two. For example a free running timer generating

an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART with a

4800 baud rate will have a 9600 baud rate.

6.2 Register Table 12. CKCON Register

CKCON (S:8Fh)

Clock Control Register

XTAL2

XTAL1

CPU

X2 bit

X2STD STD

76543210

CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2

Bit

Number Bit

Mnemonic Description

7CANX2

CAN clock (1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

6WDX2

Watchdog clock (1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

5 PCAX2 Programmable Counter Array clock (1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

4SIX2

Enhanced UART clock (MODE 0 and 2) (1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

3T2X2

Timer2 clock (1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

2T1X2

Timer1 clock (1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

20 T89C51CC01 Rev. D – 17-Dec-01

Notes: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit

has no effect.

Reset Value = 0000 0000b

1T0X2

Timer0 clock (1)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

0X2

CPU clock

Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all

the peripherals.

Set to select 6 clock periods per machine cycle (X2 mode) and to enable the

individual peripherals "X2"bits.

Bit

Number Bit

Mnemonic Description

T89C51CC01

Rev. D – 17-Dec-01

7. Data Memory The T89C51CC01 provides data memory access in two different spaces:

1. The internal space mapped in three separate segments:

• the lower 128 bytes RAM segment.

• the upper 128 bytes RAM segment.

• the expanded 1024 bytes RAM segment (ERAM).

2. The external space.

A fourth internal segment is available but dedicated to Special Function Registers,

SFRs, (addresses 80h to FFh) accessible by direct addressing mode.

Figure 2 shows the internal and external data memory spaces organization.

Figure 1. Internal memory - RAM

Figure 2. Internal and External Data Memory Organization ERAM-XRAM

Upper

128 bytes

Internal RAM

Lower

128 bytes

Internal RAM

Special

Function

Registers

80h 80h

00h

FFh FFh

direct addressing

addressing

7Fh

direct or indirect

indirect addressing

256upto1024bytes

00h

64 Kbytes

External XRAM

0000h

FFFFh

Internal ERAM

EXTRAM= 0 EXTRAM= 1

FFh or 3FFh

Internal External

22 T89C51CC01 Rev. D – 17-Dec-01

7.1 Internal Space

7.1.1 Lower 128 Bytes RAM The lower 128 bytes of RAM (see Figure 2) are accessible from address 00h to 7Fh

using direct or indirect addressing modes. The lowest 32 bytes are grouped into 4 banks

of 8 registers (R0 to R7). Two bits RS0 and RS1 in PSW register (see Figure 3) select

which bank is in use according to Table 1. This allows more efficient use of code space,

since register instructions are shorter than instructions that use direct addressing, and

can be used for context switching in interrupt service routines.

Table 1. Register Bank Selection

The next 16 bytes above the register banks form a block of bit-addressable memory

space. The C51 instruction set includes a wide selection of single-bit instructions, and

the 128 bits in this area can be directly addressed by these instructions. The bit

addresses in this area are 00h to 7Fh.

Figure 3. Lower 128 bytes Internal RAM Organization

7.1.2 Upper 128 Bytes RAM The upper 128 bytes of RAM are accessible from address 80h to FFh using only indirect

addressing mode.

7.1.3 Expanded RAM The on-chip 1024 bytes of expanded RAM (ERAM) are accessible from address 0000h

to 03FFh using indirect addressing mode through MOVX instructions. In this address

range, the bit EXTRAM in AUXR register is used to select the ERAM (default) or the

XRAM. As shown in Figure 2 when EXTRAM= 0, the ERAM is selected and when

EXTRAM= 1, the XRAM is selected.

The size of ERAM can be configured by XRS1-0 bit in AUXR register (default size is

1024 bytes).

Caution:

Note: Lower 128 bytes RAM, Upper 128 bytes RAM, and expanded RAM are made of volatile

memory cells. This means that the RAM content is indeterminate after power-up and

must then be initialized properly.

RS1 RS0 Description

0 0 Register bank 0 from 00h to 07h

0 1 Register bank 0 from 08h to 0Fh

1 0 Register bank 0 from 10h to 17h

1 1 Register bank 0 from 18h to 1Fh

Bit-Addressable Space

4 Banks of

8Registers

R0-R7

30h

7Fh

(Bit Addresses 0-7Fh)

20h

2Fh

18h 1Fh

10h 17h

08h 0Fh

00h 07h

T89C51CC01

Rev. D – 17-Dec-01

7.2 External Space

7.2.1 Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as

the bus control signals (RD#, WR#, and ALE).

Figure 4 shows the structure of the external address bus. P0 carries address A7:0 while

P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 2 describes

the external memory interface signals.

Figure 4. External Data Memory Interface Structure

Table 2. External Data Memory Interface Signals

7.2.2 External Bus Cycles This section describes the bus cycles the T89C51CC01 executes to read (see Figure 5),

and write data (see Figure 6) in the external data memory.

External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator

clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor-

mation on X2 mode.

Slow peripherals can be accessed by stretching the read and write cycles. This is done

using the M0 bit in AUXR register. Setting this bit changes the width of the RD# and

WR# signals from 3 to 15 CPU clock periods.

RAM

PERIPHERAL

T89C51CC01

P0 AD7:0

A15:8

A7:0

A15:8

D7:0

A7:0

ALE

OERD#

WR#

Latch

Signal

Name Type Description Alternative

Function

A15:8 O Address Lines

Upper address lines for the external bus. P2.7:0

AD7:0 I/O Address/Data Lines

Multiplexed lower address lines and data for the external

memory. P0.7:0

ALE O Address Latch Enable

ALE signals indicates that valid address information are available

on lines AD7:0. -

RD# O Read

Read signal output to external data memory. P3.7

WR# O Write

Write signal output to external memory. P3.6

24 T89C51CC01 Rev. D – 17-Dec-01

For simplicity, the accompanying figures depict the bus cycle waveforms in idealized

form and do not provide precise timing information. For bus cycle timing parameters

refer to the Section “AC Characteristics” of the T89C51CC01 datasheet.

Figure 5. External Data Read Waveforms

Notes: 1. RD# signal may be stretched using M0 bit in AUXR register.

2. When executing MOVX @Ri instruction, P2 outputs SFR content.

Figure 6. External Data Write Waveforms

Notes: 1. WR# signal may be stretched using M0 bit in AUXR register.

2. When executing MOVX @Ri instruction, P2 outputs SFR content.

7.3 Dual Data Pointer

7.3.1 Description The T89C51CC01 implements a second data pointer for speeding up code execution

and reducing code size in case of intensive usage of external memory accesses.

DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR

addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1

pointer 1 (see Figure 7).

ALE

RD#1

DPL or Ri D7:0

DPH or P22

CPU Clock

ALE

WR#1

DPL or Ri D7:0

CPU Clock

DPH or P22

T89C51CC01

Rev. D – 17-Dec-01

Figure 7. Dual Data Pointer Implementation

7.3.2 Application Software can take advantage of the additional data pointers to both increase speed and

reduce code size, for example, block operations (copy, compare…) are well served by

using one data pointer as a “source” pointer and the other one as a “destination” pointer.

Hereafter is an example of block move implementation using the two pointers and coded

in assembler. The latest C compiler takes also advantage of this feature by providing

enhanced algorithm libraries.

The INC instruction is a short (2 bytes) and fast (6 machine cycle) way to manipulate the

DPS bit in the AUXR1 register. However, note that the INC instruction does not directly

force the DPS bit to a particular state, but simply toggles it. In simple routines, such as

the block move example, only the fact that DPS is toggled in the proper sequence mat-

ters, not its actual value. In other words, the block move routine works the same whether

DPS is '0' or '1' on entry.

; ASCII block move using dual data pointers

; Modifies DPTR0, DPTR1, A and PSW

; Ends when encountering NULL character

; Note: DPS exits opposite to the entry state unless an extra INC AUXR1 is

added

AUXR1EQU0A2h

move:movDPTR,#SOURCE ; address of SOURCE

incAUXR1 ; switch data pointers

movDPTR,#DEST ; address of DEST

mv_loop:incAUXR1; switch data pointers

movxA,@DPTR; get a byte from SOURCE

incDPTR; increment SOURCE address

incAUXR1; switch data pointers

movx@DPTR,A; write the byte to DEST

incDPTR; increment DEST address

jnzmv_loop; check for NULL terminator

end_move:

DPH0

DPH1

DPL0

DPS AUXR1.0

DPH

DPL

DPL1

DPTR

DPTR0

DPTR1

26 T89C51CC01 Rev. D – 17-Dec-01

7.4 Registers Table 3. PSW Register

PSW (S:8Eh)

Program Status Word Register.

Reset Value= 0000 0000b

Table 4. AUXR Register

AUXR (S:8Eh)

Auxiliary Register

76543210

CY AC F0 RS1 RS0 OV F1 P

Bit

Number Bit

Mnemonic Description

7CY

Carry Flag

Carry out from bit 1 of ALU operands.

6AC

Auxiliary Carry Flag

Carry out from bit 1 of addition operands.

5F0User Definable Flag 0.

4-3 RS1:0 Register Bank Select Bits

Refer to Table 1 for bits description.

2OV

Overflow Flag

Overflow set by arithmetic operations.

1F1User Definable Flag 1.

Parity Bit

Set when ACC contains an odd number of 1’s.

Cleared when ACC contains an even number of 1’s.

76543210

- - M0 - XRS1 XRS0 EXTRAM A0

Bit

Number Bit

Mnemonic Description

7-6 - Reserved

The value read from these bits are indeterminate. Do not set this bit.

5M0

Stretch MOVX control:

the RD/ and the WR/ pulse length is increased according to the value of M0.

M0 Pulse length in clock period

130

Reserved

The value read from this bit is indeterminate. Do not set this bit.

T89C51CC01

Rev. D – 17-Dec-01

Reset Value= X00X 1100b

Not bit addressable

Table 5. AUXR1 Register

AUXR1 (S:A2h)

Auxiliary Control Register 1.

Reset Value= XXXX 00X0b

3-2 XRS1-0

ERAM size:

Accessible size of the ERAM

XRS1:0 ERAM size

0 0 256 bytes

0 1 512 bytes

1 0 768 bytes

1 1 1024 bytes (default)

1 EXTRAM

Internal/External RAM (00h - FFh)

access using MOVX @ Ri / @ DPTR

0 - Internal ERAM access using MOVX @ Ri / @ DPTR.

1 - External data memory access.

0A0

Disable/Enable ALE)

0 - ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2

mode is used)

1-ALEisactiveonlyduringaMOVXorMOVCinstruction.

Bit

Number Bit

Mnemonic Description

76543210

- - ENBOOT - GF3 0 - DPS

Bit

Number Bit

Mnemonic Description

7-6 - Reserved

The value read from these bits is indeterminate. Do not set these bits.

5 ENBOOT Enable Boot Flash

Set this bit for map the boot flash between F800h -FFFFh

Clear this bit for disable boot flash.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3GF3General Purpose Flag 3.

Always Zero

This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3

flag.

1-Reserved for Data Pointer Extension.

0DPS

Data Pointer Select Bit

Set to select second dual data pointer: DPTR1.

Clear to select first dual data pointer: DPTR0.

28 T89C51CC01 Rev. D – 17-Dec-01

8. EEPROM Data

Memory The 2k byte on-chip EEPROM memory block is located at addresses 0000h to 07FFh of

the XRAM/ERAM memory space and is selected by setting control bits in the EECON

A physical write in the EEPROM memory is done in two steps: write data in the column

latches and transfer of all data latches into an EEPROM memory row (programming).

The number of data written on the page may vary from 1 up to 128 bytes (the page

size). When programming, only the data written in the column latch is programmed and

a ninth bit is used to obtain this feature. This provides the capability to program the

whole memory by bytes, by page or by a number of bytes in a page. Indeed, each ninth

bit is set when the writing the corresponding byte in a row and all these ninth bits are

reset after the writing of the complete EEPROM row.

8.1 Write Data in the

column latches Data is written by byte to the column latches as for an external RAM memory. Out of the

11 address bits of the data pointer, the 4 MSBs are used for page selection (row) and 7

are used for byte selection. Between two EEPROM programming sessions, all the

addresses in the column latches must stay on the same page, meaning that the 4 MSB

must no be changed.

The following procedure is used to write to the column latches:

• Save and disable interrupt.

• Set bit EEE of EECON register

• Load DPTR with the address to write

• Store A register with the data to be written

• Execute a MOVX @DPTR, A

• If needed loop the three last instructions until the end of a 128 bytes page

• Restore interrupt.

Note: The last page address used when loading the column latch is the one used to select the

page programming address.

8.2 Programming The EEPROM programming consists on the following actions:

• writing one or more bytes of one page in the column latches. Normally, all bytes

must belong to the same page; if not, the first page address will be latched and the

others discarded.

• launching programming by writing the control sequence (50h followed by A0h) to the

EECON register.

• EEBUSY flag in EECON is then set by hardware to indicate that programming is in

progress and that the EEPROM segment is not available for reading.

• The end of programming is indicated by a hardware clear of the EEBUSY flag.

Note: The sequence 5xh and Axh must be executed without instructions between then other-

wise the programming is aborted.

8.3 Read Data The following procedure is used to read the data stored in the EEPROM memory:

• Save and disable interrupt

• Set bit EEE of EECON register

• Load DPTR with the address to read

• Execute a MOVX A, @DPTR

• Restore interrupt

T89C51CC01

Rev. D – 17-Dec-01

8.4 Examples ;*F*************************************************************************

;* NAME: api_rd_eeprom_byte

;* DPTR contain address to read.

;* Acc contain the reading value

;* NOTE: before execute this function, be sure the EEPROM is not BUSY

;***************************************************************************

api_rd_eeprom_byte:

MOV EECON, #02h; map EEPROM in XRAM space

MOVX A, @DPTR

MOV EECON, #00h; unmap EEPROM

ret

;*F*************************************************************************

;* NAME: api_ld_eeprom_cl

;* DPTR contain address to load

;* Acc contain value to load

;* NOTE: in this example we load only 1 byte, but it is possible upto

;* 128 bytes.

;* before execute this function, be sure the EEPROM is not BUSY

;***************************************************************************

api_ld_eeprom_cl:

MOV EECON, #02h ; map EEPROM in XRAM space

MOVX @DPTR, A

MOVEECON, #00h; unmap EEPROM

ret

;*F*************************************************************************

;* NAME: api_wr_eeprom

;* NOTE: before execute this function, be sure the EEPROM is not BUSY

;***************************************************************************

api_wr_eeprom:

MOV EECON, #050h

MOV EECON, #0A0h

ret

30 T89C51CC01 Rev. D – 17-Dec-01

8.5 Registers Table 6. EECON Register

EECON (S:0D2h)

EEPROM Control Register

Reset Value= XXXX XX00b

Not bit addressable

76543210

EEPL3 EEPL2 EEPL1 EEPL0 - - EEE EEBUSY

Bit Number Bit

Mnemonic Description

7-4 EEPL3-0 Programming Launch command bits

Write 5Xh followed by AXh to EEPL to launch the programming.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

1 EEE

Enable EEPROM Space bit

SettomaptheEEPROMspaceduringMOVXinstructions(Writeinthecolumn

latches)

Clear to map the XRAM space during MOVX.

0 EEBUSY

Programming Busy flag

Set by hardware when programming is in progress.

Cleared by hardware when programming is done.

Can not be set or cleared by software.

T89C51CC01

Rev. D – 17-Dec-01

9. Program/Code

Memory The T89C51CC01 implement 32 Kbytes of on-chip program/code memory. Figure 8

shows the partitioning of internal and external program/code memory spaces depending

on the product.

The FLASH memory increases EPROM and ROM functionality by in-circuit electrical

erasure and programming. Thanks to the internal charge pump, the high voltage needed

for programming or erasing FLASH cells is generated on-chip using the standard VDD

voltage. Thus, the FLASH Memory can be programmed using only one voltage and

allows In-System Programming commonly known as ISP. Hardware programming mode

is also available using specific programming tool.

Figure 8. Program/Code Memory Organization

Note: If the program executes exclusively from on-chip code memory (not from external mem-

ory), beware of executing code from the upper byte of on-chip memory (7FFFh) and

thereby disrupt I/O Ports 0 and 2 due to external prefetch. Fetching code constant from

this location does not affect Ports 0 and 2.

9.1 External Code

Memory Access

9.1.1 Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as

the bus control signals (PSEN#, and ALE).

Figure 9 shows the structure of the external address bus. P0 carries address A7:0 while

P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 7 describes

the external memory interface signals.

0000h

32 Kbytes

7FFFh

internal

0000h

7FFFh

FFFFh

8000h

FLASH

32 Kbytes

external

memory

32 Kbytes

external

memory

EA = 0

EA = 1

32 T89C51CC01 Rev. D – 17-Dec-01

Figure 9. External Code Memory Interface Structure

Table 7. External Code Memory Interface Signals

9.1.2 External Bus Cycles This section describes the bus cycles the T89C51CC01 executes to fetch code (see

Figure 10) in the external program/code memory.

External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator

clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor-

mation on X2 mode see section “Clock “.

For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized

form and do not provide precise timing information.

For bus cycling parameters refer to the section "AC-DC parameters".

FLASH

EPROM

T89C51CC01

P0 AD7:0

A15:8

A7:0

A15:8

D7:0

A7:0

ALE Latch

OEPSEN#

Signal

Name Type Description Alternate

Function

A15:8 O Address Lines

Upper address lines for the external bus. P2.7:0

AD7:0 I/O Address/Data Lines

Multiplexed lower address lines and data for the external memory. P0.7:0

ALE O Address Latch Enable

ALE signals indicates that valid address information are available on lines

AD7:0. -

PSEN# O Program Store Enable Output

This signal is active low during external code fetch or external code read

(MOVC instruction). -

T89C51CC01

Rev. D – 17-Dec-01

Figure 10. External Code Fetch Waveforms

9.2 FLASH Memory

Architecture T89C51CC01 features two on-chip flash memories:

• Flash memory FM0:

containing 32 Kbytes of program memory (user space) organized into 128 byte

pages,

• Flash memory FM1:

2 Kbytes for boot loader and Application Programming Interfaces (API).

The FM0 can be program by both parallel programming and Serial In-System Program-

ming (ISP) whereas FM1 supports only parallel programming by programmers. The ISP

mode is detailed in the "In-System Programming" section.

All Read/Write access operations on FLASH Memory by user application are managed

by a set of API described in the "In-System Programming" section.

Figure 11. Flash memory architecture

ALE

PSEN#

PCL

PCHPCH

PCLD7:0 D7:0

PCH

D7:0

CPU Clock

7FFFh

32 Kbytes

Flash memory

FM0

0000h

Hardware Security (1 byte)

Column Latches (128 bytes)

user space

Extra Row (128 bytes)

2Kbytes

Flash memory

FM1

boot space

FFFFh

F800h

FM1 mapped between FFFFh and

F800h when bit ENBOOT is set in

AUXR1 register

34 T89C51CC01 Rev. D – 17-Dec-01

9.2.1 FM0 Memory

Architecture The flash memory is made up of 4 blocks (see Figure 11):

3. The memory array (user space) 32 Kbytes

4. The Extra Row

5. The Hardware security bits

6. The column latch registers

User Space This space is composed of a 32 Kbytes FLASH memory organized in 256 pages of 128

bytes. It contains the user’s application code.

Extra Row (XRow) This row is a part of FM0 and has a size of 128 bytes. The extra row may contain infor-

mation for boot loader usage.

Hardware security Byte The Hardware security Byte space is a part of FM0 and has a size of 1 byte.

The 4 MSB can be read/written by software, the 4 LSB can only be read by software and

written by hardware in parallel mode.

Column latches The column latches, also part of FM0, have a size of full page (128 bytes).

The column latches are the entrance buffers of the three previous memory locations

(user array, XROW and Hardware security byte).

9.2.2 Cross Flash Memory

Access Description The FM0 memory can be program only from FM1. Programming FM0 from FM0 or from

external memory is impossible.

The FM1 memory can be program only by parallel programming.

The Table 8 show all software flash access allowed.

Table 8. Cross Flash Memory Access

Code executing from

Action FM0

(user Flash) FM1

(boot Flash)

FM0

(user Flash)

Read ok -

Load column latch ok -

Write - -

FM1

(boot flash)

Read ok ok

Load column latch ok -

Write ok -

External

memory

EA = 0

Read - -

Load column latch - -

Write - -

T89C51CC01

Rev. D – 17-Dec-01

9.3 Overview of FM0

operations The CPU interfaces to the flash memory through the FCON register and AUXR1

These registers are used to:

• Map the memory spaces in the adressable space

• Launch the programming of the memory spaces

• Get the status of the flash memory (busy/not busy)

9.3.1 Mapping of the memory

space By default, the user space is accessed by MOVC instruction for read only. The column

latches space is made accessible by setting the FPS bit in FCON register. Writing is

possible from 0000h to 7FFFh, address bits 6 to 0 are used to select an address within a

page while bits 14 to 7 are used to select the programming address of the page.

Setting FPS bit takes precedence on the EXTRAM bit in AUXR register.

The other memory spaces (user, extra row, hardware security) are made accessible in

the code segment by programming bits FMOD0 and FMOD1 in FCON register in accor-

dance with Table 9. A MOVC instruction is then used for reading these spaces.

Table 9. .FM0 blocks select bits

9.3.2 Launching programming FPL3:0 bits in FCON register are used to secure the launch of programming. A specific

sequence must be written in these bits to unlock the write protection and to launch the

programming. This sequence is 5xh followed by Axh. Table 10 summarizes the memory

spaces to program according to FMOD1:0 bits.

FMOD1 FMOD0 FM0 Adressable space

0 0 User (0000h-FFFFh)

0 1 Extra Row(FF80h-FFFFh)

1 0 Hardware Security Byte (0000h)

11reserved

36 T89C51CC01 Rev. D – 17-Dec-01

Table 10. Programming spaces

Note: The sequence 5xh and Axh must be executing without instructions between them other-

wise the programming is aborted.

Note: Interrupts that may occur during programming time must be disabled to avoid any spuri-

ous exit of the programming mode.

9.3.3 Status of the flash

memory The bit FBUSY in FCON register is used to indicate the status of programming.

FBUSY is set when programming is in progress.

9.3.4 Selecting FM1 The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh.

9.3.5 Loading the Column

Latches Any number of data from 1 byte to 128 bytes can be loaded in the column latches. This

provides the capability to program the whole memory by byte, by page or by any number

of bytes in a page.

When programming is launched, an automatic erase of the locations loaded in the col-

umn latches is first performed, then programming is effectively done. Thus no page or

block erase is needed and only the loaded data are programmed in the corresponding

page.

The following procedure is used to load the column latches and is summarized in

Figure 12:

• Disable interrupt and map the column latch space by setting FPS bit.

• Load the DPTR with the address to load.

• Load Accumulator register with the data to load.

• Execute the MOVX @DPTR, A instruction.

• If needed loop the three last instructions until the page is completely loaded.

• unmap the column latch and Enable Interrupt

Write to FCON

OperationFPL3:0 FPS FMOD1 FMOD0

User

5 X 0 0 No action

AX00

Write the column latches in user

space

Extra Row

5 X 0 1 No action

AX01

Write the column latches in extra row

space

Hardware

Security

Byte

5 X 1 0 No action

A X 1 0 Write the fuse bits space

Reserved 5 X 1 1 No action

A X 1 1 No action

T89C51CC01

Rev. D – 17-Dec-01

Figure 12. Column Latches Loading Procedure

Note: The last page address used when loading the column latch is the one used to select the

page programming address.

9.3.6 Programming the FLASH

Spaces

User The following procedure is used to program the User space and is summarized in

Figure 13:

• Load up to one page of data in the column latches from address 0000h to 7FFFh.

• Disable the interrupts.

• Launch the programming by writing the data sequence 50h followed by A0h in

FCON register (only from FM1).

The end of the programming indicated by the FBUSY flag cleared.

• Enable the interrupts.

Extra Row The following procedure is used to program the Extra Row space and is summarized in

Figure 13:

• Load data in the column latches from address FF80h to FFFFh.

• Disable the interrupts.

Column Latches

Data Load

DPTR= Address

ACC= Data

Exec:MOVX@DPTR,A

Last Byte

to load?

Column Latches Mapping

FCON = 08h (FPS=1)

Data memory Mapping

FCON = 00h (FPS = 0)

Save & Disable IT

EA= 0

Restore IT

38 T89C51CC01 Rev. D – 17-Dec-01

• Launch the programming by writing the data sequence 52h followed by A2h in

FCON register (only from FM1).

The end of the programming indicated by the FBUSY flag cleared.

• Enable the interrupts.

Figure 13. Flash and Extra row Programming Procedure

Hardware Security Byte The following procedure is used to program the Hardware Security Byte space

and is summarized in Figure 14:

• Set FPS and map Hardware byte (FCON = 0x0C)

• Save and disable the interrupts.

• Load DPTR at address 0000h.

• Load Accumulator register with the data to load.

• Execute the MOVX @DPTR, A instruction.

• Launch the programming by writing the data sequence 54h followed by A4h in

FCON register (only from FM1).

The end of the programming indicated by the FBusy flag cleared.

• Restore the interrupts

FLASH Spaces

Programming

Save & Disable IT

EA= 0

Launch Programming

FCON= 5xh

FCON= Axh

End Programming

Restore IT

Column Latches Loading

see Figure 12

FBusy

Cleared?

Clear Mode

FCON = 00h

T89C51CC01

Rev. D – 17-Dec-01

Figure 14. Hardware Programming Procedure

9.3.7 Reading the FLASH

Spaces

User The following procedure is used to read the User space:

• Read one byte in Accumulator by executing MOVC A,@A+DPTR with

A+DPTR=read@.

Note: FCON is supposed to be reset when not needed.

Extra Row The following procedure is used to read the Extra Row space and is summarized in

Figure 15:

• Map the Extra Row space by writing 02h in FCON register.

• Read one byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 &

DPTR= FF80h to FFFFh.

• Clear FCON to unmap the Extra Row.

Hardware Security Byte The following procedure is used to read the Hardware Security space and is

summarized in Figure 15:

• Map the Hardware Security space by writing 04h in FCON register.

• Read the byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 &

DPTR= 0000h.

• Clear FCON to unmap the Hardware Security Byte.

FLASH Spaces

Programming

Save & Disable IT

EA= 0

Launch Programming

FCON= 54h

FCON= A4h

End Programming

RestoreIT

FBusy

Cleared?

Clear Mode

FCON = 00h

Data Load

DPTR= 00h

ACC= Data

Exec:MOVX@DPTR,A

FCON = 0Ch

Save & Disable IT

EA= 0

End Loading

Restore IT

40 T89C51CC01 Rev. D – 17-Dec-01

Figure 15. Reading Procedure

9.3.8 Flash Protection from

Parallel Programming The three lock bits in Hardware Security Byte (see "In-System Programming" section)

are programmed according to Table 11 provide different level of protection for the on-

chip code and data located in FM0 and FM1.

The only way to write this bits are the parallel mode. They are set by default to level 4

Table 11. Program Lock bit

Program Lock bits

U: unprogrammed

P: programmed

WARNING: Security level 2 and 3 should only be programmed after Flash and Core

verification.

FLASH Spaces

Reading

FLASH Spaces Mapping

FCON= 00000xx0b

Data Read

DPTR= Address

ACC= 0

Exec:MOVCA,@A+DPTR

Clear Mode

FCON = 00h

Program Lock Bits

Protection description

Security

level LB0 LB1 LB2

1UUU

No program lock features enabled. MOVC instruction executed from

external program memory returns non encrypted data.

2PUU

MOVC instruction executed from external program memory are

disabled from fetching code bytes from internal memory, EA is sampled

and latched on reset, and further parallel programming of the Flash is

disabled.

3UPU

Same as 2, also verify through parallel programming interface is

disabled.

4 UUP

Same as 3, also external execution is disabled if code roll over beyond

7FFFh

T89C51CC01

Rev. D – 17-Dec-01

9.4 Registers

FCON RegisterFCON (S:D1h)

FLASH Control Register

Reset Value= 0000 0000b

76543210

FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY

Bit

Number Bit

Mnemonic Description

7-4 FPL3:0 Programming Launch Command Bits

Write 5Xh followed by AXh to launch the programming according to FMOD1:0.

(see Table 10.)

3FPS

FLASH Map Program Space

Set to map the column latch space in the data memory space.

Clear to re-map the data memory space.

2-1 FMOD1:0 FLASH Mode

See Table 9 or Table 10.

0 FBUSY

FLASH Busy

Set by hardware when programming is in progress.

Clear by hardwarewhen programming is done.

Can not be changed by software.

42 T89C51CC01 Rev. D – 17-Dec-01

10. In-System-

Programming (ISP) With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash

technology the T89C51CC01 allows the system engineer the development of applica-

tions with a very high level of flexibility. This flexibility is based on the possibility to alter

the customer program at any stages of a product’s life:

• Before assembly the 1st personalization of the product by programming in the FM0

and if needed also a customized Boot loader in the FM1.

Atmel provide also a standard Boot loader by default UART or CAN.

• After assembling on the PCB in its final embedded position by serial mode via the

CAN bus or UART.

This In-System-Programming (ISP) allows code modification over the total lifetime of the

product.

Besides the default Boot loader Atmel provide to the customer also all the needed Appli-

cation-Programming-Interfaces (API) which are needed for the ISP. The API are located

also in the Boot memory.

This allow the customer to have a full use of the 32 Kbyte user memory.

10.1 Flash Programming

and Erasure There are three methods of programming the Flash memory:

• The Atmel bootloader located in FM1 is activated by the application. Low level API

routines (located in FM1)will be used to program FM0. The interface used for serial

downloading to FM0 is the UART or the CAN. API can be called also by user’s

bootloader located in FM0 at [SBV]00h.

• A further method exist in activating the Atmel boot loader by hardware activation.

• The FM0 can be programmed also by the parallel mode using a programmer.

Figure 16. Flash Memory Mapping

F800h

7FFFh

32 Kbytes

Flash memory

2KbytesIAP

bootloader

FM0

FM1

Custom

Boot Loader

[SBV]00h

FFFFh

FM1 mapped between F800h and FFFFh

when API called

0000h

T89C51CC01

Rev. D – 17-Dec-01

10.2 Boot Process

10.2.1 Software boot process

example Many algorithms can be used for the software boot process. Before describing them,

We give below the description of the different flags and bytes.

Boot Loader Jump Bit (BLJB):

- This bit indicates if on RESET the user wants to jump to this application at address

@0000h on FM0 or execute the boot loader at address @F800h on FM1.

- BLJB = 0 on parts delivered with bootloader programmed.

- To read or modify this bit, the APIs are used.

Boot Vector Address (SBV):

- This byte contains the MSB of the user boot loader address in FM0.

- The default value of SBV is FFh (no user boot loader in FM0).

- To read or modify this byte, the APIs are used.

Extra Byte (EB) & Boot Status Byte (BSB):

- These bytes are reserved for customer use.

- To read or modify these bytes, the APIs are used.

10.2.2 Hardware boot process At the falling edge of RESET, the bit ENBOOT in AUXR1 register is initialized with the

value of Boot Loader Jump Bit (BLJB).

Further at the falling edge of RESET if the following conditions (called Hardware condi-

tion) are detected:

• PSEN low,

• EA high,

• ALE high (or not connected).

– After Hardware Condition the FCON register is initialized with the value 00h

and the PC is initialized with F800h (FM1).

The Hardware condition makes the bootloader to be executed, whatever BLJB value is.

If no hardware condition is detected, the FCON register is initialized with the value F0h.

Check of the BLJB value.

•IfbitBLJB=1:

User application in FM0 will be started at @0000h (standard reset).

•IfbitBLJB=0:

Boot loader will be started at @F800h in FM1.

44 T89C51CC01 Rev. D – 17-Dec-01

Figure 17. Hardware Boot Process Algorithm

10.3 Application-

Programming-Interface Several Application Program Interface (API) calls are available for use by an application

program to permit selective erasing and programming of FLASH pages. All calls are

made by functions.

All these APIs are describe in an documentation: "In-System Programing: Flash Library

for T89C51CC01".

This is available on the web site.

RESET

Hardware

condition?

BLJB == 0

bit ENBOOT in AUXR1 register

is initialized with BLJB.

Hardware

Software

ENBOOT = 1

PC = F800h

ENBOOT = 1

PC = F800h

FCON = 00h

FCON = F0h

Boot Loader

in FM1

ENBOOT = 0

PC = 0000h

Yes

Application

in FM0

T89C51CC01

Rev. D – 17-Dec-01

Table 12. List of API

10.4 XROW Bytes Table 13. Xrow mapping

API CALL Description

PROGRAM DATA BYTE Write a byte in flash memory

PROGRAM DATA PAGE Write a page (128 bytes) in flash memory

PROGRAM EEPROM BYTE Write a byte in Eeprom memory

ERASE BLOCK Erase all flash memory

ERASE BOOT VECTOR (SBV) Erase the boot vector

PROGRAM BOOT VECTOR (SBV) Write the boot vector

PROGRAM EXTRA BYTE (EB) Write the extra byte

READ DATA BYTE

READ EEPROM BYTE

READ FAMILY CODE

READ MANUFACTURER CODE

READ PRODUCT NAME

READ REVISION NUMBER

READ STATUS BIT (BSB) Read the status bit

READ BOOT VECTOR (SBV) Read the boot vector

READ EXTRA BYTE (EB) Read the extra byte

PROGRAM X2 Write the hardware flag for X2 mode

READ X2 Read the hardware flag for X2 mode

PROGRAM BLJB Write the hardware flag BLJB

READBLJB ReadthehardwareflagBLJB

Description Default value Address

Copy of the Manufacturer Code 58h 30h

Copy of the Device ID#1: Family code D7h 31h

Copy of the Device ID#2: Memories size and type F7h 60h

Copy of the Device ID#3: Name and Revision FFh 61h

46 T89C51CC01 Rev. D – 17-Dec-01

10.5 Hardware Security

Byte Table 14. Hardware Security byte

Default value after erasing chip: FFh

Note: Only the 4 MSB bits can be accessed by software.

Note: The 4 LSB bits can only be accessed by parallel mode.

76543210

X2B BLJB - - - LB2 LB1 LB0

Bit

Number Bit

Mnemonic Description

7X2B

X2 Bit

Set this bit to start in standard mode

Clear this bit to start in X2 mode.

6BLJB

Boot Loader JumpBit

- 1: To start the user’s application on next RESET (@0000h) located in FM0,

- 0: To start the boot loader(@F800h) located in FM1.

5-3 - Reserved

The value read from these bits are indeterminate.

2-0 LB2:0 Lock Bits

T89C51CC01

Rev. D – 17-Dec-01

11. Serial I/O Port The T89C51CC01 I/O serial port is compatible with the I/O serial port in the 80C52.

It provides both synchronous and asynchronous communication modes. It operates as a

Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes

(Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously

and at different baud rates

Serial I/O port includes the following enhancements:

• Framing error detection

• Automatic address recognition

Figure 18. Serial I/O Port Block Diagram

11.1 Framing Error

Detection Framing bit error detection is provided for the three asynchronous modes. To enable the

framing bit error detection feature, set SMOD0 bit in PCON register.

Figure 19. Framing Error Block Diagram

When this feature is enabled, the receiver checks each incoming data frame for a valid

stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous

transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in

SCON register bit is set.

The software may examine the FE bit after each reception to check for data errors.

Once set, only software or a reset clears the FE bit. Subsequently received frames with

Write SBUF

RI TI

SBUF

Transmitter

SBUF

Receiver

IB Bus

Mode0Transmit

Receive

Shift register

Load SBUF

Read SBUF

Interrupt Request

Serial Port

TXD

RXD

RITIRB8TB8RENSM2SM1SM0/FE

IDLPDGF0GF1POF-SMOD0SMOD1

To UART framing error control

SM0toUARTmodecontrol

Set FE bit if stop bit is 0 (framing error)

48 T89C51CC01 Rev. D – 17-Dec-01

valid stop bits cannot clear the FE bit. When the FE feature is enabled, RI rises on the

stop bit instead of the last data bit (See Figure 20. and Figure 21.).

Figure 20. UART Timing in Mode 1

Figure 21. UART Timing in Modes 2 and 3

11.2 Automatic Address

Recognition The automatic address recognition feature is enabled when the multiprocessor commu-

nication feature is enabled (SM2 bit in SCON register is set).

Implemented in the hardware, automatic address recognition enhances the multiproces-

sor communication feature by allowing the serial port to examine the address of each

incoming command frame. Only when the serial port recognizes its own address will the

receiver set the RI bit in the SCON register to generate an interrupt. This ensures that

the CPU is not interrupted by command frames addressed to other devices.

If necessary, you can enable the automatic address recognition feature in mode 1. In

this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when

the received command frame address matches the device’s address and is terminated

by a valid stop bit.

To support automatic address recognition, a device is identified by a given address and

a broadcast address.

Note: The multiprocessor communication and automatic address recognition features cannot

be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).

Data byte

SMOD0=X

Stop

bit

Start

bit

RXD D7D6D5D4D3D2D1D0

SMOD0=1

SMOD0=0

Data byte Ninth

bit Stop

bit

Start

bit

RXD D8D7D6D5D4D3D2D1D0

SMOD0=1

T89C51CC01

Rev. D – 17-Dec-01

11.3 Given Address Each device has an individual address that is specified in the SADDR register; the

SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form

the device’s given address. The don’t-care bits provide the flexibility to address one or

more slaves at a time. The following example illustrates how a given address is formed.

To address a device by its individual address, the SADEN mask byte must be 1111

1111b.

For example:

SADDR0101 0110b

SADEN1111 1100b

Given0101 01XXb

Here is an example of how to use given addresses to address different slaves:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Given1111 0X0Xb

Slave B:SADDR1111 0011b

SADEN1111 1001b

Given1111 0XX1b

Slave C:SADDR1111 0010b

SADEN1111 1101b

Given1111 00X1b

The SADEN byte is selected so that each slave may be addressed separately.

For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To com-

municate with slave A only, the master must send an address where bit 0 is clear (e.g.

1111 0000b).

For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit. To communicate with

slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both

set (e.g. 1111 0011b).

To communicate with slaves A, B and C, the master must send an address with bit 0 set,

bit 1 clear, and bit 2 clear (e.g. 1111 0001b).

11.4 Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers

with zeros defined as don’t-care bits, e.g.:

SADDR 0101 0110b

SADEN 1111 1100b

SADDR OR SADEN1111 111Xb

The use of don’t-care bits provides flexibility in defining the broadcast address, however

in most applications, a broadcast address is FFh. The following is an example of using

broadcast addresses:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Given1111 1X11b,

Slave B:SADDR1111 0011b

SADEN1111 1001b

Given1111 1X11B,

Slave C:SADDR=1111 0010b

SADEN1111 1101b

Given1111 1111b

50 T89C51CC01 Rev. D – 17-Dec-01

For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with

all of the slaves, the master must send an address FFh. To communicate with slaves A

and B, but not slave C, the master can send and address FBh.

11.5 Registers Table 15. SCON Register

SCON (S:98h)

Serial Control Register

Reset Value = 0000 0000b

Bit addressable

76543210

FE/SM0 SM1 SM2 REN TB8 RB8 TI RI

Bit

Number Bit

Mnemonic Description

7FE

Framing Error bit (SMOD0=1)

Cleartoresettheerrorstate,notclearedbyavalidstopbit.

Set by hardware when an invalid stop bit is detected.

SM0 Serial port Mode bit 0 (SMOD0=0)

Refer to SM1 for serial port mode selection.

6SM1

Serial port Mode bit 1

SM0 SM1 Mode Baud Rate

0 0 Shift Register FXTAL/12 (or FXTAL /6 in mode X2)

0 1 8-bit UART Variable

10 9-bitUARTF

XTAL/64 or FXTAL/32

1 1 9-bit UART Variable

5SM2

Serial port Mode 2 bit / Multiprocessor Communication Enable bit

Clear to disable multiprocessor communication feature.

Set to enable multiprocessor communication feature in mode 2 and 3.

4REN

Reception Enable bit

Clear to disable serial reception.

Set to enable serial reception.

3TB8

Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3

Clear to transmit a logic 0 in the 9th bit.

Set to transmit a logic 1 in the 9th bit.

2RB8

Receiver Bit 8 / Ninth bit received in modes 2 and 3

Cleared by hardware if 9th bit received is a logic 0.

Set by hardware if 9th bit received is a logic 1.

1TI

Transmit Interrupt flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the

stop bit in the other modes.

0RI

Receive Interrupt flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0, see Figure 20. and

Figure 21. in the other modes.

T89C51CC01

Rev. D – 17-Dec-01

Table 16. SADEN Register

SADEN (S:B9h)

Slave Address Mask Register

Reset Value = 0000 0000b

Not bit addressable

Table 17. SADDR Register

SADDR (S:A9h)

Slave Address Register

Reset Value = 0000 0000b

Not bit addressable

Table 18. SBUF Register

SBUF (S:99h)

Serial Data Buffer

Reset Value = 0000 0000b

Not bit addressable

76543210

Bit

Number Bit

Mnemonic Description

7-0 Mask Data for Slave Individual Address

76543210

Bit

Number Bit

Mnemonic Description

7-0 Slave Individual Address

76543210

Bit

Number Bit

Mnemonic Description

7-0 Data sent/received by Serial I/O Port

52 T89C51CC01 Rev. D – 17-Dec-01

Table 19. PCON Register

PCON (S:87h)

Power Control Register

Reset Value = 00X1 0000b

Not bit addressable

76543210

SMOD1 SMOD0 - POF GF1 GF0 PD IDL

Bit

Number Bit

Mnemonic Description

7SMOD1

Serial port Mode bit 1

Settoselectdoublebaudrateinmode1,2or3.

6SMOD0

Serial port Mode bit 0

Clear to select SM0 bit in SCON register.

Set to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

4POF

Power-Off Flag

Clear to recognize next reset type.

Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set

by software.

3GF1

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

2GF0

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

1PD

Power-Down mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

0IDL

Idle mode bit

Clear by hardware when interrupt or reset occurs.

Set to enter idle mode.

T89C51CC01

Rev. D – 17-Dec-01

12. Timers/Counters The T89C51CC01 implements two general-purpose, 16-bit Timers/Counters. Such are

identified as Timer 0 and Timer 1, and can be independently configured to operate in a

variety of modes as a Timer or an event Counter. When operating as a Timer, the

Timer/Counter runs for a programmed length of time, then issues an interrupt request.

When operating as a Counter, the Timer/Counter counts negative transitions on an

external pin. After a preset number of counts, the Counter issues an interrupt request.

The various operating modes of each Timer/Counter are described in the following

sections.

12.1 Timer/Counter

Operations A basic operation is Timer registers THx and TLx (x= 0, 1) connected in cascade to form

a 16-bit Timer. Setting the run control bit (TRx) in TCON register (see Figure 20) turns

the Timer on by allowing the selected input to increment TLx. When TLx overflows it

increments THx; when THx overflows it sets the Timer overflow flag (TFx) in TCON reg-

ister. Setting the TRx does not clear the THx and TLx Timer registers. Timer registers

can be accessed to obtain the current count or to enter preset values. They can be read

at any time but TRx bit must be cleared to preset their values, otherwise the behavior of

the Timer/Counter is unpredictable.

The C/Tx# control bit selects Timer operation or Counter operation by selecting the

divided-down peripheral clock or external pin Tx as the source for the counted signal.

TRx bit must be cleared when changing the mode of operation, otherwise the behavior

of the Timer/Counter is unpredictable.

For Timer operation (C/Tx#= 0), the Timer register counts the divided-down peripheral

clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock

periods). The Timer clock rate is FPER /6,i.e.F

OSC / 12 in standard mode or FOSC /6in

X2 mode.

For Counter operation (C/Tx#= 1), the Timer register counts the negative transitions on

the Tx external input pin. The external input is sampled every peripheral cycles. When

the sample is high in one cycle and low in the next one, the Counter is incremented.

Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition,

the maximum count rate is FPER / 12, i.e. FOSC / 24 in standard mode or FOSC /12inX2

mode. There are no restrictions on the duty cycle of the external input signal, but to

ensure that a given level is sampled at least once before it changes, it should be held for

at least one full peripheral cycle.

12.2 Timer 0 Timer 0 functions as either a Timer or event Counter in four modes of operation.

Figure 22 to Figure 25 show the logical configuration of each mode.

Timer 0 is controlled by the four lower bits of TMOD register (see Figure 21) and bits 0,

1, 4 and 5 of TCON register (see Figure 20). TMOD register selects the method of Timer

gating (GATE0), Timer or Counter operation (T/C0#) and mode of operation (M10 and

M00). TCON register provides Timer 0 control functions: overflow flag (TF0), run control

bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0).

For normal Timer operation (GATE0= 0), setting TR0 allows TL0 to be incremented by

the selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer

operation.

Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an inter-

rupt request.

It is important to stop Timer/Counter before changing mode.

12.2.1 Mode 0 (13-bit Timer) Mode 0 configures Timer 0 as an 13-bit Timer which is set up as an 8-bit Timer (TH0

(see Figure 22). The upper three bits of TL0 register are indeterminate and should be

ignored. Prescaler overflow increments TH0 register.

54 T89C51CC01 Rev. D – 17-Dec-01

Figure 22. Timer/Counter x (x= 0 or 1) in Mode 0

12.2.2 Mode 1 (16-bit Timer) Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in

cascade (see Figure 23). The selected input increments TL0 register.

Figure 23. Timer/Counter x (x= 0 or 1) in Mode 1

12.2.3 Mode 2 (8-bit Timer with

Auto-Reload) Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads

from TH0 register (see Figure 24). TL0 overflow sets TF0 flag in TCON register and

reloads TL0 with the contents of TH0, which is preset by software. When the interrupt

request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next

reload value may be changed at any time by writing it to TH0 register.

Figure 24. Timer/Counter x (x= 0 or 1) in Mode 2

FTx

CLOCK

TRx

TCON reg

TFx

TCON reg

GATEx

TMOD reg

÷6Overflow Timer x

Interrupt

Request

C/Tx#

TMOD reg

TLx

(5 bits)

THx

(8 bits)

INTx#

see section “Clock”

TRx

TCON reg

TFx

TCON reg

GATEx

TMOD reg

Overflow Timer x

Interrupt

Request

C/Tx#

TMOD reg

TLx

(8 bits)

THx

(8 bits)

INTx#

FTx

CLOCK ÷ 6

see section “Clock”

TRx

TCON reg

TFx

TCON reg

GATEx

TMOD reg

Overflow Timer x

Interrupt

Request

C/Tx#

TMOD reg

TLx

(8 bits)

THx

(8 bits)

INTx#

FTx

CLOCK ÷ 6

see section “Clock”

T89C51CC01

Rev. D – 17-Dec-01

12.2.4 Mode 3 (Two 8-bit

Timers) Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit

Timers (see Figure 25). This mode is provided for applications requiring an additional 8-

bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD reg-

ister, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a

Timer function (counting FPER /6) and takes over use of the Timer 1 interrupt (TF1) and

run control (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode

Figure 25. Timer/Counter 0 in Mode 3: Two 8-bit Counters

12.3 Timer 1 Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. Follow-

ing comments help to understand the differences:

• Timer 1 functions as either a Timer or event Counter in three modes of operation.

Figure 22 to Figure 24 show the logical configuration for modes 0, 1, and 2. Timer

1’s mode 3 is a hold-count mode.

• Timer 1 is controlled by the four high-order bits of TMOD register (see Figure 21)

and bits 2, 3, 6 and 7 of TCON register (see Figure 20). TMOD register selects the

method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of

operation (M11 and M01). TCON register provides Timer 1 control functions:

overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type

control bit (IT1).

• Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best

suited for this purpose.

• For normal Timer operation (GATE1= 0), setting TR1 allows TL1 to be incremented

by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control

Timer operation.

• Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating

an interrupt request.

• When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit

(TR1). For this situation, use Timer 1 only for applications that do not require an

interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in

and out of mode 3 to turn it off and on.

• It is important to stop Timer/Counter before changing mode.

TR0

TCON.4

TF0

TCON.5

INT0#

GATE0

TMOD.3

Overflow Timer 0

Interrupt

Request

C/T0#

TMOD.2

TL0

(8 bits)

TR1

TCON.6

TH0

(8 bits) TF1

TCON.7

Overflow Timer 1

Interrupt

Request

FTx

CLOCK ÷6

FTx

CLOCK ÷6

see section “Clock”

56 T89C51CC01 Rev. D – 17-Dec-01

12.3.1 Mode 0 (13-bit Timer) Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 reg-

ister) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register

(see Figure 22). The upper 3 bits of TL1 register are ignored. Prescaler overflow incre-

ments TH1 register.

12.3.2 Mode 1 (16-bit Timer) Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in

cascade (see Figure 23). The selected input increments TL1 register.

12.3.3 Mode 2 (8-bit Timer with

Auto-Reload) Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from

TH1 register on overflow (see Figure 24). TL1 overflow sets TF1 flag in TCON register

and reloads TL1 with the contents of TH1, which is preset by software. The reload

leaves TH1 unchanged.

12.3.4 Mode 3 (Halt) Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt

Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in mode 3.

12.4 Interrupt Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This

flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer

interrupt routine. Interrupts are enabled by setting ETx bit in IEN0 register. This assumes

interrupts are globally enabled by setting EA bit in IEN0 register.

Figure 26. Timer Interrupt System

TF0

TCON.5

ET0

IEN0.1

Timer 0

Interrupt Request

TF1

TCON.7

ET1

IEN0.3

Timer 1

Interrupt Request

T89C51CC01

Rev. D – 17-Dec-01

12.5 Registers Table 20. TCON Register

TCON (S:88h)

Timer/Counter Control Register

Reset Value= 0000 0000b

76543210

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Bit

Number Bit

Mnemonic Description

7TF1

Timer 1 Overflow Flag

Cleared by hardware when processor vectors to interrupt routine.

Set by hardware on Timer/Counter overflow, when Timer 1 register overflows.

6TR1

Timer 1 Run Control Bit

Clear to turn off Timer/Counter 1.

SettoturnonTimer/Counter1.

5TF0

Timer 0 Overflow Flag

Cleared by hardware when processor vectors to interrupt routine.

Set by hardware on Timer/Counter overflow, when Timer 0 register overflows.

4TR0

Timer 0 Run Control Bit

Clear to turn off Timer/Counter 0.

SettoturnonTimer/Counter0.

3IE1

Interrupt 1 Edge Flag

Cleared by hardware when interrupt is processed if edge-triggered (see IT1).

Set by hardware when external interrupt is detected on INT1# pin.

2IT1

Interrupt 1 Type Control Bit

Clear to select low level active (level triggered) for external interrupt 1 (INT1#).

Set to select falling edge active (edge triggered) for external interrupt 1.

1IE0

Interrupt 0 Edge Flag

Cleared by hardware when interrupt is processed if edge-triggered (see IT0).

Set by hardware when external interrupt is detected on INT0# pin.

0IT0

Interrupt 0 Type Control Bit

Clear to select low level active (level triggered) for external interrupt 0 (INT0#).

Set to select falling edge active (edge triggered) for external interrupt 0.

58 T89C51CC01 Rev. D – 17-Dec-01

Table 21. TMOD Register

TMOD (S:89h)

Timer/Counter Mode Control

Reset Value= 0000 0000b

76543210

GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00

Bit

Number Bit

Mnemonic Description

7GATE1

Timer 1 Gating Control Bit

Clear to enable Timer 1 whenever TR1 bit is set.

Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set.

6C/T1#

Timer 1 Counter/Timer Select Bit

Clear for Timer operation: Timer 1 counts the divided-down system clock.

Set for Counter operation: Timer1 counts negative transitions on external pin T1.

5M11Timer 1 Mode Select Bits

M11 M01 Operating mode

0 0 Mode 0: 8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1).

0 1 Mode 1: 16-bit Timer/Counter.

1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL1).(a)

1 1 Mode 3: Timer 1 halted. Retains count

4M01

3GATE0

Timer 0 Gating Control Bit

Clear to enable Timer 0 whenever TR0 bit is set.

Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set.

2C/T0#

Timer 0 Counter/Timer Select Bit

Clear for Timer operation: Timer 0 counts the divided-down system clock.

Set for Counter operation: Timer0 counts negative transitions on external pin T0.

1M10

Timer 0 Mode Select Bit

M10 M00 Operating mode

0 0 Mode 0: 8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0).

0 1 Mode 1: 16-bit Timer/Counter.

1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL0). (b)

1 1 Mode 3: TL0 is an 8-bit Timer/Counter

TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 bits.

0M00

a. Reloaded from TH1 at overflow.

b. Reloaded from TH0 at overflow.

T89C51CC01

Rev. D – 17-Dec-01

Table 22. TH0 Register

TH0 (S:8Ch)

Timer 0 High Byte Register.

Reset Value= 0000 0000b

Table 23. TL0 Register

TL0 (S:8Ah)

Timer 0 Low Byte Register.

Reset Value= 0000 0000b

Table 24. TH1 Register

TH1 (S:8Dh)

Timer 1 High Byte Register.

Reset Value= 0000 0000b

76543210

Bit

Number Bit

Mnemonic Description

7:0 High Byte of Timer 0.

76543210

Bit

Number Bit

Mnemonic Description

7:0 Low Byte of Timer 0.

76543210

Bit

Number Bit

Mnemonic Description

7:0 High Byte of Timer 1.

60 T89C51CC01 Rev. D – 17-Dec-01

Table 25. TL1 Register

TL1 (S:8Bh)

Timer 1 Low Byte Register.

Reset Value= 0000 0000b

76543210

Bit

Number Bit

Mnemonic Description

7:0 Low Byte of Timer 1.

T89C51CC01

Rev. D – 17-Dec-01

13. Timer 2 The T89C51CC01 timer 2 is compatible with timer 2 in the 80C52.

It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2

and TL2 that are cascade- connected. It is controlled by T2CON register (See Table )

and T2MOD register (See Table 28). Timer 2 operation is similar to Timer 0 and Timer

1. C/T2 selects FT2 clock/6 (timer operation) or external pin T2 (counter operation) as

timer clock. Setting TR2 allows TL2 to be incremented by the selected input.

Timer 2 includes the following enhancements:

• Auto-reload mode (up or down counter)

• Programmable clock-output

13.1 Auto-Reload Mode The auto-reload mode configures timer 2 as a 16-bit timer or event counter with auto-

matic reload. This feature is controlled by the DCEN bit in T2MOD register (See

Table 28). Setting the DCEN bit enables timer 2 to count up or down as shown in

Figure 27. In this mode the T2EX pin controls the counting direction.

When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the

TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value

in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.

When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the

timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers.

The underflow sets TF2 flag and reloads FFFFh into the timer registers.

The EXF2 bit toggles when timer 2 overflow or underflow, depending on the direction of

the count. EXF2 does not generate an interrupt. This bit can be used to provide 17-bit

resolution.

62 T89C51CC01 Rev. D – 17-Dec-01

Figure 27. Auto-Reload Mode Up/Down Counter

13.2 Programmable

Clock-Output In clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock genera-

tor (See Figure 28). The input clock increments TL2 at frequency FOSC/2. The timer

repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H

and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer 2 overflows do

not generate interrupts. The formula gives the clock-out frequency depending on the

system oscillator frequency and the value in the RCAP2H and RCAP2L registers:

For a 16 MHz system clock in x1 mode, timer 2 has a programmable frequency range of

61 Hz (FOSC/216) to 4 MHz (FOSC/4). The generated clock signal is brought out to T2 pin

(P1.0).

Timer 2 is programmed for the clock-out mode as follows:

• Set T2OE bit in T2MOD register.

• Clear C/T2 bit in T2CON register.

• Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L

registers.

• Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the

reload value or different depending on the application.

• To start the timer, set TR2 run control bit in T2CON register.

(DOWN COUNTING RELOAD VALUE)

TF2

EXF2

TH2

(8-bit)

TL2

(8-bit)

RCAP2H

(8-bit)

RCAP2L

(8-bit)

FFh

(8-bit) FFh

(8-bit)

TOGGLE

(UP COUNTING RELOAD VALUE)

TIMER 2

INTERRUPT

T2CONreg

T2EX:

1=UP

2=DOWN

CT/2

T2CON.1

TR2

T2CON.2

FT2

CLOCK

see section “Clock”

Clock OutFrequency–FT2clock

4 65536 RCAP2H–RCAP2L⁄()×

--------------------------------------------------------------------------------------------

T89C51CC01

Rev. D – 17-Dec-01

It is possible to use timer 2 as a baud rate generator and a clock generator simulta-

neously. For this configuration, the baud rates and clock frequencies are not

independent since both functions use the values in the RCAP2H and RCAP2L registers.

Figure 28. Clock-Out Mode

EXEN2

EXF2

OVERFLOW

T2EX

TH2

(8-bit)

TL2

(8-bit)

TIMER 2

RCAP2H

(8-bit)

RCAP2L

(8-bit)

T2OE

T2CON reg

T2MOD reg

C/T2

T2CON reg

INTERRUPT

CT/2

T2CON.1

TR2

T2CON.2

FT2

CLOCK

64 T89C51CC01 Rev. D – 17-Dec-01

13.3 Registers Table 26. T2CON Register

T2CON (S:C8h)

Timer 2 Control Register

Reset Value = 0000 0000b

Bit addressable

76543210

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#

Bit

Number Bit

Mnemonic Description

7TF2

Timer 2 overflow Flag

TF2 is not set if RCLK=1 or TCLK = 1.

Must be cleared by software.

Setbyhardwareontimer2overflow.

6EXF2

Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if

EXEN2=1.

Set to cause the CPU to vector to timer 2 interrupt routine when timer 2 interrupt

is enabled.

Must be cleared by software.

5RCLK

Receive Clock bit

Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.

Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.

4TCLK

Transmit Clock bit

Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.

Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.

3 EXEN2

Timer 2 External Enable bit

Clear to ignore events on T2EX pin for timer 2 operation.

SettocauseacaptureorreloadwhenanegativetransitiononT2EXpinis

detected, if timer 2 is not used to clock the serial port.

2TR2

Timer 2 Run control bit

Clear to turn off timer 2.

Settoturnontimer2.

1C/T2#

Timer/Counter 2 select bit

Clear for timer operation (input from internal clock system: FOSC).

Set for counter operation (input from T2 input pin).

0CP/RL2#

Timer 2 Capture/Reload bit

If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reloadon

timer 2 overflow.

Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if

EXEN2=1.

Set to capture on negative transitions on T2EX pin if EXEN2=1.

T89C51CC01

Rev. D – 17-Dec-01

Table 27. T2MOD Register

T2MOD (S:C9h)

Timer 2 Mode Control Register

Reset Value = XXXX XX00b

Not bit addressable

Table 28. TH2 Register

TH2 (S:CDh)

Timer 2 High Byte Register

Reset Value = 0000 0000b

Not bit addressable

76543210

------T2OEDCEN

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

1T2OE

Timer 2 Output Enable bit

Clear to program P1.0/T2 as clock input or I/O port.

Set to program P1.0/T2 as clock output.

0 DCEN Down Counter Enable bit

Clear to disable timer 2 as up/down counter.

Set to enable timer 2 as up/down counter.

76543210

--------

Bit

Number Bit

Mnemonic Description

7-0 HighByteofTimer2.

66 T89C51CC01 Rev. D – 17-Dec-01

Table 29. TL2 Register

TL2 (S:CCh)

Timer 2 Low Byte Register

Reset Value = 0000 0000b

Not bit addressable

Table 30. RCAP2H Register

RCAP2H (S:CBh)

Timer 2 Reload/Capture High

Byte Register

Reset Value = 0000 0000b

Not bit addressable

Table 31. RCAP2L Register

RCAP2L (S:CAH)

TIMER 2REload/Capture Low

Byte Register

Reset Value = 0000 0000b

Not bit addressable

76543210

--------

Bit

Number Bit

Mnemonic Description

7-0 Low Byte of Timer 2.

76543210

--------

Bit

Number Bit

Mnemonic Description

7-0 High Byte of Timer 2 Reload/Capture.

76543210

--------

Bit

Number Bit

Mnemonic Description

7-0 Low Byte of Timer 2 Reload/Capture.

T89C51CC01

Rev. D – 17-Dec-01

14. WatchDog Timer T89C51CC01 contains a powerful programmable hardware WatchDog Timer (WDT)

that automatically resets the chip if it software fails to reset the WDT before the selected

time interval has elapsed. It permits large Time-Out ranking from 16ms to 2s @Fosc =

12MHz in X1 mode.

This WDT consists of a 14-bit counter plus a 7-bit programmable counter, a WatchDog

Timer reset register (WDTRST) and a WatchDog Timer programming (WDTPRG) regis-

ter. When exiting reset, the WDT is -by default- disable.

To enable the WDT, the user has to write the sequence 1EH and E1H into WDTRST

ment every machine cycle while the oscillator is running and there is no way to disable

the WDT except through reset (either hardware reset or WDT overflow reset). When

WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET

pulse duration is 96xTOSC,whereT

OSC=1/FOSC. To make the best use of the WDT, it

should be serviced in those sections of code that will periodically be executed within the

time required to prevent a WDT reset

Note: When the watchdog is enable it is impossible to change its period.

Figure 29. WatchDog Timer

÷ 6

÷ PS CPU and Peripheral

Clock

Fwd

CLOCK

WDTPRG

RESET Decoder

Control

WDTRST

Enable

14-bit COUNTER 7-bit COUNTER

Outputs

Fwd Clock

RESET

---

--210

68 T89C51CC01 Rev. D – 17-Dec-01

14.1 WatchDog

Programming The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the

WDT duration.

Table 32. Machine Cycle Count

To compute WD Time-Out, the following formula is applied:

Note: Svalue represents the decimal value of (S2 S1 S0)

Find Hereafter computed Time-Out value for FoscXTAL = 12MHz in X1 mode

Table 33. Time-Out Computation

14.2 WatchDog Timer

during Power down

mode and Idle

In Power Down mode the oscillator stops, which means the WDT also stops. While in

Power Down mode, the user does not need to service the WDT. There are 2 methods of

exiting Power Down mode: by a hardware reset or via a level activated external interrupt

which is enabled prior to entering Power Down mode. When Power Down is exited with

hardware reset, the watchdog is disabled. Exiting Power Down with an interrupt is signif-

icantly different. The interrupt shall be held low long enough for the oscillator to stabilize.

When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from

resetting the device while the interrupt pin is held low, the WDT is not started until the

S2 S1 S0 Machine Cycle Count

000 2

14 -1

001 2

15 -1

010 2

16 -1

011 2

17 -1

100 2

18 -1

101 2

19 -1

110 2

20 -1

111 2

21 -1

S2 S1 S0 Fosc=12MHz Fosc=16MHz Fosc=20MHz

0 0 0 16.38 ms 12.28 ms 9.82 ms

0 0 1 32.77 ms 24.57 ms 19.66 ms

0 1 0 65.54 ms 49.14 ms 39.32 ms

0 1 1 131.07 ms 98.28 ms 78.64 ms

1 0 0 262.14ms 196.56ms 157.28ms

1 0 1 524.29ms 393.12ms 314.56ms

1 1 0 1.05 s 786.24 ms 629.12 ms

1 1 1 2.10 s 1.57 s 1.25 ms

FTime Out Fwd

12 214 2Svalue

×()1–()×

-------------------------------------------------------------------

=–

T89C51CC01

Rev. D – 17-Dec-01

interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service

for the interrupt used to exit Power Down.

To ensure that the WDT does not overflow within a few states of exiting powerdown, it is

best to reset the WDT just before entering powerdown.

In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting

T89C51CC01 while in Idle mode, the user should always set up a timer that will periodi-

cally exit Idle, service the WDT, and re-enter Idle mode.

14.2.1 Register Table 34. WDTPRG Register

WDTPRG (S:A7h)

WatchDog Timer Duration

Programming register

Reset Value = XXXX X000b

76543210

- - - - - S2 S1 S0

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

2S2

WatchDog Timer Duration selection bit 2

Work in conjunction with bit 1 and bit 0.

1S1

WatchDog Timer Duration selection bit 1

Work in conjunction with bit 2 and bit 0.

0S0

WatchDog Timer Duration selection bit 0

Work in conjunction with bit 1 and bit 2.

70 T89C51CC01 Rev. D – 17-Dec-01

Table 35. WDTRST Register

WDTRST (S:A6h Write only)

WatchDog Timer Enable

Reset Value = 1111 1111b

Note: The WDRST register is used to reset/enable the WDT by writing 1EH then E1H in

sequence without instruction between these two sequences.

76543210

--------

Bit

Number Bit

Mnemonic Description

7 - Watchdog Control Value

T89C51CC01

Rev. D – 17-Dec-01

15. Atmel CAN

Controller The Atmel CAN Controller provides all the features required to implement the serial

communication protocol CAN as defined by BOSCH GmbH. The CAN specification as

referred to by ISO/11898 (2.0A & 2.0B) for high speed and ISO/11519-2 for low speed.

The CAN Controller is able to handle all types of frames (Data, Remote, Error and Over-

load) and achieves a bitrate of 1 Mbit/s at 8MHz1Crystal frequency in X2 mode.

Notes: 1. At BRP = 1 sampling point will be fixed.

15.1 CAN Controller

Description The CAN Controller accesses are made through SFR.

Several operations are possible by SFR:

arithmetic and logic operations, transfers and program control (SFR is accessible by

direct addressing).

15 independent message objects are implemented, a pagination system manages their

accesses.

Any message object can be programmed in a reception buffer block (even non-consec-

utive buffers). For the reception of defined messages one or several receiver message

objects can be masked without participating in the buffer feature. An IT is generated

when the buffer is full. The frames following the buffer-full interrupt will not be taken into

account until at least one of the buffer message objects is re-enabled in reception.

Higher priority of a message object for reception or transmission is given to the lower

message object number.

The programmable 16-bit Timer (CANTIMER) is used to stamp each received and sent

message in the CANSTMP register. This timer starts counting as soon as the CAN con-

troller is enabled by the ENA bit in the CANGCON register.

The Time Trigger Communication (TTC) protocol is supported by the T89C51CC01.

Figure 30. CAN Controller block diagram

Bit

Stuffing /Destuffing

Cyclic

Redundancy Check

Receive Transmit

Error

Counter

Rec/Tec

Bit

Timing

Logic

Page

Encoder

µC-Core Interface

Core

Control

Interface

Bus

TxDC

RxDC

72 T89C51CC01 Rev. D – 17-Dec-01

15.2 CAN Controller

Mailbox and Registers

Organization

The pagination allows management of the 321 registers including 300(15x20) bytes of

mailboxvia34SFR’s.

All actions on the message object window SFRs apply to the corresponding message

object registers pointed by the message object number find in the Page message object

Figure 31. CAN Controller memory organization

Ch.14 - ID Tag - 1

Ch.14 - ID Tag - 2

Ch.14 - ID Tag - 4

Ch.14 - ID Tag - 3

Ch.14 - ID Mask - 1

Ch.14 - ID Mask - 2

Ch.14 - ID Mask - 4

Ch.14 - ID Mask - 3

Ch.14 - Message Data - byte 0

General Control

General Status

Bit Timing - 1

Bit Timing - 2

Bit Timing - 3

Enable Interrupt

Enable Interrupt message object - 1

Page message object

message object Status

message object Control & DLC

Message Data

ID Tag - 1

ID Tag - 2

ID Tag - 4

ID Tag - 3

ID Mask - 1

ID Mask - 2

ID Mask - 4

ID Mask - 3

message object 0 - Status

message object 0 - Control & DLC

Ch.0 - ID Tag - 1

Ch.0 - ID Tag - 2

Ch.0 - ID Tag - 4

Ch.0 - ID Tag - 3

Ch.0 - Message Data - byte 0

message object 14 - Status

message object 14 - Control & DLC

Enable Interrupt message object - 2

Status Interrupt message object - 1

Status Interrupt message object - 2

(message object number)(Data offset)

SFR’s on-chip CAN Controller registers

15 message objects

8bytes

TimStmp High

TimStmp Low

Ch.0 - ID Mask- 1

Ch.0 - ID Mask- 2

Ch.0-IDMask-4

Ch.0 - ID Mask- 3

CANTimer High

CANTimer Low

TimTTC High

TimTTC Low

TEC counter

REC counter

Timer Control

Enable message object - 1

Enable message object - 2

message object Window SFRs

Ch.0 TimStmp High

Ch.0 TimStmp Low

Ch.14 TimStmp High

Ch.14 TimStmp Low

General Interrupt

T89C51CC01

Rev. D – 17-Dec-01

15.2.1 Working on message

objects The Page message object register (CANPAGE) is used to select one of the 15 message

objects. Then, message object Control (CANCONCH) and message object Status

(CANSTCH) are available for this selected message object number in the corresponding

SFRs. A single register (CANMSG) is used for the message. The mailbox pointer is

managed by the Page message object register with an auto-incrementation at the end of

each access. The range of this counter is 8.

Note that the maibox is a pure RAM, dedicated to one message object, without overlap.

In most cases, it is not necessary to transfer the received message into the standard

memory. The message to be transmitted can be built directly in the maibox. Most calcu-

lations or tests can be executed in the mailbox area which provide quicker access.

15.3 CAN Controller

management In order to enable the CAN Controller correctly the following registers have to be

initialized:

• General Control (CANGCON),

• Bit Timing (CANBT 1,2&3),

• And for each page of 15 message objects

– message object Control (CANCONCH),

– message object Status (CANSTCH).

During operation, the CAN Enable message object registers 1&2 (CANEN 1&2) gives a

fast overview of the message objects availability.

The CAN messages can be handled by interrupt or polling modes.

A message object can be configured as follows:

• Transmit message object,

• Receive message object,

• Receive buffer message object.

• Disable

This configuration is made in the CONCH field of the CANCONCH register (see

Table 36).

When a message object is configured, the corresponding ENCH bit of CANEN 1&2 reg-

ister is set.

Table 36. Configuration for CONCH1:2

When a Transmitter or Receiver action of a message object is completed, the corre-

sponding ENCH bit of the CANEN 1&2 register is cleared. In order to re-enable the

message object, it is necessary to re-write the configuration in CANCONCH register.

Non-consecutive message objects can be used for all three types of message objects

(Transmitter, Receiver and Receiver buffer),

CONCH 1 CONCH 2 Type of message object

00disable

01Transmitter

10Receiver

1 1 Receiver buffer

74 T89C51CC01 Rev. D – 17-Dec-01

15.3.1 Buffer mode Any message object can be used to define one buffer, including non-consecutive mes-

sage objects, and with no limitation in number of message objects used up to 15.

Each message object of the buffer must be initialized CONCH2 = 1 and CONCH1 = 1;

Figure 32. Buffer mode

The same acceptance filter must be defined for each message objects of the buffer.

When there is no mask on the identifier or the IDE, all messages are accepted.

A received frame will always be stored in the lowest free message object.

When the flag Rxok is set on one of the buffer message objects, this message object

can then be read by the application. This flag must then be cleared by the software and

the message object re-enabled in buffer reception in order to free the message object.

The OVRBUF flag in the CANGIT register is set when the buffer is full. This flag can

generate an interrupt.

The frames following the buffer-full interrupt will not stored and no status will be over-

written in the CANSTCH registers involved in the buffer until at least one of the buffer

message objects is re-enabled in reception.

This flag must be cleared by the software in order to acknowledge the interrupt.

15.4 IT CAN management The different interrupts are:

• Transmission interrupt,

• Reception interrupt,

• Interrupt on error (bit error, stuff error, crc error, form error, acknowledge error),

• Interrupt when Buffer receive is full,

• Interrupt on overrun of CAN Timer.

message object 0

message object 1

message object 2

message object 3

message object 4

message object 5

message object 6

message object 7

message object 8

message object 9

message object 10

message object 11

message object 12

message object 13

Block buffer

buffer 0

buffer 1

buffer 2

buffer 3

buffer 4

buffer 5

buffer 6

buffer 7

message object 14

T89C51CC01

Rev. D – 17-Dec-01

Figure 33. CAN Controller interrupt structure

To enable a transmission interrupt:

• Enable General CAN IT in the interrupt system register,

• Enable interrupt by message object, EICHi,

• Enable transmission interrupt, ENTX.

To enable a reception interrupt:

• Enable General CAN IT in the interrupt system register,

• Enable interrupt by message object, EICHi,

• Enable reception interrupt, ENRX.

To enable an interrupt on message object error:

• Enable General CAN IT in the interrupt system register,

• Enable interrupt by message object, EICHi,

• Enable interrupt on error, ENERCH.

SIT i

i=0

i=14

OVRIT

ENRX

CANGIE.5 ENTX

CANGIE.4 ENERCH

CANGIE.3

ENBUF

CANGIE.2 ECAN

IEN1.0

RXOK i

CANSTCH.5

TXOK i

CANSTCH.6

BERR i

CANSTCH.4

SERR i

CANSTCH.3

FERR i

CANSTCH.1

CERR i

CANSTCH.2

AERR i

CANSTCH.0

EICH i

CANIE1/2

OVRTIM

CANGIT.5

CANIT

CANGIT.7

OVRBUF

CANGIT.4

FERG

CANGIT.1

AERG

CANGIT.0

SERG

CANGIT.3

CERG

CANGIT.2

ENERG

CANGIE.1

ETIM

IEN1.2

SIT i

CANSIT1/2

76 T89C51CC01 Rev. D – 17-Dec-01

To enable an interrupt on general error:

• Enable General CAN IT in the interrupt system register,

• Enable interrupt on error, ENERG.

To enable an interrupt on Buffer-full condition:

• Enable General CAN IT in the interrupt system register,

• Enable interrupt on Buffer full, ENBUF.

To enable an interrupt when Timer overruns:

• Enable Overrun IT in the interrupt system register.

When an interrupt occurs, the corresponding message object bit is set in the SIT

To acknowledge an interrupt, the corresponding CANSTCH bits (RXOK, TXOK,...) or

CANGIT bits (OVRTIM, OVRBUF,...), must be cleared by the software application.

When the CAN node is in transmission and detects a Form Error in its frame, a bit Error

will also be raised. Consequently, two consecutive interrupts can occur, both due to the

same error.

When a message object error occurs and is set in CANSTCH register, no general error

are set in CANGIE register.

15.5 Bit Timing and

BaudRate Figure 34. sample and transmission point

The baud rate selection is made by Tbit calculation:

Tbit = Tsyns + Tprs + Tphs1 + Tphs2

1. Tsyns = Tscl = (BRP[5..0]+ 1) / Fcan = 1TQ.

2. Tprs = (1 to 8) * Tscl = (PRS[2..0]+ 1) * Tscl

3. Tphs1 = (1 to 8) * Tscl = (PHS1[2..0]+ 1) * Tscl

4. Tphs2 = (1 to 8) * Tscl = (PHS2[2..0]+ 1) * Tscl

5. Tsjw = (1 to 4) * Tscl = (SJW[1..0]+ 1) * Tscl

The total number of Tscl (Time Quanta) in a bit time must be comprised between 8 to

25.

FCAN

CLOCK Prescaler BRP

PRS 3-bit length

PHS1 3-bit length

PHS2 3-bit length

SJW 2-bit length

Bit Timing

System clock Tscl

Time Quantum

Sample point

Transmission point

T89C51CC01

Rev. D – 17-Dec-01

Figure 35. General structure of a bit period

example of bit timing determination for CAN baudrate of 500kbit/s:

Fosc = 12 MHz in X1 mode => FCAN = 6MHz

Verify that the CANbaud rate you want is an integer division of FCAN clock.

FCAN/CANbaudrate = 6MHz/500kHz = 12

The time quanta TQ must be comprised between 8 and 25: TQ = 12 and BRP=0

Define the various timing parameters: Tbit = Tsyns + Tprs + Tphs1 + Tphs2 =

12TQ

Tsyns = 1TQ and Tsjw =1TQ => SJW=0

If we chose a sample point at 66.6% => Tphs2 = 4TQ => PHS2 = 3

Tbit=12=4+1+Tphs1 + Tprs, let us choose Tprs = 3 Tphs1 = 4

PHS1 = 3 and PRS=2

BRP=0soCANBT1 = 00h

SJW=0andPRS=2soCANBT2 = 04h

PHS2 = 3 and PHS1 = 3 so CANBT3 = 36h

Bit Rate Prescaler

oscillator

1/ Fcan

Tscl

system clock

one nominal bit

Tsyns (*) Tprs

Sample Point

(*) Synchronization Segment: SYNS

Tbit

Tsyns = 1xTscl (fixed)

data

Tbit Tsyns Tprs Tphs1Tphs2++ +=

Tbit calculation:

Transmission Point

Tphs1 + Tsjw (3) Tphs2 - Tsjw (4)

(1) Phase error £ 0

(2) Phase error Š 0

(3) Phase error > 0

(4) Phase error < 0

Tphs2 (2)

Tphs1 (1)

78 T89C51CC01 Rev. D – 17-Dec-01

15.6 Fault Confinement With respect to fault confinement, a unit may be in one of the three following status:

• error active,

• error passive,

• bus off.

An error active unit takes part in bus communication and can send an active error frame

when the CAN macro detects an error.

An error passive unit cannot send an active error frame. It takes part in bus communica-

tion, but when an error is detected, a passive error frame is sent. Also, after a

transmission, an error passive unit will wait before initiating further transmission.

A bus off unit is not allowed to have any influence on the bus.

For fault confinement, two error counters (TEC and REC) are implemented.

See CAN Specification for details on Fault confinement.

Figure 36. Line error mode

TEC>255

Error

Active

Error

Passive Bus

Off

Init.

TEC<127

and

REC<127

TEC>127

REC>127 128 occurrences

11 consecutive

recessive

bit

TEC: Transmit Error Counter

REC: Receive Error Counter

T89C51CC01

Rev. D – 17-Dec-01

15.7 Acceptance filter Upon a reception hit (i.e., a good comparison between the ID+RTR+RB+IDE received

and an ID+RTR+RB+IDE specified while taking the comparison mask into account) the

ID+RTR+RB+IDE received are written over the ID TAG Registers.

ID => IDT0-29

RTR => RTRTAG

RB => RB0-1TAG

IDE => IDE in CANCONCH register

Figure 37. Acceptance filter block diagram

example:

To accept only ID = 318h in part A.

ID MSK = 111 1111 1111 b

ID TAG = 011 0001 1000 b

13/32

RxDC

13/32

Write

13/32

Hit

13/32

ID MSK Registers (Ch i)

ID & RB RTR IDE

Rx Shift Register (internal)

ID & RB RTR IDE

Enable (Ch i)

ID TAG Registers (Ch i) & CanConch

ID & RB RTR IDE

80 T89C51CC01 Rev. D – 17-Dec-01

15.8 Data and Remote

frame Description of the different steps for:

•Dataframe,

• Remote frame, with automatic reply,

• Remote frame.

u uu uu

0 1 x 0 0 u uu uu

ENCH

RTR

RPLV

TXOK

RXOK

0 1 x 0 0

c uc uu

0 0 x 1 0 u cc uu

0 0 x 0 1

DATAFRAME

Node A Node B

ENCH

RTR

RPLV

TXOK

RXOK

message object in reception

message object stay in reception

message object in transmission

message object stay in

transmission

u uu uu

1 1 x 0 0

c uu uc

0 1 x 1 0

ucc uu

0 0 x 0 1

REMOTEFRAME

DATAFRAME

u uu uu

1 1 1 0 0

u uu cc

0 1 0 0 0

c uc cu

0 0 0 1 0

ENCH

RTR

RPLV

TXOK

RXOK

ENCH

RTR

RPLV

TXOK

RXOK

(immediate)

message object in reception

message object in transmission

message object stay in transmission

message object in transmission

message object in reception

message object stay in

by CAN controller by CAN controller

reception

u uu uu

1 1 x 0 0 u uu uu

ENCH

RTR

RPLV

TXOK

RXOK

1 1 0 0 0

c uu uc

0 1 x 1 0 u cc uu

1 0 0 0 1

REMOTEFRAME

ENCH

RTR

RPLV

TXOK

RXOK

u uu uu

0 1 x 0 0

c uc uu

0 0 x 1 0

u cc uc

0 0 x 0 1

DATAFRAME

(deferred)

u: modified by user

ic:modifiedbyCAN

message object in reception

message object in transmission by user

message object stay in transmission

message object stay in reception

message object in transmission

message object in reception

by CAN controller

by user

T89C51CC01

Rev. D – 17-Dec-01

15.9 Time Trigger

Communication (TTC)

and Message Stamping

The T89C51CC01 has a programmable 16-bit Timer (CANTIMH&CANTIML) for mes-

sage stamp and TTC.

This CAN Timer starts after the CAN controller is enabled by the ENA bit in the CANG-

CON register.

Two modes in the timer are implemented:

• Time Trigger Communication:

– Capture of this timer value in the CANTTCH & CANTTCL registers on Start

Of Frame (SOF) or End Of Frame (EOF), depending on the SYNCTTC bit in

the CANGCON register, when the network is configured in TTC by the TTC

bit in the CANGCON register.

Note: In this mode, CAN only sends the frame once, even if an error occurs.

• Message Stamping

– Capture of this timer value in the CANSTMPH & CANSTMPL registers of the

message object which received or sent the frame.

– All messages can be stamps.

– The stamping of a received frame occurs when the RxOk flag is set.

– The stamping of a sent frame occurs when the TxOk flag is set.

The CAN Timer works in a roll-over from FFFFh to 0000h which serves as a time base.

When the timer roll-over from FFFFh to 0000h, an interrupt is generated if the ETIM bit

in the interrupt enable register IEN1 is set.

Figure 38. Block diagram of CAN Timer

EOF on CAN frame

ENA

CANGCON.1

CANTCON

RXOK i

CANSTCH.5

TXOK i

CANSTCH.4

÷6

Fcan

CLOCK

SOF on CAN frame

TTC

CANGCON.5 SYNCTTC

CANGCON.4

CANTTCH & CANTTCL

CANSTMPH & CANSTMPL

CANTIMH & CANTIML

OVRTIM

CANGIT.5

When 0xFFFF to 0x0000

82 T89C51CC01 Rev. D – 17-Dec-01

15.10 CAN Autobaud and

Listening mode To activate the Autobaud feature, the AUTOBAUD bit in the CANGCON register must

be set. In this mode, the CAN controller is only listening to the line without acknowledg-

ing the received messages. It cannot send any message. The error flags are updated.

The bit timing can be adjusted until no error occurs (good configuration find).

In this mode, the error counters are frozen.

To go back to the standard mode, the AUTOBAUD bit must be cleared.

Figure 39. Autobaud Mode

15.11 Routines Examples 1. Init of CAN macro

// Reset the CAN macro

CANGCON = 01h;

// Disable CAN interrupts

ECAN = 0;

ETIM = 0;

// Init the Mailbox

for num_page =0; num_page <15; num_page++

{

CANPAGE = num_channel << 4;

CANCONCH = 00h

CANSTCH = 00h;

CANIDT1 = 00h;

CANIDT2 = 00h;

CANIDT3 = 00h;

CANIDT4 = 00h;

CANIDM1 = 00h;

CANIDM2 = 00h;

CANIDM3 = 00h;

CANIDM4 = 00h;

for num_data =0; num_data <8; num_data++)

{

CANMSG = 00h;

}

// Configure the bit timing

CANBT1 = xxh

CANBT2 = xxh

CANBT3 = xxh

TxDC

RxDC’

AUTOBAUD

CANGCON.3 RxDC

TxDC’

T89C51CC01

Rev. D – 17-Dec-01

// Enable the CAN macro

CANGCON = 02h

2. Configure message object 3 in reception to receive only standard (11-bit identi-

fier) message 100h

// Select the message object 3

CANPAGE = 30h

// Enable the interrupt on this message object

CANIE2 = 08h

// Clear the status and control register

CANSTCH = 00h

CANCONCH= 00h

// Init the acceptance filter to accept only message 100h in standard mode

CANIDT1 = 20h

CANIDT2 = 00h

CANIDT3 = 00h

CANIDT4 = 00h

CANIDM1 = FFh

CANIDM2 = FFh

CANIDM3 = FFh

CANIDM4 = FFh

// Enable channel in reception

CANCONCH = 88h // enable reception

Note: to enable the CAN interrupt in reception:

EA = 1

ECAN = 1

CANGIE = 20h

3. Send a message on the message object 12

// Select the message object 12

CANPAGE = C0h

// Enable the interrupt on this message object

CANIE1 = 01h

// Clear the Status register

CANSTCH = 00h;

// load the identifier to send (ex: 555h)

CANIDT1 = AAh;

CANIDT2 = A0h;

// load data to send

CANMSG = 00h

CANMSG = 01h

CANMSG = 02h

CANMSG = 03h

CANMSG = 04h

CANMSG = 05h

CANMSG = 06h

CANMSG = 07h

// configure the control register

CANCONCH = 18h

4. Interrupt routine

// Save the current CANPAGE

84 T89C51CC01 Rev. D – 17-Dec-01

// Find the first message object which generate an interrupt in CANSIT1 and

CANSIT2

// Select the corresponding message object

// Analyse the CANSTCH register to identify which kind of interrupt is

generated

// Manage the interrupt

// Clear the status register CANSTCH = 00h;

// if it is not a channel interrupt but a general interrupt

// Manage the general interrupt and clear CANGIT register

// restore the old CANPAGE

T89C51CC01

Rev. D – 17-Dec-01

15.12 CAN SFR’s Table 37. CAN SFR’s with reset values

0/8(1) 1/9 2/A 3/B 4/C 5/D 6/E 7/F

F8h IPL1

xxxx x000 CH

0000 0000 CCAP0H

0000 0000 CCAP1H

0000 0000 CCAP2H

0000 0000 CCAP3H

0000 0000 CCAP4H

0000 0000 FFh

F0h B

0000 0000 ADCLK

xx00 x000 ADCON

0000 0000 ADDL

xxxx xx00 ADDH

0000 0000 ADCF

0000 0000 IPH1

xxxx x000 F7h

E8h IEN1

xxxx x000 CL

0000 0000 CCAP0L

0000 0000 CCAP1L

0000 0000 CCAP2L

0000 0000 CCAP3L

0000 0000 CCAP4L

0000 0000 EFh

E0h ACC

0000 0000 E7h

D8h CCON

00xx xx00 CMOD

00xx x000 CCAPM0

x000 0000 CCAPM1

x000 0000 CCAPM2

x000 0000 CCAPM3

x000 0000 CCAPM4

x000 0000 DFh

D0h PSW

0000 0000 FCON

0000 0000 EECON

xxxx xx00 D7h

C8h T2CON

0000 0000 T2MOD

xxxx xx00 RCAP2L

0000 0000 RCAP2H

0000 0000 TL2

0000 0000 TH2

0000 0000 CANEN1

xx00 0000 CANEN2

0000 0000 CFh

C0h P4

xxxx xx11 CANGIE

0000 0000 CANIE1

xx00 0000 CANIE2

0000 0000 CANIDM1

xxxx xxxx CANIDM2

xxxx xxxx CANIDM3

xxxx xxxx CANIDM4

xxxx xxxx C7h

B8h IPL0

x000 0000 SADEN

0000 0000 CANSIT1

0x00 0000 CANSIT2

0000 0000 CANIDT1

xxxx xxxx CANIDT2

xxxx xxxx CANIDT3

xxxx xxxx CANIDT4

xxxx xxxx BFh

B0h P3

1111 1111 CANPAGE

0000 0000 CANSTCH

xxxx xxxx CANCONCH

xxxx xxxx CANBT1

xxxx xxxx CANBT2

xxxx xxxx CANBT3

xxxx xxxx IPH0

x000 0000 B7h

A8h IEN0

0000 0000 SADDR

0000 0000 CANGSTA

0000 0000 CANGCON

0000 x000 CANTIML

0000 0000 CANTIMH

0000 0000 CANSTMPL

0000 0000 CANSTMPH

0000 0000 AFh

A0h P2

1111 1111 CANTCON

0000 0000 AUXR1

0000 0000 CANMSG

xxxx xxxx CANTTCL

0000 0000 CANTTCH

0000 0000 WDTRST

1111 1111 WDTPRG

xxxx x000 A7h

98h SCON

0000 0000 SBUF

0000 0000 CANGIT

0x00 0000 CANTEC

0000 0000 CANREC

0000 0000 9Fh

90h P1

1111 1111 97h

88h TCON

0000 0000 TMOD

0000 0000 TL0

0000 0000 TL1

0000 0000 TH0

0000 0000 TH1

0000 0000 AUXR

0000 1000 CKCON

0000 0000 8Fh

80h P0

1111 1111 SP

0000 0111 DPL

0000 0000 DPH

0000 0000 PCON

0000 0000 87h

0/8(1) 1/9 2/A 3/B 4/C 5/D 6/E 7/F

86 T89C51CC01 Rev. D – 17-Dec-01

15.13 Registers Table 38. CANGCON Register

CANGCON (S:ABh)

CAN General Control Register

Reset Value: 0000 0x00b

7654 3210

ABRQ OVRQ TTC SYNCTTC AUTOBAUD TEST ENA GRES

Bit

Number Bit Mnemonic Description

7ABRQ

Abort request

Not an auto-resetable bit. A reset of the ENCH bit (message object control &

DLC register) is done for each message object. The pending transmission

communications are immediately aborted but the on-going communication will

be terminated normally, setting the appropriate status flags, TXOK or RXOK.

6OVRQ

Overload frame request (initiator).

Auto-resetable bit.

Set to send an overload frame after the next received message.

Cleared by the hardware at the beginning of transmission of the overload

frame.

5TTC

Network in Timer Trigger communication

set to select node in TTC.

clear to disable TTC features.

4 SYNCTTC

Synchronization of TTC

When this bit is set the TTC timer is caught on the last bit of the End Of Frame.

When this bit is clear the TTC timer is caught on the Start Of Frame.

This bit is only used in the TTC mode.

3 AUTOBAUD AUTOBAUD

set to active listening mode.

Clear to disable listening mode

2TEST

Test mode. The test mode is intended for factory testing and not for customer

use.

1ENA/STB

Enable/Standby CAN controller

When this bit is set, it enables the CAN controller and its input clock.

When this bit is clear, the on-going communication is terminated normally and

theCANcontrollerstateofthemachineisfrozen(theENCHbitofeach

message object does not change).

In the standby mode, the transmitter constantly provides a recessive level; the

receiver is not activated and the input clock is stopped in the CAN controller.

During the disable mode, the registers and the mailbox remain accessible.

Note that two clock periods are needed to start the CAN controller state of the

machine.

0GRES

General reset (software reset).

Auto-resetable bit. This reset command is ‘ORed’ with the hardware reset in

order to reset the controller. After a reset, the controller is disabled.

T89C51CC01

Rev. D – 17-Dec-01

Table 39. CANGSTA Register

CANGSTA (S:AAh)

CAN General Status Register

Note: 1. These fields are Read Only.

Reset Value: x0x0 0000b

76543210

- OVFG - TBSY RBSY ENFG BOFF ERRP

Bit

Number Bit

Mnemonic Description

Reserved

The values read from this bit is indeterminate. Do not set this bit.

6OVFG

Overload frame flag (1)

This status bit is set by the hardware as long as the produced overload frame is

sent.

This flag does not generate an interrupt

Reserved

The values read from this bit is indeterminate. Do not set this bit.

4 TBSY

Transmitter busy (1)

This status bit is set by the hardware as long as the CAN transmitter generates a

frame (remote, data, overload or error frame) or an ack field. This bit is also

active during an InterFrame Spacing if a frame must be sent.

This flag does not generate an interrupt.

3 RBSY

Receiver busy (1)

This status bit is set by the hardware as long as the CAN receiver acquires or

monitors a frame.

This flag does not generate an interrupt.

2ENFG

Enable on-chip CAN controller flag (1)

Because an enable/disable command is not effective immediately, this status bit

gives the true state of a chosen mode.

This flag does not generate an interrupt.

1BOFF

Bus off mode (1)

seeFigure36

0 ERRP Error passive mode (1)

seeFigure36

88 T89C51CC01 Rev. D – 17-Dec-01

Table 40. CANGIT Register

CANGIT (S:9Bh)

CAN General Interrupt

Note: 1. These fields are Read Only.

Reset Value: 0x00 0000b

76543210

CANIT - OVRTIM OVRBUF SERG CERG FERG AERG

Bit

Number Bit

Mnemonic Description

7CANIT

General interrupt flag (1)

This status bit is the image of all the CAN controller interrupts sent to the

interrupt controller.

Itcanbeusedinthecaseofthepollingmethod.

Reserved

The values read from this bit is indeterminate. Do not set this bit.

5OVRTIM

Overrun CAN Timer

This status bit is set when the CAN timer switches 0xFFFF to 0x0000.

If the bit ETIM in the IE1 register is set, an interrupt is generated.

Clear this bit in order to reset the interrupt.

4OVRBUF

Overrun BUFFER

0 - no interrupt.

1 - IT turned on

This bit is set when the buffer is full.

Bit resetable by user.

seeFigure33.

3 SERG Stuff error General

Detectionofmorethanfiveconsecutivebitswiththesamepolarity.

This flag can generate an interrupt. resetable by user.

2CERG

CRC error General

The receiver performs a CRC check on each destuffed received message from

thestartofframeuptothedatafield.

If this checking does not match with the destuffed CRC field, a CRC error is set.

This flag can generate an interrupt. resetable by user.

1FERG

Form error General

The form error results from one or more violations of the fixed form in the

following bit fields:

CRC delimiter

acknowledgment delimiter

end_of_frame

This flag can generate an interrupt. resetable by user.

0 AERG Acknowledgment error General

No detection of the dominant bit in the acknowledge slot.

This flag can generate an interrupt. resetable by user.

T89C51CC01

Rev. D – 17-Dec-01

Table 41. CANTEC Register

CANTEC (S:9Ch Read Only)

CAN Transmit Error Counter

Reset Value: 00h

Table 42. CANREC Register

CANREC (S:9Dh Read Only)

CAN Reception Error Counter

Reset Value: 00h

Table 43. CANGIE Register

CANGIE (S:C1h)

CAN General Interrupt Enable

76543210

TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0

Bit

Number Bit

Mnemonic Description

7-0 TEC7:0 Transmit Error Counter

seeFigure36

76543210

REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0

Bit

Number Bit

Mnemonic Description

7-0 REC7:0 Reception Error Counter

seeFigure36

76543210

- - ENRX ENTX ENERCH ENBUF ENERG -

Bit

Number Bit

Mnemonic Description

7-6 - Reserved

The values read from these bits are indeterminate. Do not set these bits.

5 ENRX Enable receive interrupt

0-Disable

1-Enable

4ENTX

Enable transmit interrupt

0-Disable

1-Enable

3 ENERCH Enable message object error interrupt

0-Disable

1-Enable

90 T89C51CC01 Rev. D – 17-Dec-01

Note: see Figure 33

Reset Value: xx00 000xb

Table 44. CANEN1 Register

CANEN1 (S:CEh Read Only)

CAN Enable message object

Registers 1

Reset Value: x000 0000b

2 ENBUF Enable BUF interrupt

0-Disable

1-Enable

1 ENERG Enable general error interrupt

0-Disable

1-Enable

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Bit

Number Bit

Mnemonic Description

76543210

- ENCH14 ENCH13 ENCH12 ENCH11 ENCH10 ENCH9 ENCH8

Bit

Number Bit

Mnemonic Description

Reserved

The values read from this bit is indeterminate. Do not set this bit.

6-0 ENCH14:8

Enable message object

0 - message object is disabled => the message object is free for a new emission

or reception.

1 - message object is enabled.

This bit is resetable by re-writing the CANCONCH of the corresponding message

object.

T89C51CC01

Rev. D – 17-Dec-01

Table 45. CANEN2 Register

CANEN2 (S:CFh Read Only)

CAN Enable message object

Registers 2

Reset Value: 0000 0000b

Table 46. CANSIT1 Register

CANSIT1 (S:BAh)

CAN Status Interrupt message

object Registers 1

Note: 1. This field is Read Only

Reset Value: x000 0000b

76543210

ENCH7 ENCH6 ENCH5 ENCH4 ENCH3 ENCH2 ENCH1 ENCH0

Bit

Number Bit

Mnemonic Description

7-0 ENCH7:0

Enable message object

0 - message object is disabled => the message object is free for a new emission

or reception.

1 - message object is enabled.

This bit is resetable by re-writing the CANCONCH of the corresponding message

object.

76543210

- SIT14 SIT13 SIT12 SIT11 SIT10 SIT9 SIT8

Bit

Number Bit

Mnemonic Description

Reserved

The values read from this bit is indeterminate. Do not set this bit.

6-0 SIT14:8

Status of interrupt by message object (1)

0 - no interrupt.

1 - IT turned on. Reset when interrupt condition is cleared by user.

SIT14:8 = 0b 0000 1001 -> IT’s on message objects 11 & 8.

seeFigure33.

92 T89C51CC01 Rev. D – 17-Dec-01

Table 47. CANSIT2 Register

CANSIT2 (S:BBh Read Only)

CAN Status Interrupt message

object Registers 2

Reset Value: 0000 0000b

Table 48. CANIE1 Register

CANIE1 (S:C2h)

CAN Enable Interrupt message

object Registers 1

Reset Value: x000 0000b

76543210

SIT7 SIT6 SIT5 SIT4 SIT3 SIT2 SIT1 SIT0

Bit

Number Bit

Mnemonic Description

7-0 SIT7:0

Status of interrupt by message object

0 - no interrupt.

1 - IT turned on. Reset when interrupt condition is cleared by user.

SIT7:0=0b00001001->IT’sonmessageobjects3&0.

seeFigure33.

76543210

- IECH14 IECH13 IECH12 IECH11 IECH10 IECH9 IECH8

Bit

Number Bit

Mnemonic Description

Reserved

The values read from this bit is indeterminate. Do not set this bit.

6-0 IECH14:8

Enable interrupt by message object

0 - disable IT.

1 - enable IT.

IECH14:8=0b00001100->EnableIT’sofmessageobjects11&10.

seeFigure33.

T89C51CC01

Rev. D – 17-Dec-01

Table 49. CANIE2 Register

CANIE2 (S:C3h)

CAN Enable Interrupt message

object Registers 2

Reset Value: 0000 0000b

Table 50. CANBT1 Register

CANBT1 (S:B4h)

CAN Bit Timing Registers 1

Note: The CAN controller bit timing registers must be accessed only if the CAN controller is dis-

abled with the ENA bit of the CANGCON register set to 0.

See Figure 35.

No default value after reset.

76543210

IECH 7 IECH 6 IECH 5 IECH 4 IECH 3 IECH 2 IECH 1 IECH 0

Bit

Number Bit

Mnemonic Description

7-0 IECH7:0

Enable interrupt by message object

0 - disable IT.

1 - enable IT.

IECH7:0 = 0b 0000 1100 -> Enable IT’s of message objects 3 & 2.

76543210

- BRP 5 BRP 4 BRP 3 BRP 2 BRP 1 BRP 0 -

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6-1 BRP5:0

Baud rate prescaler

The period of the CAN controller system clock Tscl is programmable and

determines the individual bit timing.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Tscl = BRP[5..0] + 1

Fcan

94 T89C51CC01 Rev. D – 17-Dec-01

Table 51. CANBT2 Register

CANBT2 (S:B5h)

CAN Bit Timing Registers 2

Note: The CAN controller bit timing registers must be accessed only if the CAN controller is dis-

abled with the ENA bit of the CANGCON register set to 0.

See Figure 35.

No default value after reset.

76543210

- SJW 1 SJW 0 - PRS 2 PRS 1 PRS 0 -

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6-5 SJW1:0

Re-synchronization jump width

To compensate for phase shifts between clock oscillators of different bus

controllers, the controller must re-synchronize on any relevant signal edge of the

current transmission.

The synchronization jump width defines the maximum number of clock cycles. A

bit period may be shortened or lengthened by a re-synchronization.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3-1 PRS2:0

Programming time segment

This part of the bit time is used to compensate for the physical delay times within

the network. It is twice the sum of thesignal propagationtime on thebus line, the

input comparator delay and the output driver delay.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Tsjw = Tscl x (SJW [1..0] +1)

Tprs = Tscl x (PRS[2..0] + 1)

T89C51CC01

Rev. D – 17-Dec-01

Table 52. CANBT3 Register

CANBT3 (S:B6h)

CAN Bit Timing Registers 3

Note: The CAN controller bit timing registers must be accessed only if the CAN controller is dis-

abled with the ENA bit of the CANGCON register set to 0.

See Figure 35.

No default value after reset.

76543210

- PHS2 2 PHS2 1 PHS2 0 PHS1 2 PHS1 1 PHS1 0 SMP

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6-4 PHS2 2:0

Phase segment 2

This phase is used to compensate for phase edge errors. This segment can be

shortened by the re-synchronization jump width.

3-1 PHS1 2:0

Phase segment 1

This phase is used to compensate for phase edge errors. This segment can be

lengthened by the re-synchronization jump width.

0SMP

Sample type

0 - once, at the sample point.

1 - three times, the threefold sampling of the bus is the sample point and twice

over a distance of a 1/2 period of the Tscl. The result corresponds to the majority

decision of the three values.

Tphs2 = Tscl x (PHS2[2..0] + 1)

Tphs1 = Tscl x (PHS1[2..0] + 1)

96 T89C51CC01 Rev. D – 17-Dec-01

Table 53. CANPAGE Register

CANPAGE (S:B1h)

CAN message object Page

Reset Value: 0000 0000b

Table 54. CANCONCH Register

CANCONCH (S:B3h)

CAN message object Control

and DLC Register

76543210

CHNB 3 CHNB 2 CHNB 1 CHNB 0 AINC INDX2 INDX1 INDX0

Bit

Number Bit

Mnemonic Description

7-4 CHNB3:0 Selection of message object number

The available numbers are: 0 to 14 (see Figure 31).

3AINC

Auto increment of the index (active low)

0 - auto-increment of the index (default value).

1 - non-auto-increment of the index.

2-0 INDX2:0 Index

Byte location of the data field for the defined message object (see Figure 31).

76543210

CONCH 1 CONCH 0 RPLV IDE DLC 3 DLC 2 DLC 1 DLC 0

Bit

Number Bit

Mnemonic Description

7-6 CONCH1:

Configuration of message object

CONCH1 CONCH0

0 0: disable

0 1: Launch transmission

1 0: Enable Reception

1 1: Enable Reception Buffer

NOTE:

The user must re-write the configuration to enable the corresponding bit in the

CANEN1:2 registers.

5RPLV

Reply valid

Used in the automatic reply mode after receiving a remote frame

0 - reply not ready.

1 - reply ready & valid.

4IDE

Identifier extension

0-CANstandardrev2.0A(ident=11bits).

1 - CAN standard rev 2.0 B (ident = 29 bits).

T89C51CC01

Rev. D – 17-Dec-01

No default value after reset

Table 55. CANSTCH Register

CANSTCH (S:B2h)

CAN message object Status

3-0 DLC3:0

Data length code

Number of bytes in the data field of the message.

The range of DLC is from 0 up to 8.

This value is updated when a frame is received (data or remote frame).

If the expected DLC differs from the incoming DLC, a warning appears in the

CANSTCH register.

Bit

Number Bit

Mnemonic Description

76543210

DLCW TXOK RXOK BERR SERR CERR FERR AERR

Bit

Number Bit

Mnemonic Description

7DLCW

Data length code warning

The incoming message does not have the DLC expected. Whatever the frame

type, the DLC field of the CANCONCH register is updated by the received DLC.

6TXOK

Transmit OK

The communication enabled by transmission is completed.

When the controller is readyto send a frame, if twoor moremessage objects are

enabled as producers, the lower index message object (0 to 13) is supplied first.

This flag can generate an interrupt.

5RXOK

Receive OK

The communication enabled by reception is completed.

In the case of two or more message object reception hits, the lower index

message object (0 to 13) is updated first.

This flag can generate an interrupt.

4 BERR

Bit error (only in transmission)

The bit value monitored is different from the bit value sent.

Exceptions:

the monitored recessive bit sent as a dominant bit during the arbitration field and

the acknowledge slot detecting a dominant bit during the sending of an error

frame.

This flag can generate an interrupt.

3 SERR Stuff error

Detectionofmorethanfiveconsecutivebitswiththesamepolarity.

This flag can generate an interrupt.

2CERR

CRC error

The receiver performs a CRC check on each destuffed received message from

thestartofframeuptothedatafield.

If this checking does not match with the destuffed CRC field, a CRC error is set.

This flag can generate an interrupt.

98 T89C51CC01 Rev. D – 17-Dec-01

Note: See Figure 33.

No default value after reset.

Table 56. CANIDT1 Register for V2.0 part A

CANIDT1 for V2.0 part A

(S:BCh)

CAN Identifier Tag Registers 1

No default value after reset.

Table 57. CANIDT2 Register for V2.0 part A

CANIDT2 for V2.0 part A

(S:BDh)

CAN Identifier Tag Registers 2

No default value after reset.

1FERR

Form error

The form error results from one or more violations of the fixed form in the

following bit fields:

CRC delimiter

acknowledgment delimiter

end_of_frame

This flag can generate an interrupt.

0 AERR Acknowledgment error

No detection of the dominant bit in the acknowledge slot.

This flag can generate an interrupt.

Bit

Number Bit

Mnemonic Description

76543210

IDT 10 IDT 9 IDT 8 IDT 7 IDT 6 IDT 5 IDT 4 IDT 3

Bit

Number Bit

Mnemonic Description

7-0 IDT10:3 IDentifier tag value

See Figure 37.

76543210

IDT 2 IDT 1 IDT 0 - - - - -

Bit

Number Bit

Mnemonic Description

7-5 IDT2:0 IDentifier tag value

See Figure 37.

4-0 - Reserved

The values read from these bits are indeterminate. Do not set these bits.

T89C51CC01

Rev. D – 17-Dec-01

Table 58. CANIDT3 Register for V2.0 part A

CANIDT3 for V2.0 part A

(S:BEh)

CAN Identifier Tag Registers 3

No default value after reset.

CANIDT4 for V2.0 part A

(S:BFh)

CAN Identifier Tag Registers 4

No default value after reset.

Table 59. CANIDT4 Register for V2.0 part A

CANIDT1 for V2.0 part B

(S:BCh)

CAN Identifier Tag Registers 1

No default value after reset.

76543210

--------

Bit

Number Bit

Mnemonic Description

7-0 - Reserved

The values read from these bits are indeterminate. Do not set these bits.

76543210

- - - - - RTRTAG - RB0TAG

Bit

Number Bit

Mnemonic Description

7-3 - Reserved

The values read from these bits are indeterminate. Do not set these bits.

2RTRTAG

Note: Remote transmission request tag value.

Reserved

The values read from this bit are indeterminate. Do not set these bit.

0RB0TAG

Note: Reserved bit 0 tag value.

76543210

IDT 28 IDT 27 IDT 26 IDT 25 IDT 24 IDT 23 IDT 22 IDT 21

Bit

Number Bit

Mnemonic Description

7-0 IDT28:21 IDentifier tag value

See Figure 37.

100 T89C51CC01 Rev. D – 17-Dec-01

Table 60. CANIDT2 Register for V2.0 part B

CANIDT2 for V2.0 part B

(S:BDh)

CAN Identifier Tag Registers 2

No default value after reset.

Table 61. CANIDT3 Register for V2.0 part B

CANIDT3 for V2.0 part B

(S:BEh)

CAN Identifier Tag Registers 3

No default value after reset.

Table 62. CANIDT4 Register for V2.0 part B

CANIDT4 for V2.0 part B

(S:BFh)

CAN Identifier Tag Registers 4

No default value after reset.

76543210

IDT 20 IDT 19 IDT 18 IDT 17 IDT 16 IDT 15 IDT 14 IDT 13

Bit

Number Bit

Mnemonic Description

7-0 IDT20:13 IDentifier tag value

See Figure 37.

76543210

IDT 12 IDT 11 IDT 10 IDT 9 IDT 8 IDT 7 IDT 6 IDT 5

Bit

Number Bit

Mnemonic Description

7-0 IDT12:5 IDentifier tag value

See Figure 37.

76543210

IDT 4 IDT 3 IDT 2 IDT 1 IDT 0 RTRTAG RB1TAG RB0TAG

Bit

Number Bit

Mnemonic Description

7-3 IDT4:0 IDentifier tag value

See Figure 37.

2RTRTAGRemote transmission request tag value

1RB1TAG

Note: Reserved bit 1 tag value.

0RB0TAG

Note: Reserved bit 0 tag value.

101

T89C51CC01

Rev. D – 17-Dec-01

Table 63. CANIDM1 Register for V2.0 part A

CANIDM1 for V2.0 part A

(S:C4h)

CAN Identifier Mask Registers 1

No default value after reset.

Table 64. CANIDM2 Register for V2.0 part A

CANIDM2 for V2.0 part A

(S:C5h)

CAN Identifier Mask Registers 2

No default value after reset.

Table 65. CANIDM3 Register for V2.0 part A

CANIDM3 for V2.0 part A

(S:C6h)

CAN Identifier Mask Registers 3

No default value after reset.

76543210

IDMSK 10 IDMSK 9 IDMSK 8 IDMSK 7 IDMSK 6 IDMSK 5 IDMSK 4 IDMSK 3

Bit

Number Bit

Mnemonic Description

7-0 IDTMSK10

IDentifier mask value

0 - comparison true forced.

1 - bit comparison enabled.

See Figure 37.

76543210

IDMSK 2 IDMSK 1 IDMSK 0 - - - - -

Bit

Number Bit

Mnemonic Description

7-5 IDTMSK2:

IDentifier mask value

0 - comparison true forced.

1 - bit comparison enabled.

See Figure 37.

4-0 - Reserved

The values read from these bits are indeterminate. Do not set these bits.

76543210

--------

Bit

Number Bit

Mnemonic Description

7-0 - Reserved

The values read from these bits are indeterminate.

102 T89C51CC01 Rev. D – 17-Dec-01

Table 66. CANIDM4 Register for V2.0 part A

CANIDM4 for V2.0 part A

(S:C7h)

CAN Identifier Mask Registers 4

Note: The ID Mask is only used for reception.

No default value after reset.

Table 67. CANIDM1 Register for V2.0 part B

CANIDM1 for V2.0 part B

(S:C4h)

CAN Identifier Mask Registers 1

Note: The ID Mask is only used for reception.

No default value after reset.

76543210

- - - - - RTRMSK - IDEMSK

Bit

Number Bit

Mnemonic Description

7-3 - Reserved

The values read from these bits are indeterminate. Do not set these bits.

2RTRMSK

Remote transmission request mask value

0 - comparison true forced.

1 - bit comparison enabled.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

0IDEMSK

IDentifier Extension mask value

0 - comparison true forced.

1 - bit comparison enabled.

76543210

IDMSK28 IDMSK27 IDMSK26 IDMSK25 IDMSK24 IDMSK23 IDMSK22 IDMSK21

Bit

Number Bit

Mnemonic Description

7-0 IDMSK28:

IDentifier mask value

0 - comparison true forced.

1 - bit comparison enabled.

See Figure 37.

103

T89C51CC01

Rev. D – 17-Dec-01

Table 68. CANIDM2 Register for V2.0 part B

CANIDM2 for V2.0 part B

(S:C5h)

CAN Identifier Mask Registers 2

Note: The ID Mask is only used for reception.

No default value after reset.

Table 69. CANIDM3 Register for V2.0 part B

CANIDM3 for V2.0 part B

(S:C6h)

CAN Identifier Mask Registers 3

Note: The ID Mask is only used for reception.

No default value after reset.

76543210

IDMSK20 IDMSK19 IDMSK18 IDMSK17 IDMSK16 IDMSK15 IDMSK14 IDMSK13

Bit

Number Bit

Mnemonic Description

7-0 IDMSK20:

IDentifier mask value

0 - comparison true forced.

1 - bit comparison enabled.

See Figure 37.

76543210

IDMSK 12 IDMSK 11 IDMSK 10 IDMSK 9 IDMSK 8 IDMSK 7 IDMSK 6 IDMSK 5

Bit

Number Bit

Mnemonic Description

7-0 IDMSK12:

IDentifier mask value

0 - comparison true forced.

1 - bit comparison enabled.

See Figure 37.

104 T89C51CC01 Rev. D – 17-Dec-01

Table 70. CANIDM4 Register for V2.0 part B

CANIDM4 for V2.0 part B

(S:C7h)

CAN Identifier Mask Registers 4

Note: The ID Mask is only used for reception.

No default value after reset.

Table 71. CANMSG Register

CANMSG (S:A3h)

CAN Message Data Register

No default value after reset.

76543210

IDMSK 4 IDMSK 3 IDMSK 2 IDMSK 1 IDMSK 0 RTRMSK - IDEMSK

Bit

Number Bit

Mnemonic Description

7-3 IDMSK4:0

IDentifier mask value

0 - comparison true forced.

1 - bit comparison enabled.

See Figure 37.

2RTRMSK

Remote transmission request mask value

0 - comparison true forced.

1 - bit comparison enabled.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

0IDEMSK

IDentifier Extension mask value

0 - comparison true forced.

1 - bit comparison enabled.

76543210

MSG7 MSG6 MSG5 MSG4 MSG3 MSG2 MSG1 MSG0

Bit

Number Bit

Mnemonic Description

7-0 MSG7:0

Message data

This register contains the mailbox data byte pointed at the page message object

After writing in the page message object register, this byte is equal to the

specified message location (in the mailbox) of the pre-defined identifier + index.

If auto-incrementation is used, at the end of the data register writing or reading

cycle, the mailbox pointer is auto-incremented. The range of the counting is 8

with no end loop (0, 1,..., 7, 0,...)

105

T89C51CC01

Rev. D – 17-Dec-01

Table 72. CANTCON Register

CANTCON (S:A1h)

CAN Timer ClockControl

Reset Value: 00h

Table 73. CANTIMH Register

CANTIMH (S:ADh Read Only)

CAN Timer High

Reset Value: 0000 0000b

Table 74. CANTIML Register

CANTIML (S:ACh Read Only)

CAN Timer Low

Reset Value: 0000 0000b

76543210

TPRESC 7 TPRESC 6 TPRESC 5 TPRESC 4 TPRESC 3 TPRESC 2 TPRESC 1 TPRESC 0

Bit

Number Bit

Mnemonic Description

7-0 TPRESC7:

Timer Prescaler of CAN Timer

This register is a prescaler for the main timer upper counter

range=0to255.

See Figure 38.

76543210

CANGTIM

15 CANGTIM

14 CANGTIM

13 CANGTIM

12 CANGTIM

11 CANGTIM

10 CANGTIM

9CANGTIM

Bit

Number Bit

Mnemonic Description

7-0 CANGTIM

15:8 High byte of Message Timer

See Figure 38.

76543210

CANGTIM

7CANGTIM

6CANGTIM

5CANGTIM

4CANGTIM

3CANGTIM

2CANGTIM

1CANGTIM

Bit

Number Bit

Mnemonic Description

7-0 CANGTIM

7:0 Low byte of Message Timer

See Figure 38.

106 T89C51CC01 Rev. D – 17-Dec-01

Table 75. CANSTMPH Register

CANSTMPH (S:AFh Read Only)

CAN Stamp Timer High

No default value after reset

Table 76. CANSTMPL Register

CANSTMPL (S:AEh Read Only)

CAN Stamp Timer Low

No default value after reset

Table 77. CANTTCH Register

CANTTCH (S:A5h Read Only)

CAN TTC Timer High

Reset Value: 0000 0000b

76543210

TIMSTMP

15 TIMSTMP

14 TIMSTMP

13 TIMSTMP

12 TIMSTMP

11 TIMSTMP

10 TIMSTMP 9 TIMSTMP 8

Bit

Number Bit

Mnemonic Description

7-0 TIMSTMP

15:8 High byte of Time Stamp

See Figure 38.

76543210

TIMSTMP 7 TIMSTMP 6 TIMSTMP 5 TIMSTMP 4 TIMSTMP 3 TIMSTMP 2 TIMSTMP 1 TIMSTMP 0

Bit

Number Bit

Mnemonic Description

7-0 TIMSTMP

7:0 LowbyteofTimeStamp

See Figure 38.

76543210

TIMTTC 15 TIMTTC 14 TIMTTC 13 TIMTTC 12 TIMTTC 11 TIMTTC 10 TIMTTC 9 TIMTTC 8

Bit

Number Bit

Mnemonic Description

7-0 TIMTTC15

:8 High byte of TTC Timer

See Figure 38.

107

T89C51CC01

Rev. D – 17-Dec-01

Table 78. CANTTCL Register

CANTTCL(S:A4hReadOnly)

CAN TTC Timer Low

Reset Value: 0000 0000b

76543210

TIMTTC 7 TIMTTC 6 TIMTTC 5 TIMTTC 4 TIMTTC 3 TIMTTC 2 TIMTTC 1 TIMTTC 0

Bit

Number Bit

Mnemonic Description

7-0 TIMTTC7:

0Low byte of TTC Timer

See Figure 38.

108 T89C51CC01 Rev. D – 17-Dec-01

16. Programmable

Counter Array PCA The PCA provides more timing capabilities with less CPU intervention than the standard

timer/counters. Its advantages include reduced software overhead and improved accu-

racy. The PCA consists of a dedicated timer/counter which serves as the time base for

an array of five compare/capture modules. Its clock input can be programmed to count

any of the following signals:

• PCA clock frequency / 6 (see “clock” section)

• PCA clock frequency / 2

•Timer0overflow

• External input on ECI (P1.2)

Each compare/capture modules can be programmed in any one of the following modes:

• rising and/or falling edge capture,

• software timer,

• high-speed output,

• pulse width modulator.

Module 4 can also be programmed as a watchdog timer. see Section "PCA Watchdog

Timer".

When the compare/capture modules are programmed in capture mode, software timer,

or high speed output mode, an interrupt can be generated when the module executes its

function. All five modules plus the PCA timer overflow share one interrupt vector.

The PCA timer/counter and compare/capture modules share Port 1 for external I/Os.

Thesepinsarelistedbelow.IftheportisnotusedforthePCA,itcanstillbeusedfor

standard I/O.

16.1 PCA Timer The PCA timer is a common time base for all five modules (see Figure 40). The timer

count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (see Table

8) and can be programmed to run at:

• 1/6 the PCA clock frequency.

• 1/2 the PCA clock frequency.

• the Timer 0 overflow.

• the input on the ECI pin (P1.2).

PCA component External I/O Pin

16-bit Counter P1.2 / ECI

16-bit Module 0 P1.3 / CEX0

16-bit Module 1 P1.4 / CEX1

16-bit Module 2 P1.5 / CEX2

16-bit Module 3 P1.6 / CEX3

16-bit Module 4 P1.7 / CEX4

109

T89C51CC01

Rev. D – 17-Dec-01

Figure 40. PCA Timer/Counter

The CMOD register includes three additional bits associated with the PCA.

• The CIDL bit which allows the PCA to stop during idle mode.

• The WDTE bit which enables or disables the watchdog function on module 4.

• The ECF bit which when set causes an interrupt and the PCA overflow flag CF in

CCON register to be set when the PCA timer overflows.

The CCON register contains the run control bit for the PCA and the flags for the PCA

timer and each module.

• The CR bit must be set to run the PCA. The PCA is shut off by clearing this bit.

• The CF bit is set when the PCA counter overflows and an interrupt will be generated

if the ECF bit in CMOD register is set. The CF bit can only be cleared by software.

• The CCF0:4 bits are the flags for the modules (CCF0 for module0...) and are set by

hardware when either a match or a capture occurs. These flags also can be cleared

by software.

16.2 PCA modules Each one of the five compare/capture modules has six possible functions. It can

perform:

• 16-bit Capture, positive-edge triggered

• 16-bit Capture, negative-edge triggered

• 16-bit Capture, both positive and negative-edge triggered

• 16-bit Software Timer

• 16-bit High Speed Output

• 8-bit Pulse Width Modulator.

In addition module 4 can be used as a Watchdog Timer.

CIDL CPS1 CPS0 ECF

CH CL

16 bit up/down counter

To PCA

modules

FPca/6

FPca / 2

T0 OVF

P1.2

Idle

CMOD

0xD9

WDTE

CF CR CCON

0xD8

CCF4 CCF3 CCF2 CCF1 CCF0

overflow

110 T89C51CC01 Rev. D – 17-Dec-01

Each module in the PCA has a special function register associated with it (CCAPM0 for

module 0 ...). The CCAPM0:4 registers contain the bits that control the mode that each

module will operate in.

• The ECCF bit enables the CCF flag in the CCON register to generate an interrupt

when a match or compare occurs in the associated module.

• The PWM bit enables the pulse width modulation mode.

• The TOG bit when set causes the CEX output associated with the module to toggle

when there is a match between the PCA counter and the module’s capture/compare

• The match bit MAT when set will cause the CCFn bit in the CCON register to be set

when there is a match between the PCA counter and the module’s capture/compare

• The two bits CAPN and CAPP in CCAPMn register determine the edge that a

capture input will be active on. The CAPN bit enables the negative edge, and the

CAPP bit enables the positive edge. If both bits are set both edges will be enabled.

• The bit ECOM in CCAPM register when set enables the comparator function.

16.3 PCA Interrupt Figure 41. PCA Interrupt System

16.4 PCA Capture Mode To use one of the PCA modules in capture mode either one or both of the CCAPM bits

CAPN and CAPP for that module must be set. The external CEX input for the module

(on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware

loads the value of the PCA counter registers (CH and CL) into the module’s capture reg-

isters (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the

ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated.

CF CR CCON

CCF4 CCF3 CCF2 CCF1 CCF0

Module 4

Module 3

Module 2

Module 1

Module 0

PCA Timer/Counter

ECCFn

CCAPMn.0

To Interrupt

IEN0.7

IEN0.6

ECF

CMOD.0

111

T89C51CC01

Rev. D – 17-Dec-01

Figure 42. PCA Capture Mode

16.5 16-bit Software

Timer Mode The PCA modules can be used as software timers by setting both the ECOM and MAT

bits in the modules CCAPMn register. The PCA timer will be compared to the module’s

capture registers and when a match occurs an interrupt will occur if the CCFn (CCON

SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set.

Figure 43. PCA 16-bit Software Timer and High Speed Output Mode

CEXn

n=0,4

PCACounter

(8bits) CL

(8bits)

CCAPnH CCAPnL

CCFn

CCON

PCA

Interrupt

Request

- 0CAPPnCAPNn000ECCFn

7CCAPMn Register (n = 0, 4) 0

CCAPnL

(8 bits)

CCAPnH

-ECOMn0 0MATn TOGn0 ECCFn

70 CCAPMn Register

(n = 0, 4)

(8 bits) CL

(8 bits)

16-Bit Com-

parator

Match

Enable CCFn

CCON reg

PCA

Interrupt

Request

CEXn

Compare/Capture Module

PCA Counter

“0”

“1”

Reset

Write to

CCAPnL

WritetoCCAPnH

For software Timer mode, set ECOMn and MATn.

For high speed output mode, set ECOMn, MATn and TOGn.

Toggle

112 T89C51CC01 Rev. D – 17-Dec-01

16.6 High Speed Output

Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle

each time a match occurs between the PCA counter and the module’s capture registers.

To activate this mode the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR

must be set.

Figure 44. PCA High speed Output Mode

16.7 Pulse Width

Modulator Mode All the PCA modules can be used as PWM outputs. The output frequency depends on

the source for the PCA timer. All the modules will have the same output frequency

because they all share the PCA timer. The duty cycle of each module is independently

variable using the module’s capture register CCAPLn. When the value of the PCA CL

SFR is less than the value in the module’s CCAPLn SFR the output will be low, when it

is equal to or greater than it, the output will be high. When CL overflows from FF to 00,

CCAPLn is reloaded with the value in CCAPHn. the allows the PWM to be updated with-

out glitches. The PWM and ECOM bits in the module’s CCAPMn register must be set to

enable the PWM mode.

CH CL

CCAPnH CCAPnL

ECOMn CCAPMn,n=0to4

0xDA to 0xDE

CAPNn MATn TOGn PWMn ECCFnCAPPn

16 bit comparator Match

CF CR CCON

0xD8

CCF4 CCF3 CCF2 CCF1 CCF0

PCA IT

Enable

CEXn

PCA counter/timer

“1”“0”

Write to

CCAPnL

Reset

Write to

CCAPnH

113

T89C51CC01

Rev. D – 17-Dec-01

Figure 45. PCA PWM Mode

16.8 PCA Watchdog

Timer An on-board watchdog timer is available with the PCA to improve system reliability with-

out increasing chip count. Watchdog timers are useful for systems that are sensitive to

noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that

can be programmed as a watchdog. However, this module can still be used for other

modes if the watchdog is not needed. The user pre-loads a 16-bit value in the compare

registers. Just like the other compare modes, this 16-bit value is compared to the PCA

timer value. If a match is allowed to occur, an internal reset will be generated. This will

not cause the RST pin to be driven high.

To hold off the reset, the user has three options:

• 1. periodically change the compare value so it will never match the PCA timer,

• 2. periodically change the PCA timer value so it will never match the compare

values, or

• 3. disable the watchdog by clearing the WDTE bit before a match occurs and then

re-enable it.

The first two options are more reliable because the watchdog timer is never disabled as

in option #3. If the program counter ever goes astray, a match will eventually occur and

cause an internal reset. If other PCA modules are being used the second option not rec-

ommended either. Remember, the PCA timer is the time base for all modules; changing

the time base for other modules would not be a good idea. Thus, in most applications

the first solution is the best option.

CL rolls over from FFh TO 00h loads

CCAPnH contents into CCAPnL

CCAPnL

CCAPnH

8-Bit

Comparator

CL (8 bits)

“0”

“1”

CL < CCAPnL

CL >= CCAPnL CEX

PWMn

CCAPMn.1

ECOMn

CCAPMn.6

114 T89C51CC01 Rev. D – 17-Dec-01

16.9 PCA Registers Table 79. CMOD Register

CMOD (S:D8h)

PCA Counter Mode Register

Reset Value = 00XX X000b

76543210

CIDL WDTE - - - CPS1 CPS0 ECF

Bit

Number Bit

Mnemonic Description

7CIDL

PCA Counter Idle Control bit

CleartoletthePCArunduringIdlemode.

SettostopthePCAwhenIdlemodeisinvoked.

6WDTE

Watchdog Timer Enable

Clear to disable Watchdog Timer function on PCA Module 4,

Set to enable it.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

2CPS1

EWC Count Pulse Select bits

CPS1 CPS0 Clock source

0 0 Internal Clock, FPca/6

0 1 Internal Clock, FPca/2

1 0 Timer 0 overflow

1 1 External clock at ECI/P1.2 pin (Max. Rate = FPca/4)

1CPS0

0ECF

Enable PCA Counter Overflow Interrupt bit

Clear to disable CF bit in CCON register to generate an interrupt.

Set to enable CF bit in CCON register to generate an interrupt.

115

T89C51CC01

Rev. D – 17-Dec-01

Table 80. CCON Register

CCON (S:D8h)

PCA Counter Control Register

Reset Value = 00X0 0000b

76543210

CF CR - CCF4 CCF3 CCF2 CCF1 CCF0

Bit

Number Bit

Mnemonic Description

7CF

PCA Timer/Counter Overflow flag

Set by hardware when the PCA Timer/Counter rolls over. This generates a PCA

interrupt request if the ECF bit in CMOD register is set.

Must be cleared by software.

6CR

PCA Timer/Counter Run Control bit

Clear to turn the PCA Timer/Counter off.

Set to turn the PCA Timer/Counter on.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

4CCF4

PCA Module 4 Compare/Capture flag

Set by hardware when a match or capture occurs. This generates a PCA

interrupt request if the ECCF 4 bit in CCAPM 4 register is set.

Must be cleared by software.

3CCF3

PCA Module 3 Compare/Capture flag

Set by hardware when a match or capture occurs. This generates a PCA

interrupt request if the ECCF 3 bit in CCAPM 3 register is set.

Must be cleared by software.

2CCF2

PCA Module 2 Compare/Capture flag

Set by hardware when a match or capture occurs. This generates a PCA

interrupt request if the ECCF 2 bit in CCAPM 2 register is set.

Must be cleared by software.

1CCF1

PCA Module 1 Compare/Capture flag

Set by hardware when a match or capture occurs. This generates a PCA

interrupt request if the ECCF 1 bit in CCAPM 1 register is set.

Must be cleared by software.

0CCF0

PCA Module 0 Compare/Capture flag

Set by hardware when a match or capture occurs. This generates a PCA

interrupt request if the ECCF 0 bit in CCAPM 0 register is set.

Must be cleared by software.

116 T89C51CC01 Rev. D – 17-Dec-01

Table 81. CCAPnH Registers

CCAP0H (S:FAh)

CCAP1H (S:FBh)

CCAP2H (S:FCh)

CCAP3H (S:FDh)

CCAP4H (S:FEh)

PCA High Byte

Compare/Capture Module n

Reset Value = 0000 0000b

Table 82. CCAPnL Registers

CCAP0L (S:EAh)

CCAP1L (S:EBh)

CCAP2L (S:ECh)

CCAP3L (S:EDh)

CCAP4L (S:EEh)

PCA Low Byte

Compare/Capture Module n

Reset Value = 0000 0000b

76543210

CCAPnH 7 CCAPnH 6 CCAPnH 5 CCAPnH 4 CCAPnH 3 CCAPnH 2 CCAPnH 1 CCAPnH 0

Bit

Number Bit

Mnemonic Description

7:0 CCAPnH

7:0 High byte of EWC-PCA comparison or capture values

76543210

CCAPnL 7 CCAPnL 6 CCAPnL 5 CCAPnL 4 CCAPnL 3 CCAPnL 2 CCAPnL 1 CCAPnL 0

Bit

Number Bit

Mnemonic Description

7:0 CCAPnL

7:0 Low byte of EWC-PCA comparison or capture values

117

T89C51CC01

Rev. D – 17-Dec-01

Table 83. CCAPMn Registers

CCAPM0 (S:DAh)

CCAPM1 (S:DBh)

CCAPM2 (S:DCh)

CCAPM3 (S:DDh)

CCAPM4 (S:DEh)

PCA Compare/Capture Module

n Mode registers (n=0..4)

Reset Value = X000 0000b

76543210

- ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

Bit

Number Bit

Mnemonic Description

Reserved

The Value read from this bit is indeterminate. Do not set this bit.

6ECOMn

Enable Compare Mode Module x bit

Clear to disable the Compare function.

Set to enable the Compare function.

The Compare function is used to implement the software Timer, the high-speed

output, the Pulse Width Modulator (PWM) and the Watchdog Timer (WDT).

5 CAPPn Capture Mode (Positive) Module x bit

Clear to disable the Capture function triggered by a positive edge on CEXx pin.

Set to enable the Capture function triggered by a positive edge on CEXx pin

4CAPNn

Capture Mode (Negative) Module x bit

Clear to disable the Capture function triggered by a negative edge on CEXx pin.

Set to enable the Capture function triggered by a negative edge on CEXx pin.

3MATn

Match Module x bit

Set when a match of the PCA Counter with the Compare/Capture register sets

CCFx bit in CCON register, flagging an interrupt.

2TOGn

Toggle Module x bit

The toggle mode is configured by setting ECOMx, MATx and TOGx bits.

Set when a match of the PCA Counter with the Compare/Capture register

toggles the CEXx pin.

1PWMn

Pulse Width Modulation Module x Mode bit

Set to configure the module x as an 8-bit Pulse Width Modulator with output

waveform on CEXx pin.

0 ECCFn Enable CCFx Interrupt bit

Clear to disable CCFx bit in CCON register to generate an interrupt request.

Set to enable CCFx bit in CCON register to generate an interrupt request.

118 T89C51CC01 Rev. D – 17-Dec-01

Table 84. CH Register

CH (S:F9h)

PCA Counter Register High

value

Reset Value = 0000 00000b

Table 85. CL Register

CL (S:E9h)

PCA counter Register Low value

Reset Value = 0000 00000b

76543210

CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0

Bit

Number Bit

Mnemonic Description

7:0 CH 7:0 High byte of Timer/Counter

76543210

CL 7 CL 6 CL 5 CL 4 CL 3 CL 2 CL 1 CL 0

Bit

Number Bit

Mnemonic Description

7:0 CL0 7:0 Low byte of Timer/Counter

119

T89C51CC01

Rev. D – 17-Dec-01

17. Analog-to-Digital

Converter (ADC) This section describes the on-chip 10 bit analog-to-digital converter of the

T89C51CC01. Eight ADC channels are available for sampling of the external sources

AN0 to AN7. An analog multiplexer allows the single ADC converter to select one from

the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10 bit-

cascaded potentiometric ADC.

Two kind of conversion are available:

- Standard conversion (8 bits).

- Precision conversion (10 bits).

For the precision conversion, set bit PSIDLE in ADCON register and start conversion.

The device is in a pseudo-idle mode, the CPU does not run but the peripherals are

always running. This mode allows digital noise to be as low as possible, to ensure high

precision conversion.

For this mode it is necessary to work with end of conversion interrupt, which is the only

way to wake the device up.

If another interrupt occurs during the precision conversion, it will be treated only after

this conversion is ended.

17.1 Features • 8 channels with multiplexed inputs

• 10-bit cascaded potentiometric ADC

• Conversion time 16 micro-seconds (typ.)

• Zero Error (offset) +/- 2 LSB max

• Positive External Reference Voltage Range (VREF) 2.4 to 3.0Volt (typ.)

• ADCINRange0to3Volt

• Integral non-linearity typical 1 LSB, max. 2 LSB

• Differential non-linearity typical 0.5 LSB, max. 1 LSB

• Conversion Complete Flag or Conversion Complete Interrupt

• Selectable ADC Clock

17.2 ADC Port1 I/O

Functions Port 1 pins are general I/O that are shared with the ADC channels. The channel select

bit in ADCF register define which ADC channel/port1 pin will be used as ADCIN. The

remaining ADC channels/port1 pins can be used as general purpose I/O or as the alter-

nate function that is available.

A conversion launched on a channel which are not selected on ADCF register will not

have any effect.

120 T89C51CC01 Rev. D – 17-Dec-01

Figure 46. ADC Description

Figure 47 shows the timing diagram of a complete conversion. For simplicity, the figure

depicts the waveforms in idealized form and do not provide precise timing information.

For ADC characteristics and timing parameters refer to the Section “AC Characteristics”

of the T89C51CC01 datasheet.

Figure 47. Timing Diagram

Note: Tsetup min = 4 us

Tconv=11 clock ADC = 1sample and hold + 10 bit conversion

The user must ensure that 4 us minimum time between setting ADEN and the start of the

first conversion.

17.3 ADC Converter

Operation A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).

After completion of the A/D conversion, the ADSST bit is cleared by hardware.

The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is

available in ADDH and ADDL, it must be cleared by software. If the bit EADC (IEN1.1) is

AN0/P1.0

AN1/P1.1

AN2/P1.2

AN3/P1.3

AN4/P1.4

AN5/P1.5

AN6/P1.6

AN7/P1.7

000

001

010

011

100

101

110

111

SCH2

ADCON.2 SCH0

ADCON.0

SCH1

ADCON.1

ADC

CLOCK

ADEN

ADCON.5 ADSST

ADCON.3

ADEOC

ADCON.4 ADC

Interrupt

Request

EADC

IEN1.1

CONTROL

AVSS

Sample and Hold

ADDH

VAREF

R/2R DAC

VAGND

-ADDL

SAR

ADCIN

ADEN

ADSST

ADEOC

TSETUP

TCONV

CLK

121

T89C51CC01

Rev. D – 17-Dec-01

set, an interrupt occur when flag ADEOC is set (see Figure 49). Clear this flag for re-

arming the interrupt.

ThebitsSCH0toSCH2inADCONregisterareusedfortheanaloginputchannel

selection.

Table 86. Selected Analog input

17.4 Voltage Conversion When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If

the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between

VAREF and VAGND are a straight-line linear conversion. All other voltages will result in

3FFh if greater than VAREF and 000h if less than VAGND.

Note that ADCIN should not exceed VAREF absolute maximum range! (see section

“AC-DC”)

17.5 Clock Selection The ADC clock is the same as CPU.

The maximum clock frequency for ADC is 700KHz. A prescaler is featured (ADCCLK) to

generate the ADC clock from the oscillator frequency.

Figure 48. A/D Converter clock

SCH2 SCH1 SCH0 Selected Analog input

000AN0

001AN1

010AN2

011AN3

100AN4

101AN5

110AN6

111AN7

Prescaler ADCLK A/D

Converter

ADC Clock

CPU

CLOCK

CPU Core Clock Symbol

÷ 2

122 T89C51CC01 Rev. D – 17-Dec-01

17.6 ADC Standby Mode When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN

in ADCON register. In this mode its power dissipation is about 1uW.

17.7 IT ADC management An interrupt end-of-conversion will occurs when the bit ADEOC is activated and the bit

EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software.

Figure 49. ADC interrupt structure

17.8 Routines examples 1. Configure P1.2 and P1.3 in ADC channels

// configure channel P1.2 and P1.3 for ADC

ADCF = 0Ch

// Enable the ADC

ADCON = 20h

2. Start a standard conversion

// The variable "channel" contains the channel to convert

// The variable "value_converted" is an unsigned int

// Clear the field SCH[2:0]

ADCON &= F8h

// Select channel

ADCON |= channel

// Start conversion in standard mode

ADCON |= 08h

// Wait flag End of conversion

while((ADCON & 01h)!= 01h)

// Clear the End of conversion flag

ADCON &= EFh

// read the value

value_converted = (ADDH << 2)+(ADDL)

3. Start a precision conversion (need interrupt ADC)

// The variable "channel" contains the channel to convert

// Enable ADC

EADC = 1

// clear the field SCH[2:0]

ADCON &= F8h

// Select the channel

ADCON |= channel

// Start conversion in precision mode

ADCON |= 48h

Note: to enable the ADC interrupt:

EA = 1

ADEOC

ADCON.2

EADC

IEN1.1

ADCI

123

T89C51CC01

Rev. D – 17-Dec-01

17.9 Registers Table 87. ADCF Register

ADCF (S:F6h)

ADC Configuration

Reset Value=0000 0000b

Table 88. ADCON Register

ADCON (S:F3h)

ADC Control Register

Reset Value=X000 0000b

76543210

CH 7 CH 6 CH 5 CH 4 CH 3 CH 2 CH 1 CH 0

Bit

Number Bit

Mnemonic Description

7-0 CH 0:7 Channel Configuration

Set to use P1.x as ADC input.

Clear to use P1.x as standart I/O port.

76543210

- PSIDLE ADEN ADEOC ADSST SCH2 SCH1 SCH0

Bit

Number Bit

Mnemonic Description

6 PSIDLE Pseudo Idle mode (best precision)

Set to put in idle mode during conversion

Clear to convert without idle mode.

5ADEN

Enable/Standby Mode

Set to enable ADC

Clear for Standby mode (power dissipation 1 uW).

4ADEOC

End Of Conversion

Set by hardware when ADC result is ready to be read. This flag can generate an

interrupt.

Must be cleared by software.

3 ADSST Start and Status

Set to start an A/D conversion.

Cleared by hardware after completion of the conversion

2-0 SCH2:0 Selection of channel to convert

see Table 86

124 T89C51CC01 Rev. D – 17-Dec-01

Table 89. ADCLK Register

ADCLK (S:F2h)

ADC Clock Prescaler

Reset Value: XXX0 0000b

Table 90. ADDH Register

ADDH (S:F5h Read Only)

ADC Data High byte register

Reset Value: 00h

Table 91. ADDL Register

ADDL (S:F4h Read Only)

ADC Data Low byte register

Reset Value: 00h

76543210

- - - PRS 4 PRS 3 PRS 2 PRS 1 PRS 0

Bit

Number Bit

Mnemonic Description

7-5 - Reserved

The value read from these bits are indeterminate. Do not set these bits.

4-0 PRS4:0 Clock Prescaler

fADC =fcpu clock/ (4 (or 2 in X2 mode)* (PRS +1))

76543210

ADAT 9 ADAT 8 ADAT 7 ADAT 6 ADAT 5 ADAT 4 ADAT 3 ADAT 2

Bit

Number Bit

Mnemonic Description

7-0 ADAT9:2 ADC result

bits 9-2

76543210

- - - - - - ADAT 1 ADAT 0

Bit

Number Bit

Mnemonic Description

7-2 - Reserved

The value read from these bits are indeterminate. Do not set these bits.

1-0 ADAT1:0 ADC result

bits 1-0

125

T89C51CC01

Rev. D – 17-Dec-01

18. Interrupt System

18.1 Introduction The CAN Controller has a total of 10 interrupt vectors: two external interrupts (INT0 and

INT1), three timer interrupts (timers 0, 1 and 2), a serial port interrupt, a PCA, a CAN

interrupt, a timer overrun interrupt and an ADC. These interrupts are shown below.

Figure 55. Interrupt Control System

ECAN

IEN1.0

EX0

IEN0.0

External

Interrupt 0

INT0#

IEN0.7

EX1

IEN0.2

External

Interrupt 1

INT1#

ET0

IEN0.1

Timer 0

IEN0.6

PCA

ET1

IEN0.3

Timer 1

IEN0.4

UART

EADC

IEN1.1

AtoD

Converter

ETIM

IEN1.2

CAN Timer

CAN

Interrupt Enable Lowest Priority Interrupts

Highest

Priority Enable

Priority

Interrupts

TxDC

RxDC

AIN1:0

IPH/L

controller

Timer 2

ET2

IEN0.5

TxD

RxD

CEX0:5

126 T89C51CC01 Rev. D – 17-Dec-01

Each of the interrupt sources can be individually enabled or disabled by setting or clear-

ing a bit in the Interrupt Enable register. This register also contains a global disable bit

which must be cleared to disable all the interrupts at the same time.

Each interrupt source can also be individually programmed to one of four priority levels

by setting or clearing a bit in the Interrupt Priority registers. The Table below shows the

bit values and priority levels associated with each combination.

Table 87. Priority Level Bit Values

A low-priority interrupt can be interrupted by a high priority interrupt but not by another

low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt

source.

If two interrupt requests of different priority levels are received simultaneously, the

request of the higher priority level is serviced. If interrupt requests of the same priority

level are received simultaneously, an internal polling sequence determines which

request is serviced. Thus within each priority level there is a second priority structure

determined by the polling sequence, see Table 88.

Table 88. Interrupt priority Within level

IPH.x IPL.x Interrupt Level Priority

0 0 0 (Lowest)

011

102

1 1 3 (Highest)

Interrupt Name Interrupt Address Vector Priority Number

external interrupt (INT0) 0003h 1

Timer0 (TF0) 000Bh 2

external interrupt (INT1) 0013h 3

Timer1 (TF1) 001Bh 4

PCA (CF or CCFn) 0033h 5

UART (RI or TI) 0023h 6

Timer2 (TF2) 002Bh 7

CAN (Txok, Rxok, Err or OvrBuf) 003Bh 8

ADC (ADCI) 0043h 9

CAN Timer Overflow (OVRTIM) 004Bh 10

127

T89C51CC01

Rev. D – 17-Dec-01

18.2 Registers Table 89. IEN0 Register

IEN0 (S:A8h)

Interrupt Enable Register

Reset Value: 0000 0000b

bit addressable

76543210

EA EC ET2 ES ET1 EX1 ET0 EX0

Bit

Number Bit

Mnemonic Description

7EA

Enable All interrupt bit

Clear to disable all interrupts.

Set to enable all interrupts.

If EA=1, each interrupt source is individually enabled or disabled by setting or

clearing its interrupt enable bit.

6EC

PCA Interrupt Enable

Clear to disable the PCA interrupt.

Set to enable the PCA interrupt.

5ET2

Timer 2 overflow interrupt Enable bit

Clear to disable timer 2 overflow interrupt.

Set to enable timer 2 overflow interrupt.

4ES

Serial port Enable bit

Clear to disable serial port interrupt.

Set to enable serial port interrupt.

3ET1

Timer 1 overflow interrupt Enable bit

Clear to disable timer 1 overflow interrupt.

Set to enable timer 1 overflow interrupt.

2EX1

External interrupt 1 Enable bit

Clear to disable external interrupt 1.

Set to enable external interrupt 1.

1ET0

Timer 0 overflow interrupt Enable bit

Clear to disable timer 0 overflow interrupt.

Set to enable timer 0 overflow interrupt.

0EX0

External interrupt 0 Enable bit

Clear to disable external interrupt 0.

Set to enable external interrupt 0.

128 T89C51CC01 Rev. D – 17-Dec-01

Table 90. IEN1 Register

IEN1 (S:E8h)

Interrupt Enable Register

Reset Value: xxxx x000b

bit addressable

76543210

- - - - ETIM EADC ECAN

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

2ETIM

TImer overrun Interrupt Enable bit

Clear to disable the timer overrun interrupt.

Set to enable the timer overrun interrupt.

1 EADC ADC Interrupt Enable bit

Clear to disable the ADC interrupt.

Set to enable the ADC interrupt.

0ECAN

CAN Interrupt Enable bit

Clear to disable the CAN interrupt.

Set to enable the CAN interrupt.

129

T89C51CC01

Rev. D – 17-Dec-01

Table 91. IPL0 Register

IPL0 (S:B8h)

Interrupt Enable Register

Reset Value: X000 0000b

bit addressable

76543210

- PPC PT2 PS PT1 PX1 PT0 PX0

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6 PPC PCA Interrupt Priority bit

Refer to PPCH for priority level

5PT2

Timer 2 overflow interrupt Priority bit

Refer to PT2H for priority level.

4PS

Serial port Priority bit

RefertoPSHforprioritylevel.

3PT1

Timer 1 overflow interrupt Priority bit

Refer to PT1H for priority level.

2PX1

External interrupt 1 Priority bit

Refer to PX1H for priority level.

1PT0

Timer 0 overflow interrupt Priority bit

Refer to PT0H for priority level.

0PX0

External interrupt 0 Priority bit

Refer to PX0H for priority level.

130 T89C51CC01 Rev. D – 17-Dec-01

Table 92. IPL1 Register

IPL1 (S:F8h)

Interrupt Priority Low Register 1

Reset Value: XXXX X000b

bit addressable

76543210

- - - - POVRL PADCL PCANL

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

2POVRL

Timer overrun Interrupt Priority level less significant bit.

Refer to PI2CH for priority level.

1 PADCL ADC Interrupt Priority level less significant bit.

Refer to PSPIH for priority level.

0 PCANL CAN Interrupt Priority level less significant bit.

Refer to PKBH for priority level.

131

T89C51CC01

Rev. D – 17-Dec-01

Table 93. IPL0 Register

IPH0 (B7h)

Interrupt High Priority Register

Reset Value: X000 0000b

76543210

- PPCH PT2H PSH PT1H PX1H PT0H PX0H

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6 PPCH

PCA Interrupt Priority level most significant bit

PPCH PPC Priority level

00Lowest

1 1 Highest priority

5PT2H

Timer 2 overflow interrupt High Priority bit

PT2H PT2 Priority Level

00Lowest

1 1 Highest

4 PSH

Serial port High Priority bit

PSH PS Priority Level

00Lowest

1 1 Highest

3PT1H

Timer 1 overflow interrupt High Priority bit

PT1H PT1 Priority Level

00Lowest

1 1 Highest

2PX1H

External interrupt 1 High Priority bit

PX1H PX1 Priority Level

00Lowest

1 1 Highest

1PT0H

Timer 0 overflow interrupt High Priority bit

PT0H PT0 Priority Level

00Lowest

1 1 Highest

0PX0H

External interrupt 0 high priority bit

PX0H PX0 Priority Level

00Lowest

1 1 Highest

132 T89C51CC01 Rev. D – 17-Dec-01

Table 94. IPH1 Register

IPH1 (S:FFh)

Interrupt high priority Register 1

Reset Value = XXXX X000b

76543210

- - - - POVRH PADCH PCANH

Bit

Number Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

2POVRH

Timer overrun Interrupt Priority level most significant bit

POVRH POVRLPriority level

00Lowest

11Highest

1 PADCH

ADC Interrupt Priority level most significant bit

PADCH PADCL Priority level

00Lowest

11Highest

0 PCANH

CAN Interrupt Priority level most significant bit

PCANH PCANLPriority level

00Lowest

11Highest

133

T89C51CC01

Rev. D – 17-Dec-01

19. Electrical Characteristics

19.1 Absolute Maximum

Ratings (1)

19.2 DC Parameters for Standard Voltage

TA=-40°Cto+85°C; VSS =0V;V

CC =5V±10%; F = 0 to 40 MHz.

Table 93. DC Parameters in Standard Voltage

Ambiant Temperature Under Bias:

I = industrial.................................................-40°Cto85°C

Storage Temperature ............................-65°C to + 150°C

Voltage on VCC from VSS..........................................-0.5 V to + 6V

Voltage on Any Pin from VSS............-0.5 V to VCC +0.2V

Power Dissipation................................................... 1 W(2)

Symbol Parameter Min Typ(5) Max Unit Test Conditions

VIL Input Low Voltage -0.5 0.2Vcc -

0.1 V

VIH Input High Voltage except XTAL1,

RST 0.2 VCC +

0.9 VCC +0.5 V

VIH1 Input High Voltage, XTAL1, RST 0.7 VCC VCC +0.5 V

VOL Output Low Voltage, ports 1, 2, 3

and 4(6)

0.3

0.45

1.0

IOL = 100 µA(4)

IOL =1.6mA

(4)

IOL =3.5mA

(4)

VOL1 Output Low Voltage, port 0, ALE,

PSEN (6)

0.3

0.45

1.0

IOL = 200 µA(4)

IOL =3.2mA

(4)

IOL =7.0mA

(4)

VOH Output High Voltage, ports 1, 2, 3,

4and5

VCC -0.3

VCC -0.7

VCC -1.5

IOH =-10µA

IOH =-30µA

IOH =-60µA

VCC =5V±10%

VOH1 Output High Voltage, port 0, ALE,

PSEN

VCC -0.3

VCC -0.7

VCC -1.5

IOH =-200µA

IOH =-3.2mA

IOH =-7.0mA

VCC =5V±10%

RRST RST Pulldown Resistor 20 40 200 kΩ

IIL Logical 0 Input Current ports 1, 2,

3and4 -50 µAVin=0.45V

ILI Input Leakage Current ±10 µA0.45 V < Vin <

VCC

Note: Stresses at or above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only and functional operation of the device

at these or any other conditions above those indicated in

the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions may affect

device reliability.This value is based on the maximum allow-

able die temperature and the thermal resistance of the

package.

134 T89C51CC01 Rev. D – 17-Dec-01

Notes: 1. Operating ICC is measured with all output pins disconnected; XTAL1 driven with

TCLCH,T

CHCL = 5 ns (see Figure 61.), VIL =V

SS +0.5V,

VIH =V

CC - 0.5V; XTAL2 N.C.; EA =RST=Port0=V

CC.I

CC would be slightly higher

if a crystal oscillator used (see Figure 58.).

2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH,

TCHCL =5ns,V

IL =V

SS +0.5V,V

IH =V

CC - 0.5 V; XTAL2 N.C; Port 0 = VCC;EA=RST

SS (see Figure 59.).

3. Power Down ICC is measured with all output pins disconnected; EA =V

CC,PORT0=

VCC;XTAL2NC.;RST=V

SS (see Figure 60.). In addition, the WDT must be inactive

and the POF flag must be set.

4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be super-

imposedontheV

OLs of ALE and Ports 1 and 3. The noise is due to external bus

capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0

transitions during bus operation. In the worst cases (capacitive loading 100pF), the

noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. A Schmitt

Trigger use is not necessary.

5. Typicals are based on a limited number of samples and are not guaranteed. The val-

ues listed are at room temperature.

6. Under steady state (non-transient) conditions, IOL must be externally limited as fol-

lows:

Maximum IOL per port pin: 10 mA

Maximum IOL per 8-bit port:

Port 0: 26 mA

Ports 1, 2 and 3: 15 mA

Maximum total IOL for all output pins: 71 mA

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are

not guaranteed to sink current greater than the listed test conditions.

ITL Logical 1 to 0 Transition Current,

ports 1, 2, 3 and 4 -650 µAVin=2.0V

CIO Capacitance of I/O Buffer 10 pF Fc = 1 MHz

TA=25°C

IPD Power Down Current 160 350 µA4.5V < VCC <

5.5V(3)

ICC

Power Supply Current

ICCOP =0.7Freq(MHz)+3mA

ICCIDLE =0.6Freq(MHz)+2mA

Symbol Parameter Min Typ(5) Max Unit Test Conditions

135

T89C51CC01

Rev. D – 17-Dec-01

Figure 58. ICC Test Condition, Active Mode

Figure 59. ICC Test Condition, Idle Mode

Figure 60. ICC Test Condition, Power-Down Mode

VCC

ICC

(NC)

CLOCK

SIGNAL

VCC

All other pins are disconnected.

RST

XTAL2

XTAL1

VSS

VCC

RST EA

XTAL2

XTAL1

VSS

VCC

ICC

(NC)

VCC

All other pins are disconnected.

CLOCK

SIGNAL

RST EA

XTAL2

XTAL1

VSS

VCC

ICC

(NC)

VCC

All other pins are disconnected.

136 T89C51CC01 Rev. D – 17-Dec-01
Figure 61. Clock Signal Waveform for ICC Tests in Active and Idle Modes
19.3 DC Parameters for A/D Converter
Table 94. DC Parameters for AD Converter in Precision conversion
Notes: 1. Typicals are based on a limited number of samples and are not guaranteed.
19.4 AC Parameters
19.4.1 Explanation of the AC
Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for
time). The other characters, depending on their positions, stand for the name of a signal
or the logical status of that signal. The following is a list of all the characters and what
they stand for.
Example:TAVLL = Time for Address Valid to ALE Low.
TLLPL = Time for ALE Low to PSEN Low.
TA=-40°Cto+85°C; VSS =0V;V
CC =5V±10%; F = 0 to 40 MHz.
TA=-40°Cto+85°C; VSS =0V;V
CC =5V±10%.
(Load Capacitance for port 0, ALE and PSEN = 60 pF; Load Capacitance for all other
outputs = 60 pF.)
Table 95, Table 98 and Table 101 give the description of each AC symbols.
Table 96, Table 100 and Table 102 give for each range the AC parameter.
Table 97, Table 100 and Table 103 give the frequency derating formula of the AC
parameter for each speed range description. To calculate each AC symbols. take the x
value and use this value in the formula.
Example: TLLIV and 20 MHz, Standard clock.
x = 30 ns
T = 50 ns
TCCIV = 4T - x = 170 ns
VCC-0.5V
0.45V 0.7VCC
0.2VCC-0.1
TCLCH
TCHCL
TCLCH =T
CHCL =5ns.
Symbol Parameter Min Typ(1) Max Unit Test Conditions
AVin Analog input voltage Vss- 0.2 Vref +0.2 V
Rref Resistance between Vref and Vss 12 16 24 KO
hm
Vref Reference voltage 2.40 3.00 V
Cai Analog input Capacitance 60 pF During sampling
INL Integral non linearity 1 2 lsb
DNL Differential non linearity 0.5 1 lsb
OE Offset error -2 2 lsb

137

T89C51CC01

Rev. D – 17-Dec-01

19.4.2 External Program

Memory Characteristics Table 95. Symbol Description

Table 96. AC Parameters for a Fix Clock (F= 40 MHz)

Symbol Parameter

T Oscillator clock period

TLHLL ALE pulse width

TAVLL Address Valid to ALE

TLLAX Address Hold After ALE

TLLIV ALEtoValidInstructionIn

TLLPL ALE to PSEN

TPLPH PSEN Pulse Width

TPLIV PSEN to Valid Instruction In

TPXIX Input Instruction Hold After PSEN

TPXIZ Input Instruction Float After PSEN

TAVIV Address to Valid Instruction In

TPLAZ PSEN Low to Address Float

Symbol

Min Max

Units

T25 ns

TLHLL 40 ns

TAVLL 10 ns

TLLAX 10 ns

TLLIV 70 ns

TLLPL 15 ns

TPLPH 55 ns

TPLIV 35 ns

TPXIX 0ns

TPXIZ 18 ns

TAVIV 85 ns

TPLAZ 10 ns

138 T89C51CC01 Rev. D – 17-Dec-01

Table 97. AC Parameters for a Variable Clock

19.4.3 External Program

Memory Read Cycle

Symbol Type Standard

Clock X2 Clock X parameter Units

TLHLL Min 2 T - x T - x 10 ns

TAVLL Min T-x 0.5T-x 15 ns

TLLAX Min T-x 0.5T-x 15 ns

TLLIV Max 4T-x 2T-x 30 ns

TLLPL Min T-x 0.5T-x 10 ns

TPLPH Min 3T-x 1.5T-x 20 ns

TPLIV Max 3T-x 1.5T-x 40 ns

TPXIX Min x x 0 ns

TPXIZ Max T-x 0.5T-x 7 ns

TAVIV Max 5T-x 2.5T-x 40 ns

TPLAZ Max x x 10 ns

TPLIV

TPLAZ

ALE

PSEN

PORT 0

PORT 2

A0-A7A0-A7 INSTR ININSTR IN INSTR IN

ADDRESS

OR SFR-P2 ADDRESS A8-A15ADDRESS A8-A15

12 TCLCL

TAVIV

TLHLL

TAVLL

TLLIV

TLLPL

TPLPH

TPXAV

TPXIX

TPXIZ

TLLAX

139

T89C51CC01

Rev. D – 17-Dec-01

19.4.4 External Data Memory

Characteristics Table 98. Symbol Description

Table 99. AC Parameters for a Variable Clock (F=40MHz)

Symbol Parameter

TRLRH RD Pulse Width

TWLWH WR Pulse Width

TRLDV RD to Valid Data In

TRHDX Data Hold After RD

TRHDZ Data Float After RD

TLLDV ALE to Valid Data In

TAVDV Address to Valid Data In

TLLWL ALE to WR or RD

TAVWL Address to WR or RD

TQVWX DataValidtoWRTransition

TQVWH Data set-up to WR High

TWHQX Data Hold After WR

TRLAZ RD Low to Address Float

TWHLH RD or WR High to ALE high

Symbol

Min Max

Units

TRLRH 130 ns

TWLWH 130 ns

TRLDV 100 ns

TRHDX 0ns

TRHDZ 30 ns

TLLDV 160 ns

TAVDV 165 ns

TLLWL 50 100 ns

TAVWL 75 ns

TQVWX 10 ns

TQVWH 160 ns

TWHQX 15 ns

TRLAZ 0ns

TWHLH 10 40 ns

140 T89C51CC01 Rev. D – 17-Dec-01

Table 100. AC Parameters for a Variable Clock

19.4.5 External Data Memory

Write Cycle

Symbol Type Standard

Clock X2 Clock X parameter Units

TRLRH Min 6T-x 3T-x 20 ns

TWLWH Min 6T-x 3T-x 20 ns

TRLDV Max 5T-x 2.5T-x 25 ns

TRHDX Min x x 0 ns

TRHDZ Max 2 T - x T - x 20 ns

TLLDV Max 8T-x 4T-x 40 ns

TAVDV Max 9T-x 4.5T-x 60 ns

TLLWL Min 3T-x 1.5T-x 25 ns

TLLWL Max 3 T + x 1.5 T + x 25 ns

TAVWL Min 4T-x 2T-x 25 ns

TQVWX Min T-x 0.5T-x 15 ns

TQVWH Min 7T-x 3.5T-x 25 ns

TWHQX Min T-x 0.5T-x 10 ns

TRLAZ Max x x 0 ns

TWHLH Min T-x 0.5T-x 15 ns

TWHLH Max T+x 0.5T+x 15 ns

TQVWH

TLLAX

ALE

PSEN

PORT 0

PORT 2

A0-A7 DATA OUT

ADDRESS

OR SFR-P2

TAVWL

TLLWL

TQVWX

ADDRESS A8-A15 OR SFR P2

TWHQX

TWHLH

TWLWH

141

T89C51CC01

Rev. D – 17-Dec-01

19.4.6 External Data Memory

Read Cycle

19.4.7 Serial Port Timing -

Shift Register Mode Table 101. Symbol Description (F= 40 MHz)

Table 102. AC Parameters for a Fix Clock (F= 40 MHz)

ALE

PSEN

PORT 0

PORT 2

A0-A7 DATA IN

ADDRESS

OR SFR-P2

TAVWL

TLLWL

TRLAZ

ADDRESS A8-A15 OR SFR P2

TRHDZ

TWHLH

TRLRH

TLLDV

TRHDX

TLLAX

TAVDV

Symbol Parameter

TXLXL Serial port clock cycle time

TQVHX Output data set-up to clock rising edge

TXHQX Output data hold after clock rising edge

TXHDX Input data hold after clock rising edge

TXHDV Clock rising edge to input data valid

Symbol

Min Max

Units

TXLXL 300 ns

TQVHX 200 ns

TXHQX 30 ns

TXHDX 0ns

TXHDV 117 ns

142 T89C51CC01 Rev. D – 17-Dec-01

Table 103. AC Parameters for a Variable Clock

19.4.8 Shift Register Timing

Waveforms

19.4.9 External Clock Drive

Characteristics (XTAL1) Table 104. AC Parameters

19.4.10 External Clock Drive

Waveforms

Symbol Type Standard

Clock X2 Clock X parameter

for -M range Units

TXLXL Min 12T 6T ns

TQVHX Min 10T-x 5T-x 50 ns

TXHQX Min 2 T - x T - x 20 ns

TXHDX Min x x 0 ns

TXHDV Max 10 T - x 5 T- x 133 ns

VALID VALID VALID VALID VALID

VALID

INPUT DATA VALID

0123456 87

ALE

CLOCK

OUTPUT DATA

WRITE to SBUF

CLEAR RI

TXLXL

TQVXH TXHQX

TXHDV TXHDX SET TI

SET RI

INSTRUCTION

01234567

VALID

Symbol Parameter Min Max Units

TCLCL Oscillator Period 25 ns

TCHCX High Time 5 ns

TCLCX Low Time 5 ns

TCLCH Rise Time 5 ns

TCHCL Fall Time 5 ns

TCHCX/TCLCX CyclicratioinX2mode 40 60 %

VCC-0.5V

0.45V

0.7VCC

0.2VCC-0.1

TCHCL TCLCX TCLCL

TCLCH

TCHCX

143

T89C51CC01

Rev. D – 17-Dec-01

19.4.11 AC Testing

Input/Output Waveforms

AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”.

Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”.

19.4.12 Float Waveforms

For timing purposes as port pin is no longer floating when a 100 mV change from load

voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level

occurs. IOL/IOH ≥±20mA.

19.4.13 Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.

INPUT/OUTPUT 0.2 VCC +0.9

0.2 VCC -0.1

VCC -0.5 V

0.45 V

FLOAT

VOH -0.1V

VOL +0.1V

VLOAD VLOAD +0.1V

VLOAD -0.1V

144 T89C51CC01 Rev. D – 17-Dec-01

This diagram indicates when signals are clocked internally. The time it takes the signals

to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is

dependent on variables such as temperature and pin loading. Propagation also varies

from output to output and component. Typically though (TA=25°C fully loaded) RD and

WR propagation delays are approximately 50ns. The other signals are typically 85 ns.

Propagation delays are incorporated in the AC specifications.

DATA PCL OUT DATA PCL OUT DATA PCL OUT

SAMPLED SAMPLED SAMPLED

STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5

P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2

FLOAT FLOAT FLOAT

THESE SIGNALS ARE NOT ACTIVATED DURING THE

EXECUTION OF A MOVX INSTRUCTION

INDICATES ADDRESS TRANSITIONS

EXTERNAL PROGRAM MEMORY FETCH

FLOAT

DATA

SAMPLED

DPL OR Rt OUT

INDICATES DPH OR P2 SFR TO PCH TRANSITION

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)

PCLOUT (EVEN IF PROGRAM

MEMORY IS INTERNAL)

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL

OLD DATA NEW DATA P0 PINS SAMPLED

P1, P2, P3 PINS SAMPLED P1, P2, P3 PINS SAMPLED

P0 PINS SAMPLED

RXD SAMPLED

INTERNAL

CLOCK

XTAL2

ALE

PSEN

P2 (EXT)

READ CYCLE

WRITE CYCLE

PORT OPERATION

MOV PORT SRC

MOV DEST P0

MOV DEST PORT (P1. P2. P3)

(INCLUDES INTO. INT1. TO T1)

SERIAL PORT SHIFT CLOCK

TXD (MODE 0)

DATA OUT

DPL OR Rt OUT

INDICATES DPH OR P2 SFR TO PCH TRANSITION

RXD SAMPLED

145

T89C51CC01

Rev. D – 17-Dec-01

19.5.14 Flash Memory Table 105. Timing Symbol Definitions

Table 106. Memory AC Timing

VDD= 5 V +/- 10% , TA= -40 to +85°C

Figure 62. FLASH Memory - ISP Waveforms

Figure 63. FLASH Memory - Internal Busy Waveforms

Signals Conditions

S(Hardware

condition) PSEN#,EA L Low

RRST VValid

B FBUSY flag X No Longer Valid

Symbol Parameter Min Typ Max Unit

TSVRL Input PSEN# Valid to RST Edge 50 ns

TRLSX Input PSEN# Hold after RST Edge 50 ns

TBHBL FLASH Internal Busy (Programming) Time 10 ms

RST TSVRL

PSEN#1

TRLSX

FBUSY bit TBHBL

146 T89C51CC01 Rev. D – 17-Dec-01

20. Ordering Information

Table 106. Possible order entries

Part Number Boot Loader Temperature

Range Package Packing

T89C51001UA-7CTIM UART Industrial CA-BGA Tray

T89C51001UA-RLTIM UART Industrial VQFP44 Tray

T89C51001UA-5LSIM UART Industrial PLCC44 Stick

T89C51001CA-7CTIM CAN Industrial CA-BGA Tray

T89C51001CA-RLTIM CAN Industrial VQFP44 Tray

T89C51001CA-RLSIM CAN Industrial PLC44 Stick

i
T89C51CC01
Rev. D – 17-Dec-01
Table of Contents 1. Features .......................................................................................................... 1
Description .......................................................................................................2
Block Diagram .................................................................................................2
Pin Configuration .............................................................................................3
1 I/O Configurations .....................................................................................7
2 Port 1, Port 3 and Port 4 ............................................................................7
3 Port 0 and Port2 ........................................................................................8
4 Read-Modify-Write Instructions .................................................................9
5 Quasi-Bidirectional Port Operation ............................................................10
SFR Mapping ..................................................................................................11
Clock ...............................................................................................................17
1 Description ................................................................................................17
2 Register .....................................................................................................19
Data Memory ...................................................................................................21
1 Internal Space ............................................................................................22
2 External Space ..........................................................................................23
3 Dual Data Pointer ......................................................................................24
4 Registers ...................................................................................................26
EEPROM Data Memory ..................................................................................28
1 Write Data in the column latches ...............................................................28
2 Programming .............................................................................................28
3 Read Data ................................................................................................. 28
4 Examples ...................................................................................................29
5 Registers ...................................................................................................30
Program/Code Memory ...................................................................................31
1 External Code Memory Access .................................................................31
2 FLASH Memory Architecture .....................................................................33
3 Overview of FM0 operations .....................................................................35
4 Registers ....................................................................................................41
In-System-Programming (ISP) ......................................................................42
1 Flash Programming and Erasure ............................................................42
2 Boot Process ...........................................................................................43
3 Application-Programming-Interface .........................................................44
4 XROW Bytes ...........................................................................................45
5 Hardware Security Byte ...........................................................................46
Serial I/O Port ...............................................................................................47
1 Framing Error Detection .........................................................................47
2 Automatic Address Recognition ..............................................................48
3 Given Address ........................................................................................49
4 Broadcast Address .................................................................................49
5 Registers ..................................................................................................50
Timers/Counters ............................................................................................53
1 Timer/Counter Operations .......................................................................53
2 Timer 0 ....................................................................................................53
3 Timer 1 ....................................................................................................55
4 Interrupt ................................................................................................... 56
5 Registers .................................................................................................57
Timer 2 .......................................................................................................... 61
1 Auto-Reload Mode .................................................................................61
2 Programmable Clock-Output ..................................................................62
3 Registers .................................................................................................64
WatchDog Timer ............................................................................................67

ii T89C51CC01 Rev. D – 17-Dec-01
1 WatchDog Programming .........................................................................68
2 WatchDog Timer during Power down mode and Idle ..............................68
Atmel CAN Controller.....................................................................................71
1 CAN Controller Description .....................................................................71
2 CAN Controller Mailbox and Registers Organization ..............................72
3 CAN Controller management ..................................................................73
4 IT CAN management ...............................................................................74
5 Bit Timing and BaudRate .........................................................................76
6 Fault Confinement ...................................................................................78
7 Acceptance filter ......................................................................................79
8 Data and Remote frame ..........................................................................80
9 Time Trigger Communication (TTC) and Message
Stamping ..............................................................................................................81
10 CAN Autobaud and Listening mode ......................................................82
11 Routines Examples ................................................................................82
12 CAN SFR’s ............................................................................................85
13 Registers ...............................................................................................86
Programmable Counter Array PCA ...............................................................108
1 PCA Timer ...............................................................................................108
2 PCA modules ..........................................................................................109
3 PCA Interrupt ...........................................................................................110
4 PCA Capture Mode .................................................................................110
5 16-bit Software Timer Mode ....................................................................111
6 High Speed Output Mode ........................................................................112
7 Pulse Width Modulator Mode ..................................................................112
8 PCA Watchdog Timer ..............................................................................113
9 PCA Registers .........................................................................................114
Analog-to-Digital Converter (ADC) ................................................................119
1 Features ..................................................................................................119
2 ADC Port1 I/O Functions .........................................................................119
3 ADC Converter Operation ....................................................................... 120
4 Voltage Conversion .................................................................................121
5 Clock Selection ........................................................................................121
6 ADC Standby Mode .................................................................................122
7 IT ADC management ...............................................................................122
8 Routines examples ..................................................................................122
9 Registers .................................................................................................123
Interrupt System ............................................................................................125
1 Introduction ..............................................................................................125
2 Registers .................................................................................................127
Electrical Characteristics ...............................................................................133
1 Absolute Maximum Ratings (1) ...............................................................133
2 DC Parameters for Standard Voltage ......................................................133
3 DC Parameters for A/D Converter ...........................................................136
4 AC Parameters ........................................................................................136
Ordering Information .................................................................................... 146

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