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Customer Support Dept.
April 1, 2003
To all our customers
Cautions
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better
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Remember to give due consideration to safety when making your circuit designs, with appropriate
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contained therein.
HD74HC259
8-bit Addressable Latch
ADE-205-480 (Z)
1st. Edition
Sep. 2000
Description
The HD74HC259 has a single data input (D), 8 latch outputs (Q0-Q7), 3 address inputs (A, B, and C), a
common enable input (E), and a common clear input. To operate this device as an addressable latch, data is
held on the D input, and the address of the latch into which the data is to be entered is held on the A, B and
C inputs. When enable is taken low the data flows through to the addressed output. The data is stored
when enable transitions from low to high. All unaddressed latches will remain unaffected. With enable in
the high state the device is deselected, and all latches remain in their previous state, unaffected by changes
on the data or address inputs. To eliminate the possibility of entering erroneous data into the latches, the
enable should be held high (inactive) while the address lines are changing.
If enable is held high and clear is taken low all eight latches are cleared to a low state. If enable is low all
latches except the addressed latch will be cleared. The addressed latch will instead follow the D input,
effectively implementing a 3-to-8 line decoder.
Features
High Speed Operation: tpd (Data to Output) = 16 ns typ (CL = 50 pF)
High Output Current: Fanout of 10 LSTTL Loads
Wide Operating Voltage: VCC = 2 to 6 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Inputs
Clear G Output of Addressed Latch Each Other Output Function
H L D Qio Addressable latch
H H Qio Qio Memory
L L D L 8-line demultiplexer
L H L L Clear
HD74HC259
2
Select Inputs
C B A Latch Addressed
LL L 0
LL H 1
LH L 2
LH H 3
HL L 4
HL H 5
HH L 6
HH H 7
Notes: 1. D: the level at the data input
2. Qio: the level of Qi (i = 0, 1, ···7, as apropriate) before the indicated steady-state input conditions
were established.
Pin Arrangement
(Top view)
1
2
3
4
5
6
7
8
A
B
C
Q0
Q1
Q2
Q3
GND
VCC
Clear
Enable
Q7
Q6
Q5
Q4
16
15
14
13
12
11
10
9
B
C
Q0
Q1
Q2
Q3
CLR
G
D
Q7
Q6
Q5
A
Q4
Data
input
Outputs
Outputs
Latch
select
HD74HC259
3
DC Characteristics
Ta = 25°CTa = –40 to
+85°C
Item Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions
Input voltage VIH 2.0 1.5 1.5 V
4.5 3.15 3.15
6.0 4.2 4.2
VIL 2.0 0.5 0.5 V
4.5 1.35 1.35
6.0 1.8 1.8
Output voltage VOH 2.0 1.9 2.0 1.9 V Vin = VIH or VIL IOH = –20 µA
4.5 4.4 4.5 4.4
6.0 5.9 6.0 5.9
4.5 4.18 4.13 IOH = –4 mA
6.0 5.68 5.63 IOH = –5.2 mA
VOL 2.0 0.0 0.1 0.1 V Vin = VIH or VIL IOL = 20 µA
4.5 0.0 0.1 0.1
6.0 0.0 0.1 0.1
4.5 0.26 0.33 IOL = 4 mA
6.0 0.26 0.33 IOL = 5.2 mA
Input current Iin 6.0 ±0.1 ±1.0 µA Vin = VCC or GND
Quiescent supply
current ICC 6.0 4.0 40 µA Vin = VCC or GND, Iout = 0 µA
HD74HC259
4
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25°CTa = –40 to
+85°C
Item Symbol VCC (V) Min Typ Max Min Max Unit Test Conditions
Propagation delay tPHL 2.0 185 230 ns Data to output
time tPLH 4.5 16 37 46
6.0 31 39
2.0 215 270 Latch select to output
4.5 20 43 54
6.0 37 46
2.0 200 250 Enable to output
4.5 17 40 50
6.0 34 43
tPHL 2.0 155 195 ns Clear to output
4.5 15 31 39
6.0 26 33
Pulse width tw2.0 80 100 ns Clear, Enable
4.5 16 6 20
6.0 14 17
Setup time tsu 2.0 100 125 ns Latch select or data to enable
4.5 20 5 25
6.0 17 21
Hold time th2.0 5 5 ns Latch select or data to enable
4.5 5 –1 5
6.0 5 5
Output rise/fall tTLH 2.0 75 95 ns
time tTHL 4.5 5 15 19
6.0 13 16
Input capacitance Cin 5 10 10 pF
HD74HC259
5
Package Dimensions
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
DP-16
Conforms
Conforms
1.07 g
Unit: mm
6.30
19.20
16 9
81 1.3
20.00 Max
7.40 Max
7.62
0.25
+ 0.13
– 0.05
2.54 ± 0.25 0.48 ± 0.10
0.51 Min
2.54 Min 5.06 Max
0° – 15°
1.11 Max
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
FP-16DA
Conforms
0.24 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
*0.22 ± 0.05
*0.42 ± 0.08
0.12
0.15
M
2.20 Max 5.5
10.06
0.80 Max
16 9
18
10.5 Max
+ 0.20
– 0.30
7.80
0.70 ± 0.20
0° – 8°
0.10 ± 0.10
1.15
1.27
0.40 ± 0.06
0.20 ± 0.04
HD74HC259
6
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
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received the latest product standards or specifications before final design, purchase or use.
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contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
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consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
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products.
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Copyright Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.
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