17-3-b2.fm Page 31 Saturday, August 28, 1999 9:57 PM NE W PR OD UCTS * MB 81 x x 64 3 24 2B * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 2M x 32-Bit Synchronous DRAM for Multimedia & Graphics: MB81F643242B MB811L643242B * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * The SDRAMs in a 32-bit I/O configuration can provide the effective solution for a wide range of applications, including multimedia and graphics applications. Also, these SDRAMs employ the new SCITT technology, thereby reducing the test time and cost. * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Features * * * * * * * * * * * * * 64 M-bit SDRAM with a 32-bit I/O configuration * * * Also available as extended operatingtemperature components * * * * * * JEDEC Standard 86-pin TSOP package * * * * * * Photo 1. MB81xx643242B Appearance * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * High performance series or low power consumption series * Introduction of a new test technology, SCITT * Reduced test time and cost using SCITT * FIND, Vol. 17, No. 3, August 1999 17-3-b2.fm Page 32 Saturday, August 28, 1999 9:57 PM NE W * * * PR OD UCTS * Overview * * * * * * * * * * * * * * * * * * * * * Synchronous DRAMs (SDRAMs) have been rapidly * increasing in popularity since they were employed * as main memory for personal computers. They have * multimedia, graphics, and mobile products. It is ex- figuration for many of these applications. * * * The MB81F643242B is a high-performance * * * * 0.5 mm, fully conforming to JEDEC standards. The * MB81F643242B Series consists of three speed ver- * * * sions: 143-MHz, 125-MHz, and 100-MHz. The MB811L643242B also consists of three speed ver- * * * sions: 100-MHz, 84-MHz, and 67-MHz. Also, a low * power version is available. * * version, operating at a maximum frequency of * * * 143 MHz. This SDRAM is the second- * * generation product, based on the current * mass-production 2M x 32-bit SDRAM. * * * * The MB811L643242B is a low-voltage, low * power consumption version operating at 2.5V. * * * * * These products employ a new test technology, Stat- * ic Component Interconnection Test Technology * FUJITSU/Philips (Nether- * ". . . reduces the test time and lands) collaboration. SCITT * cost required for board-level is a new XNOR circuit* * interconnection testing." * based technology that is used for board-level inter- * and for optional, extended operating-temperature products for use in special environments. * * * * * * * Examples of applications for these SDRAMs are: * * * * High-speed model: Graphics card, digital TV, * game equipment, etc. * * * * * * * * * * * * Low-voltage model: Portable video camera, * * digital camera, PDA, mobile computer, * consumer product built-in device, etc. * * * * * * * * connection testing. Using SCITT's simple method * reduces the test time and cost required for board- * level interconnection testing. * * * Extended operating-temperature models: * * * * * * * * * * Automotive equipment, such as a car * navigation system, application-specific * * * * * Product Features FUJITSU also provides support for the SCITT functions * * (SCITT), developed by a * * * * The package is an 86-pin TSOP with a pin pitch of * * * * * * * Burst type: Sequential or interleave * * * * * * * * * configuration will be adopted as the preferred con- * * * * * * * pected that the 64 M-bit SDRAM with a 32-bit I/O * * * * * * Burst length: 1, 2, 4, 8, or full page * * * * * * * CAS latency: 2 or 3 * * * * * communications equipment, consumer products, * * * * * * * * * with a 32-bit I/O configuration: * * lowing settings: * FUJITSU has now developed two series of SDRAM * * but also for various other applications, including * * * 2.5V, respectively. These SDRAMs support the fol- * * * * * also been used not only for computer main memory, * * figuration, operating at supply voltages of 3.3V and * * * * * * * SDRAMs in a "4 banks x 512K words x 32 bits" con- * * * * * * * MB 81 x x 64 3 24 2B products, etc. * * * * Other applications: Copier, communications * equipment, etc. * * * * * * * * * * * * * * * The MB81F643242B and MB811L643242B are * Table 1 lists the major characteristics of these SDRAMs and Figure 1 shows their pin assignments. * * * * * * * * * * * * * * * * * * * * * * FIND, Vol. 17, No. 3, August 1999 17-3-b2.fm Page 33 Saturday, August 28, 1999 9:57 PM NE W * PR OD UCTS MB 81 x x 64 3 24 2B * * * * * * * Table 1. MB81F643242B/MB811L643242B Major Characteristics * * * * * * Part Number * * * Speed Version 70/70L * Clock Frequency Clock Cycle Time * MHz tCK (min.) ns 143 7 RAS Cycle Time RAS-CAS Delay Time tRC (min.) tRCD(min.) ns 63 ns 21 RAS Precharge Time 12/12L 15/15L 125 100 100 84 67 8 10 10 12 15 72 90 90 100 110 * * tRP (min.) ns 17 tAC (CL=2) * * * * * * * 6 Clock Access Time tAC (CL=3) * * ns 6 * * * * * * * * 24 30 30 30 30 20 30 30 35 40 * * * * * * * ns * * * * * 10/10L * * * 10/10L * * * * 80/80L * * * * * * * * MB811L643242B * * * * MB81F643232B * * * * 6 7 8 8 8 * * * * * * * 6 7 8 8 8 * * * * * * * * * * * * * * * * * * * * * Figure 1. * MB81F643242B/MB811L643242B Pin Assignments * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Pin No. Pin Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 V CC DQ 0 V CCQ DQ 1 DQ 2 V SSQ DQ 3 DQ 4 V CCQ DQ 5 DQ 6 V SSQ DQ 7 NC V CC DQM 0 /WE /CAS /RAS /CS NC A 12 A 11 A 10/AP A0 A1 A2 DQM 2 V CC NC DQ 16 V SSQ DQ 17 DQ 18 V CCQ DQ 19 DQ 20 V SSQ DQ 21 DQ 22 V CCQ DQ 23 V CC * * * * * * * * Top *View * * * * * * 400 mil *x 875 mil 86-Pin* TSOP * Pin *Pitch * = 0.5 mm * * Low Addresses: * * A 10 A 0 to * Bank Addresses: * A 11, A 12 * Column Addresses: * A 0 to * A7 * Auto-Precharge: A* 10 * * * * * * * * * spacer * * * * * * Pin Symbol Pin No. V SS DQ 15 V SSQ DQ 14 DQ 13 V CCQ DQ 12 DQ 11 V SSQ DQ 10 DQ 9 V CCQ DQ 8 NC V SS DQM 1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DQM 3 V SS NC DQ 31 V CCQ DQ 30 DQ 29 V SSQ DQ 28 DQ 27 V CCQ DQ 26 DQ 25 V SSQ DQ 24 V SS 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * FIND, Vol. 17, No. 3, August 1999 17-3-b2.fm Page 34 Saturday, August 28, 1999 9:57 PM NE W * PR OD UCTS * * * * * MB 81 x x 64 3 24 2B Photo 2. MB81xx643242B Chip * * ing test pattern to the host controller via the I/O pins. * The host side then checks the output pattern from the * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * SCITT Functions * memory and compares the expected value and actual output value to detect open-circuit faults, shortcircuit faults, missing LSIs, and mounting errors. * * * * * * Figure 3. SCITT Technology Basic Concept * * x Address ROM & Decoder ROM * * * * * Memory Controller * Memory * * * Data Bus * Evaluation * * Output Buffer * * * * * * * * Most of the failures occurring after mounting LSIs on * * the board are attributable to open-circuit, mounting, * * * * * * * * * * * * * or short-circuit faults. In addition, new packaging technologies make the post-mounting test more * * * in collaboration with Philips, planned and developed * the method for simply testing the mutual connection * SCITT Advantages * * * * * * * * The following features of SCITT can be listed as its advantages over the boundary scan method. * * * * * * * * * * * Figure 2 shows post-mounting fault ratios. Figure 3 * * complicated. Considering these factors, FUJITSU, between LSIs mounted on the board. * * * * x Address: Address + Control Line * * * * * * No need for dedicated pins * * * * Short test time: 1/1,000 of the current test * time or less * * illustrates the basic concept of SCITT technology, * developed for detecting connection faults. * * * * * * * * * * * * * Figure 2. Post-Mounting Fault Ratios * * * * * * * 40 37% Open-Circuit Failure * * * * * Insignificant increase in chip size * * * * * * * * (%) 50 * Fault reject ratio: almost 100% * * * * Table 2 compares the interconnection tests by the * SCITT and boundary scan methods. * * * * * * * * * 30 * * * 20 * 10 * * 14% LSI Function Failure * 7% Short-Circuit Failure * * * * * 0 * * * * * * * * The host controller outputs a test pattern on the address and control pins to memory. This test pattern * had been stored in ROM in the host controller during * * The SDRAM with SCITT functions has the following SCITT specifications. * controller design. The memory outputs a correspond- * * * * * * * * Figure 4 shows the state diagram of SCITT mode. As shown in the figure, the SCITT functions are execut- * * * ed only before initialization after the supply voltage * is applied. The SCITT functions are optional; the ex- * * * * * * * * * * * * SCITT Specifications for SDRAM * * * * * 22% Mounting Failure 19% Analog Failure ecution is not required. * * * FIND, Vol. 17, No. 3, August 1999 17-3-b2.fm Page 35 Saturday, August 28, 1999 9:57 PM NE W * PR OD UCTS * * The SCITT mode is controlled by the inputs from * three pins: /CAS, /CS, and CKE. Each pin has the * * * * * following functions: * * * * * * * /CAS: For test mode entry/exit control * * * * * * * /CS: For chip select control * * * * * * * * * CKE: For test mode select control * * * * * * * * * Table 3 is the SCITT function table. Figure 5 shows * the timings for entry to and exit from the SCITT * mode. Figures 6 and 7 show test timings. Table 4 * * * * * lists AC timing values. * * * * * * * * * * * * * * * * * * MB 81 x x 64 3 24 2B Figures 8 and 9 show test patterns to be applied to * 2M x 32-bit SDRAM. The applied test patterns con- * sist of "walking-0," "walking-1," "all-0," and "all-1." * * * Using these simple test patterns contributes to the * significant reduction in test time. * * * Details on SCITT technology will be presented in * * * collaboration with * * Philips in the Inter- "Using these simple test patterns * * national Test Con- ference to be held in October 1999. contributes to the significant* * reduction in test time." * * * * The SCITT functions have been tested on actual applications and have verified the proof of concept * * * and effectiveness. These functions are applicable * not only to SDRAMs but also other devices. Follow- * ing the accelerated trend of implementing equip- * ment in digital form, multimedia products and * * * * consumer products will increasingly incorporate a * mixture of Digital Signal Processors (DSPs), high- * speed DRAMs, and flash memory. If the host pro- * cessor can perform the SCITT type of interconnection test for each memory device, the efficiency of the test will be dramatically improved. * * * * * * * * * * * * * * * * * * * * * Table 2. * SCITT and Boundary Scan Method Comparison * * * * Item * Dedicated Pins Required 5 Pins * * * * Shift Register/Pin * * TAP Controller * Instruction Register * Bypass Register * * IDCODE Register * * * Components * * * Die Size Penalty Yes Open-Circuit Fault * Yes Short-Circuit Fault * Yes * * * Missing IC Yes Mounting Error Yes * * * Test Items * * * EX Test Feature * * Sample/Preload * Feature * Bypass Feature * * Internal Logic Inspection Yes Run Test Feature * IN Test Feature * * Yes * ID Code Feature * * * * * * User Code Check Yes User Code * Feature * * * * * * * Negligible * * Yes * * Yes * * * Yes * * Yes * * No Covered by Component Shipping Test * * * * * * ID Code Check * * * * * ROM (or decoder) Comparator Circuit (controller side) * * * * * * * * * * * * * * None * * * * SCITT Technology * * * * Boundary Scan * * * * No No * Covered by DIMM/SPD Function * * * * * * * * * * * * * * * * * * * FIND, Vol. 17, No. 3, August 1999 17-3-b2.fm Page 36 Saturday, August 28, 1999 9:57 PM NE W * PR OD UCTS MB 81 x x 64 3 24 2B * * * * * * * * * * * * * * Table 3. SCITT Function Table /CAS * /OE CKE /WE * Entry H>L L L * * * * * * * * * CLK DQ X X X X X Exit L>H Test Mode L X X X X X X V V V V V X** X L * H V* * * * * * * * * * * * * * * DQM X* * * ADD * * * /RAS * L: Low Level * H: High Level * V: Valid Data * * X: Don't Care (H or L) * cf1: First /CAS Falling Edge after Power-On Sequence * * * * * * * * * * * * * * * * * * * * * * * * * * Table 4. AC Timing Values * * * * Parameter tTS Description * * * Test Mode Entry Setup Time * * * tTH tEPD Test Mode Entry Hold Time 0 -- 5 -- * Units * Test Mode to Power-On Sequence Delay Time * Test Mode Output in Low-Z Time * * * * 2 -- 0 -- 3 0 -- 20 5 -- * * * ns tTIA Test Mode Output in High-Z Time * * * Test Mode Input Access Time * Test Mode Entry to Test Delay Time * * * * * * * tETD * * * tTHZ * * * tTLZ * * * * * Max. Value * * * * Min. Value * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Figure 4. State Transition of SDRAM (with SCITT *Functions) * * * * * * * * * * * Apply Power Entry * * * * * * * * * * * * Static Component * Interconnection Test * * * * * * * * Power-On Sequence Exit * * * 1) Apply Supply Voltage 2) Enter Board Interconnection Test Mode 3) Execute Interconnection Test Function 4) Exit from Interconnection Test Mode 5) Start Clock. Attempt to Maintain an NOP Condition at the Inputs 6) Execute Normal Initialization Sequence 7) Start Normal Operation * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Normal Operation * * Once the SDRAM exits the test mode, it * cannot enter the mode until the power is * cycled off and on. * * * * * * * * * * * * * FIND, Vol. 17, No. 3, August 1999 17-3-b2.fm Page 37 Saturday, August 28, 1999 9:57 PM * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * {,z{,, zz y yy PR OD UCTS Figure 5. Entry to and Exit from SCITT Mode MB 81 x x 64 3 24 2B * * * * * * * * * * * First /CAS Edge After Power-On Sequence Normal Power-On Sequence From Here On * V CC t TH t TS * Test Mode t EPD * * * H>L * * z y , | ~ ~|} | /CS L CKE L See Table 3. for Entry and Exit * * * * * * * * * * * * * * * * Entry Exit * Test Coverage * Entry or exit cannot be executed if the /CAS, /CS, and CKE pins have problems. Figure 6. Test Timing (1) Test Mode Entry Command t ETD /CAS /CS CKE Test Pins * * * * * * * * * * * * * * * * * * * Test Mode Entry Under Test * * * * * * * * * * * * * * * * * * * t TIA t TIA Valid t TIA Valid Valid /CS-#1 /CS-#2 H * * * * * * * * * * * * * * * * DQ 0 to DQ n (bus) FIND, Vol. 17, No. 3, August 1999 Test Mode Exit * Under Test Device (under test) Changed * * Device #2 * t TIA Valid * * * * * * * * * * * * * * * * * * * * t TIA * * * A0 A1 A2 * * * CKE * * * Device #1 * * * L L * * * /CAS * * * Test Mode Entry * * * Test Timing (2) * * * Figure 7. * * * DQ 0 to DQ n * * /CS = L and CKE = H Put Output (PQ) in Low-Z State A0 A1 A2 * * * /CAS * * * Pause 200 us Test Pins * * NE W * * t TIA Valid* t TIA Valid t TIA Valid t TIA Valid * * * * * * * * * * 17-3-b2.fm Page 38 Saturday, August 28, 1999 9:57 PM NE W PR OD UCTS * MB 81 x x 64 3 24 2B * * * * * * * * * Figure 8. Test Pattern (1) Input Bus * * Output Bus * * * * * * * * /RAS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 DQM0 DQM1 DQM2 DQM3 CLK /WE DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DQM8 DQM9 DQM10 DQM11 DQM12 DQM13 DQM14 DQM15 DQM16 DQM17 DQM18 DQM19 DQM20 DQM21 DQM22 DQM23 DQM24 DQM25 DQM26 DQM27 DQM28 DQM29 DQM30 DQM31 * * * * * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H H H H H H* H H H H H H H H H H H H H H H H H H H H H H H H H H * * 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L L L L L L* L L L L L L L L L L L L L H H H H H H H H H H H H H * * * * * * * 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L H H H H H* H H H H H H H H H H H H H L L L L L L L L L L L L L * 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H L H H H H* H H H H H H H H H H H H H L H H H H H H H H H H H H * * 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H H L H H H* H H H H H H H H H H H H H H L H H H H H H H H H H H * * * * 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H H H L H H* H H H H H H H H H H H H H H H L H H H H H H H H H H * * 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 H H H H L H* H H H H H H H H H H H H H H H H L H H H H H H H H H * * * * * * 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 H H H H H H* L H H H H H H H H H H H H H H H H H L H H H H H H H * * 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 H H H H H H* H L H H H H H H H H H H H H H H H H H L H H H H H H * * * * * * * 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H H H * * 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 H H H H H H* H H L H H H H H H H H H H H H H H H H H L H H H H H * 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 H H H H H H* H H H L H H H H H H H H H H H H H H H H H L H H H H * * 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 H H H H H H* H H H H L H H H H H H H H H H H H H H H H H L H H H * * * * 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 H H H H H H* H H H H H L H H H H H H H H H H H H H H H H H L H H * * 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 H H H H H H* H H H H H H L H H H H H H H H H H H H H H H H H L H * * * * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 H H H H H H* H H H H H H H H L H H H H H H H H H H H H H H H H H * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 H H H H H H* H H H H H H H H H L H H H H H H H H H H H H H H H H * * * * * * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 H H H H H H* H H H H H H H H H H L H H H H H H H H H H H H H H H * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 H H H H H H* H H H H H H H H H H H L H H H H H H H H H H H H H H * * 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 H H H H H H* H H H H H H H H H H H H L H H H H H H H H H H H H H * * 0 = Input Low, 1 = Input High, L= Output Low, H = Output High * * * * * * * * * * * * * * * * * * * * * * Test Pattern (2) Input Bus * * Output Bus * * /RAS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 DQM0 DQM1 DQM2 DQM3 CLK /WE DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DQM8 DQM9 DQM10 DQM11 DQM12 DQM13 DQM14 DQM15 DQM16 DQM17 DQM18 DQM19 DQM20 DQM21 DQM22 DQM23 DQM24 DQM25 DQM26 DQM27 DQM28 DQM29 DQM30 DQM31 * Figure 9. * * * * * * * 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 L L L L L L* L L L L L L L L L L L L L H H H H H H H H H H H H H * * * * * * * * 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 L H H H H H* H H H H H H H H H H H H H L L L L L L L L L L L L L * 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 H L H H H H* H H H H H H H H H H H H H L H H H H H H H H H H H H * * 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 H H L H H H* H H H H H H H H H H H H H H L H H H H H H H H H H H * * * * 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 H H H L H H* H H H H H H H H H H H H H H H L H H H H H H H H H H * * 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 H H H H L H* H H H H H H H H H H H H H H H H L H H H H H H H H H * * * * * * 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 H H H H H H* L H H H H H H H H H H H H H H H H H L H H H H H H H * * 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 H H H H H H* H L H H H H H H H H H H H H H H H H H L H H H H H H * * * * * * * 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 H H H H H L H H H H H H H H H H H H H H H H H L H H H H H H H H * * 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 H H H H H H* H H L H H H H H H H H H H H H H H H H H L H H H H H * 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 H H H H H H* H H H L H H H H H H H H H H H H H H H H H L H H H H * * 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 H H H H H H* H H H H L H H H H H H H H H H H H H H H H H L H H H * * * * 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 H H H H H H* H H H H H L H H H H H H H H H H H H H H H H H L H H * * 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 H H H H H H* H H H H H H L H H H H H H H H H H H H H H H H H L H * * * * * * 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 H H H H H H* H H H H H H H H L H H H H H H H H H H H H H H H H H * * 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 H H H H H H* H H H H H H H H H L H H H H H H H H H H H H H H H H * * * * * * * 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 H H H H H H H H H H H H H L H H H H H H H H H H H H H H H H H L * * 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 H H H H H H* H H H H H H H H H H L H H H H H H H H H H H H H H H * 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 H H H H H H* H H H H H H H H H H H L H H H H H H H H H H H H H H * * 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 H H H H H H* H H H H H H H H H H H H L H H H H H H H H H H H H H * * * * 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 H H H H H H* H H H H H H H H H H H H H H H H H H H H H H H H H H * * * * * * * 0 = Input Low, 1 = Input High, L= Output Low, H = Output High * * * * * FIND, Vol. 17, No. 3, August 1999