PIC18(L)F25/45K22 PIC18(L)F25/45K22 Rev. A2/A3/A4 Silicon Errata and Data Sheet Clarification The PIC18(L)F25/45K22 family devices that you have received conform functionally to the current Device Data Sheet (DS41412C), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. The errata described in this document will be addressed in future revisions of the PIC18(L)F25/45K22 silicon. Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 2 apply to the current silicon revision (A4). Data Sheet clarifications and corrections start on page 5, following the discussion of silicon issues. The silicon revision level can be identified using the current version of MPLAB(R) IDE and Microchip's programmers, debuggers, and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 2 or PICkitTM 3: 1. 2. 3. 4. Using the appropriate interface, connect the device to the MPLAB ICD 2 programmer/ debugger or PICkitTM 3. From the main menu in MPLAB IDE, select Configure>Select Device, and then select the target part number in the dialog box. Select the MPLAB hardware tool (Debugger>Select Tool). Perform a "Connect" operation to the device (Debugger>Connect). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window. Note: If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. The DEVREV values for the various PIC18(L)F25/ 45K22 silicon revisions are shown in Table 1. SILICON DEVREV VALUES Part Number Device ID(1) Revision ID for Silicon Revision(2) A2 A3 A4 PIC18F25K22 0101 0101 010x xxxx 0 0010 0 0011 0 0100 PIC18LF25K22 0101 0101 011x xxxx 0 0010 0 0011 0 0100 PIC18F45K22 0101 0101 000x xxxx 0 0010 0 0011 0 0100 PIC18LF45K22 0101 0101 001x xxxx 0 0010 0 0011 0 0100 Note 1: 2: The Device ID is located in the last configuration memory space. Refer to the "PIC18(L)F2XK22/4XK22 Flash Memory Programming Specification" (DS41398) for detailed information on Device and Revision IDs for your specific device. 2010 Microchip Technology Inc. DS80498B-page 1 PIC18(L)F25/45K22 TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Affected Revisions(1) Issue Summary A2 A3 A4 Voltage Reference Default Value 1.1 VREFCON0 = 0X00 at Reset. X X Voltage Reference Internal Reference 1.2 Reference may be unstable at low temperatures. X X HLVD HLVD module 2. The HLVD module does not function. X X Comparators CxSYNC Control 3. The comparator output to the device pin (Cx) always bypasses the Timer1 synchronization latch. X X HS Oscillator HS Oscillator Start-up 4. HS oscillator may not start at low voltage/ high temperature. X X Clock Switching Fail-Safe mode 5.1 Execution is delayed when waking from Sleep. X X Clock Switching Fail-safe Clock Monitor 5.2 When the FCMEN Configuration bit is set and the IESO Configuration bit is not set, then a clock failure during Sleep will not be detected. CTMU Current Source 6.1 Current source is noisy. X X CTMU Control Register 6.2 Control registers are not cleared by Resets. X X CCP3, CCP4 and CCP5 PWM mode 7. Clock selection by CCP2 only. X X ADC GO/DONE bit 8. GO/DONE bit gets stuck. X X Power-on Reset (POR) Power-on Reset 9.1 Transient current spikes on some parts during power-up may cause the part to become stuck in Reset. X X X Power-on Reset (POR) Power-on Reset 9.2 Min VDD for PIC18F2X/4XK22 parts is limited to 2.3V. Min VDD for PIC18LF2X/4XK22 parts is 1.8V. X X X Timer1/3/5 Gate Timer1/3/5 Gate 10. The Timer1/3/5 gate times cannot be resolved to the two Least Significant bits, when using FOSC as the Timer1/3/5 source. X X X Note 1: X Only those issues indicated in the last column apply to the current silicon revision. DS80498B-page 2 2010 Microchip Technology Inc. PIC18(L)F25/45K22 Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A4). 3. Module: Comparators The CxSYNC controls are inoperative. The comparator output (Cx) always bypasses the Timer1 synchronization latch. Work around None. Affected Silicon Revisions 1. Module: Voltage Reference 1.1 The default value of VREFCON0 after Reset is 0x00 instead of 0x10. A2 A3 X X A4 4. Module: HS Oscillator Work around Select the desired fixed voltage reference buffer as part of initialization. The HS oscillator may not start when VDD is less than 3V, especially at high temperatures. Affected Silicon Revisions Work around A2 A3 X X 1.2 A4 Affected Silicon Revisions Internal voltage reference may become unstable at cold temperature. Work around Affected Silicon Revisions A3 X X A2 A3 X X A4 5. Module: Clock Switching None. A2 None. 5.1 A4 When Clock Fail-Safe mode or Clock Switchover mode is selected, then code execution will be delayed after waking from Sleep by the start-up time of the HFINTOSC. Work around 2. Module: HLVD Although the HLVDIF flag will be set immediately after enabling the HLVD circuit, the HLVD module is not functional and should not be used. Work around None. Affected Silicon Revisions A2 A3 X X Disable HFINTOSC stabilization time by setting the HFOFST bit of the Configuration register 3H. Affected Silicon Revisions A2 A3 X X 5.2 A4 A4 When the FCMEN Configuration bit is set and the IESO Configuration bit is not set, then a clock failure during Sleep will not be detected. Work around The IESO Configuration bit must also be set when the FCMEN Configuration bit is set. Affected Silicon Revisions A2 A3 A4 X 2010 Microchip Technology Inc. DS80498B-page 3 PIC18(L)F25/45K22 6. Module: CTMU 6.1 Current source may be noisy to the CTMU module. 9. Module: Power-on Reset (POR) 9.1 Work around None. Affected Silicon Revisions A2 A3 X X 6.2 A4 CTMU control registers are not cleared by the RESET instruction or MCLR Reset. Work around Clear the CTMU control registers as part of device initialization. Work around Ensure that the application is capable of supplying at least 30 mA of transient current during powerup. Affected Silicon Revisions A2 A3 A4 X X X 9.2 Affected Silicon Revisions A2 A3 X X A4 PWM mode does not work independently of CCP2. Clock selection is cross-wired with that of CCP2. Use CCP1 and/or CCP2 for PWM applications. Reserve CCP3, CCP4 and CCP5 for capture and compare applications. Affected Silicon Revisions X X Work around Affected Silicon Revisions A2 A3 A4 X X X 10. Module: Timer1/3/5 Gate Work around A3 Min VDD for PIC18F2X/4XK22 parts is limited to 2.3V. Min VDD for PIC18LF2X/ 4XK22 parts is 1.8V. None. 7. Module: CCP3, CCP4 and CCP5 A2 There may be transient current spikes on some parts during power-up. If the application cannot supply enough current to get past these transients, then the part may become stuck in Reset. A4 The Timer gate times cannot be resolved to the two Least Significant timer bits when the source frequency is FOSC (TMRxCS[1:0]=01). This is because the gate edges are synchronized with the FOSC/4 clock. Work around None. 8. Module: ADC GO/DONE bit may become stuck in GO mode. Work around Affected Silicon Revisions A2 A3 A4 X X X Use the ADC FRC clock selection to reduce the probability of the GO bit becoming stuck. To capture the events when the GO bit does become stuck, use one of the timers to determine if the GO bit stays set longer than expected. When this occurs, restart the ADC conversion by clearing the GO/DONE bit and then setting the GO/DONE bit. Affected Silicon Revisions A2 A3 X X DS80498B-page 4 A4 2010 Microchip Technology Inc. PIC18(L)F25/45K22 Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS41412C): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: I/O Ports In Table 10-5, the Buffer Type column listed ST (Schmitt Trigger) for functions RB1-RB7, when the Pin Type was I (Input), should be TTL. The Table below reflects the correction. TABLE 10-5: Pin PORTB I/O SUMMARY Function RB0/INT0/CCP4/ FLT0/SRI/SS2/ AN12 RB0 INT0 1 O DIG LATB<0> data output; not affected by analog input. 1 0 I TTL PORTB<0> data input; disabled when analog input enabled. I ST External interrupt 0. Compare 4 output/PWM 4 output. 1 0 O DIG I ST Capture 4 input. FLT0 1 0 I ST PWM Fault input for ECCP auto-shutdown. SRI 1 0 I ST SR Latch input. SS2(3) 1 0 I TTL SPI slave select input (MSSP2). AN12 1 1 I AN Analog input 12. RB1 0 1 O DIG LATB<1> data output; not affected by analog input. 1 0 I TTL PORTB<1> data input; disabled when analog input enabled. 1 0 I ST External Interrupt 1. 0 1 O DIG Enhanced CCP1 PWM output 3. 0 1 O DIG MSSP2 SPI Clock output. 1 0 I ST MSSP2 SPI Clock input. 0 1 O DIG MSSP2 I2CTM Clock output. 1 0 I I2C MSSP2 I2CTM Clock input. C12IN3- 1 1 I AN Comparators C1 and C2 inverting input. AN10 1 1 I AN Analog input 10. (3) SCL2(3) 3: 0 0 P1C 2: Description 1 SCK2(3) Note 1: Buffer Type 1 INT1 Legend: Pin Type 0 CCP4 RB1/INT1/P1C/ SCK2/SCL2/ C12IN3-/AN10 (3) TRIS ANSEL Setting Setting AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C. Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. Function on PORTD and PORTE for PIC18(L)F4XK22 devices. 2010 Microchip Technology Inc. DS80498B-page 5 PIC18(L)F25/45K22 TABLE 10-5: PORTB I/O SUMMARY Pin Function RB2/INT2/CTED1/ P1B/SDI2/SDA2/ AN8 RB2 RB4/IOC0/P1D/ T5G/AN11 RB5/IOC1/P2B/ P3A/CCP3/T3CKI/ T1G/AN13 Legend: Note 1: 2: 3: Pin Type Buffer Type Description 0 1 O DIG LATB<2> data output; not affected by analog input. 1 0 I TTL PORTB<2> data input; disabled when analog input enabled. External interrupt 2. INT2 1 0 I ST CTED1 1 0 I ST CTMU Edge 1 input. P1B(3) 0 1 O DIG Enhanced CCP1 PWM output 2. SDI2(3) 1 0 I ST MSSP2 SPI data input. (3) 0 0 O DIG MSSP2 I2CTM data output. I I2C MSSP2 I2CTM data input. SDA2 RB3/CTED2/P2A/ CCP2/SDO2/ C12IN2-/AN9 TRIS ANSEL Setting Setting 1 0 AN8 1 1 I AN Analog input 8. RB3 0 1 O DIG LATB<3> data output; not affected by analog input. 1 0 I TTL PORTB<3> data input; disabled when analog input enabled. CTED2 1 0 I ST CTMU Edge 2 input. P2A 0 1 O DIG Enhanced CCP1 PWM output 1. CCP2(2) 0 1 O DIG Compare 2 output/PWM 2 output. 1 0 I ST Capture 2 input. SDO2(2) 0 1 O DIG MSSP2 SPI data output. C12IN2- 1 1 I AN Comparators C1 and C2 inverting input. AN9 1 1 I AN Analog input 9. RB4 0 1 O DIG LATB<4> data output; not affected by analog input. 1 0 I TTL PORTB<4> data input; disabled when analog input enabled. IOC0 1 0 I TTL Interrupt-on-change pin. P1D 0 1 O DIG Enhanced CCP1 PWM output 4. T5G 1 0 I ST Timer5 external clock gate input. AN11 1 1 I AN Analog input 11. RB5 0 1 O DIG LATB<5> data output; not affected by analog input. 1 0 I TTL PORTB<5> data input; disabled when analog input enabled. IOC1 1 0 I TTL Interrupt-on-change pin 1. P2B(1)(3) 0 1 O DIG Enhanced CCP2 PWM output 2. P3A(1) 0 1 O DIG Enhanced CCP3 PWM output 1. CCP3(1) 0 1 O DIG Compare 3 output/PWM 3 output. 1 0 I ST Capture 3 input. T3CKI(2) 1 0 I ST Timer3 clock input. T1G 1 0 I ST Timer1 external clock gate input. AN13 1 1 I AN Analog input 13. AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C. Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. Function on PORTD and PORTE for PIC18(L)F4XK22 devices. DS80498B-page 6 2010 Microchip Technology Inc. PIC18(L)F25/45K22 TABLE 10-5: Pin PORTB I/O SUMMARY Function RB6/KBI2/PGC RB7/KBI3/PGD RB6 Note 1: 2: 3: Pin Type Buffer Type Description 0 1 O DIG LATB<6> data output; not affected by analog input. 1 0 I TTL PORTB<6> data input; disabled when analog input enabled. IOC2 1 0 I TTL Interrupt-on-change pin. TX2(3) 0 1 O DIG EUSART 2 asynchronous transmit data output. CK2(3) 0 1 O DIG EUSART 2 synchronous serial clock output. 1 0 I ST EUSART 2 synchronous serial clock input. PGC x x I ST In-Circuit Debugger and ICSPTM programming clock input. RB7 0 1 O DIG LATB<7> data output; not affected by analog input. 1 0 I TTL PORTB<7> data input; disabled when analog input enabled. IOC3 1 0 I TTL Interrupt-on-change pin. RX2(2), (3) 1 0 I ST EUSART 2 asynchronous receive data input. DT2(2), (3) 0 1 O DIG EUSART 2 synchronous serial data output. 1 0 I ST EUSART 2 synchronous serial data input. x x O DIG In-Circuit Debugger and ICSPTM programming data output. x x I ST In-Circuit Debugger and ICSPTM programming data input. PGD Legend: TRIS ANSEL Setting Setting AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I2CTM = Schmitt Trigger input with I2C. Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are set. Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and CCP2MX are clear. Function on PORTD and PORTE for PIC18(L)F4XK22 devices. 2010 Microchip Technology Inc. DS80498B-page 7 PIC18(L)F25/45K22 APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (5/2010) Initial release of this document. Rev B Document (8/2010) Updated errata to the new format; Updated for Revision A4 silicon release; Added Modules 5.2, 9.1, 9.2 and 10. Data Sheet Clarifications: Added Module 1. DS80498B-page 8 2010 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. 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Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-457-5 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2010 Microchip Technology Inc. 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