108416678 - Agere Systems, Inc.

NetLight

® 1417G5 and 1417H5-Type

ATM/SONET/SDH Transceivers with Clock Recovery

Data Sheet

January 2000

Av ailable in a small form factor, RJ-45 size, plastic package,

the 1417G5 and 1417H5-Type are high-performance, cost-

effective transceivers for ATM/SONET/SDH applications at

155 Mbits/s and 622 Mbits/s.

Features

■SONET/SDH Compliant (ITU-T G.957 Specifica-

tions)

— IR-1/S1.1, S4.1

■Small form factor, RJ-45 size, multisourced 20-pin

package

■Requires single 3.3 V power supply

■Clock recovery

■LC duplex receptacle

■Analog alarm outputs

■Uncooled 1300 nm laser transmitter with automatic

output power control

■Transmitte r dis able input

■Wide dynamic range receiver with InGaAs PIN

photodetector

■LVTTL signal-detect output

■Low power dissipation

■Raised ECL (PECL) logic data and clock interf aces

■Operating case temperature range: –40 °C to

+85 °C

■Agere Systems Inc. Reliability and Qualification

Program for built-in quality and reliability

Description

The 1417G5 and 1417H5 transceivers are high-

speed, cost-effective optical transceivers that are

compliant with the International Telecommunication

Union Telecommunication (ITU-T) G.957 specifica-

tions for use in ATM, SONET, and SDH applications.

The 1417G5 operates at the OC-3/STM-1 rate of

155 Mbits/s, and the 1417H5 operates at the OC-12/

STM-4 rate of 622 Mbits/s. The transceiver features

Agere Systems high-reliability optics and is pack-

aged in a narrow-width plastic housing with an LC

duplex receptacle. This receptacle fits into an RJ-45

form factor outline. The 20-pin package and pinout

conform to a multisource transceiver agreement.

The transmitter features differential PECL logic level

data inputs and a LVTTL logic lev el disable input. The

receiver features differential PECL logic level data

and clock outputs and a LVTTL logic level signal-

detect output.

2Ager e Systems Inc.

NetLight

1417G5 and 1417H5-Type Data Sheet

ATM/SONET/SDH Transceive rs with Cl ock Recovery January 2000

Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-

lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess

of those given in the operations sections of the data sheet. Exposure to absolute maximum ratings for extended

periods can adversely affect device reliability.

Pin Information

1-967(F).b

Figure 1. 1417G5 and 1714H5 Transceivers, 20-Pin Configuration, Top View

Table 1. Transceiver Pin Descriptions

Parameter Symbol Min Max Unit

Supply Voltage VCC 03.6V

Operating Case Temperature Range TC–40 85 °C

Storage Case Temperature Range Tstg –40 85 °C

Lead Soldering Temperature/Time — — 250/10 °C/s

Operating Wa velength Range λ1.1 1.6 nm

Number Symbol Name/Description Logic

Family

Receiver

MS MS Mounting Studs. The mounting studs are provided for transceiver mechani-

cal attachment to the circuit board. They may also provide an optional con-

nection of the transceiver to the equipment chassis ground.

1 Photode-

tector Bias Photodetector Bias. This lead supplies bias for the PIN photodetector diode. NA

EER Receiv er Signal Ground. NA

4CLK–

Received Reco vered Clock Out. The rising edge occurs at the rising edge of

the receiv ed data output. The f alling edge occurs in the middle of the received

data bit period.

PECL

5CLK+

Received Recovered Clock Out. The falling edge occurs at the rising edge

of the received data output. The rising edge occurs in the middle of the

received data bit period.

PECL

EER Receiv er Signal Ground. NA

CCR Receiv er Power Supply. NA

8SD

Signal Detect.

Normal operation: logic one output.

Fault condition: logic zero output.

LVTTL

9 RD– Received DATA Out. No internal terminations will be pro vided. PECL

10 RD+ Received DATA Out. No internal terminations will be provided. PECL

678910

15 14 13 12 11

20-PIN MODULE - TOP VIEW

RX 12345

20 19 18 17 16

Agere Systems Inc.

Data Sheet

NetLight

1417G5 and 1417H5-Type

January 2000 ATM/S ONET/SDH Transceivers with Cl ock Recovery

Transmitter

11 VCCT Transmitter Power Supply. NA

12 VEET Transmitter Signal Ground. NA

13 TDIS Tran smitt er Disable. LVTTL

14 TD+ Transmitter Data In. PECL

15 TD– Transmitter Data In Bar. PECL

16 VEET Transmitter Signal Ground. NA

17 BMON(–) Laser Diode Bias Current Monitor—Negative End. The laser bias current

is accessib le as a dc-v oltage by measuring the voltage dev eloped across pins

17 and 18.

18 BMON(+) Laser Diode Bias Current Monitor—Positive End. See pin 17 description. NA

19 PMON(–) Laser Diode Optical Power Monitor—Negative End. The back-facet diode

monitor current is accessible as a dc-voltage by measuring the voltage devel-

oped across pins 19 and 20.

20 PMON(+) Laser Diode Optical Power Monitor—Positive End. See pin 19 description. NA

Number Symbol Name/Description Logic

Family

Electrostatic Discharge

Caution: This device is susceptible to damage as

a result of electrostatic discharge (ESD).

Take proper precautions during both

handling and testing. Follow

EIA

® stan-

dard

EIA

-625.

Although protection circuitry is designed into the

device, take proper precautions to avoid exposure to

ESD. Agere Systems employs a human-body model

(HBM) for ESD-susceptibility testing and protection-

design evaluation. ESD voltage thresholds are depen-

dent on the critical parameters used to define the

model. A standard HBM (resistance = 1.5 kΩ, capaci-

tance = 100 pF) is widely used and, therefore, can be

used for comparison purposes. The HBM ESD thresh-

old established for the 1417G5 and 1417H5 transceiv-

ers is ±1000 V.

Application Information

The 1417 receiver section is a highly sensitive fiber-

optic receiver. Although the data outputs are digital

logic lev els (PECL), the device should be thought of as

an analog component. When laying out system appli-

cation boards, the 1417 transceiver should receive the

same type of consideration one would give to a sensi-

tive analog component.

Printed-Wiring Board Layout Considerations

A fiber-optic receiver employs a very high-gain, wide-

bandwidth transimpedance amplifier. This amplifier

detects and amplifies signals that are only tens of nA in

amplitude when the receiv er is operating near its sensi-

tivity limit. Any unwanted signal currents that couple

into the receiver circuitry cause a decrease in the

receiver's sensitivity and can also degrade the perfor-

mance of the receiver's signal detect (SD) circuit. To

minimiz e the coupling of unwanted noise into the

receiver, careful attention must be given to the printed-

wiring board.

At a minimum, a double-sided printed-wiring board

(PWB) with a large component-side ground plane

beneath the transceiver must be used. In applications

that include many other high-speed devices, a multi-

layer PWB is highly recommended. This permits the

placement of power and ground on separate layers,

which allows them to be isolated from the signal lines.

Multilayer construction also permits the routing of sen-

sitive signal traces away from high-level, high-speed

signal lines. To minimiz e the possibility of coupling

noise into the receiver section, high-level, high-speed

signals such as transmitter inputs and clock lines

should be routed as far away as possible from the

receiver pins.

Pin Information (continued)

Table 1. Transceiver Pin Descriptions (continued)

4Ager e Systems Inc.

NetLight

1417G5 and 1417H5-Type Data Sheet

ATM/SONET/SDH Transceive rs with Cl ock Recovery January 2000

Application Information (continued)

Noise that couples into the receiver through the power

supply pin s can also degrade performan ce. It is recom -

mended that the pi filter, shown in Figure 2, be used f or

both the transmitter and receiver power supplies.

Data Clock and Signal Detec t Outputs

The data clock and signal detect outputs of the 1417

transceiver are driv en by open-emitter NPN transistors,

which have an output impedance of appro ximately 7 Ω.

Each output can provide approximately 50 mA maxi-

mum current to a 50 Ω load terminated to VCC – 2.0 V.

Due to the high switching speeds of ECL outputs,

transmission line design must be used to interconnect

components. To ensure optimum signal fidelity, both

data outputs (RD+/RD–) and clock outputs (CLK+/

CLK–) should be terminated identically. The signal

lines connecting the data and clock outputs to the next

device should be equal in length and have matched

impedances. Controlled impedance stripline or micros-

trip construction must be used to preserv e the quality

of the signal into the next component and to minimize

reflections back into the receiver, which could degrade

its performance. Excessive ringing due to reflections

caused by improperly terminated signal lines makes it

difficult for the component receiving these signals to

deciphe r the pr ope r logic level s and ca n cause t ransi-

tions to occur where none were intended. Also, by min-

imizing high-frequency ringing, possible EMI problems

can be avoided.

The signal-detect output is LVTTL logic. A logic low at

this output indicates that the optical signal into the

receiver has been interrupted or that the light level has

fallen below the minimum signal detect threshold. This

output should not be used as an error rate indicator,

since its switching threshold is determined only by the

magnitude of the incoming optical signal.

Transceiver Processing

When the process plug is placed in the transceiver's

optical port, the trans ceiver and plug can withst and

normal wave soldering and aqueous spray cleaning

processes. However, the transceiver is not hermetic,

and should not be subjected to immersion in cleaning

solvents. The transceiver case should not be exposed

to temperatures in excess of 125 °C. The transceiver

pins can be wave soldered at 250 °C for up to 10 sec-

onds. The process plug should only be used once.

After removing the process plug from the tr ansceiver, it

mus t not be us ed ag ain as a proc ess pl ug; h ow e v er, if it

has not been contaminated, it can be reused as a dust

cover.

Transceiver Optical and Electrical Characteristics

Table 2. Transmitter Optical and Electrical Characteristics (TC = –40 °C to +85 °C; VCC = 3.135 V to 3.465 V)

Parameter Symbol Min Max Unit

Average Optical Output Power (EOL) PO–15.0 –8.0 dBm

Optical Wavelength:

STM-1 (4 nm spectral width, maximum)

STM-4 (2.5 nm spectral width, maximum)

λC1261

1274 1360

1356 nm

Dynamic Extinction Ratio EXT 8.2 — dB

Power Supply Current ICCT — 150 mA

Input Data Voltage:

Low

High VIL

VIH VCC – 1.81

VCC – 1.025 VCC – 1.62

VCC – 0.88 V

Transmit Dis able Vo ltage VDVCC – 1.3 VCC V

Transmit Enable Voltage VEN VEE VEE + 0.8 V

Laser Bias Voltage VBIAS 00.70V

Laser Back-facet Monitor Voltage VBF 0.01 0.20 V

Agere Systems Inc.

Data Sheet

NetLight

1417G5 and 1417H5-Type

January 2000 ATM/S ONET/SDH Transceivers with Cl ock Recovery

Transceiver Optical and Electrical Characteristics (continued)

Table 3. Receiver Optical and Electrical Characteristics (TC = –40 °C to +85 °C; VCC = 3.135 V to 3.465 V)

* For 1 x 10–10 BER with an optical input using 223 – 1 PRBS.

† Typical r ise and fall time is 360 ps.

1-725(F).b

Figure 2. Clock/Data Alignment

Parameter Symbol Min Max Unit

Average Sensitivity (STM-1/STM-4)* PI—–28dBm

Maximum Input Power* PMAX –8 — dBm

Link Status Switching Threshold:

Decreasing Light (STM-1/STM-4)

Increasing Light (STM-1/STM-4) LSTD

LSTI–45

–45 –29.0

–28.5 dBm

dBm

Link Status Hysteresis HYS 0.5 — dB

Power Supply Current ICCR —200mA

Output Data Voltage/Clock Voltage:

Low

High VOL

VOH VCC – 1.81

VCC – 1.025 VCC – 1.62

VCC – 0.88 V

Output Data/Clock Rise and Fall Times†tR/tF300 500 ps

Signal Detect Output Voltage:

Low

High VOL

VOH 0.0

2.4 0.8

VCC V

Clock Duty Cycle DC 45 55 %

Output Clock Random Jitter JC—0.01UI

Output Clock Random Jitter Peaking JP—0.1dB

Clock/Data Alignment: (See Figure 2.)

STM-1

STM-4

TCDA –800

–200 800

200 ns

Jitter Tolerance/Jitter Transfer

Telcordia Technologies

® GR-253-Core and

ITU-TG.958 Comp li ant

50%

CLOCKOUT

DATAOUT

TCDA

6Ager e Systems Inc.

NetLight

1417G5 and 1417H5-Type Data Sheet

ATM/SONET/SDH Transceive rs with Cl ock Recovery January 2000

Qualification and Reliability

To help ensure high product reliability and customer satisfaction, Agere Systems is committed to an intensive qual-

ity program that starts in the design phase and proceeds through the manufacturing process. Optoelectronic mod-

ules are qualified to Agere Systems internal standards using MIL-STD-883 test methods and procedures and using

sampling techniques consistent with

Telcordia Technologies

requirements. The 1417 transceiver is required to pass

an extensive and rigorous set of qualification tests.

This qualification program fully meets the intent of

Telcordia Technologies

reliability practices TR-NWT-000468 and

TA-TSY-000983 requirements . In addition, the design, dev elopment, and manufacturing facilities of Agere Systems

Optoelectronics unit have been certified to be in full compliance with the latest

ISO

® 9001 quality system stan-

dards.

Electrical Schematic

1-968(F).b

* Ferrite beads can be used as an option.

† For all capacitors, MLC caps are recommended.

Figure 3. Po wer Supply Filtering f or the Small Form Factor Transceiver

L1 = L2 = 1 µH—4.7 µH*

C1 = C2 = 10 nF†

C3 = 4.7 µF—10 µF

C4 = C5 = 4.7 µF—10 µF

RECEIVER

POST-

AMPLIFIER/

CDR

17 18 19 20

TD–

TD+

VEET 12, 16

PREAMP

RD+

RD–

VEER

VCCT

VCCR

SFF TRANSCEIVER

2, 3, 6

7C4 C5

C2 C3 C1

VCC

BMON–

BMON+

PMON–

PMON+

TDIS 13

CLK+

CLK–

VPD 1

TRANSMITTER

DRIVER

15 Ω

10 Ω

15 Ω

200 Ω

Agere Systems Inc.

Data Sheet

NetLight

1417G5 and 1417H5-Type

January 2000 ATM/S ONET/SDH Transceivers with Cl ock Recovery

Application Schematics

1-970(F).b

Figure 4. 3.3 V Transceiver Interface with 3.3 V ICs

TD+

TD– 100 ΩLVPECL

130 Ω130 Ω

VCC (3.3 V) VCC (3.3 V)

A. Transmitter Interface (LVPECL to LVPECL)

RD+/CLK+

RD–/CLK– LVPECL

VCC (3.3 V) VCC (3.3 V)

100 Ω

130 Ω

B. Receiver Interface (LVPECL to LVPECL)

Z = 50 Ω

8Ager e Systems Inc.

NetLight

1417G5 and 1417H5-Type Data Sheet

ATM/SONET/SDH Transceive rs with Cl ock Recovery January 2000

Outline Diagrams

Package Outline

Dimensions are in inches and (millimeters).

1-1086(F)

* Dimension does not comply with multisource agreement.

1.907

0.500*

0.014 (0.36)

0.070 (1.78)

0.125 (3.17)

0.299 (7.59)

0.040 (1.02)

0.018 (0.46)

0.400

(48.44)

(12.70)

(10.16)

0.535 MAX

(13.59)

0.350 (8.89)

0.385

0.115 0.246

(9.78)

(2.92) (6.25)

0.251

(6.38)

0.512

(13.00)

1417

TRANSCEIVER

0.433

1.474

1.907

0.500*

0.014 (0.36)

0.070 (1.78)

0.125 (3.17)

0.299 (7.59)

0.040 (1.02)

0.018 (0.46)

0.400

(37.44) (11.00)

(48.44)

(12.70)

(10.16)

0.535 MAX

(13.59)

0.350 (8.89)

0.385

0.115 0.246

(9.78)

(2.92) (6.25)

0.251

(6.38)

0.512

(13.00)

AGERE

SYSTEMS

Agere Systems Inc.

Data Sheet

NetLight

1417G5 and 1417H5-Type

January 2000 ATM/S ONET/SDH Transceivers with Cl ock Recovery

Outline Diagrams (continued)

Printed-Wiring Board Layout* and Recommended Panel Opening

1-1088(F)

* Per multisource agreement.

0.582

(14.78)

0.550

(13.97)

0.400

(10.20)

0.039

(1.00)

0.113

(2.87)

0.105

(2.67)

0.300

(7.62)

0.118

(3.00)

0.630

(15.75)

0.070

(1.78)

0.350

(8.89)

2.00

(0.079)

0.121

(3.07) 0.079

(3.00)

0.079

(3.00)

0.400

(10.20) 0.550

(13.97)

0.378

(9.60)

0.118

(3.00) 0.039

(1.00)

0.079

(2.00)

0.055 ± 0.004 DIA. 2X

(1.40 ± 0.1) DIA

0.032 ± 0.004 DIA. 20X

(0.81 ± 0.1) DIA

NetLight

1417G5 and 1417H5-Type Data Sheet

ATM/SONET/SDH Transceive rs with Cl ock Recovery January 2000

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

NetLight

is a registered trademark of Agere Systems Inc.

Jan uary 2000

DS00-100OPTO (Replaces DS99-227LWP)

For additional informatio n, co nta ct you r Agere Systems Account Manag er o r the foll ow ing:

INTERNET: http://www.agere.com

E-MAIL: docmaster@agere.com

N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15 P-BA, Allentown, PA 18109-3286

1-800-372-2447, FAX 610-712-4106 (In CA NADA: 1-800-553-2448, FAX 610-712-4106)

ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Ha rbour City, Kowloon

Tel. (852) 3129-2000, FAX (852) 3129-2 020

CHINA: (86) 21- 5 047-1212 ( Sh anghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Sh enz hen)

JAPAN: (81) 3- 54 21-1600 (Tokyo), KO REA: (82) 2- 767-18 50 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-27 25-585 8 (Taipei)

EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045

Laser Safety Informatio n

Class I Laser Product

FDA/CDRH Class I laser product. All versions of the transceiver are Class I laser products per CDRH, 21 CFR

1040 Laser Safety requirements. All versions are Class I laser products per

IEC

® 60825-1:1993. The transceiver

has been certified with the FDA under accession number 8720009.

CAUTION: Use of controls, adjustments, and procedures other than those specified herein may result in

hazardous laser radiation exposure.

This product complies with 21 CFR 1040.10 and 1040.11.

Wavelength = 1. 3 µm

Maximum power = 0.2 mW

Because of size constraints, laser safety labeling (Including an FD A Class IIIb label) is not affixed to the module but

is attached to the outside of the shipping carton.

Product is not shipped with power supply.

NOTICE

Unterminated optical connectors may emit laser radiation.

Do not view with optical instruments.

Ordering Information

Table 4. Ordering Information

EIA

is a registered trademar k of Electronic Industries Association.

Telcor dia Technologies

is a trademark of Telcordia Technologies Inc.

IEC

is a registered trademark of The International Electrotechnical Commission.

ISO

is a registered trademark of The International Organization for Standardization.

Description Device Code Comcode

2 x 10 Single-mode Transceiver for OC-3 /STM-1 (155 Mbits/s)

with Clock Recovery 1417G5A 108416678

2 x 10 Single-mode Transceiver for OC-12 /STM-4 (622 Mbits/s)

with Clock Recovery 1417H5A 108416686

Agere Systems Inc.

Data Sheet

NetLight

1417G5 and 1417H5-Type

January 2000 ATM/S ONET/SDH Transceivers with Cl ock Recovery

12 Ager e Systems Inc.

NetLight

1417G5 and 1417H5-Type Data Sheet

ATM/SONET/SDH Transceive rs with Cl ock Recovery January 2000