STEF01 Datasheet 8 V to 48 V fully programmable universal electronic fuse Features HTSSOP14 * * * * * * * * * * * * * * * * Operating input voltage range: 8 to 48 V Absolute maximum input voltage: 55 V Continuous current typ.: 4 A N-channel on-resistance typ.: 30 m Enable/fault functions Output clamp voltage: adjustable from 10 to 52 V Programmable undervoltage lockout Short-circuit current limit Programmable overload current limit Adjustable soft-start time Latch or auto-retry thermal protection Maximum allowable power protection Power Good Drives an optional external reverse current protection MOSFET Operating junction temperature -40 C to 125 C HTSSOP14 package Applications Maturity status link STEF01 Device summary Order code STEF01FTR Package HTSSOP14 Packing Tape and reel * * * * * Hot board insertion Electronic circuit breaker/power busing Industrial/alarm/lighting systems Distributed power systems Telecom power modules Description The STEF01 is a universal integrated electronic fuse optimized for monitoring output current and the input voltage on DC power lines. When connected in series to the main power rail, it is able to detect and react to overcurrent and overvoltage conditions. When an overload condition occurs, the device limits the output current to a safe value defined by the user. If the anomalous overload condition persists, the device goes into an open state, disconnecting the load from the power supply. The device is fully programmable. UVLO, overvoltage clamp and start-up time can be set by means of external components. The adjustable turn-on time is useful to keep the in-rush current under control during startup and hot-swap operations. The device provides either thermal latch and autoretry protection modes, which are selectable by means of a dedicated pin. The STEF01 provides a gate driver pin for an external power MOSFET to implement a reverse-current blocking circuit. The intervention of the thermal protection is signaled to the board monitoring circuits through a signal on the fault pin. DS12147 - Rev 5 - October 2018 For further information contact your local STMicroelectronics sales office. www.st.com STEF01 Device block diagram 1 Device block diagram Figure 1. Block diagram GIPD010220161057MT DS12147 - Rev 5 page 2/26 STEF01 Pin configuration 2 Pin configuration Figure 2. Pin configuration (top view ) 1 14 Expos e d pa d 7 8 HTSSOP14 GIPD010220161207MT Table 1. Pin description Pin n Symbol Note 1 UVLO A resistor divider connected between this pin, Vcc and GND sets the UVLO threshold. If left floating the UVLO is preset to 14.5 V. 2 dv/dt The internal dv/dt circuit controls the slew rate of the output voltage at turn-on. The internal capacitor allows a ramp-up time of around 3 ms. An external capacitor can be added to this pin to increase the ramp-up time. If an additional capacitor is not required, this pin should be left open. 3 GND Ground pin. 4 Auto This pin selects the thermal protection behavior. The device is set in latched mode when this pin is left floating or connected to a voltage higher than 1 V. It is set in auto-retry mode when the pin is connected to GND. A resistor divider connected between this pin, VOUT and GND sets the overvoltage clamp level. If left floating the clamp is preset to 28 V. 5 Vclamp 6, 7, 8, 9 VOUT Output port. All the pins must be tied together with short copper tracks. 10 I-Limit A resistor between this pin and VOUT sets the overload current limit level. 11 Vg Gate driver output for the optional external reverse-blocking MOSFET. Tri-state, bi-directional pin. During normal operation the pin must be left floating, or it can be used to disable the output of the device by pulling it to ground using an open drain or open collector device. 12 En/Fault 13 PG Power Good flag. It is an open drain, to be pulled up through an external resistor. 14 VCC Input port. Connect this pin to the exposed pad. Exposed pad VCC Exposed pad. Input port of the device, internally connected to the power element drain. DS12147 - Rev 5 If a thermal fault occurs, the voltage on this pin will go to an intermediate state to signal a monitoring circuit that the device is in thermal shutdown. It can be connected to another device of this family to cause a simultaneous shutdown during thermal events. page 3/26 STEF01 Maximum ratings 3 Maximum ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VCC Positive power supply voltage -0.3 to 55 V VOUT/source Output voltage pin -0.3 to VCC V I-Limit Current sense resistor pin -0.3 to VCC V ID Continuous current 6 A PG Power good flag pin -0.3 to VCC V Vclamp, UVLO Vclamp, UVLO pins -0.3 to 7 V En/Fault Enable/Fault pin -0.3 to 7 V dv/dt Startup time selection pin -0.3 to 7 V Auto Auto retry selection pin -0.3 to 7 V Vg Gate driver pin -0.3 to 65 V 150 C TJ Maximum junction temperature (1) TSTG Storage temperature range -65 to 150 C TLEAD Lead temperature (soldering) 10 s 260 C 1. The thermal limit is set above the maximum thermal rating. It is not recommended to operate the device at temperatures greater than the maximum ratings for extended periods of time. Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Table 3. Recommended operating condition Symbol Parameter Value Unit Operating power supply voltage, steady state 8 to 48 V Maximum power supply voltage, clamping active 52 V RLimit Current sense resistor range (1) 8 to 1000 ID Continuous current 4 A TJ Operating junction temperature -40 to 125 C VCC 1. Important: The RLimit resistor is mandatory in the application. Very low values of the RLimit or lack of connection of RLimit may lead to malfunction of current limiting circuit and to device damage. Table 4. Thermal data Symbol RthJA RthJC DS12147 - Rev 5 Parameter HTSSOP14 Thermal resistance junction-ambient, 2 layer PCB 140 Thermal resistance junction-ambient, 4 layer PCB 40 Thermal resistance junction-case 4 Unit C/W C/W page 4/26 STEF01 Electrical characteristics 4 Electrical characteristics VCC = 24 V, VEN = floating, CI = 10 F, CO = 47 F, TJ = 25 C (unless otherwise specified). Table 5. Electrical characteristics for STEF01 Symbol Parameter Test conditions Min. Typ. Max. Unit Under/over voltage protection Output clamping voltage VClamp VON VHyst Accuracy VCC = 36 V, VClamp = floating 28 V -5 +5 % 52 V 16 V 45 V Output clamping voltage range With external resistor divider on Vclamp pin 10 Under voltage lockout threshold Turn on, voltage going up, UVLO = floating 13 Under voltage lockout range With external resistor divider on UVLO pin 8 UVLO hysteresis 14.5 10 % Power MOSFET RDSon ON resistance VOFF Off state output voltage ID = 1 A (1) -40 C < TJ < 125 C 30 (2) 50 70 VCC = 36 V, VGS = 0, RL = infinite 1 20 m mV Current limit IShort Short circuit current limit RLimit = 22 , VOUT = gnd ILim Overload current limit RLimit = 22 , VOUT = VCC - 2 V, VCC > 8 V 1.5 3.2 4 A 4.8 A dv/dt circuit Enable to VOUT = 22 V, No Cdv/dt dv/dt 3 Output voltage ramp time Enable to VOUT = 46 V, VCC = 48 V, VClamp = 52 V, no Cdv/dt Idv/dt ms 3.6 dv/dt source pin current 100 nA Enable/Fault VIL Low level input voltage Output disabled VI(INT) Intermediate level input voltage Thermal fault, output disabled VIH High level input voltage Output enabled 2.8 VI(MAX) High state maximum voltage Pin floating 4.7 IIL Low level input current (sink) VEnable = 0 V 0 0.4 1.4 V V 5 V 5 5.3 V -20 -40 A 5 Units Maximum fan-out for fault Total number of chips that can be connected to this pin signal for simultaneous shutdown Power Good VD Power Good output threshold DS12147 - Rev 5 VCC - VOUT value for Power Good Hysteresis 1 0.1 V page 5/26 STEF01 Electrical characteristics Symbol VL Parameter Power Good output voltage low Test conditions Min. Typ. Isink = 6 mA open drain output Max. Unit 0.4 V External MOS gate driver Ig Sourcing current Device on 30 A Rp Strong pull down VEN = 0 V 450 Vg Gate driver voltage Vg-VOUT 8.5 9.5 10.5 V Auto-retry function VAR Autoretry logic level Auto-retry activated Latched protection activated 0.4 1 V Total device consumption IBias Vmin Bias current Device operational 0.4 Thermal shutdown (2) 0.1 Off state (VEN = GND) 0.1 Minimum operating voltage mA 8 V Thermal shutdown TSD Shutdown temperature (2) Hysteresis 175 Only in auto-retry mode 25 C 1. Pulsed test. 2. Guaranteed by design, but not tested in production. DS12147 - Rev 5 page 6/26 STEF01 Typical application 5 Typical application Figure 3. Application circuit VIN Vcc RL S TEF01 RP G RH C IN Exp.pa d C dv/dt R LIM ILIM PG UVLO VCLAMP dV/dt AUTO EN/Fa ult VOUT VOUT C OUT R1 R2 Vg GND GIPD010220161218MT 5.1 Operating modes 5.1.1 Turn-on and UVLO The device features a programmable UVLO block. If the input voltage exceeds the UVLO ON threshold (VON), the power pass element is turned on and the Enable/Fault pin goes up to the high state. Figure 4. UVLO block simplified diagram shows the simplified diagram of the UVLO circuit. The voltage at the UVLO pin is compared to an internal 1 V reference (0.9 V during turn OFF). The default ON threshold is set by internal divider (RHD, RLD) to 14.5 V; the ID current flowing through the internal divider is set to ~ 3 A. The UVLO threshold can be modified in accordance with power rail needs by adding the RH-RL resistor divider, as shown in Figure 4. UVLO block simplified diagram. The external divider is in parallel with the internal default one, therefore the threshold can be changed within the 8 V to 45 V range. Figure 4. UVLO block simplified diagram VCC VIN RH R HD UVLO RL IE ID UVLO ON R LD VRe f GND GIPD010220161241MT DS12147 - Rev 5 page 7/26 STEF01 Operating modes When the external divider is used, the ratio between external current IE and the internal current ID should be kept as high as possible, to guarantee maximum linearity of the circuit with respect to temperature and process variations. Setting IE/ID > 10 provides sufficient UVLO linearity, at the same time keeping overall current consumption at acceptable levels. Given the desired VON threshold, for a fixed value of the lower resistor RL, Equation 1 can be used to calculate the upper resistor RH. Equation 1 1 R H = ------------------------------------------------------------------(1 / R L + 1 / 333 ) 1 ------------------------------------------- - -----------------( VO N - 1 ) 4500 (resistor values are expressed in k) Figure 6. UVLO threshold (VON) vs RH, RL shows the relationship between RH and the UVLO turn ON threshold, for some fixed values of RL. Figure 6. UVLO threshold (VON) vs RH, RL 50000 RL=100k RL=50k RL=33k RL=20k RL=10k R H [k] 5000 500 50 5 10 15 20 25 30 VON [V] 35 40 45 50 GIPD010220161252MT The resistor divider approach described above guarantees the best UVLO performance in terms of accuracy and temperature dependance. In order to reduce the application B.O.M., the 1-resistor approach can be used also, at the expenses of overall UVLO circuit accuracy. In this case, the RH resistor can be omitted for VON thresholds higher than 14.5 V, or RL for VON lower than 14.5 V. In any case it is recommended to check that in all operating conditions, the UVLO threshold is never lower than 8 V, in order to guarantee correct operation. After an initial delay time of typically 170 s, the output voltage is supplied with a slope defined by the internal dv/dt circuitry. If no additional capacitor is connected to the dv/dt pin, the total time from the Enable signal going high and the output voltage reaching the nominal value is around 3 ms. 5.1.2 Normal operating condition The STEF01 E-fuse provides the circuitry on its output with the same voltage shown at its input, with a small voltage fall due to the N-channel MOSFET RDS-on. 5.1.3 Output voltage clamp If the input voltage exceeds the Vclamp value, the internal protection circuit clamps the output voltage to Vclamp. The overvoltage clamp threshold is preset to 28 V if the Vclamp pin is left floating, otherwise it can be externally adjusted in the range of 10 to 52 V by connecting a resistor divider (R1,R2) of appropriate value between the Vclamp pin, VOUT and GND. The setting procedure is similar to that of UVLO, the internal divider current being fixed to 10 A. Given the desired Vclamp threshold, for a fixed value of the lower resistor R2, Equation 2 can be used to calculate the upper resistor R1 DS12147 - Rev 5 page 8/26 STEF01 Operating modes Equation 2 1 R 1 = --------------------------------------------------------2 (1 / R 2 + 10 ) 1 ------------------------------------- - ------------( Vc la m p - 1 ) 2700 (resistor values are expressed in k) Figure 8. Clamping voltage (Vclamp) vs. R1, R2 shows the relation between R1 and the clamping voltage, for some fixed values of R2. Figure 8. Clamping voltage (Vclamp) vs. R1, R2 50000 R2=100k R2=50k R2=20k R2=10k R 1 [k] 5000 500 50 0 5 10 15 20 25 30 35 40 45 50 VCLAMP [V] 5.1.4 GIPD010220161301MT Current limit The STEF01 embeds an overcurrent sensing circuit, based on an internal N-channel Sense FET with a fixed ratio, used to monitor the output current (Figure 1. Block diagram). The current limiting circuit responds to overcurrent events by reducing the conductivity of the power MOSFET, in order to clamp the output current at a safe value. The overcurrent protection trip-point can be selected externally by means of the limiting resistor RLimit, according to the graphs in Section 5.1.4 Current limit and Figure 28. Current limit vs. Rlimit (zoom). The circuit features two levels of current limitation, each one valid for a certain range of output voltage (VOUT). In case of overload, when the input current surpasses the programmed overload current limit (ILIM), but the output voltage is still higher than 5.5 V (typ.), the device clamps the current to the ILIM value. If case of strong overload or short circuit, when the output voltage decreases to less than 3.5 V, the device enters the foldback current limit, with the current limited to a lower value (ISHORT) that is typically 1.5 A when RLimit = 22 . Figure 9. Current limit vs. Rlimit VIN=24V, C IN=C OUT=47F, IOUT=from 0.5A to 8A, R LIM=from 10 to 1k 12 Ilim 10 Is hort Curre nt limit [A] 8 6 4 2 0 10 100 1000 Rlimit [] AMG180720171100MT DS12147 - Rev 5 page 9/26 STEF01 Protection circuits During startup, the foldback current limit is disabled and the current is limited by the overcurrent protection at the ILIM value. Please refer also to Section 5.4 Maximum load at startup for more details. It is important to note that the RLimit is mandatory for the current limiting circuit to function properly. It is recommended to use RLimit value according to Table 3. Recommended operating condition and to the package power dissipation. Important: very low values of RLimit or failure to connect it may lead to malfunctioning of the current limiting circuit and to device damage. 5.2 Protection circuits Since the power dissipation can reach remarkable levels during startup into heavy capacitive loads, large load transients and short-circuit during operation at high voltage, the STEF01 is protected by means of two circuits: the absolute thermal protection and the maximum power dissipation protection. 5.2.1 Thermal protection The thermal protection is a standard thermal shutdown feature, which acts when the die temperature exceeds the absolute shutdown threshold, set typically to 175 C. The behavior of the STEF01 at thermal protection intervention can be changed by the user through the external Auto pin. This pin is internally pulled up. When the Auto pin is left floating or connected to a voltage higher than 1 V, the thermal protection works as latched. If the device temperature exceeds the thermal shutdown threshold, the thermal shutdown circuitry turns the power MOSFET off, disconnecting the load. The EN/Fault pin of the device will be automatically set at an intermediate voltage, typically 1.4 V, in order to signal the overtemperature event. The E-fuse can be reset either by cycling the supply voltage or by pulling down the EN pin below the VIL threshold and then releasing it. When the AUTO pin is connected to GND or to a voltage lower than 0.4 V, the thermal protection works as autoretry. Once the thermal protection threshold is reached, the power is turned off and remains in an off state until the die temperature drops below the hysteresis value. Once this occurs, the internal auto-retry circuit initiates a new startup cycle, with controlled dv/dt. During the shutdown period, the EN/Fault pin of the device will be automatically set to 0 V. 5.2.2 Maximum dissipated power protection Besides the standard thermal shutdown described in Section 5.2.1 Thermal protection, which acts when the die temperature surpasses the absolute shutdown threshold, the STEF01 is equipped with advanced thermal protection, which limits the thermal power dissipated into the device. When the power dissipation is higher than the internal limit, the power transistor is turned off. The power protection always acts in auto-retry mode, regardless of the Auto pin status. Its intervention is signaled on the EN/FAULT pin with a LOW logic state. If the fault persists, the die temperature may reach the thermal protection limit. If this happens, the device behavior is the one fixed by the user through the Auto pin signal. The maximum dissipated power protection is able to protect the device from very fast overheating events, such as those caused by a short circuit on the output during operation. 5.3 Soft start function The inrush current profile is controlled through a dedicated soft-start circuit. The startup time is set by default at 3 ms (typ.) and it can be prolonged by connecting a capacitor between the Cdv/dt pin and GND. Figure 11. Startup time illustrates the turn-on sequence. The turn-on time is defined as the time interval t between assertion of the enable signal and the Vout reaching the (VOUT(NOM)-2 V) voltage. The turn-on time is a function of the Cdv/dt capacitor, the input voltage VCC and the clamping voltage VClamp. Given the Cdv/dt external capacitor value, the turn-on time can be estimated using Equation 3 and the graph in Figure 12. Startup time vs CdV/dt , valid for normal operating conditions (VCC < VClamp). In case the startup occurs with power supply voltage higher than the clamping voltage (VCC > VClamp), the total startup time will be longer. The equation is meant as a theoretical aid in choosing the Cdv/dt capacitor, and does not take into account the capacitor tolerance, temperature and process variations. DS12147 - Rev 5 page 10/26 STEF01 Maximum load at startup Equation 3 VC C ( 300 + C d vd t ) t O N = 0.952 ------------------- ----------------------------------- + t d e la y VC la m p 113000 where time is expressed in [s] and the capacitor in [pF]; tdelay ~ 170 s, is the initial delay time. Figure 12. Startup time vs CdV/dt Figure 11. Startup time 1000 Vcc=24V Vcc=48V Vcla mp 100 VIN - 2V EN/FAULT ra mp-up time - VIN>VCla mp de la y time (tde la y) ra mp-up time - VIN<VCla mp S ta rtup time [ms ] VOUT VIN 10 1 1 10 100 1000 10000 100000 dv/dt Ca pa citor [pF] CIN = COUT = 22 F, IOUT = 0 mA, RLIM = 11 , VCLAMP = 52 V for VCC = 48 V, or VCLAMP = 28 V for VCC = 24 V GIPD020220160934MT 5.4 GIPD020220160935MT Maximum load at startup The power limiting function described in Section 5.2.2 Maximum dissipated power protection is designed to provide fast and effective protection for the internal FET. Depending on supply voltage and load, it is possible that during startup the power dissipation is such that the maximum power protection is triggered and the output is shut down before the startup is complete. The EN/Fault signal is set according to Table 6. Enable/Fault pin behavior during thermal protection events. In case of strong capacitive loads, the total startup time may be longer than the programmed startup time, since it is dependent also on the limitation current, the output load and the output capacitance value. In such a situation, the foldback current limit could activate, so that the startup is longer or eventually interrupted by the intervention of thermal protection. To avoid this occurrence, a longer startup time should be set by the appropriate selection of the Cdv/dt capacitor. 5.5 Enable-fault pin The Enable/Fault pin has the dual function of enabling/disabling the device and, at the same time, providing information about the device status to the application. The EN/Fault signal can be provided to a monitoring circuit to control the status of device. It can be used as a standard Enable pin, (HI = enable, LO = disable) or connected to an external open-drain or open-collector device. The EN/fault pin is internally pulled up to 5 V, therefore the device is enabled if the pin is left floating. In case of a thermal fault, the pin is pulled to an intermediate state, with a voltage of 1.4 V (typ.) (see Figure 6. UVLO threshold (VON) vs RH, RL ). The EN/Fault signal can be directly connected to the Enable/Fault pins of other STEF01 devices on the same application in order to implement a simultaneous enable/disable feature. When a thermal fault occurs, the latch version can be reset either by cycling the supply voltage or by pulling down the Enable pin below the VIL threshold and then releasing it. In the auto-retry operating mode, the power MOSFET remains in an off state until the die temperature drops below the hysteresis value. The EN/Fault pin is set to a low logic level and the auto-retry circuit attempts to restart the device with soft start. DS12147 - Rev 5 page 11/26 STEF01 Power Good function In case of power limit intervention, the EN/Fault pin is set to low logic level also. The following truth table and the graph in Figure 13. Enable/Fault pin status summarize the device behavior and the EN/Fault signal in all conditions. Table 6. Enable/Fault pin behavior during thermal protection events Auto pin logic level Thermal protection status Note: Maximum power protection status EN/Fault pin status Output voltage High 0 0 5V ON High 1 X 1.4 V OFF High 0 1 0V OFF Low 0 0 5V ON Low 1 X 0V OFF Low 0 1 0V OFF Maximum power protection always auto-retries (see Section 5.2.2 Maximum dissipated power protection). Figure 13. Enable/Fault pin status 5.6 Power Good function Most applications require a flag showing that the output voltage is in the correct range. This function is achieved through the Power Good (PG) pin. The Power Good function on the STEF01 is accomplished by monitoring the voltage drop on the power pass element, Vd = VCC-VOUT. Whenever the VD is lower than 1 V, the PG pin is in high impedance. If VD is higher than 1 V, the PG pin goes to low impedance; therefore if either the device is functioning well or the EN pin is in low state, the PG pin is at high impedance. The PG pin is an open drain pin, so it requires an external pull-up resistor, which must be connected between the PG pin and the desired high level voltage reference. The typical current capability of the PG pin is up to 6 mA. If the Power Good function is not used, the PG pin must remain floating. 5.7 Gate driver for reverse current blocking FET Many applications require reverse current blocking (from load to input source) to permit the completion of important system activities or writing data to non-volatile memory prior to power down or during brownout. The STEF01 provides a Vg pin suitable to control an external blocking N-channel FET, connected back-to-back with the internal one, as shown in Figure 14. STEF01 with external reverse blocking FET. DS12147 - Rev 5 page 12/26 STEF01 External capacitors and application suggestions Figure 14. STEF01 with external reverse blocking FET VIN Vcc C IN RH RL RP G C dv/dt Exp.pa d M1 VOUT S TEF01 R LIM ILIM PG UVLO VCLAMP dV/dt AUTO EN/Fa ult VOUT R1 C OUT C LOAD LOAD R2 Vg GND GIPD020220160956MT As VIN drops during input power removal, the internal logic pulls the gate of the external MOSFET down, therefore both the internal pass element and the external MOSFET are turned off, blocking any current flow from the load to the power supply. In this case, the CLOAD value is chosen according to the charge needed to complete the required operations. The typical sourcing current of the Vg driver is 30 A, with a voltage of 10 V compared to VOUT. Therefore, when a low threshold MOSFET is used, the Vg must be clamped by means of a suitable external clamping diode. When the EN pin is low, the external M1 FET is kept off by a 40 internal pull-down so that the device is disabled by the user or by internal protection circuits. 5.8 External capacitors and application suggestions Input and output capacitors are mandatory to guarantee device control loop stability and reduce the transient effects of stray inductances which may be present on the input and output power paths. In fact, when the STEF01 interrupts the current flow, input inductance generates a positive voltage spike on the input, and output inductance generates a negative voltage spike on the output. To reduce the effects of such transients, a CIN capacitor of at least 10 F must be connected between the input pin and GND, and located as close as possible to the device. For the same reason, a COUT capacitor of at least 47 F must be connected at the output port. In the event of a voltage clamp, with certain combinations of parasitic elements on the application, some small oscillations may be visible on the output voltage. This phenomenon does not affect device operation and can be mitigated by using an electrolytic capacitor for the CIN. When the device is powered via a power line made up of very long wires, where input inductance is higher than 3-4 H, the input capacitor should be increased to 47 F or more. Additional protections and methods for addressing these transients are: * Minimizing inductance of the input and output tracks * TVS diodes on the input to absorb inductive spikes * Schottky diode on the output to absorb negative spikes * Combination of ceramic and electrolytic capacitors on the input and output DS12147 - Rev 5 page 13/26 STEF01 Typical performance characteristics 6 Typical performance characteristics (The following plots are referred to the typical application circuit and, unless otherwise noted, at TA = 25 C) Figure 15. Clamping voltage vs. temperature Figure 16. UVLO voltage vs. temperature 50 20 Von 45 35 30 UVLO thre s ho ld [V] Vin=9V, Vcla mp=8V Vin=36V, Vcla mp=28V Vin=48V, Vcla mp=45V Vin=16V, Vcla mp=14V 40 VCLAMP [V] Voff 18 25 20 15 16 14 12 10 10 8 5 0 6 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 Te mpe rature [C] 50 75 100 125 150 Te mpe rature [C] IOUT = 10 mA,VIN = from 10 V to 16 V, Vclampset to 14 V AMG180720171130MT AMG180720171131MT Figure 17. Auto pin thresholds vs. temperature Figure 18. Off-state current vs. temperature 1000 300 AUTO 900 250 800 200 IBIAS _Off [A] VAR thre s ho ld [mV] LATCH 700 150 600 100 500 50 0 400 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 Te mpe rature [C] Te mpe rature [C] VIN = 48 V , VEN = GND AMG180720171132MT DS12147 - Rev 5 AMG180720171133MT page 14/26 STEF01 Typical performance characteristics Figure 19. Bias current (device operational) Figure 20. ON resistance vs. temperature 80 1000 VIN=48V 800 60 700 50 600 500 30 20 300 10 200 -25 0 25 50 75 100 125 VIN=48V 40 400 -50 VIN=24V 70 VIN=24V RDS _ON [m] IBIAS [A] 900 0 150 -50 -25 0 Te mpe rature [C] 25 50 75 100 125 150 Te mpe rature [C] IOUT= 1 A AMG180720171134MT AMG180720171135MT Figure 21. ON resistance vs. load current Figure 22. dv/dt pin current vs. temperature 60 140 125C 55 25C 50 -40C VCC=24V 130 VCC=55V 120 110 40 Idv/dt RDS _ON [m] 45 35 30 100 90 25 80 20 70 15 10 60 0 1 2 3 4 5 6 7 -50 -25 0 25 Lo ad c urre nt [A] 50 75 100 125 150 Te mpe rature [C] AMG180720171136MT AMG180720171137MT Figure 23. External gate driver pull-down resistance Figure 24. External gate driver voltage 12 800 11.5 700 11 10.5 Vg - VOUT [V] RP [] 600 500 400 10 9.5 9 8.5 8 300 7.5 7 200 -50 -25 0 25 50 75 100 125 150 Te mpe rature [C] -25 0 25 50 75 100 125 150 Te mpe rature [C] AMG180720171138MT DS12147 - Rev 5 -50 AMG180720171139MT page 15/26 STEF01 Typical performance characteristics Figure 25. External gate driver current (source) vs. temperature Figure 26. Low level En/Fault pin current (sink) vs. temperature 40 50 45 35 40 30 25 30 Ig [A] Ig [A] 35 25 20 20 15 15 10 10 5 5 0 -50 -25 0 25 50 75 100 125 150 Te mpe rature [C] 0 -50 -25 0 25 50 75 100 125 150 Te mpe rature [C] AMG180720171140MT Figure 27. En/Fault pin voltage vs. temperature AMG180720171141MT Figure 28. Current limit vs. Rlimit (zoom) 6 VI(MAX) (chip e na ble d) Enable /fault vo ltag e [V] 5 4 3 VIH (Ena ble high thre s hold) 2 VI(INT) (Fa ult s ta tus ) 1 0 -50 -25 0 25 50 75 100 125 150 Te mpe rature [C] AMG180720171142MT Figure 29. VOUT ramp-up vs. Enable DS12147 - Rev 5 VIN = 24 V, CIN = COUT = 47 F, IOUT = from 0.5 A to 8 A, RLIM = from 10 to 50 AMG180720171143MT Figure 30. VOUT clamping (28 V) page 16/26 STEF01 Typical performance characteristics Figure 31. VOUT clamping (44 V) Figure 32. Response to overload (latch) Figure 33. Response to overload (autoretry) Figure 34. UVLO DS12147 - Rev 5 page 17/26 STEF01 Typical performance characteristics Figure 35. Enable turn-on with external FET DS12147 - Rev 5 Figure 36. Enable turn-off with external FET page 18/26 STEF01 Package information 7 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 7.1 HTSSOP14 package information Figure 37. HTSSOP14 package outline BOTTOM VIEW SIDE VIEW TOP VIEW DS12147 - Rev 5 7256412 page 19/26 STEF01 HTSSOP14 package information Table 7. HTSSOP14 mechanical data Dim. mm Min. Typ. Max. A 1.00 1.10 1.20 A1 0.05 0.10 0.15 A2 0.80 1.00 1.05 b 0.19 0.25 0.30 c 0.09 D 4.90 D1 3.00 E 6.20 6.40 6.60 E1 4.30 4.40 4.50 E2 3.00 e 0.25 5.00 5.10 3.20 3.20 0.65 BSC L 0.45 0.60 0.75 L1 0.95 1.00 1.05 k 0 aaa 8 0.10 Figure 38. HTSSOP14 recommended footprint DS12147 - Rev 5 page 20/26 STEF01 HTSSOP14 packing information 7.2 HTSSOP14 packing information Figure 39. HTSSOP14 carrier tape outline Table 8. HTSSOP14 carrier tape mechanical data DS12147 - Rev 5 Dim. Value (mm) Ao 6.8 0.1 Bo 5.4 0.1 Ko 1.6 0.1 Ki 1.3 0.1 F 5.5 0.05 P1 8.0 0.1 W 12.0 0.3 page 21/26 STEF01 Revision history Table 9. Document revision history DS12147 - Rev 5 Date Revision Changes 04-Aug-2017 1 Initial release. 15-Feb-2018 2 Update: ID value Table 2. Absolute maximum ratings. 24-May-2018 3 Updated maturity status link on the cover page. 13-Jul-2018 4 Updated pin 11 note Table 1. Pin description. 01-Oct-2018 5 Updated VIL, VIH and VI(MAX) values in Table 5. Electrical characteristics for STEF01. page 22/26 STEF01 Contents Contents 1 Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 4 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 Typical application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.1 5.2 Operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.1.1 Turn-on and UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.1.2 Normal operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1.3 Output voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1.4 Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Protection circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2.1 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2.2 Maximum dissipated power protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 Soft start function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 Maximum load at startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.5 Enable-fault pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.6 Power good function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.7 Gate driver for reverse current blocking FET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.8 External capacitors and application suggestions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 7 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 7.1 HTSSOP14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.2 HTSSOP14 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 DS12147 - Rev 5 page 23/26 STEF01 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . Recommended operating condition . . . . . . . . . . . . . . . . . Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical characteristics for STEF01 . . . . . . . . . . . . . . . . Enable/Fault pin behavior during thermal protection events . HTSSOP14 mechanical data . . . . . . . . . . . . . . . . . . . . . . HTSSOP14 carrier tape mechanical data . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . . . . . . . DS12147 - Rev 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 4 . 4 . 4 . 5 12 20 21 22 page 24/26 STEF01 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 6. Figure 8. Figure 9. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. DS12147 - Rev 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin configuration (top view ) . . . . . . . . . . . . . . . . . . Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . UVLO block simplified diagram . . . . . . . . . . . . . . . . UVLO threshold (VON) vs RH, RL . . . . . . . . . . . . . . Clamping voltage (Vclamp) vs. R1, R2 . . . . . . . . . . . Current limit vs. Rlimit . . . . . . . . . . . . . . . . . . . . . . Startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Startup time vs CdV/dt . . . . . . . . . . . . . . . . . . . . . . Enable/Fault pin status . . . . . . . . . . . . . . . . . . . . . STEF01 with external reverse blocking FET . . . . . . . Clamping voltage vs. temperature . . . . . . . . . . . . . . UVLO voltage vs. temperature . . . . . . . . . . . . . . . . Auto pin thresholds vs. temperature . . . . . . . . . . . . Off-state current vs. temperature. . . . . . . . . . . . . . . Bias current (device operational). . . . . . . . . . . . . . . ON resistance vs. temperature . . . . . . . . . . . . . . . . ON resistance vs. load current . . . . . . . . . . . . . . . . dv/dt pin current vs. temperature. . . . . . . . . . . . . . . External gate driver pull-down resistance . . . . . . . . . External gate driver voltage . . . . . . . . . . . . . . . . . . External gate driver current (source) vs. temperature. Low level En/Fault pin current (sink) vs. temperature . En/Fault pin voltage vs. temperature . . . . . . . . . . . . Current limit vs. Rlimit (zoom) . . . . . . . . . . . . . . . . . VOUT ramp-up vs. Enable. . . . . . . . . . . . . . . . . . . . VOUT clamping (28 V) . . . . . . . . . . . . . . . . . . . . . . VOUT clamping (44 V) . . . . . . . . . . . . . . . . . . . . . . Response to overload (latch) . . . . . . . . . . . . . . . . . Response to overload (autoretry) . . . . . . . . . . . . . . UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enable turn-on with external FET . . . . . . . . . . . . . . Enable turn-off with external FET . . . . . . . . . . . . . . HTSSOP14 package outline. . . . . . . . . . . . . . . . . . HTSSOP14 recommended footprint . . . . . . . . . . . . HTSSOP14 carrier tape outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 3 . 7 . 7 . 8 . 9 . 9 11 11 12 13 14 14 14 14 15 15 15 15 15 15 16 16 16 16 16 16 17 17 17 17 18 18 19 20 21 page 25/26 STEF01 IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2018 STMicroelectronics - All rights reserved DS12147 - Rev 5 page 26/26