1
1
2
2
3
3
4
4
D D
C C
B B
A A
584/15/2015
Author:
Date:
Revision:
Sheet of
Jorge Amodio v2.1 PCB02
Renesas YLCDRZA1H MCU Module
MCU e-MMC, SDRAM, I2C Iinterfaces & GPIO
P7_9/A1
P7_10/A2
P7_11/A3
P7_12/A4
P7_13/A5
P7_14/A6
P7_15/A7
P8_0/A8
P8_1/A9
P8_2/A10
P8_3/A11
P8_4/A12
P8_5/A13
P8_6/A14
P8_7/A15
P8_8
P8_9
P8_10/RS_DEN
P8_11/RS_ON
P8_12/PWM1E-BLEN
P8_13-TOUCH_RST
P8_14/RSPCK2
P8_15/SSL20
P9_0/MOSI2
P9_1/MISO2
P1_0/SCL0
P1_1/SDA0
P1_2/SCL1
P1_3/SDA1
P1_4/CAN1RX
P1_5/IRQ5-ET_IRQ
P1_6/SCL3
P1_7/SDA3
P7_0/MD_BOOT2
P7_1/CS3#-SDRAM2_CS#
P7_2/RAS#
P7_3/CAS#
P7_4/CKE
P7_5/RD/WR#
P7_6/WE0#/DQMLL
P7_7/WE1#/DQMLU
P7_8/IRQ1
P1_8/AN0_ALS
P1_9/IRQ3-AUDIO_IRQ
P1_10/IRQ4-TOUCH_IRQ
P1_11/TINT19-PMOD_IRQ
P1_12/TINT20-USBH_OC
P1_13-USBH_5V_EN
P1_14/ET_COL
P1_15-LCD_ON
P2_12/SPBIO01
P2_13/SPBIO11
P2_14/SPBIO21
P2_15/SPBIO31
P2_0/ET_TXCLK
P2_1/ET_TXER
P2_2/ET_TXEN
P2_3/ET_CRS
P2_4/ET_TXD0
P2_5/ET_TXD1
P2_6/ET_TXD2
P2_7/ET_TXD3
P2_8/ET_RXD0
P2_9/ET_RXD1
P2_10/ET_RXD2
P2_11/ET_RXD3
P10_0/VIO_CLK
P10_1/VIO_VSYNC
P10_2/VIO_HSYNC
P10_3/VIO_FLD
P10_4/VIO_D0
P10_5/VIO_D1
P10_6/VIO_D2
P10_7/VIO_D3
P10_8/VIO_D4
P10_0/VIO_D5
P10_10/VIO_D6
P10_11/VIO_D7
P10_12/SSISCK
P10_13/SSIWS
P10_14/SSIRxD
P10_15/SSITxD
P11_0/LCD_DATA7
P11_1/LCD_DATA6
P11_2/LCD_DATA5
P11_3/LCD_DATA4
P11_4/LCD_DATA3
P11_5/LCD_DATA2
P11_6/LCD_DATA1
P11_7/LCD_DATA0
P11_8/LCD_DEN
P11_9/LCD_VSYNC
P11_10/LCD_HSYNC
P11_11-LED1R
P11_12/MMC_ D4
P11_13/MMC_ D5
P11_14/MMC_ D6
P11_15/MMC_ D7
P7_12/A4/SSISCK4/RXD[3]/TIOC4A/IRQ4
M1
P7_13/A5/SSIWS4/MDIO/TIOC4B/IRQ5
N1
P7_15/A7/RSPCK0/RXCLK/CTS5/SCIc_TXD0/IrTXD/TIOC4D
N3
P8_1/A9/MOSI0/RXDV/TXD5/SCIc_RXD0/IrRXD
P2
P8_3/A11/DV1_DATA0/RSPCK2/RTS5/UARTH_CLK/IRQ1/SCK2
R1
P8_5/A13/DV1_DATA2/MOSI2/UARTH_RxD
R3
P8_9/A17/DV1_DATA6/SPBIO1_1/SPDIF_OUT/TIOC1B/PWM1B/RxD3/SSIWS5
V3
P8_11/A19/MLB_CLK/SPBIO3_1/TIOC3B/RxD5/PWM1D/SGOUT_1/SSITxD5
W3
P8_13/A21/MLB_SIG/SPBSSL_1/TIOC3D/TXD5/PWM1F/SGOUT_3/SSIWS4
V4
P8_14/A22/SPBIO4_0/SPBIO0_1/TIOC2A/RSPCK2/PWM1G/TxD4/SSIDATA4
Y2
P9_1/A25/SPBIO7_0/CRx0/IRQ0/MISO2/MSQ/SDA0O
AA3
P7_0/MD_BOOT2/CS0/DV0_DATA16/MDC/SCK4/LTXD0/TIOC0A
H4
P7_3/CAS/DV0_DATA19/TXEN/SCK7/CTx2/SSIRxD1/TIOC0D
J3
P7_4/CKE/DV0_DATA20/TXD[0]/TXD7/UARTH_CLK/SSITxD1/TIOC1A
J2
P7_6/WE0/DQMLL/DV0_DATA22/TXD[2]/CTS7/UARTH_TxD/SSIWS2/TIOC2A
K3
P7_8/RD/SSISCK3/CRx0/TIOC3A/IRQ1
K4
P1_13/AN5/DV0_HSYNC/WAIT/MST
Y18
P1_11/AN3/IRQ5/TCLKD/MSN_DVDEC1
AA18
P1_9/AN1/IRQ3/VIO_D15/DV0_DATA15/MSN_VDC51
AB18
P11_12/CRx1/RSPCK1/IRQ3/MMC_D4/LCD0_TCON2 G2
P11_13/CTx1/SSL01/LCD0_TCON4/MMC_D5/LCD0_TCON1 G1
P11_14/SPDIF_IN/MOSI1/LCD0_TCON5/MMC_D6/LCD0_TCON0 H3
P11_15/SPDIF_OUT/MISO1/IRQ1/MMC_D7/LCD0_CLK J4
P11_5/DV0_DATA17/SD_WP_0/SSIWS4/LCD0_DATA2 L1
P11_6/DV0_DATA18/SD_D1_0/SSIDATA4/MMC_D1/LCD0_DATA1 M2
P11_8/DV0_DATA20/SD_CLK_0/RTS5/MMC_CLK/LCD0_TCON6 T1
P11_10/DV0_DATA22/SD_D3_0/TxD5/MMC_D3/LCD0_TCON4 T3
P11_11/DV0_DATA23/SD_D2_0/RxD5/MMC_D2/LCD0_TCON3 U3
P10_1/DV0_VSYNC/TCLKB/PWM2B/TXER/LCD0_DATA22/VIO_VD AA5
P10_3/DV0_DEN/TCLKD/PWM2D/CRS/LCD0_DATA20/VIO_FLD AB5
P7_1/CS3/DV0_DATA17/TXCLK/TXD4/DV0_CLK/SSISCK1/TIOC0B
H2
P7_2/RAS/DV0_DATA18/TXER/RXD4/CRx2/SSIWS1/TIOC0C
H1
P7_5/RD/WR/DV0_DATA21/TXD[1]/RXD7/UARTH_RxD/SSISCK2/TIOC1B
J1
P7_7/WE1/DQMLU/DV0_DATA23/TXD[3]/RTS7/SSIDATA2/TIOC2B
K2
P7_9/A1/SSIWS3/RXD[0]/CTx0/DARC_BPFCLK1/TIOC3B/IRQ0
K1
P7_10/A2/SSIRxD3/RXD[1]/CTx1/DARC_FMCLK/TIOC3C/IRQ2
L3
P7_11/A3/SSITxD3/RXD[2]/CRx1/DARC_FMIN/TIOC3D/IRQ3
L2
P11_4/DV0_DATA16/SD_CD_0/SSISCK4/MMC_CD/LCD0_DATA3 L4
P11_7/DV0_DATA19/SD_D0_0/CTS5/MMC_D0/LCD0_DATA0 M3
P7_14/A6/SSIDATA4/CRS/TIOC4C/IRQ6
N2
P8_0/A8/SSL00/RXER/SCK5/SCIc_SCK0
P1
P8_2/A10/MISO0/RXD5/IRQ0
P3
P8_4/A12/DV1_DATA1/SSL20/IERxD/RxD2
R2
P11_9/DV0_DATA21/SD_CMD_0/SCK5/MMC_CMD/LCD0_TCON5 T2
P8_6/A14/DV1_DATA3/MISO2/UARTH_TxD/IETxD/TxD2
U2
P8_7/A15/DV1_DATA4/AUDIO_XOUT/IRQ5/COL
U4
P8_8/A16/DV1_DATA5/SPBIO0_1/SPDIF_IN/TIOC1A/PWM1A/TxD3/SSISCK5
V2
P8_10/A18/DV1_DATA7/SPBIO2_1/TIOC3A/CTx4/PWM1C/SGOUT_0/DV0_CLK
W2
P8_12/A20/MLB_DAT/SPBCLK_1/TIOC3C/SCK5/PWM1E/SGOUT_2/SSISCK4
Y1
P8_15/A23/SPBIO5_0/SPBIO1_1/TIOC2B/SSL20/PWM1H/RxD4
AA1
P9_0/A24/SPBIO6_0/CTx0/TCLKC/MOSI2/SCL0O
AB2
P10_0/DV0_CLK/TCLKA/PWM2A/TXCLK/LCD0_DATA23/VIO_CLK AB4
P10_2/DV0_HSYNC/TCLKC/PWM2C/TXEN/LCD0_DATA21/VIO_HD Y6
P1_8/AN0/IRQ2/DREQ0/VIO_D14/DV0_DATA14/MSN_VDC50
AA17
P1_10/AN2/IRQ4/TCLKB/MSN_DVDEC0
Y17
P1_12/AN4/DV0_VSYNC/VIO_FLD/MPSEL
AB19
P1_14/AN6/COL/MSD
AA19
P1_15/AN7
Y19
P10_4/DV0_DATA0/TIOC0A/PWM2E/TXD[0]/LCD0_DATA19/VIO_D0 N19
P10_6/DV0_DATA2/TIOC0C/PWM2G/TXD[2]/LCD0_DATA17/VIO_D2 N21
P10_5/DV0_DATA1/TIOC0B/PWM2F/TXD[1]/LCD0_DATA18/VIO_D1 N20
P10_7/DV0_DATA3/TIOC0D/PWM2H/TXD[3]/LCD0_DATA16/VIO_D3 M22
P2_0/D16/TXCLK/DV0_DATA0/SPBIO0_1/MLB_CLK/IRQ5/VIO_D0/LCD0_DATA16 L21
P10_10/DV0_DATA6/TIOC2A/RXD[2]/LCD0_DATA13/VIO_D6 H21
P2_1/D17/TXER/DV0_DATA1/SPBIO1_1/MLB_DAT/TIOC2A/VIO_D1/LCD0_DATA17 K22
P10_8/DV0_DATA4/TIOC1A/RXD[0]/LCD0_DATA15/VIO_D4 J21
P10_9/DV0_DATA5/TIOC1B/RXD[1]/LCD0_DATA14/VIO_D5 J20
P10_11/DV0_DATA7/TIOC2B/RXD[3]/LCD0_DATA12/VIO_D7 H20
P2_3/D19/CRS/DV0_DATA3/SPBIO3_1/IERxD/CTS1/VIO_D3/LCD0_DATA19 G20
P2_5/D21/TXD[1]/DV0_DATA5/SSIWS5/SPBSSL_1/TxD1/VIO_D5/LCD0_DATA21 E22
P2_2/D18/TXEN/DV0_DATA2/SPBIO2_1/MLB_SIG/TIOC2B/VIO_D2/LCD0_DATA18 F21
P2_4/D20/TXD[0]/DV0_DATA4/SSISCK5/SPBCLK_1/SCK1/VIO_D4/LCD0_DATA20 F19
P10_12/DV0_DATA8/SSISCK1/RSPCK0/LCD0_DATA11/VIO_D8 E21
P10_14/DV0_DATA10/SSIRxD1/MOSI0/LCD0_DATA9/VIO_D10 D22
P2_6/D22/TXD[2]/DV0_DATA6/SSIRxD5/RxD1/VIO_D6/LCD0_DATA22 E20
P2_7/D23/TXD[3]/DV0_DATA7/SSITxD5/IETxD/RTS1/VIO_D7/LCD0_DATA23 C22
P10_13/DV0_DATA9/SSIWS1/SSL00/LCD0_DATA10/VIO_D9 F20
P10_15/DV0_DATA11/SSITxD1/MISO0/LCD0_DATA8/VIO_D11 D21
P2_8/D24/RXD[0]/DV0_DATA8/SSISCK0/LCD0_TCON6/LCD1_DATA8/VIO_D8/RSPCK4 D20
P2_9/D25/RXD[1]/DV0_DATA9/SSIWS0/LRXD0/LCD1_DATA9/VIO_D9/SSL40 C21
P2_10/D26/RXD[2]/DV0_DATA10/SSIRxD0/LTXD0/LCD1_DATA10/VIO_D10/MOSI4 B22
P2_12/D28/RSPCK0/DV0_DATA12/SPBIO4_0/CRx3/IRQ6/LCD1_DATA12/TIOC1B A21
P2_14/D30/MOSI0/DV0_DATA14/SPBIO6_0/CRx4/TxD0/LCD1_DATA14/IRQ0 C18
P1_0/SCL0/DV0_DATA16/TCLKA/IRQ0/VIO_VD/DV0_VSYNC/SCL0I
A19
P1_2/SCL1/DV0_DATA18/FRB/IRQ2/ICN_SCK/LCD1_EXTCLK/SCL1I
B18
P1_4/SCL2/DV0_CLK/CRx1/IRQ4/ICN_SCK/CAN_CLK/SCL2I
B17
P1_6/SCL3/DV1_VSYNC/IERxD/IRQ6/VIO_D12/DV0_DATA12/MLB_CLK/SCL3I
A17
P2_11/D27/RXD[3]/DV0_DATA11/SSITxD0/TIOC1A/LCD1_DATA11/VIO_D11/MISO4 E19
P2_13/D29/SSL00/DV0_DATA13/SPBIO5_0/CTx3/SCK0/LCD1_DATA13/IRQ7 A20
P2_15/D31/MISO0/DV0_DATA15/SPBIO7_0/CAN_CLK/RxD0/LCD1_DATA15/IRQ1 B19
P1_1/SDA0/DV0_DATA17/TCLKC/IRQ1/VIO_HD/DV0_HSYNC/SDA0I
C17
P1_3/SDA1/DV0_DATA19/COL/IRQ3/ICN_SDATA/SDA1I
A18
P1_5/SDA2/DV1_CLK/CRx4/IRQ5/VIO_CLK/ICN_SDATA/LCD1_EXTCLK/SDA2I
C16
P1_7/SDA3/DV1_HSYNC/LRXD0/IRQ7/VIO_D13/DV0_DATA13/SDA3I
B16
P11_1/DV0_DATA13/TIOC4B/MLB_DAT/TxD6/LCD0_DATA6/VIO_D13 C6
P11_3/DV0_DATA15/TIOC4D/LCD0_DATA4/VIO_D15 C5
P11_0/DV0_DATA12/TIOC4A/MLB_CLK/SCK6/LCD0_DATA7/VIO_D12 A4
P11_2/DV0_DATA14/TIOC4C/MLB_SIG/RxD6/LCD0_DATA5/VIO_D14 B4
RZ/1AH-BGA324
U6A
+3V3
4K70
R16
81
4K70 RA5A
72
4K70 RA5B
63
4K70 RA5C
54
4K70 RA5D