Intel(R) Wireless Flash Memory (W18/W30 SCSP) 32WQ and 64WQ Family with Asynchronous RAM Datasheet Product Features Device Architecture -- Flash Density: 32-Mbit, 64-Mbit -- Async PSRAM Density: 8-, 16-, 32Mbit; Async SRAM Density: 4-, 8-, 16Mbit -- Top, Bottom or Dual flash parameter configuration Device Voltage -- Flash VCC = 1.8 V; Flash VCCQ = 1.8 V or 3.0 V -- RAM VCC = 3.0 V; RAM VCCQ = 1.8 V or 3.0 V Device Packaging -- 88 balls (8 x 10 active ball matrix); Area: 8x10 mm; Height: 1.2 mm to 1.4 mm PSRAM Performance -- 70 ns initial access, 25 ns async page reads at 1.8 V I/O -- 70 ns initial access async PSRAM at 1.8V I/O -- 88 ns initial access, 30 ns async page reads at 1.8 V I/O -- 85 ns initial access, 35 ns async page reads at 3.0 V I/O -- 70 ns initial access, 25 ns async page reads at 3.0 V I/O SRAM Performance -- 70 ns initial access at 1.8 V or 3.0 V I/O Flash Performance -- 65 ns initial access at 1.8 V I/O -- 70 ns initial access at 3.0 V I/O -- 25 ns async page at 1.8 V or 3.0 V I/O -- 14 ns sync reads (tCHQV) at 1.8 V I/O -- 20 ns sync reads (tCHQV) at 3.0 V I/O -- Enhanced Factory Programming: 3.10 s/Word (Typ) Flash Architecture -- Read-While-Write/Erase -- Asymmetrical blocking structure -- 4-KWord parameter blocks (Top or Bottom); 32-KWord main blocks -- 4-Mbit partition size -- 128-bit One-Time Programmable (OTP) Protection Register -- Zero-latency block locking -- Absolute write protection with block lock using F-VPP and F-WP# Flash Software -- Intel(R) Flash Data Integrator (FDI) and Common Flash Interface (CFI) Quality and Reliability -- Extended Temperature: -25 C to +85 C -- Minimum 100K flash block erase cycle -- 90 nm ETOXTM IX flash technology -- 130 nm ETOXTM VIII flash technology The Intel(R) Wireless Flash Memory (W18/W30 SCSP) family offers various flash plus static RAM combinations in a common package footprint. The flash memory features 1.8 V lowpower operations with flexible, multi-partition, dual-operation Read-While-Write / Read-WhileErase, asynchronous, and synchronous reads. This SCSP device integrates up to two flash die, one PSRAM die, and one SRAM die in a low-profile package compatible with other SCSP families with QUAD+ ballout. Order Number: 251407, Revision: 010 18-Oct-2005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. 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Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. *Other names and brands may be claimed as the property of others. Copyright (c) 2005, Intel Corporation. All Rights Reserved. 18-Oct-2005 2 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet 32WQ and 64WQ Family--Intel(R) Wireless Flash Memory (W18/W30 SCSP) 1.0 Introduction....................................................................................................................................6 1.1 1.2 2.0 Nomenclature ....................................................................................................................... 6 Conventions.......................................................................................................................... 6 Functional Overview .....................................................................................................................8 2.1 2.2 Block Diagram ...................................................................................................................... 8 Flash Memory Map and Partitioning ..................................................................................... 9 3.0 Package Information ...................................................................................................................11 4.0 Ballout and Signal Description ..................................................................................................13 4.1 4.2 5.0 Maximum Ratings and Operating Conditions...........................................................................16 5.1 5.2 5.3 6.0 Absolute Maximum Ratings ................................................................................................ 16 Operating Conditions .......................................................................................................... 17 Capacitance........................................................................................................................ 17 Electrical Specifications .............................................................................................................18 6.1 7.0 Signal Ballout......................................................................................................................13 Signal Descriptions .............................................................................................................14 DC Characteristics.............................................................................................................. 18 AC Characteristics ......................................................................................................................21 7.1 7.2 7.3 7.4 Flash AC Characteristics ....................................................................................................21 SRAM AC Characteristics...................................................................................................21 PSRAM AC Characteristics ................................................................................................ 24 Device AC Test Conditions................................................................................................. 29 8.0 Flash Power Consumption .........................................................................................................30 9.0 Device Operation ......................................................................................................................... 31 9.1 9.2 Bus Operations ...................................................................................................................31 Flash Command Definitions................................................................................................ 34 10.0 Flash Read Operations ............................................................................................................... 35 11.0 Flash Program Operations .........................................................................................................36 12.0 Flash Erase Operations .............................................................................................................. 37 13.0 Flash Security Modes.................................................................................................................. 38 14.0 Flash Read Configuration Register ........................................................................................... 39 15.0 SRAM Operations ........................................................................................................................ 40 15.1 15.2 Power-up Sequence and Initialization ................................................................................ 40 Data Retention Mode.......................................................................................................... 40 16.0 PSRAM Operations......................................................................................................................42 16.1 16.2 16.3 Datasheet Power-Up Sequence and Initialization................................................................................ 42 16.1.1 16Mbit PSRAM Power-Up Sequence (Non-Page Mode).......................................42 Standby Mode/ Deep Power-Down Mode .......................................................................... 43 PSRAM Special Read and Write Constraints .....................................................................43 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 18-Oct-2005 3 Intel(R) Wireless Flash Memory (W18/W30 SCSP)--32WQ and 64WQ Family Appendix A Write State Machine ........................................................................................................ 45 Appendix B Common Flash Interface................................................................................................. 46 Appendix C Flash Flowcharts .............................................................................................................47 Appendix D Additional Information .................................................................................................... 48 Appendix E Ordering Information ....................................................................................................... 49 18-Oct-2005 4 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet 32WQ and 64WQ Family--Intel(R) Wireless Flash Memory (W18/W30 SCSP) Revision History Date Revision Description June 2003 -001 Initial release. September 2003 -002 Changed PSRAM Read values. Added new Transient Equivalent Testing Load Circuit figure. General text edits. May 2004 -006 Reformatted the datasheet and moved sections around according to the new layout. August 2004 -007 Added 90 nm product information. Added line items to Table 21 "32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash Only)" on page 50. Added DC and AC specs for the new line items and edits to related sections. January 2005 -008 Added line items to Table 21 "32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash Only)" on page 50 Added 32WQ product information. June 2005 -009 Added line items to Table 21 "32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash Only)" on page 50 October 2005 -010 Removed Power-up sequence from Section 16; Added 70ns PSRAM (non-page mode) specification Updated Ordering Information Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 18-Oct-2005 5 Intel(R) Wireless Flash Memory (W18/W30 SCSP) 1.0 Introduction This document contains information pertaining to the products in the Intel(R) Wireless Flash Memory (W18/W30 SCSP) family with asynchronous RAM. The W18/W30 SCSP 32WQ and 64WQ families offer a wide variety of stacked combinations that include single flash die, two flash die, flash + PSRAM, and flash + SRAM options.This document provides information where this SCSP family differs from the Intel(R) Wireless Flash Memory (W18/W30) discrete device. Refer to the discrete datasheets Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for flash product details not included in this SCSP datasheet. 1.1 Nomenclature 0x 0b Byte CFI CUI DU ETOX FDI k (noun) Kb KB Kword M (noun) Mb MB OTP PLR PR PRD RCR RFU SCSP SR SRD Word WSM 1.2 Hexadecimal prefix Binary prefix 8 bits Common Flash Interface Command User Interface Don't Use EPROM Tunnel Oxide Flash Data Integrator (Intel(R) software solution) 1 thousand 1024 bits 1024 bytes 1024 words 1 million 1,048,576 bits 1,048,576 bytes One-Time Programmable Protection Lock Register Protection Register Protection Register Data Read Configuration Register Reserved for Future Use Stacked Chip Scale Package Status Register Status Register Data 16 bits Write State Machine Conventions Group Membership Brackets: Square brackets are used to designate group membership or to define a group of signals with a similar function, such as A[21:1] and SR[4,1]. VCC vs. VCC: When referring to a signal or package-connection name, the notation used is VCC, etc. When referring to a timing or electrical level, the notation used is subscripted such as VCC, etc. 18-Oct-2005 6 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Device: This term is used interchangeably throughout this document to denote either a particular die, or the combination of multiple die within a single package. F[3:1]-CE#, F[2:1]-OE#: This is the method used to refer to more than one chip-enable or output enable at the same time. When each is referred to individually, the reference will be F1CE# and F1-OE# (for die #1), and F2-CE# and F2-OE# (for die #2). F-VCC, P-VCC or S-VCC: When referencing flash memory signals or timings, the notation used is F-VCC or F-VCC, respectively. When the reference is to PSRAM signals or timings, the notation is prefixed with "P-" (e.g., P-VCC, P-VCC). When referencing SRAM signals or timings, the notation is prefixed with "S-" (e.g., S-VCC or S-VCC). P-VCC and S-VCC are RFU for stacked combinations that do not include PSRAM or SRAM. R-OE#, R-LB#, R-UB#, R-WE#: These are used to identify RAM OE#, LB#, UB#, WE# signals, and are usually shared between 2 or more RAM die. R-OE#, R-LB#, R-UB# and R-WE are RFU for stacked combinations that do not include PSRAM or SRAM. Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 18-Oct-2005 7 Intel(R) Wireless Flash Memory (W18/W30 SCSP) 2.0 Functional Overview This section provides an overview of the features and capabilities of the Intel(R) Wireless Flash Memory (W18/W30 SCSP) family with asynchronous RAM device. The W18/W30 SCSP device provides flash + RAM die combinations. Products range from single flash die, two flash die, flash + PSRAM, or flash + SRAM. You can choose a W18 SCSP device or a W30 SCSP device with SRAM or PSRAM offered with the same package footprint and signal ballout. Table 21 on page 50 lists possible product combinations for the 32-Mbit and 64-Mbit W18/W30 SCSP family. 2.1 Block Diagram Figure 1 shows all internal package connections for the SCSP family with multiple die. See Table 21 for valid combinations of flash and RAM die. Unused connections on combinations with less than three die are reserved and should not be used. Please contact your local Intel representative for details regarding any reserved or RFU pins. Figure 1. Block Diagram F2-VCC F2-CE# F2-OE# Flash Die #2 32- or 64-Mbit W18/W30 F-WE# F-VPP VCCQ WAIT CLK ADV# F-WP# F-RST# F1-OE# F1-CE# F1-VCC A[MAX:0] S-VCC/P-VCC P-CS#/S-CS1# S-CS2 R-OE# 18-Oct-2005 8 Flash Die #1 32- or 64-Mbit W18/W30 VSS D[15:0] RAM Die 4-, 8-, 16-Mbit SRAM or 16- or 32-Mbit PSRAM Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 R-WE# P-MODE R-UB# R-LB# Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) 2.2 Flash Memory Map and Partitioning Consult the latest Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and the Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702), for individual flash die memory map and partitioning information. Table 1 and Table 2 show memory map and partitioning information for dual-flash memory die configurations. Flash Die #1 (with F1-CE# as its Chip Select) is configured as a bottom boot while Flash Die #2 (with F2-CE# as its Chip Select) is configured as top boot. Table 1. 64-Mbit Flash + 32-Mbit Flash Die W18/W30 SCSP Memory Map and Partitioning Partitioning Parameter Partition Flash Die #2 (32-Mbit) Flash Die #1 (64-Mbit) Main Partitions Main Partitions Parameter Partition Datasheet Partition 0 Block Size (KW) Block # Address Range 4 63-70 1F8000-1FFFFF 32 56-62 1C0000-1F7FFF Partition 1 32 48-55 180000-1BFFFF Partition 2 32 40-47 140000-17FFFF Partition 3 32 32-39 100000-13FFFF Partitions 4-7 32 0-31 000000-0FFFFF Partitions 8-15 32 71-134 200000-3FFFFF Partitions 4-7 32 39-70 100000-1FFFFF Partition 3 32 31-38 0C0000-0FFFFF Partition 2 32 23-30 080000-0BFFFF Partition 1 32 15-22 040000-07FFFF 32 8-14 008000-03FFFF 4 0-7 000000-007FFF Partition 0 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 18-Oct-2005 9 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Table 2. 64-Mbit Dual-Flash Die W18/W30 SCSP Memory Map and Partitioning Partitioning Parameter Partition Top Parameter Bottom Parameter Main Partitions Main Partitions Parameter Partition 18-Oct-2005 10 Partition 0 Block Size (KW) Block # Address Range 4 127-134 3F8000-3FFFFF 32 120-126 3C0000-3F7FFF Partition 1 32 112-119 380000-3BFFFF Partition 2 32 104-111 340000-37FFFF Partition 3 32 96-103 300000-33FFFF Partitions 4-7 32 64-95 200000-2FFFFF Partitions 8-15 32 0-63 000000-1FFFFF Partitions 8-15 32 71-134 200000-3FFFFF Partitions 4-7 32 39-70 100000-1FFFFF Partition 3 32 31-38 0C0000-0FFFFF Partition 2 32 23-30 080000-0BFFFF Partition 1 32 15-22 040000-07FFFF 32 8-14 008000-03FFFF 4 0-7 000000-007FFF Partition 0 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) 3.0 Package Information The following packages are offered with the 32WQ and 64WQ Family: * Figure 2, "Mechanical Specifications for 1- or 2-Die SCSP Device (8x10x1.2 mm)" * Figure 3, "Mechanical Specifications for Triple-Die SCSP Device (8x10x1.4 mm)" Figure 2. Mechanical Specifications for 1- or 2-Die SCSP Device (8x10x1.2 mm) Mark 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 S2 A A B B C C D D E E F D F G G H H J J K K L L M M e b E Top View - Ball Down Bottom View - Ball Up A2 A1 A Y Drawing not to scale. Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D Datasheet Symbol A A1 A2 b D E e N Y S1 S2 Min Millimeters Nom Max 1.200 Notes 0.200 0.325 9.900 7.900 1.100 0.500 Min Inches Nom Ma 0.04 0.0079 0.860 0.375 10.000 8.000 0.800 88 1.200 0.600 0.425 10.100 8.100 0.0128 0.3898 0.3110 0.100 1.300 0.700 0.0433 0.0197 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 0.0339 0.0148 0.3937 0.3150 0.0315 88 0.0472 0.0236 0.01 0.39 0.31 0.00 0.05 0.02 18-Oct-2005 11 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Figure 3. Mechanical Specifications for Triple-Die SCSP Device (8x10x1.4 mm) A1 Index Mark S1 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 S2 A A B B C C D D E E F D F G G H H J J K K L L M M e b E Top View - Ball Down Bottom View - Ball Up A2 A1 A Y Drawing not to scale. Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along E Corner to Ball A1 Distance Along D 18-Oct-2005 12 Symbol A A1 A2 b D E e N Y S1 S2 Min Millimeters Nom Max 1.400 Notes 0.200 0.325 9.900 7.900 1.100 0.500 Min Inches Nom Max 0.0551 0.0079 1.070 0.375 10.000 8.000 0.800 88 1.200 0.600 0.425 10.100 8.100 0.0128 0.3898 0.3110 0.100 1.300 0.700 0.0433 0.0197 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 0.0421 0.0148 0.3937 0.3150 0.0315 88 0.0472 0.0236 0.0167 0.3976 0.3189 0.0039 0.0512 0.0276 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) 4.0 Ballout and Signal Description 4.1 Signal Ballout Figure 4 shows the 32WQ and 64WQ W18/W30 SCSP family 88-ball (8x10 active ball matrix) device. Figure 4. 88-Ball (8x10 Active Ball Matrix) QUAD+ Ballout 1 2 3 7 8 A DU DU DU DU A B A4 A18 A19 VSS F1-VCC F2-VCC A21 A11 B C A5 R-LB# A23 VSS S-CS2 CLK A22 A12 C D A3 A17 A24 F-VPP R-WE# P1-CS# A9 A13 D E A2 A7 A25 F-WP# ADV# A20 A10 A15 E F A1 A6 R-UB# F-RST# F-WE# A8 A14 A16 F G A0 DQ8 DQ2 DQ10 DQ5 DQ13 WAIT F2-CE# G H R-OE# DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 F2-OE# H J S-CS1# F1-OE# DQ9 DQ11 DQ4 DQ6 DQ15 VCCQ J K F1-CE# P2-CS# F3-CE# S-VCC P-VCC F2-VCC VCCQ P-Mode/ P-CRE K L VSS VSS VCCQ F1-VCC VSS VSS VSS VSS L M DU DU DU DU M 1 2 7 8 3 4 4 5 6 5 6 Top View - Ball Side Down Legend: Datasheet Global Signals De-Populated Balls Flash Specific SRAM/PSRAM Specific Do Not Use Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 18-Oct-2005 13 Intel(R) Wireless Flash Memory (W18/W30 SCSP) 4.2 Signal Descriptions Table 3 describes active signals used on the 32WQ and 64WQ W18/W30 SCSP family. Table 3. Symbol Signal Descriptions (Sheet 1 of 2) Type Name and Function ADDRESS INPUTS: Inputs for all die addresses during read and write operations. Addresses are internally latched during write operations. * 4-Mbit: A[17:0] * 8-Mbit: A[18:0] A[21:0] Input * 16-Mbit: A[19:0] * 32-Mbit: A[20:0] * 64-Mbit: A[21:0] A0 is the lowest-order word address. A[25:22] denote high-order addresses reserved for future device densities D[15:0] CLK Input/ Output Input DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles; outputs data during read cycles. Data signals float when the device or its outputs are deselected. Data are internally latched during writes. FLASH CLOCK: CLK synchronizes the selected flash die to the memory bus frequency in synchronous-read mode. During synchronous read operations, the initial address is latched on the rising edge of ADV#, or the rising/ falling edge of CLK when ADV# is low, whichever occurs first. CLK is only used in synchronous-read mode. Refer to the flash discrete product datasheet for information on how to use this signal in asynchronous-read mode. ADV# Input FLASH ADDRESS VALID: Low-true; During synchronous read operations, the initial address is latched on the rising edge of ADV#, or the rising/ falling edge of CLK when ADV# is low, whichever occurs first. Refer to the flash discrete product datasheet for information on how to use this signal in asynchronous-read mode. WAIT F[3:1]-CE# Output Input FLASH WAIT: When asserted, WAIT indicates invalid data from the selected flash die on D[15:0]. WAIT is High-Z whenever the flash die is deselected (CE# = V IL). WAIT is not gated by OE#. WAIT is only used in synchronous array-read mode. Refer to the flash discrete product datasheet for information on how to use this signal in asynchronous-read mode. FLASH CHIP ENABLE: Low-true; CE#-low selects the associated flash memory die. When asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the associated flash die is deselected; power is reduced to standby levels, data and WAIT outputs are placed in High-Z. F1-CE# selects flash die #1; F2-CE# selects flash die #2 and is RFU on combinations with only one flash die. F3-CE# selects flash die #3 and is RFU on SCSP combinations with only one or two flash die. S-CS1# S-CS2 Input SRAM CHIP SELECTS: When both SRAM chip selects are asserted, SRAM internal control logic, input buffers, decoders, and sense amplifiers are active. When either/both SRAM chip selects are deasserted (S-CS1# = V IH and/or S-CS2 = VIL), the SRAM is deselected and its power is reduced to standby levels. S-CS1# and S-CS2 are only available on SCSP combinations with SRAM die. PSRAM CHIP SELECTS: Low-true; When asserted, PSRAM internal control logic, input buffers, decoders, and sense amplifiers are active. When deasserted, the PSRAM is deselected and its power is reduced to standby levels. P[2:1]-CS# 18-Oct-2005 14 Input P1-CS# selects PSRAM die #1 and is available only on SCSP combinations with PSRAM die. This ball is RFU on SCSP combinations without PSRAM. P2-CS# selects PSRAM die #2 and is available only on SCSP combinations with two PSRAM die. This ball is RFU on SCSP combinations without PSRAM or with a single PSRAM. Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Table 3. Symbol Signal Descriptions (Sheet 2 of 2) Type Name and Function FLASH OUTPUT ENABLE: Low-true; OE#-low enables the flash output buffers. OE#-high disables the flash output buffers, and places the flash outputs in High-Z. F[2:1]-OE# Input R-OE# Input F1-OE# controls the outputs of flash die #1; F2-OE# controls the outputs of flash die #2 and #3, and is available only on SCSP combinations with two or three flash die and is RFU on SCSP combinations with only one flash die. RAM OUTPUT ENABLE: Low-true; R-OE#-low enables the RAM output buffers. R-OE#-high disables the RAM output buffers, and places the RAM outputs in High-Z. R-OE# is only available on SCSP combinations with RAM die. R-UB# R-LB# Input RAM UPPER/ LOWER BYTE ENABLES: Low-true; During RAM reads, R-UB#-low enables the RAM high-order bytes on D[15:8], and R-LB#-low enables the RAM low-order bytes on D[7:0]. R-UB# and R-LB# are only available on SCSP combinations with either SRAM die or PSRAM die. FLASH WRITE ENABLE: Low-true; WE# controls writes to the selected flash die. Address and data are latched on the rising edge of WE#. F-WE# Input R-WE# Input F-WP# Input FLASH WRITE PROTECT: Low-true; WP# enables/disables the lock-down protection mechanism of the flash die. WP#-low enables the lock-down mechanism- locked down blocks cannot be unlocked with software commands. WP#-high disables the lock-down mechanism, allowing locked down blocks to be unlocked with software commands. F-RST# Input FLASH RESET: Low-true; RST#-low initializes flash internal circuitry and disables flash operations. RST#-high enables flash operation. Exit from reset places the flash in asynchronous read array mode. F-VPP F-VPEN Power RAM WRITE ENABLE: Low-true; R-WE# controls writes to the RAM die. R-WE# is only available on SCSP combinations with RAM die. FLASH PROGRAM/ ERASE POWER: A valid F-VPP voltage on this ball enables flash program/erase operations. Flash memory array contents cannot be altered when F-V PP(VPEN) < VPPLK(VPENLK). Erase/ program operations at invalid F-V PP(VPEN) voltages should not be attempted. Refer to the flash discrete product datasheet for additional details. F-VPEN (Erase/Program/Block Lock Enables) is not available for W18/W30 products. PSRAM MODE: Low-true; P-MODE is used to enter/exit low power mode. P-MODE Input Low power mode is not applicable to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0, 38F1030W0YTQE, 38F1030W0YBQE. P-Mode is only available on SCSP combinations with PSRAM die. F[2:1]-VCC Power FLASH LOGIC Power: F1-VCC supplies power to the core logic of flash die #1; F2-VCC supplies power to the core logic of flash die #2 and #3. Write operations are inhibited when F-V CC < VLKO. Device operations at invalid F-VCC voltages should not be attempted. F2-VCC is only available on SCSP combinations with two or three flash die, and is RFU on SCSP combinations with only one flash die. SRAM Power Supply: Supplies power to the SRAM die. S-VCC Power P-VCC Power VCCQ Power FLASH OUTPUT-BUFFER Power: Supplies power for the I/O output buffers. VSS Power Ground: Connect to ground. Do not float any VSS connection. RFU -- Reserved for Future Use: Reserve for future device functionality/ enhancements. DU -- Do Not Use: Do not connect to any other signal, or power supply; must be left floating. Datasheet S-VCC is only available on SCSP combinations with SRAM die. PSRAM Power Supply: Supplies power to the PSRAM die. P-VCC is only available on SCSP combinations with PSRAM die. Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 18-Oct-2005 15 Intel(R) Wireless Flash Memory (W18/W30 SCSP) 5.0 Maximum Ratings and Operating Conditions 5.1 Absolute Maximum Ratings Warning: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. NOTICE: This document contains information available at the time of its release. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Table 4. Absolute Maximum Ratings Parameter Min Max Unit Temperature under Bias Expanded -25 +85 C Storage Temperature -55 +125 C -0.2 +2.45 V Voltage On Any Signal (except F[2:1]-VCC, VCCQ, F-VPP, S-VCC and P-VCC) 1.8 V I/O 3.0 V I/O F-VPP Voltage ISH Output Short Circuit Current 7 1,2,3 -0.2 +3.6 V 2,3 -0.5 +2.45 V 2,3 1.8 V I/O -0.2 +2.45 V 1,2,3 3.0 V I/O -0.2 +3.6 V 2,3 -0.2 +14.0 V 2,3,4,5 - 100 mA 6 F[2:1]-VCC Voltage VCCQ, S-VCC and P-VCC Voltage Notes Notes: 1. 90 nm is only avail with the 1.8 V I/O. 2. All Specified voltages are relative to V SS. Minimum DC voltage is -0.2 V on input/output signals, - 0.2 V on F[2:1]-VCC and F-VPP signals. For 90 nm devices, during transitions, this level may overshoot to -1.5 V for periods < 20 ns, during transitions, may overshoot to F-V CC + 1.5 V for periods < 20 ns. 3. All Specified voltages are relative to V SS. Minimum DC voltage is -0.2 V on input/output signals, - 0.2 V on F[2:1]-VCC and F-VPP signals. For 130 nm devices, during transitions, this level may overshoot to -2 V for periods < 20 ns, during transitions, may overshoot to F-V CC + 2 V for periods < 20 ns. 4. Maximum DC voltage on F-VPP may overshoot to +14.0 V for periods < 20 ns. 5. F-VPP program voltage is normally VPPL. The maximum DC voltage on F-VPP may overshoot to +14 V for periods < 20 ns. F-V PP can be VPPH for 1000 erase cycles on main blocks, 2500 cycles on parameter blocks. 6. Output shorted for no more than one second. No more than one output shorted at a time. 7. Devices available with -30o C temperature specifications are: 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0, 38F1030W0YTQE, 38F1030W0YBQE, 18-Oct-2005 16 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) 5.2 Operating Conditions Warning: Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. Table 5. Operating Conditions Symbol Flash + SRAM Flash + PSRAM Unit Notes 2 Min Max Min Max Min Max Operating Temperature -25 +85 -25 +85 -25 +85 C F-VCC Flash Supply Voltage 1.7 1.95 1.7 1.95 1.7 1.95 V VCCQ S-VCC P-VCC Flash I/O Voltage 3.0 V I/O 2.2 3.3 2.2 3.3 2.7 3.1 V PSRAM and SRAM Supply Voltage 1.8 V I/O 1.7 1.95 1.7 1.95 1.8 1.95 V VPPL Flash Program Logic Level 0.9 1.95 0.9 1.95 0.9 1.95 V VPPH Flash Factory Program Voltage 11.4 12.6 11.4 12.6 11.4 12.6 V TC Note: 1. 2. 5.3 Flash + Flash Parameter 1 F-VPP is normally V PPL. F-VPP can be connected to 11.4 V-12.6 V for 1000 cycles on main blocks for extended temperatures and 2500 cycles on parameter blocks at extended temperature. Devices available with -30o C temperature specifications are: 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0, 38F1030W0YTQE, 38F1030W0YBQE,. Capacitance NOTICE: Refer to the 1.8-Volt Intel(R) Wireless Flash Memory Datasheet (order number 290701) and 1.8-Volt Intel(R) Wireless Flash Memory with 3 Volt I/0 Datasheet (order number 290702) for flash capacitance details. For SCSP products with two flash die, flash capacitances for each of the flash die need to be considered accordingly. Table 6. Datasheet SRAM, PSRAM Capacitance Symbol Parameter Typ Unit Condition CIN Input Capacitance 10 pF VIN = 0.0 V, Tc = 25 C, f = 1 MHz COUT Output Capacitance 10 pF VOUT = 0.0 V, Tc = 25 C, f = 1 MHz Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 18-Oct-2005 17 Intel(R) Wireless Flash Memory (W18/W30 SCSP) 6.0 Electrical Specifications 6.1 DC Characteristics SRAM and PSRAM DC characteristics are shown in Table 7 and Table 8. Refer to the Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and the Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for flash DC characteristics. Table 7. SRAM DC Characteristics 1.8 V SRAM Parameter S-VCC Description 3.0 V SRAM Test Conditions Unit Min Max Min Max Voltage Range 1.7 1.95 2.2 3.3 V VDR VCC for Data Retention 1.0 - 1.5 - V 4M - 25 - 45 ICC Operating Current at min cycle time 8M - 35 - 50 16M - 40 - 55 4M - 4 - 10 8M - 6 - 10 16M - 10 - 15 S-CS1# S-VCC-0.2V 4M - 12 - 15 or S-CS2 VSS+0.2V 8M - 20 - 25 Address/Data toggling at minimum cycle time 16M - 30 - 45 1.8 V SRAM: 4M - 6 - 5 S-VCC = 1.0 V 8M - 10 - 12 16M - 18 - 15 S-VCC 0.15 - S-VCC 0.1 - V -0.1 0.2 -0.1 0.1 V ICC2 ISB IDR Operating Current at max cycle time (1 s) Standby Current Current in Data Retention mode IIO = 0 mA IIO = 0 mA 3.0 V SRAM: S-VCC = 1.5 V IOH = -100 A mA mA A A VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage S-VCC 0.4 S-VCC+ 0.2 S-VCC 0.4 S-VCC + 0.2 V VIL Input LOW Voltage -0.2 0.4 -0.2 0.6 V IOH Output HIGH Current - - - - mA IOL Output LOW Current *IIL Input Leakage Current -0.2 < VIN < S-VCC + 0.2 V *ILDR Input Leakage Current in Data Retention Mode -0.2 < VIN < S-VCC + 0.2 V IOL = 100 A, VCCMIN S-VCC = VDR - - - - mA -1 +1 -1 +1 A -1 +1 -1 +1 A * Input leakage currents include Hi-Z output leakage for bi-directional buffers with tri-state outputs. 18-Oct-2005 18 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Table 8. PSRAM DC Characteristics 1.8 V PSRAM Parameter VCC Description 3.0 V PSRAM Test Conditions Unit Max Min Max 1.8 1.95 2.7 3.1 8M - - - 30 16M - 30 - 35 16M - 20 - - mA 3 32M - 35 - 45 mA 2 8M - - - 5 16M - 5 - 7 mA 2 A 2, 4 A 2, 5 A 2, 4 Voltage Range V mA ICC ICC2 ISB Operating Current at min cycle time Operating Current at max cycle time (1 s) Standby Current IIO = 0 mA IIO = 0 mA 32M - - - 7 8M - - - 80 All inputs stable (either high or low) 16M - 100 - 100 P-CS# P-VCC0.2V or 16M - - - 85 32M - 100 - 100 16M - - - 10 32M - 30 - 10 IOH = -0.5 mA 0.8P VCC - 2.4 - V 4 IOH = -0.1 mA 1.4 - P-VCC 0.3 - V 5 IOL = 1 mA, - 0.2P VCC - 0.4 V 4 IOL = 0.1 mA, VCCMin -0.1 0.2 -0.1 0.3 V 5 0.8P VCC P-VCC + 0.3 P-VCC 0.3 P-VCC + 0.2 V 4 P-VCC 0.3 P-VCC + 0.2 P-VCC0.4 P-VCC + 0.2 V 5 -0.3 0.2P VCC -0.2 0.5 V 4 -0.2 0.4 -0.2 0.6 V 5 Address/Data toggling at minimum cycle time Deep PowerDown VOH Output HIGH Voltage VOL VIH VIL Datasheet Output LOW Voltage Input HIGH Voltage Input LOW Voltage 2 P-CS# P-VCC0.2V. P-Mode P-VCC0.2V Isbd Note Min P-Mode 0.2 V Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 18-Oct-2005 19 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Table 8. PSRAM DC Characteristics IIL Input Leakage Current IOL Output Leakage Current Notes: 1. 2. 3. 4. 5. -0.2 < VIN < P-VCC + 0.2 V -0.2 < VIN < P-VCC + 0.2 V P-VCC = VDR -1 +1 -1 +1 A 1, 2 -1 +1 -1 +1 A 1, 2 Input Leakage currents include Hi-Z output leakage for bi-directional buffers with tri-state outputs. All currents are in RMS unless noted otherwise. Applicable only to parts 38F1030W0YxQF & 38F2030W0YxQF Applicable to parts with P-Mode pin (38F2030W0ZxQ1, 38F2040W0YxQ0, 28F2240WWYxQ0). Applicable to No-P-Mode (38F1030W0YxQE, 38F1030W0YxQ2, 38F1030W0ZxQ0, 38F2030W0YxQ1, 38F2030W0YxQE, 38F2030W0YxQ2, 38F2030W0YxQF, 38F2030W0ZxQ2, 38F2040W0ZxQ0) 18-Oct-2005 20 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) 7.0 AC Characteristics 7.1 Flash AC Characteristics Refer to the Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) 7.2 SRAM AC Characteristics Table 9. SRAM AC Characteristics -- Read Operations # Symbol1 R1 tRC Read Cycle Time R2 tAA Address to Output Delay - 70 ns 1 R3 tCO1 S-CS1# to Output Delay - 70 ns 1 R3 tCO2 S-CS2 to Output Delay - 70 ns 1 R4 tOE R-OE# to Output Delay - 35 ns 1 R5 tBA R-UB#, R-LB# to Output Delay - 70 ns 1 R6 tLZ S-CS1# or S-CS2 to Output in Low-Z 5 - ns 1,3,4 R7 tOLZ R-OE# to Output in Low-Z 0 - ns 1,4 R8 tHZ S-CS1# or S-CS2 to Output in High-Z 0 25 ns 1,2,3,4 R9 tOHZ R-OE# to Output in High-Z 0 25 ns 1,2,4 R10 tOH Output Hold (from Address, S-CS1#, S-CS2 or R-OE# Change, whichever occurs first) 0 - ns 1 R11 tBLZ R-UB#, R-LB# to Output in Low-Z 0 - ns 1,4 R12 tBHZ R-UB#, R-LB# to Output in High-Z 0 25 ns 1,4 Note: 1. 2. 3. 4. Parameter Min Max Unit Notes 70 - ns 1 See Figure 5, "AC Waveform SRAM Read Operations" . Timings of t HZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. At any given temperature and voltage condition, tHZ (Max) is less than tLZ (Max) both for a given device and from device to device interconnection. Sampled but not 100% tested. Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 18-Oct-2005 21 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Figure 5. AC Waveform SRAM Read Operations R1 Address Stable Standby ADDRESSES R3 R8 S-CS1# R6 S-CS2 R7 R9 R-OE# R-WE# R4 R2 DATA R10 Valid Data R11 R5 R12 R-UB#, R-LB# Table 10. SRAM AC Characteristics -- Write Operations # Symbol 1 W1 tWC Write Cycle Time 70 - ns 1 W2 tAS Address Setup to R-WE# (S-CS1#) and R-UB#/R-LB# Low 0 - ns 1,4 W3 tWP R-WE# (S-CS1#) Pulse Width 55 - ns 1,2,3 W4 tDW Data to Write Time Overlap 30 - ns 1 W5 tAW Address Setup to R-WE# (S-CS1#) High 60 - ns 1 W6 tCW S-CS1# (R-WE#) Setup to R-WE# (S-CS1#) High 60 - ns 1 W7 tDH Data Hold from R-WE# (S-CS1#) High 0 - ns 1 W8 tWR Write Recovery 0 - ns 1,5 W9 tBW R-UB#, R-LB# Setup to R-WE# (S-CS1#) High 60 - ns 1 Parameter Min Max Unit Notes Notes: 1. See Figure 6, "AC Waveform SRAM Write Operations" . 2. A write occurs during the overlap (tWP ) of low S-CS1# and low R-WE#. A write begins when S-CS1# goes low and RWE# goes low with asserting R-UB# and R-LB# for single byte operation or simultaneously asserting R-UB#R-LB# and R-LB# for double byte operation. A write ends at the earliest high transition of S-CS1# and R-WE#. 3. tWP is measured from S-CS1# low to the end of a write. 4. tAS is measured from the address valid to the beginning of a write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as S-CS1# or R-WE# goes high. 18-Oct-2005 22 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Figure 6. AC Waveform SRAM Write Operations W1 Address Stabl e Standby ADDRESSES W6 W8 S-CS1# S-CS2 R-OE# W3 W5 R-WE# W4 DATA W7 Data In W2 W9 R-UB#, R-LB# Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 18-Oct-2005 23 Intel(R) Wireless Flash Memory (W18/W30 SCSP) 7.3 PSRAM AC Characteristics Table 11. PSRAM AC Characteristics (85ns or 88ns Initial Access) -- Read Operations 1.8 V # 4. 5. 3.0 V Parameter5 Unit Min Max Min Max Notes R1 tRC Read Cycle Time 88 4,000 85 4,000 ns R2 tAA Address to Output Delay - 88 - 85 ns R3 tCO P-CS# to Output Delay - 88 - 85 ns R4 tOE R-OE# to Output Delay - 65 - 40 ns R5 tBA R-UB#, R-LB# to Output Delay - 88 - 85 ns R6 tLZ P-CS# to Output in Low-Z 10 - 10 - ns 1,2 R7 tOLZ R-OE# to Output in Low-Z 5 - 0 - ns 2 R8 tHZ P-CS# to Output in High-Z - 25 0 25 ns 1,2,3 R9 tOHZ R-OE# to Output in High-Z - 25 0 25 ns 2,3 R10 tOH Output Hold (from Address, P-CS# or ROE# change, whichever occurs first) 5 - 0 - ns R11 tBLZ R-UB#, R-LB# to Output in Low-Z 5 - 0 - ns 2 R12 tBHZ R-UB#, R-LB# to Output in High-Z - 25 0 25 ns 2 PR1 tPC Page Cycle Time 30 - 40 - ns 4 PR2 tPA Page Access Time - 30 - 35 ns 4 Note: 1. 2. 3. Symbol At any given temperature and voltage condition, tHZ (Max) is less than tLZ (Max) both for a given device and from device to device interconnection. Sampled but not 100% tested. Timings of tHZ and t OHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4-Word Page read only available for 32-Mbit PSRAM. No page mode feature for 16-Mbit PSRAM. Applicable to parts with 85ns or 88ns initial access time: (38F2030W0ZxQ1, 38F2040W0YxQ0, 38F2040W0ZxQ0, 28F2240WWYxQ0). 18-Oct-2005 24 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Table 12. PSRAM AC Characteristics (70ns Initial Access)-- Read Operations 1.8 V # Symbol1 R1 5. 6. 7. Max Min Max 70 15000 70 15000 70 8000 - - Notes Read Cycle Time R2 tAA Address to Output Delay - 70 - 70 ns R3 tCO P-CS# to Output Delay - 70 - 70 ns R4 tOE R-OE# to Output Delay - 45 - 45 ns R5 tBA R-UB#, R-LB# to Output Delay - 70 - 70 ns R6 tLZ P-CS# to Output in Low-Z 5 - 5 - ns R7 tOLZ R-OE# to Output in Low-Z 0 - 0 - ns R8 tHZ P-CS# to Output in High-Z 0 25 0 25 ns 3, 4 R9 tOHZ R-OE# to Output in High-Z 0 25 0 25 ns 4 R10 tOH Output Hold (from Address, P-CS# or ROE# change, whichever occurs first) 0 - 0 - ns R11 tBLZ R-UB#, R-LB# to Output in Low-Z 0 - 0 - ns R12 tBHZ R-UB#, R-LB# to Output in High-Z 0 25 0 25 ns PR1 tPC Page Cycle Time 25 - 25 - ns 5 tPA Page Access Time - 25 - 25 ns 5 tCEL CE# low-time restriction - 8,000 ns 4 ns 6 Note: 1. 4. Unit Min tRC PR2 2. 3. 3.0 V Parameter7 ns 2 3 See Figure 7, "AC Waveform of PSRAM Read Operations" on page 27 and Figure 8, "AC Waveform of PSRAM 4-Word Page Read Operation" on page 27 Spec's only applicable to parts 38F1030W0YxQF & 38F2030W0YxQF At any given temperature and voltage condition, tHZ (Max) is less than tLZ (Max) both for a given device and from device to device interconnection. Timings of t HZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 4-Word Page read only available for 16-Mbit PSRAM. No page mode feature for 8-Mbit PSRAM. Parts 38F1030W0YxQF & 38F2030W0YxQF do not support page mode, so this spec will not apply to them CE# must go high and be maintained high for a minimum of 10ns at least once every 8,000ns Applicable to 70ns initial access P-SRAM's (38F1030W0YxQE, 38F1030W0YxQ2, 38F1030W0ZxQ0, 38F2030W0YxQ1, 38F2030W0YxQE, 38F2030W0YxQ2, 38F2030W0YxQF, 38F2030W0ZxQ2) Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 18-Oct-2005 25 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Table 13. PSRAM AC Characteristics--Write Operations 1.8 V # Symbol1 3.0 V Parameter7 Write Cycle Time Unit Notes Min Max Min Max 70 8000 70 - ns 0 - 0 - ns 4 2,3 W1 tWC W2 tAS W3 tWP R-WE#(P-CS#) Pulse Width 55 - 55 - ns W4 tDW Data to Write Time Overlap 35 - 35 - ns W5 tAW 60 - 60 - ns W6 tCW 60 - 60 - ns W7 tDH 0 - 0 - ns W8 tWR Write Recovery 0 - 0 - ns W9 tBW R-UB#, R-LB# Setup to R-WE# (P-CS#) Going High 60 - 60 - ns tCEL P-CE# low-time restriction - 8,000 - - ns 7,8 tWPH Write High Pulse Width 10 - - - ns 8 W10 Address Setup to R-WE# (P-CS#) and R-UB#, R-LB# going low Address Setup to R-WE# (P-CS#) Going High P-CS# (R-WE#) Setup to R-WE# (P-CS#) Going High Data Hold from R-WE# (P-CS#) High 5 Notes: 1. See Figure 9, "AC Waveform PSRAM Write Operation" . 2. A write occurs during the overlap (tWP) of low P-CS# and low R-WE#. A write begins when P-CS# goes low and R-WE# goes low with asserting R-UB# or R-LB# for single byte operation or simultaneously asserting R-UB# and R-LB# for double byte operation. A write ends at the earliest transition when P-CS# goes high and R-WE# goes high. 3. tWP is measured from P-CS# going low to end of a write. 4. tAS is measured from the address valid to the beginning of a write. 5. tWR is measured from the end of a write to the address change. tWR applied in case a write ends as P-CS# or R-WE# going high. 6. W3 is 70 ns for continuous write operations over 50 times. 7. P-CE# must go high and be maintained high for a minimum of 10ns at least once every 8,000ns 8. Spec's only applicable to parts 38F1030W0YxQF & 38F2030W0YxQF 9. Applicable to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0, 38F1030W0YTQE, 38F1030W0YBQE. 18-Oct-2005 26 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Figure 7. AC Waveform of PSRAM Read Operations R1 R2 ADDRESSES R3 R8 P-CS# R5 R12 R-UB#, R-LB# R4 R9 R-OE# R7 R11 R6 R10 DAT A Figure 8. Valid Data AC Waveform of PSRAM 4-Word Page Read Operation R1 R2 A[Max:2] Vali d Address A[1:0] Valid Address PR1 Valid Address Valid Address Valid Address R3 R8 P-CS# R4 R9 R-OE# R7 R6 DATA Note: Datasheet PR2 Vali d Data Vali d Data Vali d Data Vali d Data Available only for 32-Mbit PSRAM and line items with 16-Mbit PSRAM (70 ns) 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0, 38F1030W0YTQE, 38F1030W0YBQE. Not applicable to 8-Mbit PSRAM. Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 18-Oct-2005 27 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Figure 9. AC Waveform PSRAM Write Operation W1 W2 ADDRESSES W6 P-CS# W9 R-UB#, R-LB# W8 W3 W5 R-WE# W4 DAT A 18-Oct-2005 28 W7 Data In Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) 7.4 Device AC Test Conditions Figure 10. Transient Input/Output Reference Waveform VCCQ , P-VCC Input VCCQ /2, P-VCC/2 VCCQ /2, P-VCC/2 Test Points Output 0V Note: Figure 11. AC test inputs are driven to VCCQ, P-VCC for logic "1" and 0.0 V for logic "0". input/output timing begins/ ends at VCCQ/2, P-VCC /2. Input rise and fall time (10% to 90%) < 5 ns. Worse case speed occurs at VCC = VCCMin. Transient Equivalent Testing Load Circuit I/O Output Z O = 50 Ohms 50 Ohms C L = 30 pf P-VCC /2 = VCCQ /2 Notes: 1. Test configuration component value for worst case specification conditions. 2. CL includes jig capacitance. Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 18-Oct-2005 29 Intel(R) Wireless Flash Memory (W18/W30 SCSP) 8.0 Flash Power Consumption Refer to the Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for information regarding flash read modes and operations. 18-Oct-2005 30 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) 9.0 Device Operation 9.1 Bus Operations Bus operations for the W18/W30 SCSP family involve the following chip enable and output enable signals, respectively: * F1-CE# for Flash Die#1 and F2-CE# for Flash Die#2 * F1-OE# for Flash Die#1 and F2-OE# for Flash Die#2 All other control signals are shared between the two flash die. Table 14 to Table 16 explain the bus operations of products across this SCSP family. Refer to the W18/W30 discrete datasheets (order numbers 290701 and 290702) for single flash die SCSP bus operations. F1-CE# F1-OE# F-WE# ADV# F-VPP WAIT F2-CE# F2-OE# D[15:0] Sync Array Read H L L H L X Active H X Flash DOUT 2, 3, 4 All Async / Sync Non-Array Read H L L H X X Asserted H X Flash DOUT 1, 3, 4, 5 Write H L H L X VPPL or VPPH Asserted H X Flash DIN 3, 4, 6 Output Disable H L H H X X Active X X Flash High-Z 4 Standby H H X X X X High-Z X X Flash High-Z 4 Reset L X X X X X High-Z X X Flash High-Z 4 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Notes Mode Device Flash Die#1 Flash-Only Bus Operations F-RST# Table 14. 18-Oct-2005 31 F1-OE# F-WE# ADV# F-VPP WAIT F2-CE# F2-OE# D[15:0] H H X H L X Active L L Flash DOUT 2, 3, 4 All Async / Sync Non-Array Read H H X H X X Asserted L L Flash DOUT 1, 3, 4, 5 Write H H X L X VPPL or VPPH Asserted L H Flash DIN 3, 4, 6 Output Disable H X X H X X Active L H Flash High-Z 4 Standby H X X X X X High-Z H X Flash High-Z 4 Reset L X X X X X High-Z X X Flash High-Z 4 Flash Die#2 Notes F1-CE# Sync Array Read Device Mode F-RST# Intel(R) Wireless Flash Memory (W18/W30 SCSP) Notes: 1. For asynchronous read operation, both die may be simultaneously selected, but may not simultaneously drive the memory bus. See Section 9.2, "Flash Command Definitions" on page 34 for details regarding flash selection overlap. 2. WAIT is only valid during synchronous flash reads. WAIT is driven if F-CE# is asserted. Refer to the W18 or W30 datasheet (order number 290701 and 29702) for further information regarding WAIT Signal. 3. For either flash die, F[2:1]-OE# and F-WE# should never be asserted simultaneously. If done so on a particular flash die, F[2:1]-OE# will override F-WE#. 4. L means VIL while H means VIH. X can be VIL or VIH for inputs, VPPL, VPPH or VPPLK for F-VPP. 5. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0]. 6. Refer to W18/W30 datasheet for valid DIN during flash writes. X Active All Async/ Sync Non-array Read H L L H X X Asserted Write H L H L L VPPL or VPPH Output Disable H L H H X Standby H H X X Reset L X X X 18-Oct-2005 32 Notes L D[15:0] WAIT H R-UB#, R-LB# F-VPP L R-WE# ADV# L R-OE# F-WE# H S-CS2 F[2:1]-OE# Sync Array Read Mode S-CS1# F[2:1]-CE# Flash + SRAM Bus Operations F-RST# Flash Die(#1 or #2) Device Table 15. Flash DOUT 1, 2, 3, 5 Flash DOUT 1, 2, 3, 5, 6 Asserted Flash DIN 3, 7 X Active Flash High-Z 5 X X High-Z Flash High-Z 5 X X High-Z Flash High-Z 5 SRAM must be in High-Z Any SRAM mode allowed Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) R-OE# R-WE# R-UB#, R-LB# D[15:0] L SRAM DOUT 1, 4, 8, 2 Write L H X L L SRAM DIN 4, 5, 8, 2 Output Disable L H H H X SRAM High-Z 5, 2 H X X X X L SRAM High-Z 5, 8, 2 X SRAM High-Z 9, 2 Read SRAM Flash must be in High-Z Standby Any flash mode allowed Data Retention Same as SRAM standby Notes S-CS2 H WAIT L F-VPP H ADV# L Mode F-WE# S-CS1# F[2:1]-OE# F[2:1]-CE# Flash + SRAM Bus Operations F-RST# Device Table 15. Notes: 1. For asynchronous read operation, all die may be simultaneously selected, but may not simultaneously drive the memory bus. 2. WAIT is only valid during synchronous flash reads. WAIT is driven if F-CE# is asserted. 3. For flash die, F[2:1]-OE# and F-WE# should never be asserted simultaneously. If done so, F[2:1]-OE# will override F-WE#. 4. For SRAM, R-OE# and R-WE# should never be asserted simultaneously. 5. X can be VIL or VIH for inputs, VPPL, VPPH or VPPLK for F-VPP. 6. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0]. 7. Refer to W18 and W30 datasheet for valid DIN during flash writes. 8. The SRAM is enabled and/or disabled with the logical function: S-CS1# OR S-CS2. 9. The SRAM can be placed into data retention mode by lowering S-VCC to the V DR limit when in standby mode. X Active All Async/ Sync Non-array Read H L L H X X Asserted Write H L H L X VPPL or VPPH Output Disable H L H H X Standby H H X X Reset L X X X Datasheet Notes L D[15:0] WAIT H R-UB#, R-LB# F-VPP L R-WE# ADV# L R-OE# F-WE# H P-Mode F[2:1]-OE# Sync Array Read Mode P-CS# F[2:1]-CE# Flash + PSRAM Bus Operations F-RST# Flash Die(#1 or #2) Device Table 16. Flash DOUT 1, 2, 3, 4, 6 Flash DOUT 1, 2, 3, 4, 6, 7 Asserted Flash DIN 3, 4, 6, 8 X Active Flash High-Z 6 X X High-Z Flash High-Z 6 X X High-Z Flash High-Z 6 PSRAM must be in High-Z Any PSRAM mode allowed Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 18-Oct-2005 33 Intel(R) Wireless Flash Memory (W18/W30 SCSP) R-OE# R-WE# R-UB#, R-LB# D[15:0] L PSRAM DOUT Write L H H L L Output Disable L H H H X Standby H H X X X PSRAM High-Z 6, 2 H L X X X PSRAM High-Z 6, 9, 2 Read PSRAM Flash#1 and #2 must be in High-Z Any flash mode allowed Deep PowerDown PSRAM DIN PSRAM High-Z Notes P-Mode H WAIT L F-VPP H ADV# L Mode F-WE# P-CS# F[2:1]-OE# F[2:1]-CE# Flash + PSRAM Bus Operations F-RST# Device Table 16. 1, 5, 2 5, 2 6, 2 Notes: 1. For asynchronous read operation, all die may be simultaneously selected, but may not simultaneously drive the memory bus. For synchronous burst-mode reads, only two die (one flash and the PSRAM) may be simultaneously selected. 2. WAIT is only valid during synchronous flash reads. WAIT is driven if F-CE# is asserted. 3. F1-CE# for Flash Die#1, F2-CE# for Flash Die#2. F1-OE# is for Flash Die#1, F2-OE# for Flash Die#2. 4. For either flash die, F[2:1]-OE# and F-WE# should never be asserted simultaneously. If done so on a particular flash die, F[2:1]OE# will override F-WE#. 5. For PSRAM, R-OE# and R-WE# should never be asserted simultaneously. 6. X can be VIL or VIH for inputs, VPPL,VPPH or VPPLK for F-VPP. 7. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0]. 8. Refer to W30/W18 datasheet for Valid DIN during flash writes. 9. Deep power-down is not applicable to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0, 38F1030W0YTQE, 38F1030W0YBQE. 9.2 Flash Command Definitions Refer to the discrete datasheets, Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for information regarding flash command definitions. 18-Oct-2005 34 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) 10.0 Flash Read Operations Refer to the Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for information regarding flash read modes and operations. Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 18-Oct-2005 35 Intel(R) Wireless Flash Memory (W18/W30 SCSP) 11.0 Flash Program Operations Refer to the Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for information regarding flash read modes and operations. 18-Oct-2005 36 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) 12.0 Flash Erase Operations Refer to the Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for information regarding flash read modes and operations. Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 18-Oct-2005 37 Intel(R) Wireless Flash Memory (W18/W30 SCSP) 13.0 Flash Security Modes Refer to the Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for information regarding flash read modes and operations. 18-Oct-2005 38 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) 14.0 Flash Read Configuration Register Refer to the Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for information regarding flash read modes and operations. Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 18-Oct-2005 39 Intel(R) Wireless Flash Memory (W18/W30 SCSP) 15.0 SRAM Operations 15.1 Power-up Sequence and Initialization The SRAM functionality and reliability are independent of the power-up sequence and power-up slew rate of the core S-VCC. Any power-up sequence and power-up slew rate is possible under use conditions. SRAM reliability is also independent of the power-down sequence and power-down slew rate of the core S-VCC. 15.2 Data Retention Mode Table 17. SRAM Data Retention Operation Symbol Parameter tSDR Data Retention Set-up Time tRDR Data Retention Recovery Time Note: 1. Min Max Unit 0 - ns tRC - ns Notes 1 tRC is defined in Table 7.2, "SRAM AC Characteristics" on page 21. Figure 12. SRAM Data Retention Operation Waveform--S-CS1# Controlled tSDR Data Retention Mode tRDR S-VCC S-VCCmin S-VIHmin VDR S-CS1# VSS 18-Oct-2005 40 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Figure 13. SRAM Data Retention Operation Waveform--S-CS2 Controlled tSDR Data Retention Mode tRDR S-VCC S-CS2 S-VCCMIN VDR VILMAX VSS Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 18-Oct-2005 41 Intel(R) Wireless Flash Memory (W18/W30 SCSP) 16.0 PSRAM Operations 16.1 Power-Up Sequence and Initialization The PSRAM functionality and reliability are independent of the power-up sequence and slew rate of the core P-VCC. Any power-up sequence and slew rate is possible under use conditions. PSRAM reliability are also independent of the power-down sequence and slew rate of the core P-VCC. The following power-up sequence and register setting should be used before starting normal operation. The PSRAM power-up sequence is represented in Figure 14. Following power application, make P-Mode high after fixing P-Mode to a low level for a period of tI1. Make P-CS# high before making P-Mode high. P-CS# and P-Mode are fixed to a high level for period of tI3. Figure 14. Timing Waveform for Power-Up Sequence Register Setting Power Up P-VCC tI2 P-CS# tI1 tI3 P-MODE Table 18. Power-Up Sequence Specifications Parameter Description Min Max Unit Notes tI1 Power application with P-Mode held low 50 -- s 1,2,3 tI2 P-CS# high to P-Mode high 10 -- ns tI3 P-Mode high to P-CS# low 500 -- s Notes: 1. Toggle P-Mode to low when starting the power-up sequence. 2. tI1 is specified from when the power supply voltage reaches VCCMIN. 3. Does not apply to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, and 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0, 38F1030W0YTQE, 38F1030W0YBQE line items. Valid PSRAM operations for these line items can begin 200 s after PVcc has reached P-Vcc min. 16.1.1 16Mbit PSRAM Power-Up Sequence (Non-Page Mode) For the non-page mode PSRAM (part's RD38F1030W0YQF, PF38F1030W0YQF, RD38F2030W0YQF, PF38F2030W0YQF) the PSRAM functionality and reliability must be independent of the power-up sequence and power-up slew rate of the core Vcc and the I/O Vcc 18-Oct-2005 42 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) (Vccq.) Any power-up sequence and power-up slew rate is possible under use conditions. PSRAM reliability must also be independent of the power-down sequence and power-down slew rate of the core Vcc and the I/O Vcc (Vccq.) Once power supply voltages have reached the minimum spec value of 1.7V (or higher), CE# must be maintained high for minimum 200us prior to commencing valid PSRAM operation. 16.2 Standby Mode/ Deep Power-Down Mode Caution: All line items that do not have the P-Mode pine will not have the deep power-down feature (38F1030W0YxQE, 38F1030W0YxQ2, 38F1030W0ZxQ0, 38F2030W0YxQ1, 38F2030W0YxQE, 38F2030W0YxQ2, 38F2030W0YxQF, 38F2030W0ZxQ2, 38F2040W0ZxQ0). Data is lost during deep power-down mode as shown in the Table below. Wake-up from deep power-down mode involves the same initialization sequence as discussed in Section 16.1, "PowerUp Sequence and Initialization" on page 42. Figure 15. Mode Memory Cell Data Delay time to go Active Standby Valid 0 ns Deep Power-Down Invalid Start-Up Sequence Timing Waveform for Entering Deep Power-Down Mode 1 us P-MODE P-CS# Suspend Mode Deep Power Down Mode Device Mode 16.3 PSRAM Special Read and Write Constraints Caution: This section will not apply to line items that do not have the P-Mode pine will not have the deep power-down feature (38F1030W0YxQE, 38F1030W0YxQ2, 38F1030W0ZxQ0, 38F2030W0YxQ1, 38F2030W0YxQE, 38F2030W0YxQ2, 38F2030W0YxQF, 38F2030W0ZxQ2, 38F2040W0ZxQ0). Table 19. PSRAM Special Read Constraints Datasheet Description Min Max Unit Cannot have sub tRC address toggle for more than 4 s in active mode. Need either a read operation or P-CS# high for tRC in that time frame N/A N/A - P-CS# high level pulse width 10 - ns Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Notes 1 18-Oct-2005 43 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Table 19. PSRAM Special Read Constraints R-UB#/R-LB# high level pulse width 10 - ns R-OE# high level pulse width in active mode (P-CS# low) 10 10,000 ns P-CS# low to R-OE# low - 10,000 ns Address Skew time (unstable address with P-CS# low) - 10 ns 1 2 Notes: 1. Toggling of these control signals is not necessary during address controlled read operations. 2. Address skew time (tSKEW) indicates the following three types of time depending on the condition. a. When switching P-CS# from high to low, t SKEW is the time from the P-CS# low input point until the next address is determined. b. When switching P-CS# from low to high, tSKEW is the time from the address change start point to the P-CS# high input point. c. When P-CS# is fixed to low, tSKEW is the time from the address start point until the next address is determined. Since specs are defined for tSKEW only when P-CS# is active, tSKEW is not subject to limitations when P-CS# is switched from high to low following address determination, or when the address is changed after P-CS# is switched from low to high. Table 20. PSRAM Special Write Constraints Description Min Max Unit Need either R-WE# high or P-CS# high for at least tWC time, for every 4us window during write operations. N/A N/A - R-OE# high to R-WE# low in active mode (P-CS# low) 0 10,000 ns R-WE# high to R-OE# low in active mode (P-CS# low) 10 10,000 ns Address Skew time (unstable address with P-CS# low) - 10 ns Notes 1 Note: 1. Address skew time (tSKEW) indicates the following three types of time depending on the condition. a. When switching P-CS# from high to low, tSKEW is the time from the P-CS# low input point until the next address is determined. b. When switching P-CS# from low to high, tSKEW is the time from the address change start point to the P-CS# high input point. c. When P-CS# is fixed to low, tSKEW is the time from the address start point until the next address is determined. Since specs are defined for tSKEW only when P-CS# is active, tSKEW is not subject to limitations when P-CS# is switched from high to low following address determination, or when the address is changed after P-CS# is switched from low to high. 18-Oct-2005 44 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Appendix A Write State Machine Refer to the Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for the WSM details. Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 18-Oct-2005 45 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Appendix B Common Flash Interface Refer to the Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for the CFI details. 18-Oct-2005 46 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Appendix C Flash Flowcharts Refer to the Intel(R) Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel(R) Wireless Flash Memory (W30) Datasheet (order number 290702) for the flash flowchart details. Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 18-Oct-2005 47 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Appendix D Additional Information : Order Number Document 290701 Intel(R) Wireless Flash Memory (W18) Datasheet 290702 Intel(R) Wireless Flash Memory with 3 Volt I/O (W30) Datasheet 251216 64-Mbit 1.8 Volt Intel(R) Wireless Flash Memory SCSP Family Application Note Notes: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. For the most current information on Intel (R) Flash memory products, software and tools, visit our website at http://developer.intel.com/design/flash. 18-Oct-2005 48 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Appendix E Ordering Information Figure 16 shows the decoder for products in this SCSP family with both flash and RAM. Figure 17 shows the decoder for products in this SCSP family with flash die only (no RAM). Table 23, "32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash + PSRAM)" on page 52 lists available product combinations. Flash #2 Family Flash #1 Family RAM #1 RAM #2 Flash #2 Decoder for Flash + RAM SCSP Family Devices Flash #1 Figure 16. R D 3 8 F 2 0 3 0 W 0 Z B Q 0 Device D etails Packa ge R D = S CS P P F = P b-free SC SP 0-9, A-D = 1 st Generation, 130 nm E-R = 2 nd Generation, 90 nm (note: 90 nm is only 1.8 V I/O ) Produc t Line D esignator 38F = F lash & RA M Stack D evice S-Z = 3 rd Generation, TB D Pinout Indica tor Q = Q UA D+ ballout Flash Dens ity 2 = 64-M bit 1 = 32-M bit 0 = N o die Param eter Loc ation RAM Dens ity Voltage 4 3 2 1 0 Datasheet = = = = = 32-M bit 16-M bit 8-M bit 4-M bit N o D ie B = Bottom P aram eter T = Top P aram eter D = Dual Param eter Y = 1.8 Volt I/O Z = 3 V olt I/O Produc t Fa m ily W = Intel(R) W ireless F lash M em ory 0 = N o D ie Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 18-Oct-2005 49 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Flash 3/4 Family Flash 1/2 Family Flash #4 Flash #3 Flash #2 Decoder for Flash-Only SCSP Family Devices Flash #1 Figure 17. R D 4 8 F 2 2 0 0W 0 Z D Q 0 Device Details 0-9, A-D = 1stGeneration, 130 nm E-R = 2nd Generation, 90 nm Package RD = SCSP PF = Pb-free SCSP (note: 90 nm is only 1.8 V I/O) S-Z = 3rd Generation, TBD Product Line Designator Pinout Indicator Q = QUAD+ Ballout 48F = Flash-only Stack Device Parameter Location Flash Density D = Dual Parameter T = Top Parameter B = Bottom Parameter 2 = 64-Mbit 1 = 32-Mbit 0 = No Die Voltage Y = 1.8 Volt I/O Z = 3 Volt I/O Product Family W = Intel(R) Wireless Flash Memory 0 = No Die Table 21. 32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash Only) Package Flash Component Product Number (1,2,3,4,5) Size (mm) Type Ballout 32 W30 8 x 10 x 1.2 Lead-free Quad + 64 W30 8 x 10 x 1.2 Lead-free Quad + 64 W18 + 32 W18 8 x 10 x 1.2 Leaded Quad + RD48F2100W0YDQE 64 W18 + 64W18 8 x 10 x 1.2 Leaded Quad + RD48F2200W0YDQ0 PF48F1000W0ZTQ0 PF48F1000W0ZBQ0 PF48F2000W0ZTQ0 PF48F2000W0ZBQ0 Notes: 18-Oct-2005 50 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) 1. 2. 3. 4. 5. Table 22. W18 = Intel(R) Wireless Flash Memory (W18) with 1.8 V I/O; W30 = Intel(R) Wireless Flash Memory (W30) with 3.0 V I/O. B = Bottom Parameter, where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter. T = Top Parameter where Flash Die #1, F1-CE# = Top Parameter and Flash Die #2, F2-CE# = Bottom Parameter. D = Dual Parameter where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter. Parts ending with "QE" are 90 nm Flash devices. 32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash + SRAM) Flash Component RAM Size in Mbit and Family Size in Mbit and Type Size (mm) Type Ballout 4 SRAM 8 x 10 x 1.2 Leaded Quad+ 8 SRAM 8 x 10 x 1.2 Leaded Quad+ 16 SRAM 8 x 10 x 1.2 Leaded Quad+ 8 SRAM 8 x 10 x 1.2 Leaded Quad+ 16 SRAM 8 x 10 x 1.2 Leaded Quad+ 64 W18 + 64 W18 16 SRAM 8 x 10 x 1.4 Leaded Quad+ RD38F2230WWYDQ0 64 W30 + 64 W30 16 SRAM 8 x 10 x 1.4 Leaded Quad+ RD38F2230WWZDQ0 Package Product Number(1,2,3,4) 64 W18 RD38F2010W0YTQ0 RD38F2010W0YBQ0 RD38F2020W0YTQ0 RD38F2020W0YBQ0 RD38F2030W0YTQ0 RD38F2030W0YBQ0 RD38F2020W0ZTQ0 RD38F2020W0ZBQ0 64 W30 RD38F2030W0ZTQ0 RD38F2030W0ZBQ0 Notes: 1. W18 = Intel(R) Wireless Flash Memory (W18) with 1.8 V I/O; W30 = Intel(R) Wireless Flash Memory (W30) with 3.0 V I/O. 2. B = Bottom Parameter, where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter. 3. T = Top Parameter where Flash Die #1, F1-CE# = Top Parameter and Flash Die #2, F2-CE# = Bottom Parameter. 4. D = Dual Parameter where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter. Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 18-Oct-2005 51 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Table 23. 32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash + PSRAM) (Sheet 1 of 2) Flash Component RAM Package Size in Mbit and Family Size in Mbit and Type Size (mm) Ballout Type 32 W18 16 PSRAM 8 x 10 x 1.2 Quad+ Lead-free Product Number (1,2,3,4,5) Leaded 32 W18 16 PSRAM 8 x 10 x 1.2 Leaded 32 W30 16 PSRAM 8 x 10 x 1.2 Leaded Lead-free 16 PSRAM 8 x 10 x 1.2 Lead-free Leaded Lead-free 16 PSRAM 8 x 10 x 1.2 Lead-free Leaded 16 PSRAM 8 x 10 x 1.2 Quad+ Leaded Lead-free Leaded 64 W18 32 PSRAM 8 x 10 x 1.2 70 ns, No PMODE pin & Non-Page Mode Support RD38F1030W0ZTQ0 RD38F1030W0ZBQ0 70 ns, PF38F1030W0ZTQ0 No PMODE pin PF38F1030W0ZBQ0 RD38F2030W0YTQ1 RD38F2030W0YBQ1 PF38F2030W0YTQ1 PF38F2030W0YBQ1 70 ns, RD38F2030W0YTQE No PMODE pin RD38F2030W0YBQE PF38F2030W0YTQE PF38F2030W0YBQE RD38F2030W0YTQ2 RD38F2030W0YBQ2 PF38F2030W0YTQ2 PF38F2030W0YBQ2 RD38F2030W0YTQF RD38F2030W0YBQF 70 ns, No PMODE pin & Non-Page Mode Support PF38F2030W0YTQF PF38F2030W0YBQF RD38F2030W0ZTQ1 85 ns, RD38F2030W0ZBQ1 with PMODE pin RD38F2030W0ZTQ2 RD38F2030W0ZBQ2 70 ns, PF38F2030W0ZTQ2 No PMODE pin PF38F2030W0ZBQ2 RD38F2040W0YTQ0 RD38F2040W0YBQ0 88 ns, PF38F2040W0YTQ0 with PMODE pin QUAD+ Lead-free 18-Oct-2005 52 PF38F1030W0YTQ2 PF38F1030W0YBQ2 Quad+ Leaded 64 W30 RD38F1030W0YTQ2 RD38F1030W0YBQ2 Quad+ Leaded 64 W18 70 ns, No PMODE pin Quad+ Lead-free 64 W18 PF38F1030W0YTQE PF38F1030W0YBQE Quad+ Lead-free PSRAM used PF38F2040W0YBQ0 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Table 23. 32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash + PSRAM) (Sheet 2 of 2) Flash Component RAM Package Size in Mbit and Family Size in Mbit and Type Size (mm) Ballout Type 64 W30 32 PSRAM 8 x 10 x 1.2 QUAD+ Leaded 64 W18 + 64 W18 32 PSRAM 8 x 10 x 1.4 QUAD+ Leaded 64 W30 + 64 W30 32 PSRAM 8 x 10 x 1.4 QUAD+ Leaded Product Number (1,2,3,4,5) PSRAM used RD38F2040W0ZTQ0 85 ns, RD38F2040W0ZBQ0 No PMODE pin RD38F2240WWYDQ0 (6) 88 ns, RD38F2240WWYDQ1 with PMODE pin RD38F2240WWZDQ0 85 ns, RD38F2240WWZDQ1 No PMODE pin Notes: 1. W18 = Intel(R) Wireless Flash Memory (W18) with 1.8 V I/O; W30 = Intel(R) Wireless Flash Memory (W30) with 3.0 V I/O. 2. B = Bottom Parameter, where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter. 3. T = Top Parameter where Flash Die #1, F1-CE# = Top Parameter and Flash Die #2, F2-CE# = Bottom Parameter. 4. D = Dual Parameter where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top Parameter. 5. Parts ending with "QE" are 90 nm Flash devices. 6. RD38F2240WWYDQ0 = Engineering Samples; RD38F2240WWYDQ1 = Production Datasheet Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 18-Oct-2005 53 Intel(R) Wireless Flash Memory (W18/W30 SCSP) 18-Oct-2005 54 Intel(R) Wireless Flash Memory (W18/W30 SCSP) Order Number: 251407, Revision: 010 Datasheet