PF38F2030W0YTQE - Micron Technology, Inc.

Order Number: 251407, Re vision: 010

18-Oct-2005

Intel® Wireless Flash Memory

(W18/W30 SCSP)

32WQ and 64WQ Family with Asynchronous RAM

Datas h eet

Product Features

The Intel® Wirele ss Fl as h Memor y (W 18 / W30 SCSP) fami ly offe rs va r io u s fla sh pl us st a tic

RAM combinations in a common package footprint . The flas h m emo ry features 1.8 V low-

power opera tions with fle xible, multi-partition, dua l-ope ration Re a d-While-Write / Read-While-

Era se, asynchronous, an d synchronous rea ds. This SCSP device integrates up to t wo flash die,

one PSRAM die, and one SRAM die in a lo w- profile package comp atible with other SCS P

families wi th QUAD+ ballout.

■Device Arch itecture

—Flash Den sity: 32-Mbit , 64-Mbit

—Asyn c PSRAM Dens ity: 8-, 16-, 32 -

Mbit; Async SRAM Density: 4-, 8-, 16-

Mbit

—Top, Bottom or Dual flash parameter

configuration

■Device Voltage

—Flash VCC = 1.8 V; Fla s h VCCQ = 1. 8 V

or 3.0 V

—RAM VCC = 3.0 V; RAM VCCQ = 1.8 V

or 3.0 V

■Device Packag ing

—88 balls (8 x 10 active ball matrix);

Area: 8x10 mm; Height: 1.2 mm to 1.4

■PSRAM Performance

—70 ns initi al acces s, 25 ns async page

reads at 1.8 V I/O

—70 ns initi al access async PSRAM at

1.8V I/O

—88 ns initi al acces s, 30 ns async page

reads at 1.8 V I/O

—85 ns initi al acces s, 35 ns async page

reads at 3.0 V I/O

—70 ns initi al acces s, 25 ns async page

reads at 3.0 V I/O

■SRAM Performance

—70 ns initi al access at 1.8 V or 3.0 V I/O

■Flash Perfor man ce

—65 ns initi al access at 1.8 V I/O

—70 ns initi al access at 3.0 V I/O

—25 ns as ync page a t 1.8 V or 3.0 V I/O

—14 ns sync reads (t CHQV) at 1. 8 V I/O

—20 ns sync reads (t CHQV) at 3. 0 V I/O

—Enhanced Factory Programming:

3.10 µs/Word (Typ)

■Flash Archi tecture

—Read-While-Write/Erase

—Asymm e trical b l oc king str ucture

—4-KWord parameter blocks (Top or

Bott om); 32-KWord main blocks

—4-Mbit partition size

—128-bit On e -Time Pr ogrammable (OTP )

Protection Register

—Zero-latency block lockin g

—Abso lute wri te prote ction wit h block

lock using F-VPP and F-WP#

■Fl ash Software

—Intel® Flash Data Int egr ator (FDI) and

Common Flash Interface (CFI)

■Quality and Reliability

—Exten ded Temperat ur e: –25 °C to +85 °C

—Minimum 100K flash block erase cycle

—90 nm ETOX™ IX flash technology

—130 nm ETOX™ VIII flash technology

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

2 Order Number: 25140 7, Re vision: 010

Lega l Lin es an d Dis c laimers

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Contact your local Intel sale s office or your distribu tor to obtain the latest specifi cation s and befo re placi ng your product order.

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*Other names and br ands m ay be claimed as the proper ty of others.

32WQ and 64WQ Family—Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 3

1.0 Introduction....................................................................................................................................6

1.1 Nomenclature .......................................................................................................................6

1.2 Conventions..........................................................................................................................6

2.0 Fu n ctiona l Overview .....................................................................................................................8

2.1 Block Di a gram ........................... .............. ............. ............. ....... ... .............. ... ............. ...........8

2.2 Flash Memory Map and Partitioning.....................................................................................9

3.0 Package Information...................................................................................................................11

4.0 Ballout and Signal Descri ption ..................................................................................................13

4.1 Signal Ballout......................................................................................................................13

4.2 Signal Descriptions.............................................................................................................14

5.0 Maximum Ratings and Operat ing Conditions...........................................................................16

5.1 Absolute Maximum Ratings................................................................................................16

5.2 Operati n g Cond iti o n s................. ....... ... .............. ... .................... ....... ... ............. .... ...............17

5.3 Capacitance........................................................................................................................17

6.0 Electrical Specifications.............................................................................................................18

6.1 DC Characteristics..............................................................................................................18

7.0 AC Characteristics ......................................................................................................................21

7.1 Flash AC Char ac te ris ti cs..... ... ........................... ...... .... ............. ... .............. ... ......................21

7.2 SRAM AC Charac te ristics........................... ............. ....... ... .................... ....... ... .............. ... ..2 1

7.3 PSRAM AC Characteristics................................................................................................24

7.4 Device AC Test Conditions.................................................................................................29

8.0 Flash Power Cons ump tion .........................................................................................................30

9.0 Device Operat ion.........................................................................................................................31

9.1 Bus Operations...................................................................................................................31

9.2 Flash Co mmand De fin i tio ns.... ........................... ............. ............. ....... ... .............. ... ............34

10.0 Flash Read Operat ions ...............................................................................................................35

11.0 Flas h Program Operations .........................................................................................................36

12. 0 F lash E r ase Ope r ati o n s ..............................................................................................................37

13.0 Flash Secur ity Modes..................................................................................................................38

14.0 Flash Re ad Configuration Register ...........................................................................................39

15. 0 SRAM Operat ions........................................................................................................................40

15.1 Powe r-up Seque nc e and Initi a li za tio n ..... ...... .... ............. ... .............. ... ............. .... ............. ..40

15.2 Data Retention Mode..........................................................................................................40

16.0 PSRAM Operatio ns ......................................................................................................................42

16.1 Power-Up Sequence and Initialization................................................................................42

16.1.1 16Mbit PSRAM Power-Up Sequence (Non-Page Mode).......................................42

16.2 Standby Mode/ Deep Power-Down Mode ..........................................................................43

16.3 PSRAM Special Read and Write Constraints.....................................................................43

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )—32WQ an d 64WQ F am ily

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

4 Order Number: 25140 7, Re vision: 010

Appendi x A W r it e State Mach ine ........................................................................................................45

Appendix B C ommon Flash Interface .................................................................................................46

Appendix C Flas h Flowcha rts .............................................................................................................47

Appendix D A dditi onal Inform at io n ....................................................................................................48

Appendix E Ordering Infor mation.......................................................................................................49

32WQ and 64WQ Family—Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 5

Revision History

Date Revision Description

June 2003 -001 Initial release.

September

2003 -002 Changed PS RA M Read values.

Added new Transient E quivalent Testing Load Circuit figure.

General text edits.

May 2004 -006 Reformatted the datasheet and moved sections around according to the new layout.

August 2004 -007

Added 90 nm product information.

Added line items to Table 21 “32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash

Only)” on page 50.

Added DC and AC specs for the new line items and edits to related sections.

January 2005 -008 Added line items to Table 21 “32W Q and 64WQ W18/W30 SCSP Ordering Information (Flash

Only)” on page 50

Added 32WQ product information.

June 2005 -009 Added line items to Table 21 “32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash

Only)” on page 50

October 2005 - 010 Removed Power-up sequence from Section 16; Added 70ns PSRAM (non-page mode)

specification Updated Ordering Information

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

6 Order Number: 25140 7, Re vision: 010

1.0 Introduction

This document contains inf ormation perta ining t o the products in the Intel® Wireless Flash

Memory (W18/W30 SCS P) family with a synchronous RAM. The W18/W30 SCSP 32WQ a nd

64WQ f amilie s of fe r a wide va rie ty of s tacked com binati ons that in clud e sing le flas h di e, two flas h

die , flash + PS RAM, and fla sh + SRAM options.This document provides inform a tion where t his

SC SP fa mi l y di ffers fr om the Int el® Wirel e ss Flash Memory ( W18/W30) di screte device.

Refer to the dis crete datasheets I ntel® Wireless F lash Mem ory (W18 ) Datasheet (order number

290701) an d Intel® Wireless Flash Memory (W30) Datasheet (o rder number 290702) for flash

product det a ils not included in this SCS P datashee t.

1.1 Nomenclature

0x Hexadecim al prefix

0b Binary prefix

Byte 8 bits

CFI Comm on Flash Interface

CUI Command User Interface

DU Don’t Use

ETOX EPROM Tunnel Oxide

FDI Flash Data Integra tor (Intel® softwar e solution)

k (noun) 1 thousand

Kb 1024 bits

KB 1024 bytes

Kword 1024 word s

M (noun) 1 million

Mb 1,048,576 bits

MB 1,048,576 bytes

OTP One-Time Programmable

PLR Protectio n Lock Register

PR Prot ec tion Regi ster

PRD Protection Register Data

RCR Read Configuration Register

RFU Reserved for Future Us e

SCSP Sta c ked Chip S cale Package

SR Status Register

SRD Status Regi ster Data

Wo rd 16 bits

WSM Write State Machine

1.2 Conventions

Group Membership Brackets: Square br a c kets a re used to de signa te grou p members hip or to

define a group of signals with a similar function, such as A[21:1] and SR[4,1].

VCC vs. VCC: When referring to a signal or p ackage-connection name, the notation used is VCC ,

etc. When r eferring to a timing or electri cal level, the notation used is su bs cripted such as

VCC, etc.

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 7

Device: This term is used interch a ngeably thr oughout this document to denote either a particular

die, or the combination of multiple die within a single pa ckage.

F[ 3:1]-CE#, F[2:1]-OE#: This is the meth od used to refe r to more than one chip-enable or output

enable at th e same time. When each is referred to indivi dually, the reference will be F1-

CE# and F1-OE# (for die #1), a nd F2-CE # and F2 -OE# (for die #2).

F- VCC, P-VCC or S-VCC: When refer e ncing flash memor y signals or timings , the notation used

is F- VC C o r F- V CC, respectiv ely. When t he reference is to PSRAM sig nals or tim ings , the

notation is prefixed with “P-” (e.g., P-VCC, P-VCC). Wh e n re fe r e nc i ng SR AM sig n al s or

timin gs, the not ation is pr efixed with “S -” (e.g., S-VCC or S-VCC). P-VCC and S-VCC

are RFU for stac ked combination s that do not include PSRAM or SRAM.

R-O E#, R-LB #, R- UB# , R -WE#: Thes e are used to identi fy RAM OE#, LB#, UB#, WE# signals,

and are usually shared between 2 or mor e RAM die. R-OE #, R-LB #, R-UB# and R-WE

are RFU for stac ked combination s that do not include PSRAM or SRAM.

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

8 Order Number: 25140 7, Re vision: 010

2.0 Functional Overview

This sectio n pr ovides an overview of the features and capabilities of the Intel® Wirele ss F las h

Memory (W18/W30 SCS P) family with a synchronous RAM devic e .

The W1 8/W30 SCSP de vice provides flash + RAM die combinations. Products range from single

flash d ie, two flash die, flash + PSRAM, or flash + SRAM. You can choose a W18 SCSP device or

a W30 SCSP device with S RAM or PSRAM offered with the same package fo otprint and signal

ballout.

Tab le 21 on page 50 lists poss ible pr oduct combinat ions for the 32-Mbit and 64-Mbit W18/W 30

SC SP fa mil y.

2.1 Block Diagram

Figure 1 s how s all internal package con nections for the SCSP family with multiple die. See Table

21 for valid combinations of flash and RAM die. Unused co nnections on com binations with le ss

than three die ar e rese rved and should not be used.

Plea se cont a c t your loc a l Intel representative for details regarding a ny reserved or RFU pins.

Figu re 1. Bl o ck Diagram

Fl ash Di e #2

32- or 64-Mbi t W18/W30

RAM Die

4-, 8-, 16-Mbit SRAM

16- or 32-Mbit PSRAM

Fl ash Di e #1

32- or 64-Mbi t W18/W30

F2-VCC

S-VCC/P-VCC

F2-CE#

F2-OE#

R-WE#

R-UB#

R-LB#

S-CS2

VSS

F1-VCC

F1-CE#

F1-OE#

A[MAX:0]

P-CS#/S-CS1#

R-OE#

A[MAX:0] D[15:0]

CLK

F-WP#

ADV#

F-RST#

F-WE#

VCCQ

F-VPP

WAIT

P-MODE

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 9

2.2 Flash Memory Map and Partitioning

Cons ult the late st Intel® Wireless Flash Memory (W18) Datasheet (orde r number 290701) and th e

Intel® Wi reless Flash Memory (W30) Datasheet (order number 290702), for indivi dual flash die

mem ory map and partitioning inform a tion.

Table 1 and Table 2 show memory map and partitioning information for dual-flash mem ory die

configu ration s. Flas h Die #1 (with F1-CE# as its Chip Select) is conf igured as a bottom boot while

Flash Die #2 ( with F2-CE # as its Ch ip Select) is configured as top boot.

Table 1. 64-Mbit Flash + 32-Mbit Flash Die W18/W30 SCSP Memory Map and Parti tioning

Partitioning Block Size

(KW) Block # Address Range

Flash Die #2

(32-Mbit)

Parameter

Partition Partition 0 4 63-70 1F8000-1FFFFF

32 56-62 1C0000-1F7FFF

Main

Partitions

Partition 1 32 48-55 180000-1BFFFF

Partition 2 32 40-47 140000-17FFFF

Partition 3 32 32-39 100000-13FFFF

Partitions 4- 7 32 0-31 000000-0FFFFF

Flash Die #1

(64-Mbit)

Main

Partitions

Partitions 8-15 32 71-134 200000-3FFFFF

Partitions 4- 7 32 39-70 100000-1FFFFF

Partition 3 32 31-38 0C0000-0FFFFF

Partition 2 32 23-30 080000-0BFFFF

Partition 1 32 15-22 040000-07FFFF

Parameter

Partition Partition 0 32 8-14 008000-03FFFF

4 0-7 000000-007FFF

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

10 Order Number: 25140 7, Revis i on: 01 0

Table 2. 64-Mbit Dual-Flash Die W18/W30 SCSP Memory Map and Partitioning

Partitioning Block Size

(KW) Block # Address Range

Top

Parameter

Parame ter

Partition Partition 0 4 127-134 3F8000-3FFFFF

32 120-126 3C0000-3F7FFF

Main

Partitions

Partition 1 32 112-119 380000-3BF FFF

Partition 2 32 104-111 340000-37FFFF

Partition 3 32 96-103 300000-33FFFF

Partitions 4-7 32 64-95 200000-2FFFFF

Partitions 8-15 32 0-63 000000-1FFFFF

Bottom

Parameter

Main

Partitions

Partitions 8-15 32 71-134 200000-3FFFFF

Partitions 4-7 32 39-70 100000-1FFFFF

Partition 3 32 31-38 0C0000-0FFFFF

Partition 2 32 23-30 080000-0BFFFF

Partition 1 32 15-22 040000-07FFFF

Parame ter

Partition Partition 0 32 8-14 008000-03FFFF

4 0-7 000000-007FFF

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 11

3.0 Package Information

The following packages are offered with the 32WQ and 64WQ Family:

• Figure 2, “Mechanical Specific a t ions for 1- or 2-Die SCSP Device (8x 10x1.2 mm)”

• Figur e 3, “Mechan ical Specifications for Triple-Die SCSP Device (8x10x1.4 mm)”

Figure 2. Mechanical Specifications for 1- or 2-Die SCSP Device (8x10x1.2 mm)

Millimeters Inches

Dimensions Symbol Min Nom Max Notes Min Nom M

P ackage Hei ght A 1.200 0.04

B al l H eight A1 0.200 0.00 79

Package Body Thickness A2 0.860 0.0339

B al l (Lead) Width b 0.325 0.37 5 0.42 5 0.01 28 0.014 8 0.01

Package Body Length D 9.900 10.00 0 10.100 0.38 98 0.393 7 0.39

Package Body Width E 7.900 8.000 8.100 0.3110 0.315 0 0.31

Pitch e 0. 8 00 0 .031 5

Ball (Lead) Coun t N 88 88

S eating Pl ane C opl anar i ty Y 0 . 100 0 . 00

C orner to Ball A1 Distance Along E S1 1.100 1. 200 1.300 0.0433 0.047 2 0.05

C orner to Ball A1 Distance Along D S2 0.500 0. 600 0.700 0.0197 0.023 6 0.02

T op View - Ball

Down Bot t om View - Ball Up

Drawin g not to scale.

2345678

12345678

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

12 Order Number: 25140 7, Revis i on: 01 0

Fig ur e 3. Me chanic al Specification s fo r Tr ipl e-D ie SCSP Device (8x10x1 .4 mm)

Millimeters Inches

Dimensions Symbol Min Nom Max Notes Min Nom Max

Package Height A 1.400 0.0551

Ball Height A1 0.200 0.0079

Pac kage Body T hickne ss A2 1. 07 0 0. 0421

Ball (L ead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167

Pac kage Body Lengt h D 9.900 10.0 00 10. 100 0. 3898 0.3937 0.3976

Pac kage Body Width E 7. 90 0 8.0 00 8.10 0 0.3110 0.3150 0.3189

Pitch e 0.800 0.0315

Ball ( Lea d) Count N 88 88

Seating Plane Coplanarity Y 0.100 0.0039

Corner to Ball A1 D istance Along E S1 1.100 1 .200 1. 300 0. 0433 0.0472 0.0512

Corner to Ball A1 D istance Along D S2 0.500 0 .600 0. 700 0. 0197 0.0236 0.0276

T op View - Ball D ow n Bot t om Vie w - Ball U p

Drawing not to scale.

12345678

Index

Mark 12345678

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 13

4.0 Ballo ut and Signal Description

4.1 Signal Ballout

Figure 4 sh ows the 32WQ a nd 64WQ W18 /W30 SCSP family 88-ball (8x10 act ive ball matrix)

device.

Fig u re 4. 88 -Ball (8x1 0 Active Ball Matri x) QUAD+ Ballou t

12345678

ADU DU DU DU A

BA4 A18 A19 VSS F1-VCC F2-VCC A21 A11 B

CA5 R-LB# A23 VSS S-CS2 CLK A22 A12 C

DA3 A17 A24 F-VPP R-WE# P1-CS# A9 A13 D

EA2 A7 A25 F-WP# ADV# A20 A10 A15 E

FA1 A6 R-UB# F-RST# F-WE# A8 A14 A16 F

GA0 DQ8 DQ2 DQ10 DQ5 DQ13 WAIT F2-CE# G

HR-OE# DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 F2-OE# H

JS-CS1# F1-OE# DQ9 DQ11 DQ4 DQ6 DQ15 VCCQ J

KF1-CE# P2-CS# F3-CE# S-VCC P-VCC F2-VCC VCCQ P-Mode/

P-CRE K

LVSS VSS VCCQ F1-VCC VSS VSS VSS VSS L

MDU DU DU DU M

12345678

Top View - Ball Side Down

SRAM/PSRAM Specifi c

De-P opu lat ed Bal ls

Glob al Sign als

Legend:

Do Not Use

Flash Sp ec if ic

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

14 Order Number: 25140 7, Revis i on: 01 0

4.2 S ig nal Descrip tions

Table 3 desc ribes a c tive signals used on the 32WQ and 64WQ W18/W30 SCS P family.

Table 3. Signal Desc ri ptions (She et 1 of 2)

Symbol Ty pe Name and Function

A[21:0] Input

ADDRESS INPUTS: Inputs for all die addresses during read and write operations. Addresses are

internally latched during write operations.

• 4-Mbit: A[17:0]

• 8-Mbit: A[18:0]

• 16-Mbit: A[19:0]

• 32-Mbit: A[20:0]

• 64-Mbit: A[21:0]

A0 is the lowest-order w o rd address.

A[25:22] denote high-order addresses reserved for future device densities

D[15:0] Input/

Output

DATA INPUTS/OUTPUTS: Inputs data and commands during write cycles; outputs data during read

cycles. Data signals float when the device or its outputs are deselected. Data are internally latched

during writes.

CLK Input

FLASH CLOCK: CLK synchronizes the selected flash die to the memory bus frequency in

synchronous-read mode. During synchronous read operations, the initial address is latched on the

rising edge of ADV#, or the rising/ falling edge of CLK when ADV # is low, whichever occurs first.

CLK is only used in synchronous-read mode. Refer to the flash discrete product datasheet for

information on how to use this signal in asynchronous-read mode.

ADV# Input

FLASH ADDRE SS VALID: Low-true; During synchronous read operations, the initial address is

latched on the rising edge of ADV#, or the rising/ falling edge of CLK when ADV# is low, whichever

occurs first.

Refer to the flash discrete product datasheet for information on how to use this signal in

asynchronous -read mode.

WAIT Output

FLASH WAIT: When asserted, WAIT indicates invalid data from the selected fl ash die on D[15:0].

WAIT is High-Z whenever the flash die is deselected (CE# = VIL). WAIT is not gated by OE#.

WAIT is only used in synchronous array-read mode. Refer to the flash discrete product datasheet for

information on how to use this signal in asynchronous-read mode.

F[3:1]-CE# Input

FLASH CHIP ENABLE: Low-true ; CE#- low select s the associated flash memory die. When asserted,

flash internal cont rol logic, input buf fers, decoders, and sense ampl ifiers are active. When deass erted,

the associ ated fla sh die is deselect ed; power is reduced to st andby levels, data and W A IT output s ar e

placed in High-Z.

F1-CE# selects flash die #1; F2-CE# selects flash die #2 and is RFU on combinations with only one

flash die. F3-CE# selects flash die #3 and is RFU on SCSP combinations with only one or two flash

die.

S-CS1#

S-CS2 Input

SRAM CHIP SELECTS: When both SR AM chip selects are asserted, SRAM internal control logic,

input buffers, decoders, and sense amplifiers are active. When either/both SRAM chip selects are

deasserted (S-CS1# = VIH and/or S-CS2 = VIL), the SRAM is deselected and its power is reduced to

standby levels.

S-CS1# and S-CS2 are only available on SCSP combinations with SRAM die.

P[2:1]-CS# Input

PSRAM CHIP SELECTS: Low-true; When asserted, PSRAM internal control logic, input buffers,

decoders, and sense amplifi ers are active. When deasserted, the PSRAM is dese lected and its power

is reduced to standby levels.

P1-CS# selects PSRAM die #1 and is available only on SCSP combinations with PSRAM die. This

ball is RFU on SCSP combinations w ithout PSRAM. P2-CS# selects PSRAM die #2 and is available

only on SCSP combinations with two PSRAM die. This ball is RFU on SCSP combinations without

PSRAM or w ith a single PSRAM.

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 15

F[2:1]-OE# Input

FLASH OUTPUT ENAB LE: Low-true; OE#-low enables the flash output buffers. OE#-high disables

the flash output buffers, and places the flash outputs in High-Z.

F1-OE# control s the outputs of flash die #1; F2-OE# controls the output s of fl ash d ie #2 and #3, an d is

available only on SCSP combinations with two or three flash die and is RFU on SCSP combinations

with only one flash die.

R-OE# Input RAM OUT PUT ENABLE: Low-true; R-OE#-low enables the RAM output buffers. R-OE#-high

disables the RAM output buffers, and places the RAM outputs in High-Z.

R-OE# is only available on SCSP combinations with RAM die.

R-UB#

R-LB# Input RAM UPPER/ LOWER BYTE ENABLES: Low-true; D uring RAM reads, R-UB#-lo w enables the RAM

high-order bytes on D[15:8], and R-LB#-low enables the RAM low-order bytes on D[7:0].

R-UB# and R-LB# are only available on SCSP combinations with either SRAM die or PSRAM die.

F-WE# Input FLASH W RITE ENABLE: Low-true; WE# controls writes to the selected flash die. Address and data

are latched on the rising edge of WE#.

R-WE# Input RAM WRITE ENABLE: Low-true; R-WE# controls writes to the RAM die.

R-WE# is only available on SCSP combinations with RAM die.

F-WP# Input

FLASH WRITE PROTECT: Low-true; WP# enables/disables the lock-down protection mechanism of

the flash die. WP#-low enables the lock-down mechanism- locked down blocks cannot be unlocked

with sof twa re com mands. WP#-hi gh di sables the loc k- down mec hanism , al lowi ng l ocked dow n bl ocks

to be unlocked with software commands.

F-RST# Input FLASH RESET: Low-true; RST#-low initializes flash internal circuitry and disables flash operations.

RST#-high enables flash operation. Exit from reset places the flash in asynchronous read array

mode.

F-VPP

F-VPEN Power

FLASH PROGRAM/ ERASE POWER: A valid F-VPP voltage on this ball enables fl ash program/erase

operations. Flash memory array contents cannot be altered when F-VPP(VPEN) < VPPLK(VPENLK).

Erase/ program operations at invalid F-VPP(VPEN) voltages should not be attempted. Refer to the

flash discrete product datasheet for additional details.

F-VPEN (Erase/Program/Block Lock Enables) is not available for W18/W30 products.

P-MODE Input

PSRAM MODE: Low-true; P-MODE is used to enter/exit low power mode.

Low power mode is not applicable to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1,

38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W 0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0,

38F1030W0YTQE, 38F1030W0YBQE.

P-Mode is only available on SCSP combinations with PSRAM die.

F[2:1]-VCC Power

FLASH LOGIC Power: F1-VCC supplies power to the core logic of flash die #1; F2-VCC supplies

power to the core logic of flash die #2 and #3. Write operations are inhibited when F-VCC < VLKO.

Device operations at invalid F-VCC voltages should not be attempted.

F2-VCC is only available on SCSP combinations with two or three flash die, and is RFU on SCSP

combinations with only one flash die.

S-VCC Power SRAM Powe r Supply: Supplies power to the SRAM die.

S-VCC is only available on SCSP combinations with SRAM die.

P-VCC Power PSRAM Power Supply: Supplies power to the PSRAM die.

P-VCC is only available on SCSP combinations with PSRAM die.

VCCQ Power FLASH OUTPUT-BUFFER Power: Supplies power for the I/O output buffers.

VSS Power Ground: Connect to ground. Do not float any VSS connection.

RFU — Reserved for F uture Use: Reserve for future device functionality/ enhancements.

DU — Do Not Us e: Do not connect to any other signal, or power supply; must be left floating.

Table 3. Signal Descriptions (Sheet 2 of 2)

Symbol Type Name and Function

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

16 Order Number: 25140 7, Revis i on: 01 0

5.0 Maximum Ratings and Operating Conditions

5.1 Absolute Max imum Ratings

Warning: Stressin g the device beyond the “Absolute Ma ximum Ra tings” may cause pe rmanent damage .

These are stress ratings only.

NOTICE: This document contains information available at the time of its release. The specifications are

subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet

before finalizing a design.

Table 4. Absolute Maximum Ratings

Parameter Min Max Unit Notes

Temperature under Bias Expanded –25 +85 °C 7

Storage Temperatur e –55 +125 °C

Voltage On Any Signal (except F[2:1]-VCC,

VCCQ, F-VPP, S-VCC and P-VCC)

1.8 V I/O –0.2 +2.45 V 1,2,3

3.0 V I/O –0.2 +3.6 V 2,3

F[2:1]-VCC Voltage –0.5 +2.45 V 2,3

VCCQ, S-VCC and P-VCC Voltage 1.8 V I/O –0.2 +2.45 V 1,2,3

3.0 V I/O –0.2 +3.6 V 2,3

F-VPP Voltage –0.2 +14.0 V 2,3,4,5

ISH Output Short Circuit Current – 100 mA 6

Notes:

1. 90 nm is only avail with the 1.8 V I/O.

2. All Specified voltages are relative to VSS. Minimum D C voltage is –0.2 V on input/output signals, –

0.2 V on F[2:1]-VCC and F-VPP signals. For 90 nm devices, during transitions, this level may

overshoot to –1.5 V for periods < 20 ns, during transitions, may overshoot to F-VCC + 1.5 V for

periods < 20 ns.

3. All Specified voltages are relative to VSS. Minimum D C voltage is –0.2 V on input/output signals, –

0.2 V on F[2:1]-VCC and F-VPP signals. For 130 nm devices, during transitions, this level may

overshoot to –2 V for p eriods < 20 ns, during transiti ons, ma y ov ershoot to F- VCC + 2 V for per iods <

20 ns.

4. Maximum DC voltage on F-VP P may overshoot to +14.0 V for periods < 20 ns.

5. F-VPP prog ram volt age is nor ma lly V PPL. The max imum D C v oltage on F-VPP may overshoot to +14

V for periods < 20 ns. F-VPP can be VPPH for 1000 erase cycles on main blocks, 2500 cycles on

parameter blocks.

6. Output shorted for no more than one second. No more than one output shorted at a time.

7. Devices available with -30o C te mperatur e specif icatio ns are: 38F202 0W0ZTQ1, 38F2020W0ZBQ1,

38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W 0ZBQ 2 , 38F1030W0ZTQ0,

38F1030W0ZBQ0, 38F1030W0YTQE, 38F1030W0YBQE,

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 17

5.2 Operating Conditions

Warning: Operation be yond the “Operat i ng Conditions” is not recommended and extended expos ure b e yond

the “Operating Conditions” may affect device reliability.

5.3 Capacitance

Table 5. Operating Conditions

Symbol Parameter

Flash +

Flash Flash +

SRAM Flash +

PSRAM Unit Notes

Min Max Min Max Min Max

TCOperating Temperature –25 +85 –25 +85 –25 +85 °C 2

F-VCC Flash Supply Voltage 1.7 1.95 1.7 1.95 1.7 1.95 V

VCCQ

S-VCC

P-VCC

Flash I/O Voltage

PSRAM and SRAM

Supply Voltage

3.0 V I/O 2.2 3.3 2.2 3.3 2.7 3.1 V

1.8 V I/O 1.7 1.95 1.7 1.95 1.8 1.95 V

VPPL Flash Program Logic Level 0.9 1.95 0.9 1.95 0.9 1.95 V

VPPH Flash Factory Program Voltage 11.4 12.6 11.4 12.6 11.4 12.6 V 1

Note:

1. F-VPP is normally VPPL. F-VPP can be connected to 11.4 V–12.6 V for 1000 cycles on main blocks

for extended temperatures and 2500 cycles on parameter blocks at extended temperature.

2. Devices av ailable wit h -30o C temperature spec ifications ar e: 38F2020W0ZTQ1, 38F2020W0ZBQ1,

38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0,

38F1030W0ZBQ0, 38F1030W0YTQE, 38F1030W0YBQE,.

NOTI CE : Ref er to the 1.8-Volt Intel ® Wir eless Flash Memory Datasheet (order number 29070 1)

and 1.8-Volt Intel® Wir eless Flas h Memory with 3 Volt I /0 D atasheet (order number 290702) for

flash capacitance details. For SCSP products with two flash die, flash capacitances for each

of the flash die need to be considered accordingly.

Table 6. SRA M , PSR AM Capacitance

Symbol Parameter Typ Unit Condition

CIN Input Capacitance 10 pF VIN = 0.0 V, Tc = 25 °C, f = 1 MHz

COUT Output Capacitance 10 pF VOUT = 0.0 V, Tc = 25 °C, f = 1 MHz

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

18 Order Number: 25140 7, Revis i on: 01 0

6.0 Electrical Specifications

6.1 DC Characteristics

SRAM and PSRAM DC ch aracteristics are shown in Table 7 and Table 8. Refer to the Intel®

Wir el ess Flash Memory (W18) Datasheet (order number 290701) and the Intel® Wireless Flash

Memory (W30) Datasheet (order nu mb er 290702) for fl ash DC characteristics .

Table 7. S RAM D C Chara cteristic s

Parameter Description Test Conditions 1.8 V SRAM 3.0 V SRAM Unit

Min Max Min Max

S-VCC Voltage Range 1.7 1.95 2.2 3.3 V

VDR VCC for Data R etention 1.0 – 1.5 – V

ICC Operating Current at

min cycle time IIO = 0 mA

4M–25–45

mA8M–35–50

16M – 40 – 55

ICC2 Operating Current at

max cycle time (1 µs) IIO = 0 mA

4M–4–10

mA8M–6–10

16M – 10 – 15

ISB Standby Current

S-CS1# ≥ S-VCC-0.2V

or S-CS2 ≤ VSS+0.2V

Address/Data toggling at

minimum cycle time

4M–12–15

µA

8M–20–25

16M – 30 – 45

IDR Current in Dat a

Retention mode

1.8 V SRAM:

S-VCC = 1.0 V

3.0 V SRAM:

S-VCC = 1.5 V

4M–6–5

µA

8M–10–12

16M – 18 – 15

VOH Output HIGH Voltage IOH = -100 µAS-VCC -

0.15 –S-VCC -

0.1 –V

VOL Output LOW Voltage IOL = 100 µA,

VCCMIN -0.1 0.2 -0.1 0.1 V

VIH Input HIGH Voltage S-VCC -

0.4 S-VCC+

0.2 S-VCC -

0.4 S-VCC+

0.2 V

VIL Input LOW Voltage -0.2 0.4 -0.2 0.6 V

IOH Output HIGH Curren t – – – – mA

IOL Output LOW Current – – – – mA

*IIL Input Leakage Current -0.2 < VIN < S-VCC + 0.2 V -1 +1 -1 +1 µA

*ILDR Input Leakage Current

in Data Retention

Mode

-0.2 < VIN < S-VCC + 0.2 V

S-VCC = VDR -1 +1 -1 +1 µA

* Input leakage currents include Hi-Z outp ut leakage for bi-dir ectional buffers with tri-state out puts.

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 19

Table 8. PSRAM DC Characteristics

Parameter Description Test Conditions 1.8 V PSRAM 3.0 V PSRAM Unit Note

Min Max Min Max

VCC Voltage Range 1.8 1.95 2.7 3.1 V

ICC Operating Current

at min cycle time IIO = 0 mA

8M – – – 30 mA 2

16M – 30 – 35

16M – 20 – – mA 3

32M – 35 – 45 mA 2

ICC2 Operating Current

at max cycle time

(1 µs) IIO = 0 mA

8M – – – 5

mA 216M – 5 – 7

32M – – – 7

ISB Standby Current

P-CS# ≥ P-VCC-

0.2V.

All inputs stable

(either high or

low)

8M – – – 80

µA2, 4

16M – 100 – 100

P-CS# ≥ P-VCC-

0.2V or

P-Mode ≥ P-VCC-

0.2V

Address/Data

toggling at

minimum cycle

time

16M – – – 85

µA2, 5

32M – 100 – 100

Isbd Deep Power-

Down P-Mode ≤ 0.2 V 16M – – – 10 µA2, 4

32M – 30 – 10

VOH Output HIGH

Voltage

IOH = -0.5 mA 0.8P -

VCC –2.4–V4

IOH = -0.1 mA 1.4 – P-VCC -

0.3 –V5

VOL Output LOW

Voltage IOL = 1 mA, – 0.2P -

VCC –0.4V4

IOL = 0.1 mA, VCCMin -0.1 0.2 -0.1 0.3 V 5

VIH Input HIGH

Voltage

0.8P -

VCC P-VCC +

0.3 P-VCC -

0.3 P-VCC +

0.2 V4

P-VCC -

0.3 P-VCC +

0.2 P-VCC-

0.4 P-VCC +

0.2 V5

VIL Input LOW

Voltage –0.3 0.2P -

VCC -0.2 0.5 V 4

–0.2 0.4 -0.2 0.6 V 5

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

20 Order Number: 25140 7, Revis i on: 01 0

IIL Input Leakage

Current -0.2 < VIN < P-VCC + 0.2 V -1 +1 -1 +1 µA1, 2

IOL Output Leakage

Current -0.2 < VIN < P-VCC + 0.2 V

P-VCC = VDR -1 +1 -1 +1 µA1, 2

Notes:

1. Input Leakage currents include Hi-Z output leakage for bi-directional buffers w ith tri-state outputs.

2. All currents are in RMS unless noted otherwise.

3. Applicable only to parts 38F1030W0YxQF & 38F2030W0YxQF

4. Applicable to parts with P-Mode pin (38F2030W0ZxQ1, 38F2040W0YxQ0, 28F2240WWYxQ0).

5. Applicable to No-P-Mode (38F1030W0YxQE, 38F1030W0YxQ2, 38F1030W0ZxQ0, 38F2030W0YxQ1,

38F2030W0YxQE, 38F2030W0YxQ 2, 38F2030W0YxQF, 38F2030W0ZxQ2, 38F2040W0ZxQ0)

Table 8. P SRAM DC Charac teristics

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 21

7.0 AC Characterist ics

7.1 Flash AC Characteristics

Refer to the Intel® Wir eless Flash Memory (W18) Datasheet (order number 290701) a nd Intel®

Wireless Flash Memory (W30) Datasheet (orde r numb e r 29 070 2)

7.2 SRAM AC Characteristics

Table 9. S RAM AC Char acteristics — Read O p eration s

#Symbol

1Parameter Min Max Unit Notes

R1 tRC Read Cycle Time 70 – ns 1

R2 tAA Address to Output Delay – 70 ns 1

R3 tCO1 S -CS1# to Output Delay – 70 ns 1

R3 tCO2 S -CS2 to Output Delay – 70 ns 1

R4 tOE R-OE# to Output Delay – 35 ns 1

R5 tBA R-UB#, R-LB# to Output Delay – 70 ns 1

R6 tLZ S-CS1# or S-CS2 to Output in Low-Z 5 – ns 1,3,4

R7 tOLZ R-OE# to Output in Low-Z 0 – ns 1,4

R8 tHZ S-CS1# or S-CS2 to Output in High-Z 0 25 ns 1,2,3,4

R9 tOHZ R-OE# to Output in High-Z 0 25 ns 1,2,4

R10 tOH Output Hold (from Address, S-CS1#, S-CS2 or R-OE# Change,

whichever occurs first) 0–ns 1

R11 tBLZ R-UB#, R-LB# to Output in Low-Z 0 – ns 1,4

R12 tBHZ R-UB#, R-LB# to Output in High-Z 0 25 ns 1,4

Note:

1. See Figure 5, “AC Waveform SRAM Read Operations” .

2. Timings of tHZ and tOHZ are defined as the time at wh ich the outputs achieve the open circuit conditions and are not

referenced to output voltage levels.

3. At any given temperature and voltage condition, tHZ ( Max) is les s than tLZ (M ax) both for a given device and from devic e

to device interconnection.

4. Samp led but not 100% tested.

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

22 Order Number: 25140 7, Revis i on: 01 0

Fig ur e 5. AC Wavefo rm SRAM Read O peratio n s

Table 10. SRAM AC Characteristics — Write Operations

# Symbol1Parameter Min Max Unit Notes

W1 tWC Write Cycle Tim e 70 – ns 1

W2 tAS Address S etup to R-WE# (S-CS1#) and R-UB#/R-LB# Low 0 – ns 1,4

W3 tWP R-WE# (S-CS1#) Pulse Width 55 – ns 1,2,3

W4 tDW Data to Write Time Overlap 30 – ns 1

W5 tAW Address S etup to R-WE# (S-CS1#) High 60 – ns 1

W6 tCW S-CS1# (R-WE#) Setup to R-WE# (S-CS1#) H igh 60 – ns 1

W7 tDH Data Hold from R-WE# (S-CS1#) High 0 – ns 1

W8 tWR Write Recovery 0 – ns 1,5

W9 tBW R-UB#, R-LB# Setup to R-WE# (S-CS1#) High 60 – ns 1

Notes:

1. See Figure 6, “AC Waveform SRAM Wr ite Operations” .

2. A write occurs during the overlap (tWP) of low S-CS1# and low R-WE#. A write begins when S-CS1# goes low and R-

WE# goes low with asserting R-UB# and R-LB# for single byte operation or simultaneously asserting R-UB#R-LB# and

R-LB# for double byte operation. A write ends at the earliest high transition of S-CS1# and R-WE#.

3. tWP is measured from S-CS1# low to the end of a write.

4. tAS is measured from the address valid to the beginning of a write.

5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as S-CS1# or R-WE#

goes high.

Address S t able

Valid Data

R12

R11R5

R10

R9R7

R8R3

R1R1

Standby

ADDRESSES

S-CS1#

S-CS2

R-OE#

R-WE#

DATA

R-UB#, R-LB#

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 23

Fig u re 6. AC Waveform SRA M Write Operatio ns

Address Stable

Data In

W9W9W2

W7W4

W5 W3W3

W8W6

W1W1

Standby

ADDRESSES

S-CS1#

S-CS2

R-OE#

R-WE#

DATA

R-UB#, R-LB#

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

24 Order Number: 25140 7, Revis i on: 01 0

7.3 PSRAM AC Characteristics

Table 11. PSRAM AC Characteristics (85ns or 88ns Initial Access) — Read Operations

# Symbol Parameter51.8 V 3.0 V Unit Notes

Min Max Min Max

R1 tRC Read Cycle Time 88 4,000 85 4,000 ns

R2 tAA Address to Output Delay – 88 – 85 ns

R3 tCO P-CS# to Output Delay – 88 – 85 ns

R4 tOE R-OE# to Output Delay – 65 – 40 n s

R5 tBA R-UB#, R-LB# to Output Delay – 88 – 85 ns

R6 tLZ P-CS# to Output in Low-Z 10 – 10 – ns 1,2

R7 tOLZ R-OE# to Output in Low-Z 5 – 0 – ns 2

R8 tHZ P-CS# to Output in High-Z – 25 0 25 ns 1,2,3

R9 tOHZ R-OE# to Output in High-Z – 25 0 25 n s 2,3

R10 tOH Output Hold (from Address, P-CS# or R-

OE# change, whichever occurs first) 5–0–ns

R11 tBLZ R-UB#, R-LB# to Output in Low-Z 5 – 0 – ns 2

R12 tBHZ R-UB#, R-LB# to Output in High-Z – 25 0 25 ns 2

PR1 tPC Page Cycle Time 30 – 40 – ns 4

PR2 tPA Page Access Time – 30 – 35 ns 4

Note:

1. At any given tempe rature and volt age condi tion, t HZ (Max) is less than t LZ (Max) both for a given device and from devi ce

to device interconnection.

2. Sampled but not 100% tested.

3. Timings of tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not

referenced to output voltage levels.

4. 4-Word Page read only available for 32-Mbit PSRAM. No page mode feature for 16-Mbit PSRAM.

5. Applicable to parts with 85ns or 88ns initial access time: (38F2030W0ZxQ1, 38F2040W0YxQ0, 38F2040W0ZxQ0,

28F2240WWYxQ0).

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 25

Table 12. PSRA M AC Characteristics (70n s Initial Acce ss)— Read Op erat ions

#Symbol

1Parameter71.8 V 3.0 V Unit Notes

Min Max Min Max

R1 tRC Read Cycle Time 70 15000 70 15000 ns

70 8000 – – 2

R2 tAA Address to Output Delay – 70 – 70 ns

R3 tCO P-CS# to Output Delay – 70 – 7 0 ns

R4 tOE R-OE# to Output Delay – 45 – 45 ns

R5 tBA R-UB#, R-LB# to Output Delay – 70 – 70 ns

R6 tLZ P-CS# to Output in Low-Z 5 – 5 – ns 3

R7 tOLZ R-OE# to Output in Low-Z 0 – 0 – ns

R8 tHZ P-CS# to Output in High-Z 0 25 0 2 5 n s 3, 4

R9 tOHZ R-OE# to Output in High-Z 0 25 0 25 ns 4

R10 tOH Ou tput Hold (from Address, P-CS# or R-

OE# change, whichever occurs first) 0–0–ns

R11 tBLZ R-UB#, R-LB# to Output in Low-Z 0 – 0 – ns

R12 tBHZ R-UB#, R-LB# to Output in High-Z 0 25 0 25 ns

PR1 tPC Page Cycle Time 25 – 25 – ns 5

PR2 tPA Page A ccess Time – 25 – 25 ns 5

tCEL CE# low-time restriction – 8,000 ns 4 ns 6

Note:

1. See Figure 7, “AC Waveform of PSRAM Read Operations” on page 27 and Figure 8, “AC Waveform of P SRAM 4-Word

Page Read Operation” on page 27

2. Spec’s only applicable to parts 38F1030W0YxQF & 38F2030W0YxQF

3. At any given temperature and volt age condi tion, tHZ (M ax) is less than tLZ (Max) both for a given device and from devic e

to device interconnection.

4. Timings of tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not

referenced to output voltage levels.

5. 4-Word Page read only available for 16-Mbit PSR AM. No page mode feature for 8-Mbit PSRAM. Parts

38F1030W0YxQF & 38F2030W0YxQF do not support page mode, so this spec will not apply to them

6. CE# must go high and be maintained high for a minimum of 10ns at least once every 8,000ns

7. Applicable to 70ns initial access P-SRAM’s (38F1030W0YxQE, 38F1030W0YxQ2, 38F1030W0ZxQ0,

38F2030W0YxQ1, 38F2030W0YxQE, 38F2030W0YxQ2, 38F2030W0YxQF, 38F2030W0ZxQ2)

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

26 Order Number: 25140 7, Revis i on: 01 0

Table 13. PS RAM AC Char acte ristics—Write Operation s

#Symbol

1Parameter71.8 V 3.0 V Unit Notes

Min Max Min Max

W1 tWC Write Cycle Time 70 8000 70 – ns

W2 tAS Address Setup to R-WE#

(P-CS#) and R-UB#, R-LB# going low 0– 0 –ns4

W3 tWP R-WE#(P-CS#) Pulse Width 55 – 55 – ns 2,3

W4 tDW Data to Write Time Overlap 35 – 35 – ns

W5 tAW Address Setup to R-WE#

(P-CS# ) Going High 60 – 60 – ns

W6 tCW P-CS# (R-WE#) Setup to R-WE# (P-CS#)

Going High 60 – 60 – ns

W7 tDH Data Hold from R-WE#

(P-CS# ) High 0– 0 –ns

W8 tWR Write Recovery 0 – 0 – ns 5

W9 tBW R-UB#, R-LB# Setup to R-WE# (P-CS#) Going

High 60 – 60 – ns

tCEL P-CE# low-time restriction – 8,000 – – ns 7,8

W10 tWPH Write H igh Pulse Widt h 10 – – – ns 8

Notes:

1. See Figure 9, “A C Waveform PSRAM Write Operation” .

2. A write occurs during the overlap (tWP) of low P-CS# and low R-WE#. A write begins when P-CS# goes low and R-WE#

goes low with asserting R-UB# or R-LB# for single byte operation or simultaneously asserting R-UB# and R-LB# for

double byte operation. A write ends at the earliest transition when P-CS# goes high and R-WE# goes high.

3. tWP is measured from P-CS# going low to end of a write.

4. tAS is measured from the address valid to the beginning of a write.

5. tWR is measured from the end of a write to the address change. tWR applied in case a write ends as P-CS# or R-WE#

going high.

6. W3 is 70 ns for continuous write operations over 50 times.

7. P-CE# must go high and be maintained high for a minimum of 10ns at least once every 8,000ns

8. Spec’s only applicable to parts 38F1030W0YxQF & 38F2030W0YxQF

9. Applicable to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1, 38F2030W0ZTQ2,

38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0, 38F1030W0YTQE, 38F1030W0YBQE.

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 27

Note: Available only for 32-Mbit PSR AM and line items with 16-Mbit PSRAM (70 ns) 38F2030W0YTQ1,

38F2030W0YBQ1, 38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0,

38F1030W0YTQE, 38F1030W0YBQE. Not applicable to 8-Mbit PS RAM.

Figure 7. AC Wa veform of PS RAM Re ad Ope rat ion s

Fig ur e 8. AC Wavefo r m o f P SRAM 4-Wo rd Page Read Operation

Valid Data R10R6R11

R9R4

R12R5

R8R3

R2 R1

ADDRESSES

P-CS#

R-UB#, R-LB#

R-OE#

DATA

Val id Addres

Val i d Addres

Valid Da ta Val id Da ta Val id Da ta Val id Da ta

PR2R6 R7

R9R4

R8R3

PR1PR1

R2 R1

[Max:2]

A[1:0]

P-CS#

R-OE#

DATA

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

28 Order Number: 25140 7, Revis i on: 01 0

Figu r e 9. AC Waveform PSRAM Write Ope ratio n

Da ta In W7W4

W5 W3W3

W2 W1

ADDRESSES

P-CS#

R-UB#, R-LB#

R-WE#

DATA

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 29

7.4 Device AC Test Conditions

Figure 10. Tra nsient Inpu t/Output Reference Waveform

Note: AC test input s are dr iven to VCCQ, P- VCC for logic “1” and 0.0 V for logi c “0”. in put/output timi ng begins/

ends at VCCQ/2, P-VCC/2. Input rise and fall time (10% to 90%) < 5 ns. Worse case speed occurs at

VCC = VCCMin.

Figure 11. Transient Equivalent Testing Load Circuit

Notes:

1. Test configuration component value for worst case specification conditions.

2. CL includes jig capacitance.

Tes t P oint s

CCQ

/2,

P-V

CCQ

/2,

P-V

Input Output

0 V

CCQ

, P-V

I/O

Output

= 50 O hms

= 30 pf

Ohms

P-V

/2 = V

CCQ

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

30 Order Number: 25140 7, Revis i on: 01 0

8.0 Flash Power Consumption

Refer to the Intel® Wireless Flash Memory (W18) Datasheet (orde r number 290701) and Intel®

Wir el ess Flash Memory (W30) Datasheet (ord e r nu mb er 290 7 02 ) for inform a ti o n re gardi n g fl a sh

read modes a nd opera tions.

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 31

9.0 Device Operation

9.1 Bus Operations

Bus ope ration s for the W1 8/W30 SC SP f amily in vol ve t he fol low ing ch ip e nable an d out put enab le

signals, respectively:

•F1-CE# for Flash Die#1 and F2-CE# for Flash Die#2

•F1-OE# for Flash Die#1 and F2-OE# for Flash Die#2

All othe r control signals are share d between the two flash die. Table 14 to Ta ble 16 e xplain the bus

ope rations of products across this SCS P family. Refer to the W1 8/W30 discret e da ta shee t s (order

numbers 290701 an d 290702 ) for sin gle flash die SCSP bus operations .

Tabl e 14. Fl ash -Onl y Bus Operat ions

Device

Mode

F-RST#

F1-CE#

F1-OE#

F-WE#

ADV#

F-VPP

WAIT

F2-CE#

F2-OE#

D[15:0]

Notes

Flash Die#1

Sync Array Read H L L H L X Active H X Flash

DOUT 2, 3, 4

All Async /

Sync No n-Array

Read HLLHX XAsserted H X Flash

DOUT 1, 3, 4, 5

Write H L H L X VPPL

VPPH Asserted H X Flash

DIN 3, 4, 6

Output Disable H L H H X X Active X X Flash

High-Z 4

Standby H H X X X X High-Z X X Flash

High-Z 4

Reset LXXXX XHigh-Z X X Flash

High-Z 4

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

32 Order Number: 25140 7, Revis i on: 01 0

Flash Die#2

Sync Array Read H H X H L X Active L L Flash

DOUT 2, 3, 4

All Async /

Sync Non-Array

Read HHXHX XAsserted L L Flash

DOUT 1, 3, 4, 5

Write H H X L X VPPL

VPPH Asserted L H Flash

DIN 3, 4, 6

Output Disable H X X H X X Active L H Flash

High-Z 4

Standby HXXXX XHigh-Z H X Flash

High-Z 4

Reset LXXXX XHigh-Z X X Flash

High-Z 4

Notes:

1. For asynchronous read operation, both die may be simultaneously selected, but may not simultaneously drive the

memory bus. See Section 9.2, “Flash Com m and Definitions” on page 34 for details regarding flash selection

overlap.

2. WAIT is only valid during synchronous flash reads. WAIT is driven if F-CE# is asserted. Refer to the W18 or W30

datasheet (order number 290701 and 29702) for further information regarding WAIT Signal.

3. For either flash die, F[2:1]-OE# and F-WE# should never be asserted simultaneously. If done so on a particular

flash die, F[2:1]-OE# will override F-WE#.

4. L m eans VIL while H means VIH. X can be VIL or VIH for inputs, V PPL, V PPH or VPPLK for F-VPP.

5. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0].

6. Refer to W18/W30 datasheet for valid DIN during flash writes.

Table 15. Fl ash + SRAM B u s Op erat ions

Device

Mode

F-RST#

F[2:1]-CE#

F[2:1]-OE#

F-WE#

ADV#

F-VPP

WAIT

S-CS1#

S-CS2

R-OE#

R-WE#

R-UB#,

R-LB#

D[15:0]

Notes

Flash Die(#1 or #2)

Sync

Array

Read HLLHL XActive

SRAM must be in High-Z

Flash

DOUT 1, 2, 3, 5

All Asyn c/

Sync

Non-array

Read H L L H X X Asserted Flash

DOUT 1, 2, 3, 5, 6

Write H L H L L VPPL

VPPH Asserted Flash

DIN 3, 7

Output

Disable HLHHX X Active

Any SRAM mode allowed

Flash

High-Z 5

Standby HHXXX XHigh-Z Flash

High-Z 5

Reset LXXXX XHigh-Z Flash

High-Z 5

Device

Mode

F-RST#

F1-CE#

F1-OE#

F-WE#

ADV#

F-VPP

WAIT

F2-CE#

F2-OE#

D[15:0]

Notes

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 33

SRAM

Read Flash must be in High-Z LHLHLSRAM

DOUT 1, 4, 8, 2

Write L H X L L SRAM

DIN 4, 5, 8, 2

Output

Disable

Any flash mode allowed

LHHHXSRAM

High-Z 5, 2

Standby HXXXXSRAM

High-Z 5, 8, 2

Data

Retention Same as SRAM standby SRAM

High-Z 9, 2

Notes:

1. For asynchronous r ead operati on, all die may be si multaneously se lected, but may not sim u lt aneously drive the

memory bus.

2. WAIT is only valid during synchronous flash reads. WAIT is driven if F-CE# is asserted.

3. For flash die, F[2:1]-OE# and F-WE# should never be asserted simultaneously. If done so, F[2:1]-OE# will

override F-WE#.

4. For SRAM, R-OE# and R-WE# should never be asserted simultaneously.

5. X can be VIL or VIH for inputs, VPPL, VPPH or VPPLK for F-VPP.

6. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0].

7. Refer to W18 and W30 datasheet for valid DIN during flash w rites.

8. The SRAM is enabled and/or disabled with the logical function: S-CS1# OR S-CS2.

9. The SRAM can be placed into data retention mode by lowering S-VCC to the VDR limit when in standby mode.

Tabl e 16. Fl ash + PSRAM Bus Opera tions

Device

Mode

F-RST#

F[2:1]-CE#

F[2:1]-OE#

F-WE#

ADV#

F-VPP

WAIT

P-CS#

P-Mode

R-OE#

R-WE#

R-UB#,

R-LB#

D[15:0]

Notes

Flash Die(#1 or #2)

Sync

Array

Read HLLHL XActive

PSRAM must be in High-Z

Flash

DOUT 1, 2, 3, 4, 6

All Async/

Sync

Non-array

Read H L L H X X Asserted Flash

DOUT 1, 2, 3, 4, 6, 7

Write H L H L X VPPL

VPPH Asserted Flash

DIN 3, 4, 6, 8

Output

Disable HLHHX XActive

Any PSRAM mode allowed

Flash

High-Z 6

Standby H H X X X X High-Z Flash

High-Z 6

Reset LXXXX XHigh-Z Flash

High-Z 6

Tabl e 15. Fl ash + SR AM Bus Operation s

Device

Mode

F-RST#

F[2:1]-CE#

F[2:1]-OE#

F-WE#

ADV#

F-VPP

WAIT

S-CS1#

S-CS2

R-OE#

R-WE#

R-UB#,

R-LB#

D[15:0]

Notes

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

34 Order Number: 25140 7, Revis i on: 01 0

9.2 Flash Comma nd Defin itions

Refer to the discrete datasheet s , Intel® Wireless Flash Memory (W18) Datasheet (order number

290701) an d Intel® Wireless Flash Memory (W30) Datasheet (ord e r numbe r 290702) for

infor mation regarding flash command definitions.

PSRAM

Read

Flash#1 and #2 must be in High-Z

LHLHL

PSRAM

DOUT 1, 5, 2

Write L H H L L PSRAM

DIN 5, 2

Output

Disable

Any flash mode allowed

LHHHX

PSRAM

High-Z 6, 2

Standby H H X X X PSRAM

High-Z 6, 2

Deep

Power-

Down HLXXX

PSRAM

High-Z 6, 9, 2

Notes:

1. For async hr onous read oper ation, a ll di e may b e simu ltan eously selec ted, but may not simul taneously drive the memory b us. For

synchronous burst-mode reads, only two die (one flash and the PSRAM ) may be simultaneously selected.

2. WAIT is only valid during synchronous flash reads. WAIT is driven if F- CE# is asserted.

3. F1-CE# for Flash Die#1, F2-CE# for Flash Die#2. F1-OE# is for Flash Die#1, F2-OE# for Flash Die#2.

4. For either flash die, F[2:1]-OE# and F-WE# should never be asserted simultaneously. If done so on a particular flash die, F[2:1]-

OE# will override F-WE#.

5. For PSRAM, R-OE# and R-WE# should never be asserted simultaneously.

6. X can be VIL or VIH for inputs, VPPL,VPPH or VPPLK for F-VPP.

7. Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0].

8. Refer to W30/W18 datasheet for Valid DIN during flash writes.

9. Deep power-down is not applicable to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ1, 38F2030W0YBQ1,

38F2030W0ZTQ2, 38F2030W0ZBQ2, 38F1030W0ZTQ0, 38F1030W0ZBQ0, 38F1030W0YTQE, 38F1030W0YBQE.

Table 16. Fl ash + PSRAM Bus Op eratio n s

Device

Mode

F-RST#

F[2:1]-CE#

F[2:1]-OE#

F-WE#

ADV#

F-VPP

WAIT

P-CS#

P-Mode

R-OE#

R-WE#

R-UB#,

R-LB#

D[15:0]

Notes

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 35

10.0 Flash Read Operations

Refer to the Intel® Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel®

Wireless Flash Memory (W30) Datasheet (order n umber 29 0702 ) for informati on regardin g flash

rea d mode s and ope ra tions.

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

36 Order Number: 25140 7, Revis i on: 01 0

11.0 Flash P ro gram Operatio ns

Refer to the Intel® Wireless Flash Memory (W18) Datasheet (orde r number 290701) and Intel®

Wir el ess Flash Memory (W30) Datasheet (ord e r nu mb er 290 7 02 ) for inform a ti o n re gardi n g fl a sh

read modes a nd opera tions.

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 37

12.0 Flash Erase Operatio ns

Refer to the Intel® Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel®

Wireless Flash Memory (W30) Datasheet (order n umber 29 0702 ) for informati on regardin g flash

rea d mode s and ope ra tions.

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

38 Order Number: 25140 7, Revis i on: 01 0

13.0 Flash Security Modes

Refer to the Intel® Wireless Flash Memory (W18) Datasheet (orde r number 290701) and Intel®

Wir el ess Flash Memory (W30) Datasheet (ord e r nu mb er 290 7 02 ) for inform a ti o n re gardi n g fl a sh

read modes a nd opera tions.

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 39

14.0 Flash Read Configuration Register

Refer to the Intel® Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel®

Wireless Flash Memory (W30) Datasheet (order n umber 29 0702 ) for informati on regardin g flash

rea d mode s and ope ra tions.

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

40 Order Number: 25140 7, Revis i on: 01 0

15.0 SRAM Operations

15.1 Power-up Sequence and Initialization

The SRA M functionality and re liability are independent of the power-up sequence and po we r-up

slew rate of the core S-VCC. Any power-up s e quence and power-up slew rate is possible un de r use

conditions. SRAM reliab ility is also indepen dent of the power -down seq uence and po wer-down

slew rate of the core S- VCC.

15.2 Dat a Retention Mode

Table 17. SRAM Data Retention Operation

Symbol Parameter Min Max Unit Notes

tSDR Data Retention Set-up Time 0 – ns

tRDR Data Retention Recovery Time tRC –ns 1

Note:

1. tRC is defined in Table 7.2, “SRAM AC Characteristics” on page 21.

Figure 12. S R AM D ata Retention Operation Waveform—S-CS1# Control led

S-V

CCmin

S-V

IHmin

SDR

Data Retention M ode t

RDR

S-CS1#

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 41

Figure 13. SRAM Data Retention Operation Wavefor m— S-C S2 Control le d

S-V

-V

CCMIN

ILMAX

S-CS2

SDR

Data Retention Mode t

RDR

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

42 Order Number: 25140 7, Revis i on: 01 0

16.0 PSRAM Operations

16.1 Power-Up Sequence and Initialization

The PSRAM functionality and rel iability are indep e ndent of the power-up sequence and sl ew rate

of the cor e P- VCC. A ny power-up seq uenc e a nd s lew rate is po ssi ble und er use co nditio ns . PSRA M

reliability are also indepen dent of the power-do wn s equence and sl ew rate of the cor e P-VCC.

The following power-up seque nce and regi ster setting should be used before sta rting normal

operation . The PSRAM pow er-up sequence is represented in Figure 14. Fo llo wi n g pow er

applic a tion, make P -Mode h i gh after fixing P-Mo de to a low lev e l for a period of tI1. Make P-C S#

high before making P- Mode high. P-CS# and P-Mod e a re fixed to a high level for per iod of t I3.

16.1.1 1 6Mbi t PSRAM P ower-Up Sequence (Non-Page Mode )

For the non-page mode PSRAM (part’s RD38 F1030W0YQF, PF38F1030W0YQF,

RD38F2030W 0YQF, PF 38F2030W0YQF) the PSRAM functionality and reliabi lity must be

indepen dent of the power- up sequence and power-up slew rate of the core Vcc and the I/O Vcc

Figure 14. Timi ng Wa ve form for Power-Up Seque nce

Table 18. P ower-Up Sequence Specifications

Parameter Description Min Max Unit Notes

tI1 Power application with P-Mode held low 50 —µs 1,2,3

tI2 P-CS# high to P-Mode high 10 —ns

tI3 P-Mode high to P -CS# low 500 —µs

Notes:

1. Toggle P-Mode to low when starting the power-up sequence.

2. tI1 is specified from when the power supply voltage reaches VCCMIN.

3. Does not apply to 38F2020W0ZTQ1, 38F2020W0ZBQ1, 38F2030W0YTQ 1,

38F2030W0YBQ1, 38F2030W0ZTQ2, and 38F2030W0ZBQ2,

38F1030W0ZTQ0, 38F1030W0ZBQ0, 38F1030W0YTQE, 38F1030W0YBQE

line items. Valid PSRAM operations for these li ne items ca n begin 200 µs after P-

Vcc has reached P-Vcc min.

Reg i ster Se tti ng

tI3tI1

tI2

Po wer Up

P-VCC

P-CS#

P-MODE

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 43

(Vcc q. ) A ny power-up sequence and power-up slew r ate is possib le under use conditions . PSRAM

reliabil ity mus t a lso be indep e ndent o f the power-dow n sequence and powe r-down slew rate of the

core Vcc and the I/O Vcc (Vccq.)

Once power supply voltages ha ve reached the minimum spec value of 1.7V (or highe r), CE# must

be maintained high for mini mum 200us prior to commen c ing valid PSRAM ope ration.

16.2 Standby Mode/ Deep Power-Down Mode

Caution: All line items that do not have the P-Mode pine will not have the deep power-down feature

(38F1030W0YxQE, 38F1030W0YxQ2, 38F1030W0ZxQ0, 38F2030W0YxQ1,

38F2030W0YxQE, 38F2030W0YxQ2, 38 F2030W0YxQF, 38F2030W0ZxQ2,

38F2040W0ZxQ0).

Data is lost during deep power-down mode as shown in the Table below. Wake-up from deep

power-down m ode invol ve s the sam e initializati on sequenc e a s discu ssed in Section 16.1, “Power-

Up Sequence and Initia lization” on page 42.

16.3 PSRAM Special Read and Write Constraints

Caution: This section will not ap ply to line ite ms that do not have the P-Mode pine will not have the deep

power-down fea ture (3 8F1030W0YxQE , 38F1030W0YxQ2, 38F1030W0Zx Q0,

38F 203 0W0Yx Q1, 38F20 30W 0YxQE , 3 8F 2030W0 Yx Q2, 3 8F 20 30W0Yx QF, 38 F2 030W0Z xQ2 ,

38F2040W0ZxQ0).

Mode Memory Cell Data Delay time to go Active

Standby Valid 0 ns

Deep Power-Down Invalid Start-Up Sequence

Figure 15. Timing Waveform for Enter ing Dee p Pow er- Dow n Mode

Table 19. PSRA M Special Read C o n strai n ts

Description Min Max Unit Notes

Cannot have sub tRC address toggle for more than 4 µs in

active mode. Need either a read operation or P-CS# high

for tRC in that time frame N/A N/A –

P-CS# high level pulse width 10 – ns 1

Deep Power Down ModeDeep Power Down ModeSuspend M ode

1 us

P-MODE

P-CS#

Device M ode

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

44 Order Number: 25140 7, Revis i on: 01 0

R-UB#/R-LB# high level pulse width 10 – ns 1

R-OE# high level pulse width in active mode (P-CS# low) 10 10,000 ns

P-CS# low to R-OE# low – 10,000 ns

Address Skew time (unstable address with P- CS# low) – 10 ns 2

Notes:

1. Toggling of these control signals is not necessary during address controlled read operations.

2. Address skew time (tSKEW) indicates the following three types of time depending on the condition.

a. When switching P-CS# from high to low, tSKEW is the time from the P-CS# low input point until the

next address is determined.

b. When switching P-CS# from low to high, tSKEW is the time from the address change start point to

the P-CS# high input point.

c. When P-CS# is fixed to low, tSKEW is the time from the address st ar t point until the next address is

determined.

Since specs are defined for tSKEW only when P-CS# i s acti ve, t SKEW is not s ubject to li mitatio ns

when P -CS# is s witche d f rom h igh to low follo win g addr ess dete rmina tion, or when th e ad dress

is chan ged after P-CS# is switch ed from low to high.

Table 20. PS RAM Special Write Cons traints

Description Min Max Unit Notes

Need either R-WE# high or P-CS# high for at least tWC

time, for every 4us window during write operations. N/A N/A –

R-OE# high to R-W E# low in active mode (P-CS# low) 0 10,000 ns

R-WE# high to R-OE# low in active mode (P-CS# low) 10 10,000 ns

Address Skew time (unstable address with P- CS# low) – 10 ns 1

Note:

1. Address skew time (tSKEW) indicates the following three types of time depending on the condition.

a. When switching P-CS# from high to low, tSKEW is the time from the P-CS # low input point until the

next address is determined.

b. When switching P-CS# from low to high, tSKEW is the time from the address change start point to

the P-CS# high input point.

c. When P-CS# is fixed to low, tSKEW is the time from the address start point until the next address is

determined.

Since specs are defined for tSKEW only when P-CS# is active, tSKEW is not subject to limit ations when P-CS#

is switched from high to low following address determination, or when the address is changed after P-CS# is

switched from low to high.

Table 19. PSRAM Special Read Constraints

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 45

Appendix A Write State Machine

Refer to the Intel® Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel®

Wireless Flash Memory (W30) Datasheet (order number 290702) for the WSM details.

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

46 Order Number: 25140 7, Revis i on: 01 0

Appendix B Common Flash Interface

Refer to the Intel® Wireless Flash Memory (W18) Datasheet (orde r number 290701) and Intel®

Wir el ess Flash Memory (W30) Datasheet (order number 290702) for the CFI details.

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 47

Appendix C Flash Flowcharts

Refer to the Intel® Wireless Flash Memory (W18) Datasheet (order number 290701) and Intel®

Wireless Flash Memory (W30) Datasheet (order number 290702) for the flash flowchart details.

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

48 Order Number: 25140 7, Revis i on: 01 0

Appendix D Additional Information

Order Number Document

290701 Intel® Wireless Flash Memory (W18) Datasheet

290702 Intel® Wireless Flash Memory with 3 Volt I/O (W30) Datasheet

251216 64-Mbit 1.8 Volt Intel® Wireless Flash Memory SCSP Family A pplication Note

Notes:

1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International

customers should contact their local Intel or distribution sales office.

2. For the mo st current infor mation on Intel® Flash memory products, software and tools, visit our

website at http://developer.intel.com/design/flash.

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 49

Appendix E Ordering Information

Figure 16 shows the decod er f or prod ucts in this SCSP family w ith bo th flas h and RAM. Figure 17

sho ws the decod e r for products in this SCSP family with flash die only (no RAM). Table 23,

“32WQ a n d 64WQ W18/W3 0 SCSP Ord erin g Information (Flash + PSRAM ) ” on p age 52 lis ts

available product combination s .

Figure 16. Decoder for Flash + RAM SCSP Fami ly De vices

F 2 0 W 0 Z B Q8D 3R

Package

Pinout In dicator

Pro duct Line

Designator

Flash De nsity

Voltage

Prod uct Fam ily

RD = SCSP

PF = Pb-free SCSP

38F = Flash & RAM Stack D evice

2 = 64-Mbit

1 = 32-Mbit

0 = No die

W = In tel® Wireless F la sh Mem o ry

0 = No Die

Y = 1.8 Volt I/O

Z = 3 V olt I/O

Q= QUAD+ ballout

3 0

RAM Density

4 = 32-M bit

3 = 16-M bit

2 = 8-Mbit

1 = 4-Mbit

0 = No Die

P aramete r Loc a tio n

B = B o ttom Pa ra m e te r

T = Top Parameter

D = D u al Pa r ameter

Device Details

0-9, A -D = 1st Ge neration, 13 0 nm

E-R = 2nd Ge n e ration , 9 0 n m

(note: 90 nm is only 1.8 V I/O )

S-Z = 3rd G e ne ratio n , TBD

Flash #1

Flash #2

RAM #2

RAM #1

Flash #1 Family

Flash #2 Family

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

50 Order Number: 25140 7, Revis i on: 01 0

Notes:

Figure 17. Decoder for Flash- Onl y SCSP Fami l y Device s

Table 21. 32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash Only)

Flash Component Package Product Number (1,2,3,4,5)

Size (mm) Type Ballout

32 W30 8 x 10 x 1.2 Lead-free Q uad + PF48F1000W0ZTQ0

PF48F1000W0ZBQ0

64 W30 8 x 10 x 1.2 Lead-free Q uad + PF48F2000W0ZTQ0

PF48F2000W0ZBQ0

64 W18 + 32 W18 8 x 10 x 1.2 Leaded Q uad + RD48F2100W0YDQE

64 W18 + 64W18 8 x 10 x 1.2 Leaded Quad + RD48F2200W0YDQ0

F 2 2 W 0 Z D Q8D 4R

Package

Pinout Indicator

Product Line

Designator

Flash Density

Voltage

Produ ct Family

RD = SCSP

PF = Pb-free SCSP

48F = Flash-only Stack Device

2 = 64-Mbit

1 = 32-Mbit

0 = No Die

W = Inte l® Wireless Flash Memory

0 = No Die

Y = 1.8 Volt I/O

Z = 3 Volt I/O

Q = QUA D+ Ballout

0 0 0

P a ra m e ter L o c atio n

D = Dual Parameter

Flash #1

Flash #2

Flash 1/2 Family

Flash #4

Flash #3

Flash 3/4 Family

D evic e Details

0-9, A-D = 1st

Generation, 130 nm

E-R = 2 nd G eneration, 90 nm

(note: 90 nm is only 1.8 V I/O)

S-Z = 3rd Generation, TBD

B = Bottom Param eter

T = Top Parameter

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 51

1. W18 = Intel® Wireless Flash Memory (W18) with 1.8 V I/O; W30 = Intel® Wireless Flash Memory (W30)

with 3.0 V I/O.

2. B = Bottom Parameter, where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# =

Top Parameter.

3. T = Top Parameter where Flash Die #1, F1-CE# = Top Parameter and Flash Die #2, F2-CE# = Bottom

Parameter.

4. D = Dual Parameter where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top

Parameter.

5. Parts ending with “QE” are 90 nm Flash devices.

Notes:

1. W18 = Intel® Wireless Flash Memory (W18) with 1.8 V I/O; W30 = Intel® Wireless Flash Memory (W30)

with 3.0 V I/O.

2. B = Bottom Parameter, where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# =

Top Parameter.

3. T = Top Parameter where Flash Die #1, F1-CE# = Top Parameter and Flash Die #2, F2-CE# = Bottom

Parameter.

4. D = Dual Parameter where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top

Parameter.

Tabl e 22. 32 WQ and 64WQ W1 8/W30 SCSP Ord erin g Inform ation (Fla sh + SR AM )

Flash

Component RAM Package

Product Number(1,2,3,4)

Size in Mbit and

Family Size in Mbit

and Type Size (mm) Type Ballout

64 W18

4 SRAM 8 x 10 x 1.2 Leaded Quad+ RD38F2010W0YTQ0

RD38F2010W0YBQ0

8 SRAM 8 x 10 x 1.2 Leaded Quad+ RD38F2020W0YTQ0

RD38F2020W0YBQ0

16 SRAM 8 x 10 x 1.2 Leaded Quad+ RD38F2030W0YTQ0

RD38F2030W0YBQ0

64 W30

8 SRAM 8 x 10 x 1.2 Leaded Quad+ RD38F2020W0ZTQ0

RD38F2020W0ZBQ0

16 SRAM 8 x 10 x 1.2 Leaded Quad+ RD38F2030W0ZTQ0

RD38F2030W0ZBQ0

64 W18 + 64 W18 16 SRAM 8 x 10 x 1.4 Leaded Quad+ RD38F2230WWYDQ0

64 W30 + 64 W30 16 SRAM 8 x 10 x 1.4 Leaded Quad+ RD38F2230WWZDQ0

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

52 Order Number: 25140 7, Revis i on: 01 0

Table 23. 32WQ and 64WQ W18/W30 SCSP Ordering Information (Flash + PSRAM) (Sheet 1 of

Flash Component RAM Package Product N umber

(1,2,3,4,5) PSRAM used

Size in Mbit and

Family Size in Mbit

and Type Size (mm) Ballout Type

32 W18 16 PSRAM 8 x 10 x 1.2 Quad+ Lead-free PF38F1030W0YTQE

PF38F1030W0YBQE 70 ns,

No PMODE pin

32 W18 16 PSRAM 8 x 10 x 1.2 Quad+ Leaded RD38F1030W0YTQ2

RD38F1030W0YBQ2 70 ns,

No PMODE pin

& Non-Page

Mode Support

Lead-free PF38F1030W0YTQ2

PF38F1030W0YBQ2

32 W30 16 PSRAM 8 x 10 x 1.2 Quad+

Leaded RD38F1030W0ZTQ0

RD38F1030W0ZBQ0 70 ns,

No PMODE pin

Lead-free PF38F1030W0ZTQ0

PF38F1030W0ZBQ0

64 W18 16 PSRAM 8 x 10 x 1.2 Quad+

Leaded RD38F2030W0YTQ1

RD38F2030W0YBQ1

70 ns,

No PMODE pin

Lead-free PF38F2030W0YTQ1

PF38F2030W0YBQ1

Leaded RD38F2030W0YTQE

RD38F2030W0YBQE

Lead-free PF38F2030W0YTQE

PF38F2030W0YBQE

64 W18 16 PSRAM 8 x 10 x 1.2 Quad+

Leaded RD38F2030W0YTQ2

RD38F2030W0YBQ2

70 ns,

No PMODE pin

& Non-Page

Mode Support

Lead-free PF38F2030W0YTQ2

PF38F2030W0YBQ2

Leaded RD38F2030W0YTQF

RD38F2030W0YBQF

Lead-free PF38F2030W0YTQF

PF38F2030W0YBQF

64 W30 16 PSRAM 8 x 10 x 1.2 Quad+

Leaded RD38F2030W0ZTQ1

RD38F2030W0ZBQ1 85 ns,

with PMODE pin

Leaded RD38F2030W0ZTQ2

RD38F2030W0ZBQ2 70 ns,

No PMODE pin

Lead-free PF38F2030W0ZTQ2

PF38F2030W0ZBQ2

64 W18 32 PSRAM 8 x 10 x 1.2 QUAD+ Leaded RD38F2040W0YTQ0

RD38F2040W0YBQ0 88 ns,

with PMODE pin

Lead-free PF38F2040W0YTQ0

PF38F2040W0YBQ0

Intel® Wireless Flash Memory (W18/W30 SCSP)

Datasheet Int el ® Wireless F l ash Memory (W18/W30 SCS P ) 18-Oct-2005

Order Nu m ber: 251407 , Revi sion: 010 53

Notes:

1. W18 = Intel® Wireless Flash Memory (W18) with 1.8 V I/O; W30 = Intel® Wireless Flash Memory (W30)

with 3.0 V I/O.

2. B = Bottom Parameter, where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# =

Top Parameter.

3. T = Top Parameter where Flash Die #1, F1-CE# = Top Parameter and Flash Die #2, F2-CE# = Bottom

Parameter.

4. D = Dual Parameter where Flash Die #1, F1-CE# = Bottom Parameter and Flash Die #2, F2-CE# = Top

Parameter.

5. Parts ending with “QE” are 90 nm Flash devices.

6. RD 38F2240WWYDQ0 = Engineering Samples; RD38F2240WWYDQ1 = Production

64 W30 32 PSRAM 8 x 10 x 1.2 QUAD+ Leaded RD38F2040W0ZTQ0

RD38F2040W0ZBQ0 85 ns,

No PMODE pin

64 W18 + 64 W18 32 PSRAM 8 x 10 x 1.4 QUAD+ Leaded RD38F2240WWYDQ0(6)

RD38F2240WWYDQ1 88 ns,

with PMODE pin

64 W30 + 64 W30 32 PSRAM 8 x 10 x 1.4 QUAD+ Leaded RD38F2240WWZDQ0

RD38F2240WWZDQ1 85 ns,

No PMODE pin

Tab le 23. 32W Q an d 64 WQ W1 8/ W30 SC SP Orde ri ng Info rma ti on ( Fla sh + P SR AM) (She et 2 o f

Flash Component RAM Package Product Number

(1,2,3,4,5) PSRAM used

Size in Mbit and

Family Size in Mbit

and Type Size (mm) Ba llout Type

Intel ® Wi reless F lash M emory ( W18/W30 SCS P )

18-Oct-2005 Intel® Wireless Flash Memory (W18/W30 SCSP) Datasheet

54 Order Number: 25140 7, Revis i on: 01 0