AD9643170EBZ - ANALOG DEVICES

Network Clock Generator, Two Outputs

AD9575

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Fully integrated VCO/PLL core

0.39 ps rms jitter from 12 kHz to 20 MHz at 156.25 MHz

0.15 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz

0.40 ps rms jitter from 12 kHz to 20 MHz at 106.25 MHz

0.15 ps rms jitter from 637 kHz to 10 MHz at 106.25 MHz

Input crystal frequency of 19.44 MHz, 25 MHz, or

25.78125 MHz

Pin selectable divide ratios for 33.33 MHz, 62.5 MHz,

100 MHz, 106.25 MHz, 125 MHz, 155.52 MHz, 156.25 MHz,

159.375 MHz, 161.13 MHz, and 312.5 MHz outputs

LVDS/LVPECL/LVCMOS output format

Integrated loop filter

Space saving 4.4 mm × 5.0 mm TSSOP

100 mA power supply current (LVDS output)

120 mA power supply current (LVPECL output)

3.3 V operation

APPLICATIONS

GbE/FC/SONET line cards, switches, and routers

CPU/PCI-E applications

Low jitter, low phase noise clock generation

GENERAL DESCRIPTION

The AD9575 provides a highly integrated, dual output clock

generator function including an on-chip PLL core that is

optimized for network clocking. The integer-N PLL design is

based on the Analog Devices, Inc., proven portfolio of high

performance, low jitter frequency synthesizers to maximize line

card performance. Other applications with demanding phase

noise and jitter requirements also benefit from this part.

The PLL section consists of a low noise phase frequency detector

(PFD), a precision charge pump (CP), a low phase noise voltage

controlled oscillator (VCO), and pin selectable feedback and

output dividers.

By connecting an external crystal, popular network output fre-

quencies can be locked to the input reference. The output divider

and feedback divider ratios are pin programmable for the required

output rates. No external loop filter components are required,

thus conserving valuable design time and board space.

The AD9575 is available in a 16-lead, 4.4 mm × 5.0 mm TSSOP

and can be operated from a single 3.3 V supply. The temperature

range is −40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

DD × 5

GND × 5

AD9575

XTAL

OSC

VCO

PFD/CP

THIRD-ORDER

LPF

DIVIDERS

100MHz

TO 3 12.5M Hz

LVDS OR

LVPECL

LVCMOS 33.33MHz/

62.5MHz/SEL1

LDO

08462-001

SEL0

SEL

Figure 1.

AD9575

Rev. A | Page 2 of 16

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3 

PLL Characteristics ...................................................................... 3

LVDS Clock Output Jitter (Typ/Max) ........................................ 4

LVPECL Clock Output Jitter (Typ/Max) ................................... 4

Output Frequency Select ............................................................. 5

Clock Outputs ............................................................................... 5

Timing Characteristics ................................................................ 5

Power .............................................................................................. 6

Crystal Oscillator .......................................................................... 6

Timing Diagrams .......................................................................... 6

Absolute Maximum Ratings ............................................................7

Thermal Resistance .......................................................................7

ESD Caution...................................................................................7

Pin Configuration and Function Descriptions ..............................8

Typical Performance Characteristics ..............................................9

Terminology .................................................................................... 11

Theory of Operation ...................................................................... 12

Phase Frequency Detector (PFD) and Charge Pump ............ 12

Power Supply ............................................................................... 12

LVPECL Clock Distribution ..................................................... 12

LVDS Clock Distribution .......................................................... 13

LVCMOS Clock Distribution ................................................... 13

Typical Application Circuit ....................................................... 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

REVISION HISTORY

3/10—Rev. 0 to Rev. A

Changes to Features Section............................................................ 1

Changes to Table 1, Table 2, and Table 3 ....................................... 4

Changes to Table 4 and Table 6 ....................................................... 5

Changes to Table 7 and Table 8 ....................................................... 6

Changes to Table 12 .......................................................................... 8

Added Figure 11; Renumbered Figures Sequentially ................ 10

Changes to Figure 13 ...................................................................... 10

Changes to Theory of Operation Section and Figure 19 ........... 12

Changes to Figure 24 ...................................................................... 13

1/10—Revision 0: Initial Version

AD9575

Rev. A | Page 3 of 16

SPECIFICATIONS

Typical (typ) values are given for VS = 3.3 V ± 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are

given over the full VS and TA (−40°C to +85°C) variation.

PLL CHARACTERISTICS

Table 1.

LVDS LVCMOS LVPECL

Parameter Min Typ Max Min Typ Max Min Typ Max Unit

PHASE NOISE CHARACTERISTICS

PLL Noise (100 MHz Output)

At 1 kHz −123 −122 dBc/Hz

At 10 kHz −128 −129 dBc/Hz

At 100 kHz −131 −131 dBc/Hz

At 1 MHz −150 −151 dBc/Hz

At 10 MHz −156 −158 dBc/Hz

At 30 MHz −156 −158 dBc/Hz

PLL Noise (106.25 MHz Output)

At 1 kHz −121 −121 dBc/Hz

At 10 kHz −127 −128 dBc/Hz

At 100 kHz −130 −130 dBc/Hz

At 1 MHz −149 −150 dBc/Hz

At 10 MHz −156 −158 dBc/Hz

At 30 MHz −156 −159 dBc/Hz

PLL Noise (125 MHz Output)

At 1 kHz −120 −120 dBc/Hz

At 10 kHz −126 −127 dBc/Hz

At 100 kHz −128 −129 dBc/Hz

At 1 MHz −148 −150 dBc/Hz

At 10 MHz −155 −157 dBc/Hz

At 30 MHz −156 −158 dBc/Hz

PLL Noise (155.52 MHz Output)

At 1 kHz −118 −118 dBc/Hz

At 10 kHz −123 −123 dBc/Hz

At 100 kHz −125 −125 dBc/Hz

At 1 MHz −147 −149 dBc/Hz

At 10 MHz −155 −157 dBc/Hz

At 30 MHz −156 −157 dBc/Hz

PLL Noise (156.25 MHz Output)

At 1 kHz −118 −118 dBc/Hz

At 10 kHz −124 −125 dBc/Hz

At 100 kHz −126 −127 dBc/Hz

At 1 MHz −146 −148 dBc/Hz

At 10 MHz −155 −157 dBc/Hz

At 30 MHz −155 −157 dBc/Hz

PLL Noise (159.375 MHz Output)

At 1 kHz −118 −118 dBc/Hz

At 10 kHz −124 −125 dBc/Hz

At 100 kHz −126 −126 dBc/Hz

At 1 MHz −146 −147 dBc/Hz

At 10 MHz −155 −156 dBc/Hz

At 30 MHz −155 −157 dBc/Hz

AD9575

Rev. A | Page 4 of 16

LVDS LVCMOS LVPECL

Parameter Min Typ Max Min Typ Max Min Typ Max Unit

PLL Noise (161.132812 MHz Output)

At 1 kHz −118 −119 dBc/Hz

At 10 kHz −122 −123 dBc/Hz

At 100 kHz −126 −126 dBc/Hz

At 1 MHz −144 −146 dBc/Hz

At 10 MHz −154 −156 dBc/Hz

At 30 MHz −155 −156 dBc/Hz

PLL Noise (312.5 MHz Output)

At 1 kHz −112 −112 dBc/Hz

At 10 kHz −119 −119 dBc/Hz

At 100 kHz −120 −120 dBc/Hz

At 1 MHz −140 −142 dBc/Hz

At 10 MHz −152 −154 dBc/Hz

At 30 MHz −153 −155 dBc/Hz

PLL Noise (33.33 MHz Output)

At 1 kHz −131 dBc/Hz

At 10 kHz −138 dBc/Hz

At 100 kHz −140 dBc/Hz

At 1 MHz −155 dBc/Hz

At 5 MHz −155 dBc/Hz

PLL Noise (62.5 MHz Output)

At 1 kHz −126 dBc/Hz

At 10 kHz −133 dBc/Hz

At 100 kHz −134 dBc/Hz

At 1 MHz −150 dBc/Hz

At 5 MHz −152 dBc/Hz

Spurious Content −70 −70 dBc

PLL Figure of Merit −217 −217 dBc/Hz

LVDS CLOCK OUTPUT JITTER (TYP/MAX)

Typical (typ) values are given for VS = 3.3 V ± 10%, TA = 25°C, unless otherwise noted. Maximum (max) values are given over the full VS

and TA (−40°C to +85°C) variation.

Table 2.

Jitter Integration

Bandwidth

100

MHz

106.25

MHz

125

MHz

155.52

MHz

156.25

MHz

159.375

MHz

161.13

MHz

312.5

MHz Unit

12 kHz to 20 MHz 0.38/0.50 0.40/0.54 0.37/0.47 0.41/0.54 0.39/0.51 0.38/0.51 0.44/0.61 0.36/0.48 ps rms

1.875 MHz to 20 MHz 0.15/0.27 ps rms

637 kHz to 10 MHz 0.15/0.21 ps rms

LVPECL CLOCK OUTPUT JITTER (TYP/MAX)

Typical (typ) values are given for VS = 3.3 V ± 10%, TA = 25°C, unless otherwise noted. Maximum (max) values are given over the full VS

and TA (−40°C to +85°C) variation.

Table 3.

Jitter Integration

Bandwidth

100

MHz

106.25

MHz

125

MHz

155.52

MHz

156.25

MHz

159.375

MHz

161.13

MHz

312.5

MHz Unit

12 kHz to 20 MHz 0.36/0.46 0.44/0.68 0.36/0.45 0.40/0.52 0.39/0.64 0.41/0.62 0.43/0.69 0.38/0.49 ps rms

1.875 MHz to 20 MHz 0.19/0.54 ps rms

637 kHz to 10 MHz 0.22/0.35 ps rms

AD9575

Rev. A | Page 5 of 16

OUTPUT FREQUENCY SELECT

Minimum (min) and maximum (max) values are given over the full VS and TA (−40°C to +85°C) variation.

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

Select Pins (SEL0/SEL1)

Logic 1 Voltage 0.83 × VS + 0.2 V

Logic 0 Voltage 0.33 × VS − 0.2 V

Logic 1 Current 190 μA Pull-up to VS

Logic 0 Current 150 μA Pull-down to GND

CLOCK OUTPUTS

Typical (typ) values are given for VS = 3.3 V ± 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are

given over the full VS and TA (−40°C to +85°C) variation.

Table 5.

Parameter Min Typ Max Unit Test Conditions/Comments

LVDS CLOCK OUTPUT Termination = 100 Ω differential; default

Output Frequency 312.5 MHz

Differential Output Voltage (VOD) 250 340 450 mV See Figure 2 for definition

Delta VOD 25 mV

Output Offset Voltage (VOS) 1.125 1.25 1.375 V

Delta VOS 25 mV

Short-Circuit Current (ISA, ISB) 14 24 mA Output shorted to GND

Duty Cycle 45 50 55 %

LVPECL CLOCK OUTPUT

Output Frequency 312.5 MHz

Output High Voltage (VOH) VS − 1.5 VS − 1.05 VS − 0.8 V

Output Low Voltage (VOL) VS − 2.5 VS − 1.75 VS − 1.7 V

Differential Output Voltage (VOD) 430 640 800 mV See Figure 2 for definition

Duty Cycle 45 50 55 %

LVCMOS CLOCK OUTPUT

Output Frequency 62.5 MHz

Output High Voltage (VOH) VS − 0.1 V

Output Low Voltage (VOL) 0.1 V

Duty Cycle 45 50 55 %

TIMING CHARACTERISTICS

Table 6.

Parameter Min Typ Max Unit Test Conditions/Comments

LVDS

Termination = 100 Ω differential; CLOAD = 0 pF;

CAC = 0.1 μF

Output Rise Time, tRL 150 200 300 ps 20% to 80%, measured differentially

Output Fall Time, tFL 150 200 300 ps 80% to 20%, measured differentially

LVPECL

Termination = 200 Ω to GND; CLOAD = 0 pF;

CAC = 0.1 μF

Output Rise Time, tRL 180 250 300 ps 20% to 80%, measured differentially

Output Fall Time, tFL 180 250 300 ps 80% to 20%, measured differentially

LVCMOS

Termination = 50 Ω to 0 V; CLOAD = 5 pF;

CAC = 0.1 μF

Output Rise Time, tRC 0.50 0.70 1.10 ns 20% to 80%

Output Fall Time, tFC 0.50 0.70 1.10 ns 80% to 20%

AD9575

Rev. A | Page 6 of 16

POWER

Table 7.

Parameter Min Typ Max Unit

POWER SUPPLY 3.0 3.3 3.6 V

POWER SUPPLY CURRENT

LVDS 100 130 mA

LVPECL 120 160 mA

CRYSTAL OSCILLATOR

Table 8.

Parameter Min Typ Max Unit Test Conditions/Comments

CRYSTAL SPECIFICATION Parallel resonant/fundamental mode

Frequency 19.44 25 25.78125 MHz

ESR 40 Ω

Load Capacitance 14 pF Cx/2 (see Figure 24) + parasitic capacitance

Phase Noise −138 dBc/Hz At 1 kHz offset

Stability −30 +30 ppm

TIMING DIAGRAMS

DIFFERENTIAL

SIGNAL

80%

20%

50%

08462-003

SINGLE-ENDED

LVCMOS

5pF LOAD

80%

20%

8462-004

Figure 2. LVDS or LVPECL Timing and Differential Amplitude Figure 3. LVCMOS Timing

AD9575

Rev. A | Page 7 of 16

ABSOLUTE MAXIMUM RATINGS

Table 9.

Parameter Rating

VDD, VDDA, VDDX, VDD_CMOS to GND −0.3 V to +3.6 V

XO1, XO2 to GND −0.3 V to VS + 0.3 V

LVDS/LVPECL OUT, LVDS/LVPECL OUT,

CMOS OUT/SEL1, SEL0 to GND

−0.3 V to VS + 0.3 V

Junction Temperature1 150°C

Storage Temperature Range −65°C to +150°C

Lead Temperature (10 sec) 300°C

1 See Table 10 for θJA.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 10. Thermal Resistance1

Package Type θJA Unit

16-Lead TSSOP (RU-16) 90.3 °C/W

1 Thermal impedance measurements were taken on a 4-layer board in still air

in accordance with EIA/JESD51-7.

ESD CAUTION

AD9575

Rev. A | Page 8 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VDDA

VDDX

XO1

GNDA

GNDX

XO2

GNDA

VDDA

GND

LVDS /LV P E CL O UT

CMOS OUT/SEL1

GND_CMOS

VDD_CMOS

VDD

SEL0

AD9575

TOP VIEW

(No t to Scale)

08462-005

Figure 4. Pin Configuration

Table 11. Pin Function Descriptions

Pin No. Mnemonic Description

1, 7 GNDA Analog Ground.

2, 8 VDDA Analog Power Supply (3.3 V).

3 VDDX Crystal Oscillator Power Supply.

4, 5 XO1, XO2 External Crystal.

6 GNDX Crystal Oscillator Ground.

9 GND_CMOS Ground for LVCMOS Output.

10 CMOS OUT/SEL1 LVCMOS Output/Output Frequency Select.

11 VDD_CMOS Power Supply for LVCMOS Output.

12 VDD Power Supply for LVDS or LVPECL Output.

13 LVDS/LVPECL OUT Complementary LVDS or LVPECL Output.

14 LVDS/LVPECL OUT LVDS or LVPECL Output.

15 GND Ground for LVDS or LVPECL Output.

16 SEL0 Output Frequency Select.

Table 12. Output Frequency Selection1

Mode XTAL SEL0 SEL1 LVDS/LVPECL Output LVCMOS Output

1 25 MHz GND X2100 MHz 33.33 MHz

2 25 MHz VS GND 156.25 MHz High-Z

3 25.78125 MHz VS GND 161.13 MHz High-Z

4 25 MHz No connect XX

2125 MHz 62.5 MHz

5 25 MHz 15 kΩ pull-up VS 159.375 MHz High-Z

6 25 MHz 15 kΩ pull-up GND 312.5 MHz High-Z

7 25 MHz VS V

S 106.25 MHz High-Z

8 19.44 MHz VS No connect 155.52 MHz High-Z

1 The AD9575 must be power-cycled if the select pin voltages are altered.

2 X = in Mode 1, Pin 10 is configured as an LVCMOS output (33.33 MHz) by forcing Pin 16 to GND. In Mode 4, Pin 10 is configured as an LVCMOS output (62.5 MHz) by

leaving Pin 16 unconnected.

AD9575

Rev. A | Page 9 of 16

TYPICAL PERFORMANCE CHARACTERISTICS

–160

–155

–150

–145

–140

–135

–130

–125

–120

–115

–

110

1k 10k 100k 1M 10M 100M

FRE QUENC Y (Hz)

PHASE NOISE (dBc/Hz )

08462-006

Figure 5. Phase Noise at LVPECL, 100 MHz Clock Output

–160

–155

–150

–145

–140

–135

–130

–125

–120

–115

–

110

1k 10k 100k 1M 10M 100M

FRE QUENC Y ( Hz )

PHASE NOISE (dBc/Hz)

08462-007

Figure 6. Phase Noise at LVPECL, 106.25 MHz Clock Output

–160

–155

–150

–145

–140

–135

–130

–125

–120

–115

–

110

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

PHASE NO ISE ( dBc/ Hz )

08462-008

Figure 7. Phase Noise at LVPECL, 125 MHz Clock Output

–160

–155

–150

–145

–140

–135

–130

–125

–120

–115

–

110

1k 10k 100k 1M 10M 100M

FRE QUENC Y ( Hz )

PHASE NOISE (dBc/Hz)

08462-009

Figure 8. Phase Noise at LVPECL, 155.52 MHz Clock Output

–160

–155

–150

–145

–140

–135

–130

–125

–120

–115

–

110

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

PHASE NO I SE ( d Bc/ Hz)

08462-010

Figure 9. Phase Noise at LVPECL, 156.25 MHz Clock Output

–160

–155

–150

–145

–140

–135

–130

–125

–120

–115

–

110

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

PHASE NOISE (dBc/Hz)

08462-011

Figure 10. Phase Noise at LVPECL, 159.375 MHz Clock Output

AD9575

Rev. A | Page 10 of 16

–160

–155

–150

–145

–140

–135

–130

–125

–120

–115

–

110

1k 10k 100k 1M 10M 100M

FRE QUENC Y ( Hz )

PHASE NOISE (dBc/Hz)

08462-027

Figure 11. Phase Noise at LVPECL, 161.13 MHz Clock Output

–160

–155

–150

–145

–140

–135

–130

–125

–120

–115

–

110

1k 10k 100k 1M 10M 100M

FRE QUENC Y ( Hz )

PHASE NOISE (dBc/ Hz )

08462-012

Figure 12. Phase Noise at LVPECL, 312.5 MHz Clock Output

08462-021

100

110

120

130

140

SUPPLY CURRENT (mA)

80 1234

MODE

5678

LVPECL

LVDS

Figure 13. Typical Supply Current vs. Mode (see Table 12)

M2 50mV 2n s

M3 50mV 2n s

08462-022

Figure 14. 156.25 MHz LVDS Output

M2 100mV 1 ns

M3 100mV 1 ns

8462-023

Figure 15. 312.5 MHz LVPECL Output

M2 100mV 1 0ns

M3 100mV 1 0ns

08462-024

Figure 16. 62.5 MHz LVCMOS Output

AD9575

Rev. A | Page 11 of 16

TERMINOLOGY

Phase Jitter

An ideal sine wave can be thought of as having a continuous

and even progression of phase with time from 0° to 360° for

each cycle. Actual signals, however, display a certain amount of

variation from ideal phase progression over time. This phenom-

enon is called phase jitter. Although many causes can contribute

to phase jitter, one major cause is random noise, which is charac-

terized statistically as Gaussian (normal) in distribution.

This phase jitter leads to a spreading out of the energy of the

sine wave in the frequency domain, producing a continuous

power spectrum. This power spectrum is usually reported as

a series of values whose units are dBc/Hz at a given offset in

frequency from the sine wave (carrier). The value is a ratio

(expressed in decibels) of the power contained within a 1 Hz

bandwidth with respect to the power at the carrier frequency.

For each measurement, the offset from the carrier frequency

is also given.

Phase Noise

It is meaningful to integrate the total power contained within

some interval of offset frequencies (for example, 10 kHz to

10 MHz). This is called the integrated phase noise over that

frequency offset interval and can be readily related to the time

jitter due to the phase noise within that offset frequency interval.

Phase noise has a detrimental effect on error rate performance

by increasing eye closure at the transmitter output and reducing

the jitter tolerance/sensitivity of the receiver.

Time Jitter

Phase noise is a frequency domain phenomenon. In the time

domain, the same effect is exhibited as time jitter. When

observing a sine wave, the time of successive zero crossings is

seen to vary. In a square wave, the time jitter is seen as a

displacement of the edges from their ideal (regular) times of

occurrence. In both cases, the variations in timing from the

ideal are the time jitter. Because these variations are random in

nature, the time jitter is specified in units of seconds root mean

square (rms) or 1 sigma of the Gaussian distribution.

Additive Phase Noise

Additive phase noise is the amount of phase noise that is attrib-

utable to the device or subsystem being measured. The phase

noise of any external oscillators or clock sources is subtracted.

This makes it possible to predict the degree to which the device

affects the total system phase noise when used in conjunction

with the various oscillators and clock sources, each of which

contributes its own phase noise to the total. In many cases, the

phase noise of one element dominates the system phase noise.

Additive Time Jitter

Additive time jitter is the amount of time jitter that is attribut-

able to the device or subsystem being measured. The time jitter

of any external oscillators or clock sources is subtracted. This

makes it possible to predict the degree to which the device affects

the total system time jitter when used in conjunction with the

various oscillators and clock sources, each of which contributes

its own time jitter to the total. In many cases, the time jitter of

the external oscillators and clock sources dominates the system

time jitter.

AD9575

Rev. A | Page 12 of 16

THEORY OF OPERATION

XTAL

OSC

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

1/n 1/k

SEL

LVCMOS

CMOS OUT/SEL1

DDX GNDX

GNDA

DD_CMOS GND_CMOS

SEL0

1/m

VLDO

2.488GHz TO

2.55GHz V CO LVDS

100MHz

AD9575

08462-015

LDO

LVDS/LVPECL OUT

Figure 17. Detailed Block Diagram

Figure 17 shows a block diagram of the AD9575. The chip features

a PLL core, which is configured to generate the specific clock

frequencies via pin programming. By appropriate connection of

the select pins, SEL0 and SEL1, the divide ratios of the feedback

divider (n), LVDS output divider (m), and LVCMOS output

divider (k) can be programmed (see Table 1 2). In Mode 1 and

Mode 4, Pin 10 is configured as an LVCMOS output by forcing

Pin 16 to GND (33.33 MHz output) or by leaving Pin 16 uncon-

nected (62.5 MHz output). In conjunction with a band-select

VCO that operates over the range of 2.488 GHz to 2.55 GHz,

a wide range of popular network reference frequencies can

be generated. This PLL is based on proven Analog Devices

synthesizer technology, noted for its exceptional phase noise

performance. The AD9575 is highly integrated and includes

the loop filter, a regulator for supply noise immunity, all the

necessary dividers, output buffers, and a crystal oscillator. A

user need only supply an external crystal to implement a

clocking solution that requires no processor intervention.

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

The PFD takes inputs from the reference clock and feedback

divider to produce an output proportional to the phase and

frequency difference between them. Figure 18 shows a

simplified schematic.

08462-016

D1 Q1

CLR1

REFCLK

HIGH UP

D2 Q2

CLR2

HIGH DOWN

CHARGE

PUMP

GND

FEEDBACK

DIVIDER

Figure 18. PFD Simplified Schematic

POWER SUPPLY

The AD9575 requires a 3.3 V ± 10% power supply for VS. The

Specifications section gives the performance expected from the

AD9575 with the power supply voltage within this range. The

absolute maximum range of −0.3 V to +3.6 V, with respect to

GND, must never be exceeded on the VDD, VDDA, VDDX,

and VDD_CMOS pins.

Good engineering practice should be followed in the layout

of power supply traces and the ground plane of the PCB. The

power supply should be bypassed on the PCB with adequate

capacitance (>10 μF). The AD9575 should be bypassed with

adequate capacitors (0.1 μF) at all power pins as close as possible

to the part. The layout of the AD9575 evaluation board is a

good example.

LVPECL CLOCK DISTRIBUTION

Because they are open emitter, the LVPECL outputs require

a dc termination to bias the output transistors. The simplified

equivalent circuit in Figure 19 shows the LVPECL output stage.

08462-026

LVPECL

TERM

LVPECL

50Ω50Ω

50Ω

0.1µF

200Ω200Ω

Figure 19. LVPECL AC-Coupled Termination

In most applications, a standard LVPECL far-end termination is

recommended, as shown in Figure 20. The resistor network is

designed to match the transmission line impedance (50 Ω) and

the desired switching threshold (1.3 V).

AD9575

Rev. A | Page 13 of 16

3.3V 50Ω

50Ω

SINGLE-ENDED

(NO T CO UP L E D)

3.3V

LVPECL

127Ω127Ω

83Ω83Ω

08462-025

= V

– 1.3 V

LVPECL

Figure 20. LVPECL Far-End Termination

LVDS CLOCK DISTRIBUTION

The AD9575 is also available with low voltage differential

signaling (LVDS) outputs. LVDS uses a current mo de output

stage with a factory programmed current level. The normal

value (default) for this current is 3.5 mA, which yields a 350 mV

output swing across a 100 Ω resistor. The LVDS outputs meet or

exceed all ANSI/TIA/EIA-644 specifications.

A recommended termination circuit for the LVDS outputs is

shown in Figure 21.

50Ω

LVDS LVDS

100Ω

8462-017

Figure 21. LVDS Output Termination

See the AN-586 Application Note on the Analog Devices

website at www.analog.com for more information about LVDS.

LVCMOS CLOCK DISTRIBUTION

The AD9575 provides a 33.33 MHz or 62.5 MHz clock output,

which is a dedicated LVCMOS level. Whenever single-ended

LVCMOS clocking is used, some of the following general guide-

lines should be followed.

Point-to-point nets should be designed such that a driver has

only one receiver on the net, if possible. This allows for simple

termination schemes and minimizes ringing due to possible

mismatched impedances on the net. Series termination at the

source is generally required to provide transmission line

matching and/or to reduce current transients at the driver (see

Figure 22). The value of the resistor is dependent on the board

design and timing requirements (typically 10 Ω to 100 Ω is

used). LVCMOS outputs are limited in terms of the capacitive

load or trace length that they can drive. Typically, trace lengths

less than 6 inches are recommended to preserve signal rise/fall

times and preserve signal integrity.

10Ω

MICROSTRIP

GND

5pF

60.4

Ω

1.0 INCH

CMOS

08462-018

Figure 22. Series Termination of LVCMOS Output

Termination at the far end of the PCB trace is a second option.

The LVCMOS output of the AD9575 does not supply enough

current to provide a full voltage swing with a low impedance

resistive, far-end termination, as shown in Figure 23. The far-end

termination network should match the PCB trace impedance

and provide the desired switching point.

The reduced signal swing may still meet receiver input

requirements in some applications. This can be useful when

driving long trace lengths on less critical nets.

50Ω

10Ω

PULLUP = 3.3

LVCMOS 3pF

100Ω

8462-019

Figure 23. LVCMOS Output with Far-End Termination

TYPICAL APPLICATION CIRCUIT

VDDA

VDDX

XO1

GNDA

GNDX

XO2

GNDA

VDDA

GND

LVDS/LVPECL OUT

CMOS OUT/SEL1

GND_CMOS

VDD_CMOS

VDD

SEL0

AD9575

50ΩR

100Ω

50Ω

1nF0.1µF

0.1µF 0.1µF

0.1µF

Cx1 = 22pF

Cx2 = 22pF V

08462-028

Figure 24. Typical Application Circuit (in LVDS Configuration)

AD9575

Rev. A | Page 14 of 16

OUTLINE DIMENSIONS

16 9

PIN 1

SEATING

PLANE

8°

0°

4.50

4.40

4.30

6.40

BSC

5.10

5.00

4.90

0.65

BSC

0.15

0.05

1.20

MAX 0.20

0.09 0.75

0.60

0.45

0.30

0.19

COPLANARITY

0.10

COM PLI ANT T O JEDEC S TANDARDS MO-153-AB

Figure 25. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

ORDERING GUIDE

Model1Temperature Range Package Description Package Option

AD9575ARUZLVD −40°C to +85°C 16-Lead Thin Shrink Small Outline Package (TSSOP), 96 pcs per Tube,

LVDS Output Format

RU-16

AD9575ARUZPEC −40°C to +85°C 16-Lead Thin Shrink Small Outline Package (TSSOP), 96 pcs per Tube,

LVPECL Output Format

RU-16

AD9575-EVALZ-LVD LVDS Outputs, Evaluation Board

AD9575-EVALZ-PEC LVPECL Outputs, Evaluation Board

1 Z = RoHS Compliant Part.

AD9575

Rev. A | Page 15 of 16

NOTES

AD9575

Rev. A | Page 16 of 16

NOTES

registered trademarks are the property of their respective owners.

D08462-0-3/10(A)