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DRail-To-Rail Input/Output
DWide Bandwidth ...3 MHz
DHigh Slew Rate . . . 2.4 V/µs
DSupply Voltage Range . . . 2.7 V to 16 V
DSupply Current . . . 550 µA/Channel
DLow Power Shutdown Mode
IDD(SHDN) ... 25 µA/Channel
DInput Noise Voltage . . . 39 nV/√Hz
DInput Bias Current...1 pA
DSpecified Temperature Range
−40°C to 125°C . . . Industrial Grade
DUltrasmall Packaging
5 or 6 Pin SOT-23 (TLV2370/1)
8 or 10 Pin MSOP (TLV2372/3)
description
The TLV237x single supply operational amplifiers provide rail-to-rail input and output capability. The TLV237x
takes the minimum operating supply voltage down to 2.7 V over the extended industrial temperature range while
adding the rail-to-rail output swing feature. The TLV237x also provides 3-MHz bandwidth from only 550 µA. The
maximum recommended supply voltage is 16 V, which allows the devices to be operated from (±8 V supplies
down to ±1.35 V) a variety of rechargeable cells.
The CMOS inputs enable use in high-impedance sensor interfaces, with the lower voltage operation making
an ideal alternative for the TLC227x in battery-powered applications. The rail-to-rail input stage further
increases its versatility. The TLV237x is the seventh member of a rapidly growing number of RRIO products
available from TI, and it is the first to allow operation up to 16-V rails with good ac performance.
All members are available in PDIP and SOIC with the singles in the small SOT-23 package, duals in the MSOP,
and quads in the TSSOP package.
The 2.7-V operation makes the TLV237x compatible with Li-Ion powered systems and the operating supply
voltage range of many micro-power microcontrollers available today including TI’s MSP430.
SELECTION OF SIGNAL AMPLIFIER PRODUCTS†
DEVICE VDD (V) VIO
(µV) Iq/Ch
(µA) IIB (pA) GBW
(MHz) SR
(V/µs) SHUTDOWN RAIL-
TO-
RAIL SINGLES/DUALS/QUADS
TLV237x 2.7−16 500 550 1 3 2.4 Yes I/O S/D/Q
TLC227x 4−16 300 1100 1 2.2 3.6 — O D/Q
TLV27x 2.7−16 500 550 1 3 2.4 — O S/D/Q
TLC27x 3−16 1100 675 1 1.7 3.6 — — S/D/Q
TLV246x 2.7−6 150 550 1300 6.4 1.6 Yes I/O S/D/Q
TLV247x 2.7−6 250 600 2 2.8 1.5 Yes I/O S/D/Q
TLV244x 2.7−10 300 725 1 1.8 1.4 — O D/Q
†Typical values measured at 5 V, 25°C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
!"#$%&'(!$" !) *+%%,"( ') $# -+./!*'(!$" 0'(,1
%$0+*() *$"#$%& ($ )-,*!#!*'(!$") -,% (, (,%&) $# ,2') ")(%+&,"()
)('"0'%0 3'%%'"(41 %$0+*(!$" -%$*,))!"5 0$,) "$( ",*,))'%!/4 !"*/+0,
(,)(!"5 $# '// -'%'&,(,%)1
Copyright 2001−2005, Texas Instruments Incorporated
Operational Amplifier
−
+
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SLOS270D − MARCH 2001 − REVISED JANUAR Y 2005
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FAMILY PACKAGE TABLE(1)
DEVICE
NUMBER OF
PACKAGE TYPES
SHUTDOWN
UNIVERSAL
DEVICE
NUMBER OF
CHANNELS PDIP SOIC SOT-23 TSSOP MSOP
SHUTDOWN
UNIVERSAL
EVM BOARD
TLV2370 1 8 8 6 — — Yes
TLV2371 1 8 8 5 — — —
Refer to the EVM
TLV2372 2 8 8 — — 8 — Refer to the EVM
Selection Guide
TLV2373 2 14 14 — — 10 Yes
Selection Guide
(Lit# SLOU060)
TLV2374 4 14 14 — 14 — —
(Lit# SLOU060)
TLV2375 4 16 16 — 16 — Yes
TLV2370 and TLV2371 AVAILABLE OPTIONS(1)
VIOMAX AT
PACKAGED DEVICES
T
A
VIOMAX AT
25
°
C
SMALL OUTLINE
†
SOT-23
PLASTIC DIP
TA
25°C
SMALL OUTLINE
(D)†(DBV)‡SYMBOL
PLASTIC DIP
(P)
−40°C to 125°C4.5 mV TLV2370ID
TLV2371ID TLV2370IDBV
TLV2371IDBV VBFI
VBGI TLV2370IP
TLV2371IP
†This package is available taped and reeled. To order this packaging option, add an R suf fix to the part number (e.g., TLV2370IDR).
‡This package is only available taped and reeled. For standard quantities (3,000 pieces per reel), add an R suffix (e.g., TLV2370IDBVR). For
smaller quantities (250 pieces per mini-reel), add a T suf fix to the part number (e.g., TLV2370IDBVT).
TLV2372 AND TLV2373 AVAILABLE OPTIONS(1)
PACKAGED DEVICES
T
A
VIOMAX AT
25
°
C
SMALL
OUTLINE
MSOP PLASTIC
DIP
PLASTIC
DIP
TA
25°C
OUTLINE
(D)§(DGK)§SYMBOL (DGS)§SYMBOL
DIP
(N)
DIP
(P)
−40°C
to
125°C4.5 mV TLV2372ID
TLV2373ID TLV2372IDGK
—APG
——
TLV2373IDGS —
API —
TLV2373IN TLV2372IP
—
§This package is available taped and reeled. To order this packaging option, add an R suf fix to the part number (e.g., TLV2372IDR).
TLV2374 and TLV2375 AVAILABLE OPTIONS(1)
VIOMAX AT
PACKAGED DEVICES
TAVIOMAX AT
25°CSMALL OUTLINE
(D)¶PLASTIC DIP
(N) TSSOP
(PW)¶
−40°C to 125°C4.5 mV TLV2374ID
TLV2375ID TLV2374IN
TLV2375IN TLV2374IPW
TLV2375IPW
¶This package is available taped and reeled. To order this packaging option, add an R suf fix to the part number
(e.g., TLV2374IDR).
1. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website
at www.ti.com.
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TLV237x PACKAGE PINOUTS(1)
(TOP VIEW)
TLV2375
D, N, OR PW PACKAGE
1
2
3
4
5
10
9
8
7
6
1OUT
1IN−
1IN+
GND
1SHDN
VDD
2OUT
2IN−
2IN+
2SHDN
3
2
4
5
(TOP VIEW)
1
OUT
GND
IN+
VDD
IN−
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN−
1IN+
GND
NC
1SHDN
NC
VDD
2OUT
2IN−
2IN+
NC
2SHDN
NC
(TOP VIEW)
TLV2371
DBV PACKAGE
3
2
4
6
(TOP VIEW)
1
OUT
GND
IN+
VDD
IN−
TLV2370
DBV PACKAGE
5SHDN
1
2
3
4
8
7
6
5
NC
IN−
IN+
GND
SHDN
VDD
OUT
NC
TLV2370
D OR P PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
NC
IN−
IN+
GND
NC
VDD
OUT
NC
TLV2371
D OR P PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
GND
VDD
2OUT
2IN−
2IN+
TLV2372
D, DGK, OR P PACKAGE
(TOP VIEW)
TLV2373
DGS PACKAGE
(TOP VIEW)
TLV2373
D OR N PACKAGE
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN−
1IN+
VDD
2IN+
2IN−
2OUT
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
(TOP VIEW)
TLV2374
D, N, OR PW PACKAGE
NC − No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1OUT
1IN−
1IN+
VDD+
2IN+
2IN−
2OUT
1/2SHDN
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
3/4SHDN
TYPICAL PIN 1 INDICATORS
Printed or
Molded Dot Bevel Edges
Pin 1
Molded “U” Shape
Pin 1
Stripe Pin 1 Pin 1
NOTE: (1) If there is not a Pin 1 indicator, turn device to enable reading the symbol from the left to right. Pin 1 is at the lower left corner of the
device.
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) 16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID ±VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.2 V to VDD + 0.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current range, II ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current range, IO ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: I-suffix −40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltage values, except differential voltages, are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE θJC
(°C/W) θJA
(°C/W) TA ≤ 25°C
POWER RATING
D (8) 38.3 176 710 mW
D (14) 26.9 122.3 1022 mW
D (16) 25.7 114.7 1090 mW
DBV (5) 55 324.1 385 mW
DBV (6) 55 294.3 425 mW
DGK (8) 54.23 259.96 481 mW
DGS (10) 54.1 257.71 485 mW
N (14, 16) 32 78 1600 mW
P (8) 41 104 1200 mW
PW (14) 29.3 173.6 720 mW
PW (16) 28.7 161.4 774 mW
recommended operating conditions
MIN MAX UNIT
Supply voltage, VDD
Single supply 2.7 16
V
Supply voltage, VDD Split supply ±1.35 ±8V
Common-mode input voltage range, VICR 0 VDD V
Operating free-air temperature, TAI-suffix −40 125 °C
Turnon voltage level, V(ON), relative to GND pin voltage 2 V
Turnoff voltage level, V(OFF), relative to GND pin voltage 0.8 V
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electrical characteristics at specified free-air temperature, VDD = 2.7 V, 5 V, and 15 V (unless
otherwise noted)
dc performance
PARAMETER TEST CONDITIONS TAMIN TYP MAX UNIT
VIO
Input offset voltage
VIC = VDD/2,
VO = VDD/2,
25°C 2 4.5
mV
VIO Input offset voltage VIC = VDD/2,
RS = 50 Ω
VO = VDD/2, Full range 6mV
VIO
Offset voltage drift
RS = 50 Ω
25°C
2
V/°C
α
VIO
Offset voltage drift
RS = 50
25°C 2 µV/°C
VIC = 0 to VDD,
25°C 50 68
VIC = 0 to VDD,
RS = 50 Ω
VDD = 2.7 V
Full range 49
VIC = 0 to VDD−1.35V,
VDD = 2.7 V 25°C 56 70
VIC = 0 to VDD−1.35V,
RS = 50 ΩFull range 54
VIC = 0 to VDD,
25°C 55 72
CMRR
Common-mode rejection ratio
VIC = 0 to VDD,
RS = 50 Ω,
VDD = 5 V
Full range 54
dB
CMRR Common-mode rejection ratio
VIC = 0 to VDD−1.35V,
VDD = 5 V 25°C 67 80 dB
VIC = 0 to VDD−1.35V,
RS = 50 Ω,Full range 64
VIC = 0 to VDD,
25°C 64 82
VIC = 0 to VDD,
RS = 50 Ω,
VDD = 15 V
Full range 63
VIC = 0 to VDD−1.35V,
VDD = 15 V 25°C 67 84
VIC = 0 to VDD−1.35V,
RS = 50 Ω,Full range 66
VDD = 2.7 V
25°C 98 106
VDD = 2.7 V Full range 76
AVD
Large-signal differential voltage
VO(PP) = VDD/2,
VDD = 5 V
25°C 100 110
dB
AVD
Large-signal differential voltage
amplification
VO(PP) = VDD/2,
RL = 10 kΩVDD = 5 V Full range 86 dB
amplification
RL = 10 k
VDD = 15 V
25°C 81 83
VDD = 15 V Full range 79
input characteristics
PARAMETER TEST CONDITIONS TAMIN TYP MAX UNIT
25°C 1 60
I
IO
Input offset current 70°C 100 pA
IIO
Input offset current
VDD = 15 V, VIC = VDD/2,
125°C 1000
pA
VDD = 15 V, VIC = VDD/2,
VO = VDD/2 25°C 1 60
I
IB
Input bias current
VO = VDD/2
70°C 100 pA
IIB
Input bias current
125°C 1000
pA
ri(d) Differential input resistance 25°C 1000 GΩ
CIC Common-mode input capacitance f = 21 kHz 25°C 8 pF
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electrical characteristics at specified free-air temperature, VDD = 2.7 V, 5 V, and 15 V (unless
otherwise noted) (continued)
output characteristics
PARAMETER TEST CONDITIONS TAMIN TYP MAX UNIT
VDD = 2.7 V
25°C 2.55 2.58
VDD = 2.7 V Full range 2.48
VIC = VDD/2, IOH = −1 mA
VDD = 5 V
25°C 4.9 4.93
VIC = VDD/2, IOH = −1 mA VDD = 5 V Full range 4.85
VDD = 15 V
25°C 14.92 14.96
VOH
High-level output voltage
VDD = 15 V Full range 14.9
V
VOH High-level output voltage
VDD = 2.7 V
25°C 1.9 2 V
VDD = 2.7 V Full range 1.6
VIC = VDD/2, IOH = −5 mA
VDD = 5 V
25°C 4.6 4.68
VIC = VDD/2, IOH = −5 mA VDD = 5 V Full range 4.5
VDD = 15 V
25°C 14.7 14.8
VDD = 15 V Full range 14.6
VDD = 2.7 V
25°C 0.1 0.15
VDD = 2.7 V Full range 0.22
VIC = VDD/2, IOL = 1 mA
VDD = 5 V
25°C 0.05 0.1
VIC = VDD/2, IOL = 1 mA VDD = 5 V Full range 0.15
VDD = 15 V
25°C 0.05 0.08
VOL
Low-level output voltage
VDD = 15 V Full range 0.1
V
VOL Low-level output voltage
VDD = 2.7 V
25°C 0.52 0.7 V
VDD = 2.7 V Full range 1.1
VIC = VDD/2, IOL = 5 mA
VDD = 5 V
25°C 0.28 0.4
VIC = VDD/2, IOL = 5 mA VDD = 5 V Full range 0.5
VDD = 15 V
25°C 0.19 0.3
VDD = 15 V Full range 0.35
VDD = 2.7 V, VO = 0.5 V from rail
Positive rail 25°C 4
V
DD
= 2.7 V, V
O
= 0.5 V from rail
Negative rail 25°C 5
IO
Output current
VDD = 5 V, VO = 0.5 V from rail
Positive rail 25°C 7
mA
I
O
Output current
V
DD
= 5 V, V
O
= 0.5 V from rail
Negative rail 25°C 8
mA
VDD = 15 V, VO = 0.5 V from rail
Positive rail 25°C 16
V
DD
= 15 V, V
O
= 0.5 V from rail
Negative rail 25°C 15
power supply
PARAMETER TEST CONDITIONS TAMIN TYP MAX UNIT
VDD = 2.7 V 25°C 470 560
IDD
Supply current (per channel)
VO = VDD/2,
VDD = 5 V 25°C 550 660
µA
I
DD
Supply current (per channel)
V
O
= V
DD
/2,
VDD = 15 V
25°C 750 900 µ
A
V
DD
= 15 V
Full range 1200
PSRR
Supply voltage rejection ratio
VDD = 2.7 V to 15 V,
VIC = VDD/2,
25°C 70 80
dB
PSRR
Supply voltage rejection ratio
(∆VDD /∆VIO)
VDD = 2.7 V to 15 V,
No load
VIC = VDD/2,
Full range 65 dB
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electrical characteristics at specified free-air temperature, VDD = 2.7 V, 5 V, and 15 V (unless
otherwise noted) (continued)
dynamic performance
PARAMETER TEST CONDITIONS TAMIN TYP MAX UNIT
UGBW
Unity gain bandwidth
RL = 2 k
Ω
,
VDD = 2.7 V 25°C 2.4
MHz
UGBW Unity gain bandwidth
RL = 2 kΩ
,
CL = 10 pF VDD = 5 V to 15 V 25°C 3 MHz
VDD = 2.7 V
25°C1.4 2
V/ s
V = V /2,
VDD = 2.7 V Full range 1V/µs
SR
Slew rate at unity gain
VO(PP) = VDD/2,
CL = 50 pF,
VDD = 5 V
25°C1.6 2.4
V/ s
SR Slew rate at unity gain
O(PP) DD
C
L
= 50 pF,
RL = 10 k
ΩVDD = 5 V Full range 1.2 V/µs
RL = 10 kΩ
VDD = 15 V
25°C1.9 2.1
V/ s
VDD = 15 V Full range 1.4 V/µs
φmPhase margin RL = 2 kΩ, CL = 100 pF 25°C 65°
Gain margin RL = 2 kΩ, CL = 10 pF 25°C 18 dB
ts
Settling time
VDD = 2.7 V,
V(STEP)PP = 1 V, AV = −1,
CL = 10 pF, RL = 2 kΩ0.1%
25°C
2.9
s
tsSettling time VDD = 5 V, 15 V,
V(STEP)PP = 1 V, AV = −1,
CL = 47 pF, RL = 2 kΩ0.1%
25°C
2
µs
noise/distortion performance
PARAMETER TEST CONDITIONS TAMIN TYP MAX UNIT
VDD = 2.7 V,
AV = 1 0.02%
VDD = 2.7 V,
V
O(PP)
= V
DD
/2 V,
R = 2 k , f = 10 kHz
AV = 10 25°C0.05%
THD + N
Total harmonic distortion plus noise
VO(PP) = VDD/2 V,
RL = 2 kΩ, f = 10 kHz AV = 100
25 C
0.18%
THD + N Total harmonic distortion plus noise
VDD = 5 V, 15 V,
AV = 1 0.02%
VDD = 5 V, 15 V,
V
O(PP)
= V
DD
/2 V,
R = 2 k , f = 10 kHz
AV = 10 25°C0.09%
VO(PP) = VDD/2 V,
RL = 2 kΩ, f = 10 kHz AV = 100
25 C
0.5%
Vn
Equivalent input noise voltage
f = 1 kHz
25°C
39
nV/√Hz
VnEquivalent input noise voltage f = 10 kHz 25°C35
nV/√Hz
InEquivalent input noise current f = 1 kHz 25°C 0.6 fA/√Hz
shutdown characteristics
PARAMETER TEST CONDITIONS TAMIN TYP MAX UNIT
VDD = 2.7 V, 5 V,
25°C 25 30
A
IDD(SHDN)
Supply current in shutdown mode (TLV2370,
VDD = 2.7 V, 5 V,
SHDN = 0 V Full range 35 µA
IDD(SHDN
)
Supply current in shutdown mode (TLV2370,
TLV2373, TLV2375) (per channel)
VDD = 15 V,
25°C 40 45
A
TLV2373, TLV2375) (per channel)
VDD = 15 V,
SHDN = 0 V Full range 50 µA
t(on) Amplifier turnon time (see Note 2)
RL = 2 kΩ
25°C 0.8 µs
t(off) Amplifier turnoff time (see Note 2)
R
L
= 2 k
Ω25°C 1 µs
NOTE: Disable time and enable time are defined as the interval between application of the logic signal to the SHDN terminal and the point at
which the supply current has reached one half of its final value.
µ
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Input offset voltage vs Common-mode input voltage 1, 2, 3
CMRR Common-mode rejection ratio vs Frequency 4
Input bias and offset current vs Free-air temperature 5
VOL Low-level output voltage vs Low-level output current 6, 8, 10
VOH High-level output voltage vs High-level output current 7, 9, 11
VO(PP) Peak-to-peak output voltage vs Frequency 12
IDD Supply current vs Supply voltage 13
PSRR Power supply rejection ratio vs Frequency 14
AVD Differential voltage gain & phase vs Frequency 15
Gain-bandwidth product vs Free-air temperature 16
SR
Slew rate
vs Supply voltage 17
SR Slew rate vs Free-air temperature 18
φmPhase margin vs Capacitive load 19
VnEquivalent input noise voltage vs Frequency 20
Voltage-follower large-signal pulse response 21, 22
Voltage-follower small-signal pulse response 23
Inverting large-signal response 24, 25
Inverting small-signal response 26
Crosstalk vs Frequency 27
Shutdown forward & reverse isolation vs Frequency 28
IDD(SHDN) Shutdown supply current vs Supply voltage 29
IDD(SHDN) Shutdown pin leakage current vs Shutdown pin voltage 30
IDD(SHDN) Shutdown supply current/output voltage vs Time 31, 32
µ
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TYPICAL CHARACTERISTICS
Figure 1
−200
0
200
400
600
800
1000
0 0.4 0.8 1.2 1.6 2 2.4 2.7
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
VDD = 2.7 V
TA = 25°C
VICR − Common-Mode Input Voltage − V
VIO − Input Offset Voltage − V
µ
Figure 2
−200
0
200
400
600
800
1000
012345
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
VICR − Common-Mode Input Voltage − V
VIO − Input Offset Voltage − V
µ
VDD = 5 V
TA = 25 °C
Figure 3
−200
0
200
400
600
800
1000
0246810121415
INPUT OFFSET VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
VICR − Common-Mode Input Voltage −V
VIO − Input Offset Voltage − V
µ
VDD =15 V
TA = 25 °C
Figure 4
0
20
40
60
80
100
120
10 100 1 k 10 k 100 k 1 M
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
f − Frequency − Hz
CMRR − Common-Mode Rejection Ratio − dB
VDD = 5 V, 15 V
VDD = 2.7 V
Figure 5
−50
0
50
100
150
200
250
300
−40−25 −10 5 20 35 50 65 80 95 110 125
VDD = 2.7 V, 5 V and 15 V
VIC = VDD/2
TA − Free-Air Temperature − °C
INPUT BIAS/OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
IIB − Input Bias / Offset Current − pA
/IIO
Figure 6
0
0.40
0.80
1.20
1.60
2
2.40
2.80
0 2 4 6 8 10 12 14 16 18 20 22 24
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
IOL − Low-Level Output Current − mA
VDD = 2.7 V
OL
V − Low-Level Output Voltage − V
TA = 25 °C
TA = 125 °C
TA = 70 °C
TA = 0 °C
TA = −40 °C
Figure 7
0
0.40
0.80
1.20
1.60
2
2.40
2.80
0123456789101112
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
IOH − High-Level Output Current − mA
VOH − High-Level Output Voltage − V
VDD = 2.7 V
TA = 125°C
TA = 70°C
TA = 25°C
TA = 0°C
TA =−40°C
Figure 8
0
0.50
1
1.50
2
2.50
3
3.50
4
4.50
5
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
IOL − Low-Level Output Current − mA
VDD = 5 V
OL
V − Low-Level Output Voltage − V
TA = 125 °C
TA = 70 °C
TA = 25 °C
TA = 0 °C
TA = −40 °C
Figure 9
0
0.50
1
1.50
2
2.50
3
3.50
4
4.50
5
0 5 10 15 20 25 30 35 40 45
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
IOH − High-Level Output Current − mA
VOH − High-Level Output Voltage − V
VCC = 5 V
TA = −40°C
TA = 0°C
TA = 25°C
TA = 70°C
TA = 125°C
µ
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TYPICAL CHARACTERISTICS
Figure 10
0
2
4
6
8
10
12
14
15
020 40 60 80 100 120 140 160
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
IOL − Low-Level Output Current − mA
VDD = 15 V
OL
V − Low-Level Output Voltage − V
TA =125°C
TA =70°C
TA =25°C
TA =0°C
TA =−40°C
Figure 11
0
2
4
6
8
10
12
14
15
0 20 40 60 80 100 120 140 160
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
IOH − High-Level Output Current − mA
VOH − High-Level Output Voltage − V
VDD = 15 V
TA = −40°C
TA = 0°C
TA = 25°C
TA = 70°C
TA = 125°C
Figure 12
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
10 100 1 k 10 k 100 k 1 M 10 M
PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
f − Frequency − Hz
− Peak-to-Peak Output Voltage − V
VO(PP)
AV = −10
RL = 2 kΩ
CL = 10 pF
TA = 25°C
THD = 5%
VDD = 15 V
VDD = 5 V
VDD = 2.7 V
Figure 13
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
VCC − Supply Voltage − V
DD
I Supply Current − − mA/Ch
AV = 1
VIC = VDD / 2 TA = 125°C
TA = 70°C
TA = 25°C
TA = 0°C
TA = −40°C
Figure 14
0
20
40
60
80
100
120
10 100 1 k 10 k 100 k 1 M
VDD = 5 V, 15 V
TA = 25°C
VDD = 2.7 V
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
f − Frequency − Hz
PSRR − Power Supply Rejection Ratio − dB
Figure 15
−40
−20
0
20
40
60
80
100
120
10 100 1 k 10 k 100 k 1 M 10 M
−180
−135
−90
−45
0
45
90
135
180
DIFFERENTIAL VOLTAGE GAIN AND PHASE
vs
FREQUENCY
f − Frequency − Hz
− Differential Voltage Gain − dB
Phase − °
VDD=5 Vdc
RL=2 kΩ
CL=10 pF
TA=25°C
AVD
Phase
Gain
Figure 16
0
0.5
1
1.5
2
2.5
3
3.5
4
−40−25−10 5 20 35 50 65 80 95 110 125
GAIN BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE
GBWP − Gain Bandwidth Product − MHz
TA − Free-Air Temperature − °C
VDD = 15 V
VDD = 2.7 V
VDD = 5 V
µ
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TYPICAL CHARACTERISTICS
Figure 17
0
0.5
1
1.5
2
2.5
3
2.5 4.5 6.5 8.5 10.5 12.5 14.5
SLEW RATE
vs
SUPPLY VOLTAGE
SR − Slew Rate − V/ s
VCC − Supply Voltage −V
AV = 1
RL = 10 kΩ
CL = 50 pF
TA = 25°C
SR−
SR+
µ
Figure 18
0
0.5
1
1.5
2
2.5
3
3.5
−40 −25−10 5 20 35 50 65 80 95 110 125
SLEW RATE
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
SR+
SR−
VDD = 5 V
AV = 1
RL = 10 kΩ
CL = 50 pF
VI = 3 V
SR − Slew Rate − V/ s
µ
Figure 19
0
10
20
30
40
50
60
70
80
90
100
10 100 1000
PHASE MARGIN
vs
CAPACITIVE LOAD
CL − Capacitive Load − pF
VDD = 5 V
RL= 2 kΩ
TA = 25°C
AV = Open Loop
Phase Margin − °
Rnull = 100
Rnull = 0
Rnull = 50
Figure 20
0
10
20
30
40
50
60
70
80
90
100
10 100 1 k 10 k 100 k
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
f − Frequency − Hz
nV/ Hz− Equivalent Input Noise Voltage −Vn
VDD = 2.7, 5, 15 V
TA = 25°C
Figure 21
0
1
2
3
4
024681012141618
0
1
2
3
4
VI
t − Time − µs
VDD = 5 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = 3 VPP
TA = 25°C
VI− Input Voltage − V
VO
VO− Output V oltage − V
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE
Figure 22
0
3
6
9
12
024681012141618
0
3
6
9
12
VI
t − Time − µs
VDD = 15 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = 9 VPP
TA = 25°C
VI− Input Voltage − V
VO
VO− Output Voltage − V
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE
Figure 23
0
0.04
0.08
0.12
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
0
0.04
0.08
0.12
VI
t − Time − µs
VDD = 5 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = 100 mVPP
TA = 25°C
VI− Input Voltage − mV
VO
VO− Output V oltage − mV
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE
µ
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TYPICAL CHARACTERISTICS
Figure 24
246810 12 14 16
VI
t − Time − µs
VDD = 5 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = 3 VPP
TA = 25°C
VI− Input Voltage − V
VO
VO− Output V oltage − V
4
3
2
1
0
0
1
2
3
INVERTING LARGE-SIGNAL RESPONSE
20
Figure 25
0246810121416
t − Time − µs
INVERTING LARGE-SIGNAL RESPONSE
VDD = 15 V
AV = −1
RL = 2 kΩ
CL = 10 pF
VI = 9 Vpp
TA = 25°C
VO
− Output Voltage − VVO
VI
− Input Voltage − VVI
12
9
6
3
0
9
6
3
0
Figure 26
0
0.05
0.10
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
0
0.05
0.1
INVERTING SMALL-SIGNAL RESPONSE
VDD = 5 V
AV = −1
RL = 2 kΩ
CL = 10 pF
VI = 100 mVpp
TA = 25°CVO
− Output Voltage − VVO
VI
− Input Voltage − VVI
t − Time − µs
Figure 27
−140
−120
−100
−80
−60
−40
−20
0
10 100 1 k 10 k 100 k
CROSSTALK
vs
FREQUENCY
f − Frequency −Hz
VDD = 2.7, 5, & 15 V
VI = VDD/2
AV = 1
RL = 2 kΩ
TA = 25°C
Crosstalk − dB
Crosstalk in Shutdown
Crosstalk
Figure 28
0
20
40
60
80
100
120
140
160
10 100 1 k 10 k 100 k 1 M 1 M
SHUTDOWN FORWARD AND
REVERSE ISOLATION
vs
FREQUENCY
f − Frequency − Hz
Shutdown Forward and Reverse Isolation − dB
VDD = 2.7 V, 5 V & 15 V
VI = VDD /2
RL = 2 kΩ
CL= 10 pF
AV = 1
TA = 25°C
Figure 29
0
5
10
15
20
25
30
35
40
45
50
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
− Shutdown Supply Current −
SHUTDOWN SUPPLY CURRENT
vs
SUPPLY VOLTAGE
IDD A/Chµ
SHDN = 0 V
VI = VDD/2
AV = 1
VDD − Supply Voltage − V
TA = 125°C
TA = 70°C
TA = 25°C
TA = 0°C
TA = −40°C
Figure 30
0
50
100
150
200
250
0123456789101112131415
SHUTDOWN PIN LEAKAGE CURRENT
vs
SHUTDOWN PIN VOLTAGE
Shutdown Pin Voltage − V
DD
I Shutdown Pin Leakage Current −−pA
TA = 125°C
µ
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TYPICAL CHARACTERISTICS
−1.5
0
1.5
3
4.5
6
7.5
0
2
4
6
8
10
−0.25
0
0.25
0.50
0.75
1
−40 −20 0 20 40 60 80 100 120 140 160
IDD(SHDN = 0)
SHUTDOWN SUPPLY CURRENT/OUTPUT VOLTAGE
vs
TIME
− Supply Current − mA/Ch
IDD SHDN − Shutdown Pulse − V
t − Time − µs
SHDN
VDD = 15 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = VDD/2
TA = 25°C
VO
− Output Voltage − VVO
Figure 31
−1.0
−0.5
0
0.5
1
1.5
2
2.5
−2 −1 0 1 2 3 4 5 6 7 8 9 10
0
1
2
3
4
5
6
−0.25
0
0.25
0.50
0.75
1
IDD(SHDN = 0)
SHUTDOWN SUPPLY CURRENT/OUTPUT VOLTAGE
vs
TIME
− Supply Current − mA/Ch
IDD SHDN − Shutdown Pulse − V
t − Time − µs
SHDN
VDD = 5 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = VDD/2
TA = 25°C
VO
− Output Voltage − VVO
Figure 32
µ
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APPLICATION INFORMATION
rail-to-rail input operation
The TLV237x input stage consists of two differential transistor pairs, NMOS and PMOS, that operate together
to achieve rail-to-rail input operation. The transition point between these two pairs can be seen in Figure 1,
Figure 2, and Figure 3 for a 2.7-V, 5-V, and 15-V supply. As the common-mode input voltage approaches the
positive supply rail, the input pair switches from the PMOS differential pair to the NMOS differential pair. This
transition occurs approximately 1.35 V from the positive rail and results in a change in offset voltage due to
different device characteristics between the NMOS and PMOS pairs. If the input signal to the device is large
enough to swing between both rails, this transition results in a reduction in common-mode rejection ratio
(CMRR). If the input signal does not swing between both rails, it is best to bias the signal in the region where
only one input pair is active. This is the region in Figure 1 through Figure 3 where the of fset voltage varies slightly
across the input range and optimal CMRR can be achieved. This has the greatest impact when operating from
a 2.7-V supply voltage.
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device’s
phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than
10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as shown
in Figure 33. A minimum value of 20 Ω should work well for most applications.
CLOAD
RF
Input Output
RGRNULL
+
−
VDD/2
Figure 33. Driving a Capacitive Load
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
VOO +VIOǒ1)ǒRF
RGǓǓ"IIB)RSǒ1)ǒRF
RGǓǓ"IIB– RF
+
−
VI+
RG
RS
RF
IIB−
VO
IIB+
Figure 34. Output Offset Voltage Model
µ
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APPLICATION INFORMATION
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 35).
VIVO
C1
+
−
RGRF
R1
f–3dB +1
2pR1C1
VO
VI+ǒ1)RF
RGǓǒ1
1)2pfR1C1Ǔ
VDD/2
Figure 35. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
VI
C2
R2R1
C1
RF
RG
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
(
=1
Q
2 − )
RGRF
_
+f–3dB +1
2pRC
VDD/2
Figure 36. 2-Pole Low-Pass Sallen-Key Filter
µ
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APPLICATION INFORMATION
circuit layout considerations
To achieve the levels of high performance o f the TLV237x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
DGround planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
DProper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
DSockets—Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
DShort trace runs/compact part placements—Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier . Its length should be kept as short as possible. This helps to minimize stray capacitance at the
input of the amplifier.
DSurface-mount passive components—Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
shutdown function
Three members of the TLV237x family (TLV2370/3/5) have a shutdown terminal for conserving battery life in
portable applications. When the shutdown terminal is tied low, the supply current is reduced to 25 µA/channel,
the amplifier is disabled, and the outputs are placed in a high impedance mode. To enable the amplifier, the
shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left floating, care
should be taken to ensure that parasitic leakage current at the shutdown terminal does not inadvertently place
the operational amplifier into shutdown.
µ
SLOS270D − MARCH 2001 − REVISED JANUAR Y 2005
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APPLICATION INFORMATION
general power dissipation considerations
For a given θJA, the maximum power dissipation is shown in Figure 37 and is calculated by the following formula:
PD+ǒTMAX–TA
qJA Ǔ
Where: PD= Maximum power dissipation of TLV237x IC (watts)
TMAX= Absolute maximum junction temperature (150°C)
TA= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
1
0.75
0.5
0
−55−40 −25 −10 5
Maximum Power Dissipation − W
1.25
1.5
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
1.75
20 35 50
0.25
TA − Free-Air Temperature − °C
2
65 80 95 110 125
MSOP Package
Low-K Test PCB
θJA = 260°C/W
TJ = 150°C
PDIP Package
Low-K Test PCB
θJA = 104°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
SOT-23 Package
Low-K Test PCB
θJA = 324°C/W
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 37. Maximum Power Dissipation vs Free-Air Temperature
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV2370ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2370IDBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2370IDBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2370IDBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2370IDBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2370IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2370IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2370IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2370IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2370IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2371ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2371IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2371IDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2371IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2371IDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2371IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2371IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2371IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV2371IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2371IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2372ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2372IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2372IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2372IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2372IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2372IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2372IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2372IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2372IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2372IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2373ID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2373IDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2373IDGS ACTIVE MSOP DGS 10 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2373IDGSG4 ACTIVE MSOP DGS 10 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2373IDGSR ACTIVE MSOP DGS 10 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2373IDGSRG4 ACTIVE MSOP DGS 10 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2373IDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV2373IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2373IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2373INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2374ID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2374IDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2374IDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2374IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2374IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2374INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2374IPW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2374IPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2374IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2374IPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2375ID ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2375IDG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2375IDR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2375IDRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2375IN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2375INE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV2375IPW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 4
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV2375IPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2375IPWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV2375IPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV2371, TLV2372, TLV2374 :
•Automotive: TLV2371-Q1, TLV2372-Q1, TLV2374-Q1
•Enhanced Product: TLV2371-EP, TLV2374-EP
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 5
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV2370IDBVR SOT-23 DBV 6 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TLV2370IDBVT SOT-23 DBV 6 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TLV2370IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV2371IDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TLV2371IDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TLV2371IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV2372IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV2372IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV2372IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV2373IDGSR MSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV2373IDGSR MSOP DGS 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV2373IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLV2374IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLV2374IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TLV2375IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TLV2375IPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV2370IDBVR SOT-23 DBV 6 3000 182.0 182.0 20.0
TLV2370IDBVT SOT-23 DBV 6 250 182.0 182.0 20.0
TLV2370IDR SOIC D 8 2500 340.5 338.1 20.6
TLV2371IDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV2371IDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TLV2371IDR SOIC D 8 2500 340.5 338.1 20.6
TLV2372IDGKR VSSOP DGK 8 2500 364.0 364.0 27.0
TLV2372IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0
TLV2372IDR SOIC D 8 2500 340.5 338.1 20.6
TLV2373IDGSR MSOP DGS 10 2500 358.0 335.0 35.0
TLV2373IDGSR MSOP DGS 10 2500 364.0 364.0 27.0
TLV2373IDR SOIC D 14 2500 333.2 345.9 28.6
TLV2374IDR SOIC D 14 2500 333.2 345.9 28.6
TLV2374IPWR TSSOP PW 14 2000 367.0 367.0 35.0
TLV2375IDR SOIC D 16 2500 333.2 345.9 28.6
TLV2375IPWR TSSOP PW 16 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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