ASYNCHRONOUS
SRAM 128K x 24 SRAM
+3.3V SUPPLY, THREE MEGABIT
THREE CHIP ENABLES
GVT73128A24/GVT73128S24
128K X 24 ASYNCHRONOUS SRAM
GALVANTECH, INC.
Galvantech, Inc. reserves the right to change
products or specifications without notice.
Rev. 8/99
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051
Tel (408) 566-0688 Fax (408) 566-0699Web Site www.galvantech.com
FEATURES
•Fast access times: 9, 10, 12 and 15ns
•Fast OE# access times: 4, 5, 6 and 7ns
•Single +3.3V+0.3V power supply
•Fully static -- no clock or timing strobes necessary
•All inputs and outputs are TTL-compatible
•Three state outputs
•Easy memory expansion with CE#, CE1#, CE2 and OE#
options
•Automatic chip deselect power down
•High-performance, low-power consumption, CMOS,
double-metal proces s
•Low profile 100 pin TQFP and 119 bump, 14mm x 22mm
PBGA (Ball Grid Array) packages
•Multiple Ground and VCC pins for maximum noise
immunity
OPTIONSMARKING
•Timing
9ns access -9
10ns access -10
12ns access -12
15ns access -15
•Packages
100-pin TQFP T
119-lead BGA B
•Temperature
Commercial None (0°C to 70°C)
Industrial I (-40°C to 85°C)
GENERAL DESCRIPTION
The GVT73128A24 and GVT73128S24 are organized as
a 131,072 x 24 SRAM using a four-transistor memory cell
with a high performance, silicon gate, low-power CMOS
process. Galvantech SRAMs are fabricated using triple-layer
polysilicon, double-layer metal technology.
This device offers multiple power and ground pins for
improved performance and noise immunity. For increased
system flexibility and eliminating bus contention problems,
this device offers multiple chip enables (CE#, CE1# and
CE2), and output enable (OE#) with this organization. For
GVT73128S24 device in 100-pin TQFP package, separate
byte enables (BE0#, BE1#, and BE2#) are also available to
control individual bytes.
Writing to the device is accomplished by bringing Chip
Enables (CE# and CE1#) and Write Enable (WE#) inputs
LOW and CE2 HIGH. Reading from the device is
accomplished by bringing Chip Enables (CE# and CE1#)
LOW and bringing CE2 and Write Enable (WE#) inputs
HIGH, along with Output Enable (OE#) being asserted LOW.
The device offers a low power standby mode when chip
is not selected. This allows system designers to meet low
standby power requirements.
August 31, 19992Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GVT73128A24/GVT73128S24
128K X 24 ASYNCHRONOUS SRAM
GALVANTECH,
FUNCTIONAL BLOCK DIAGRAM
Note: BE0#, BE1# and BE2# are available for GVT73128S24 only.
CE#
ADDRESS BUFFER
ROW DECODER
COLUMN DECODER
MEMORY ARRAY
128K X 24
I/O BUFFER
DQ0
CONTROL
A16
A0
DQ23
VCC
VSS
CE1#
CE2
BE0#
BE1#
BE2#
WE#
OE#
August 31, 19993Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GVT73128A24/GVT73128S24
128K X 24 ASYNCHRONOUS SRAM
GALVANTECH,
128Kx24, 119-Bump PBGA (Top View) 128Kx24, 100-PIN TQFP (Top View)
Note: BE0#, BE1# and BE2# are available for GVT73128S24 in 100-pin TQFP package only. For GVT73128A24 in
100-pin TQFP package, pin# 47, 48 and 49 are NC.
100-pin TQFP
100 99 98 97 96 95 94 93 92 91 90 89 88
1
2
3
4
5
6
7
8
9
10
31 32 33 34 35 36 37 38 39 40 41 42 43
87 86 85 84 83 82 81
80
79
78
77
76
75
74
73
72
71
70
69
68
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
44 45 46 47 48 49 50
NC
NC
A11
A3
NC
NC
CE#
A4
NC
NC
VSS
CE1#
A16
A5
VCC
NC
VCC
VSS
VSS
VCC
DQ4
DQ5
DQ6
DQ7
VCC
VSS
DQ8
DQ9
VCC
NC
NC
VSS
NC
NC
NC
A10
A9
A8
VSS
VCC
A0
BE1#
BE0#
A2
A1
NC
A7
OE#
WE#
A6
BE2#
NC
A12
A13
A14
A15
CE2
DQ0
DQ1
VSS
VCC
DQ2
DQ3
VCC
VSS
VCC
VSS
NC
DQ10
DQ11
NC
VCC
VSS
VSS
VCC
DQ20
DQ21
DQ22
DQ23
VCC
VSS
DQ12
DQ13
VSS
VCC
NC
NC
DQ16
DQ17
VSS
VCC
DQ18
DQ19
VCC
VSS
VCC
VSS
NC
DQ14
DQ15
1234567
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
NC
NC
NC
NC
A11
A10
A9
CE2
A8
A7
CE#
NC
NC
WE#
OE#
CE1#
VSS
VCC
NC
A0
A6
VCC
VSS
A1
A2
NC
NC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
NC
NC
DQ6
DQ7
DQ8
DQ9
DQ10
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS VCC
VSS
VCC
NC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A12 A13
A14
A3
A4
A5
A16A15
VCCVCC
DQ11DQ15
DQ14
DQ13
DQ12
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
NC NC
NCNC
August 31, 19994Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GVT73128A24/GVT73128S24
128K X 24 ASYNCHRONOUS SRAM
GALVANTECH,
PIN DESCRIPTIONS
TQFP PINS
GVT73128A24TQFP PINS
GVT73128S24BGA PINSSYMBOLTYPEDESCRIPTION
44, 45, 46, 85, 86,
87, 43, 38, 37, 36,
35, 98, 97, 96, 95,
94, 88
44, 45, 46, 85, 86,
87, 43, 38, 37, 36,
35, 98, 97, 96, 95,
94, 88
5T, 6T, 6U, 6B,
6A, 5B, 5U, 3U,
3T, 2U, 2T, 2A,
2B, 3B, 3A, 4A,
5A
A0-A16InputAddress Inputs: These inputs determine which cell is
addressed.
42 42 4TWE#InputWrite Enable: This input determines if the cycle is a
READ or WRITE cycle. WE# is LOW for a WRITE cycle
and HIGH for a READ cycle.
89, 90,
93 89, 90,
93 4B, 5C,
3CCE#, CE1#,
CE2InputChip Enable: These inputs are used to enable the
device. When CE# and CE1# are LOW and CE2 is
HIGH, the chip is selected. When CE# or CE1# are
HIGH or CE2 is LOW, the chip is disabled and
automatically goes into standby power mode.
-47,
48,49-BE0#,
BE1#, BE2#InputByte Enable: These active LOW inputs are available for
GVT73128A24 in 100-pin TQFP package only. These
active LOW inputs allow individual bytes to be written
or read. When BE0# is LOW, the data is written to or
read from the lower byte (DQ0-DQ7). When BE1# is
LOW, the data is written to or read from the middle byte
(DQ8-DQ15). When BE2# is LOW, the data is written
to or read from the higher byte (DQ16-DQ23).
39 39 4UOE#InputOutput Enable: This active LOW input enables the
output drivers.
77, 76, 73, 72, 69,
68, 63, 62, 59, 58,
55, 54, 22, 23, 26,
27, 4, 5, 8, 9, 12,
13, 18, 19
77, 76, 73, 72, 69,
68, 63, 62, 59, 58,
55, 54, 22, 23, 26,
27, 4, 5, 8, 9, 12,
13, 18, 19
7C, 7D, 7E, 7F,
7G, 7H, 7K, 7L,
7M, 7N, 7P, 7R,
8M, 8N, 8P, 8R,
8C, 8D, 8E, 8F,
8G, 8H, 8K, 8L
DQ0-DQ23Input/OutputSRAM Data I/O: Data inputs and data outputs.
2, 7, 11, 14, 20, 24,
28, 41, 53, 57, 61,
67, 70, 74, 79, 92
2, 7, 11, 14, 20, 24,
28, 41, 53, 57, 61,
67, 70, 74, 79, 92
1J, 2D, 2F, 2H,
2K, 2M, 2P, 3E,
3G, 3J, 3L, 3N
5E, 5G, 5J, 5L,
5N, 6D, 6F, 6H,
6K, 6M, 6P, 7J
VCCSupplyPower Supply: 3.3V + 0.3V
3, 6, 10, 17, 21, 25,
29, 40, 52, 56, 60,
64, 71, 75, 78, 91
3, 6, 10, 17, 21, 25,
29, 40, 52, 56, 60,
64, 71, 75, 78, 91
2E, 2G, 2J, 2L,
2N, 3D, 3F, 3H,
3K, 3M, 3P, 4D,
4E, 4F, 4G, 4H,
4J, 4K, 4L, 4M,
4N, 4P, 5D, 5F,
5H, 5K, 5M, 5P,
6E, 6G, 6J, 6L,
6N
VSS GroundGround
1, 15, 16, 30, 31,
32, 33, 34, 47, 48,
49, 50, 51, 65, 66,
80, 81, 82, 83, 84,
99, 100
1, 15, 16, 30, 31,
32, 33, 34, 50, 51,
65, 66, 80, 81, 82,
83, 84, 99, 100
1A, 1B, 1T, 1U,
2C, 2R, 3R, 4C,
4R, 5R, 6C, 6R,
7A, 7B, 7T, 7U
NC -No Connect: These signals are not internally
connected. User can connect them to VCC, VSS, or
any signal lines or simply leave them floating.
August 31, 19995Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GVT73128A24/GVT73128S24
128K X 24 ASYNCHRONOUS SRAM
GALVANTECH,
TRUTH TABLE
Note: BE0#, BE1# and BE2# are available for GVT73128S24 in 100-pin TQFP package only.
MODECE #CE1#CE 2WE#OE#BE0#BE1#BE2#DQ0-
DQ7DQ8-
DQ15DQ16-
DQ23POWER
STANDBYHX X X X X X X HIGH-ZHIGH-ZHIGH-ZSTANDBY
STANDBY X HX X X X X X HIGH-ZHIGH-ZHIGH-ZSTANDBY
STANDBY XXLX X X X X HIGH-ZHIGH-ZHIGH-ZSTANDBY
BYTE 0 READ
(DQ0-DQ7)L L H H L L H H QHIGH-ZHIGH-ZACTIVE
BYTE 1 READ
(DQ8-DQ15)L L H H LHLHHIGH-ZQHIGH-ZACTIVE
BYTE 2 READ
(DQ16-DQ23)L L H H LH H LHIGH-ZHIGH-ZQACTIVE
WORD READ
(DQa-DQd)L L H H L L L L QQQACTIVE
WORD WRITE
(DQa-DQd)L L HLXLLLDDDACTIVE
BYTE 0 WRITE
(DQ0-DQ7)L L HLXLH H D HIGH-ZHIGH-ZACTIVE
BYTE 1 WRITE
(DQ8-DQ15)L L HLXHLHHIGH-ZDHIGH-ZACTIVE
BYTE 2 WRITE
(DQ16-DQ23)L L HLXH H LHIGH-ZHIGH-ZDACTIVE
OUTPUT
DISABLE
L L HX X HHHHIGH-ZHIGH-ZHIGH-ZACTIVE
L L H H H XXXHIGH-ZHIGH-ZHIGH-ZACTIVE
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply Relative to VSS........-0.5V to +4.6V
VIN ...........................................................-0.5V to VCC+1.0V
Storage Temperature (plastic) ..........................-65oC to +150o
Ambient Temperature ......................................-55oC to +125o
Junction Temperature .................................................. +125o
Power Dissipation ...........................................................1.0W
Short Circuit Output Current .........................................50mA
*Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.This is a stress
rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
August 31, 19996Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GVT73128A24/GVT73128S24
128K X 24 ASYNCHRONOUS SRAM
GALVANTECH,
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(All Temperature Ranges; VCC = 3.3V +0.3V unless otherwise noted)
CAPACITANCE
DESCRIPTIONCONDITIONSSYMBOLMINMAXUNITSNOTES
Input High (Logic 1) VoltageData Inputs (DQx)VIHD2.2VCC+0.5V1, 2
All Other InputsVIH2.24.6V1, 2
Input Low (Logic 0) VoltageVIl-0.50.8V1, 2
Input Leakage Current0V < VIN < VCCILI-5 5 uA
Output Leakage CurrentOutput(s) disabled,
0V < VOUT < VCCILO-5 5 uA
Output High VoltageIOH = -4.0mA VOH2.4V1
Output Low VoltageIOL = 8.0mA VOL0.4V1
Supply VoltageVCC3.03.6V1
DESCRIPTIONCONDITIONS SYMTYP-9-10-12-15UNITSNOTES
Power Supply
Current: OperatingDevice selected; CE# < VIL; VCC =MAX;
f=fMAX; outputs openIcc80 165 150 130 110 mA3, 14
TTL StandbyCE# >VIH; VCC = MAX; f=fMAXISB130 55 50 45 40 mA14
CMOS StandbyCE1# >VCC -0.2; VCC = MAX;
all other inputs < VSS +0.2 or >VCC -0.2;
all inputs static; f= 0
ISB25 10 10 10 10 mA14
DESCRIPTIONCONDITIONSSYMBOLMAXUNITSNOTES
Input CapacitanceTA = 25oC; f = 1 MHz
VCC = 3.3VCI6 pF4
Input/Output Capacitance (DQ)CI/O8 pF4
August 31, 19997Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GVT73128A24/GVT73128S24
128K X 24 ASYNCHRONOUS SRAM
GALVANTECH,
AC ELECTRICAL CHARACTERISTICS
(Note 5) (All Temperature Ranges; VCC = 3.3V +0.3V)
DESCRIPTION- 9- 10- 12- 15
SYMMINMAXMINMAXMINMAXMINMAXUNITSNOTES
READ Cycle
READ cycle timetRC 9 10 12 15 ns
Address access timetAA 9 10 12 15 ns
Chip Enable access timetACE9 10 12 15 ns
Output hold from address changetOH3 3 3 3 ns
Chip Enable to output in Low-ZtLZCE3 3 3 3 ns4, 7
Chip disable to output in High-ZtHZCE4 5 6 7 ns4, 6, 7
Output Enable access timetAOE4 5 6 7 ns
Output Enable to output in Low-ZtLZOE0 0 0 0 ns
Output Enable to output in High-ZtHZOE5 5 6 7 ns4, 6
Byte Enable access timetABE 5 5 6 7 ns
Byte Enable to output in Low-ZtLZBE0 0 0 0 ns4, 7
Byte disable to output in High-ZtHZBE5 5 6 7 ns4, 6, 7
Chip Enable to power-up timetPU0 0 0 0 ns4
Chip disable to power-down timetPD9 10 12 15 ns4
WRITE Cycle
WRITE cycle timetWC9 10 12 15 ns
Chip Enable to end of writetCW7 7 8 9 ns
Address valid to end of write, with OE#
HIGHtAW7 7 8 9 ns
Address setup timetAS 0 0 0 0 ns
Address hold from end of writetAH0 0 0 0 ns
WRITE pulse widthtWP2 9 9 10 11 ns
WRITE pulse width, with OE# HIGHtWP1 7 7 8 9 ns
Data setup timetDS 5.5 6 6 7 ns
Data hold timetDH 0 0 0 0 ns
Write disable to output in Low-ZtLZWE3 3 4 5 ns4, 7
Write Enable to output in High-ZtHZWE5 5 6 7 ns4, 6, 7
Byte Enable to end of writetBW7 7 8 9 ns
AC TEST CONDITIONS
Input pulse levels0V to 3.0V
Input rise and fall times1.5ns
Input timing reference levels1.5V
Output reference levels1.5V
Output loadSee Figures 1 and 2
OUTPUT LOADS
Vt = 1.5V
30 pF
DQ
Z0 = 50Ω
Fig. 1 OUTPUT LOAD EQUIVALENT
50Ω
DQ
3.3v
317Ω
351Ω
Fig. 2 OUTPUT LOAD EQUIVALENT
5 pF
August 31, 19998Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GVT73128A24/GVT73128S24
128K X 24 ASYNCHRONOUS SRAM
GALVANTECH,
NOTES
1. All voltages referenced to VSS (GND).
2. Overshoot: VIH ≤ +6.0V for t ≤ tRC /2.
Undershoot: VIL ≤ -2.0V for t ≤ tRC /2
3. Icc is given with no output current. Icc increases with greater
output loading and faster cycle times.
4. This parameter is sampled.
5. Test conditions as specified with the output loading as shown in
Fig. 1 unless otherwise noted.
6. Output loading is specified with CL=5pF as in Fig. 2. Transition
is measured +500mV from steady state voltage.
7. At any given temperature and voltage condition, tHZCE is less
than tLZCE and tHZWE is less than tLZWE.
8. WE# is HIGH for READ cycle.
9. Device is continuously selected. Chip enable and output enables
are held in their active state.
10. Address valid prior to, or coincident with, latest occurring chip
enable.
11. tRC = Read Cycle Time.
12. Chip Enable and Write Enable can initiate and terminate a
WRITE cycle.
13. Capacitance derating applies to capacitance different from the
load capacitance shown in Fig. 1.
14. Typical values are measured at 3.3V, 25oC and 15ns cycle time.
August 31, 19999Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GVT73128A24/GVT73128S24
128K X 24 ASYNCHRONOUS SRAM
GALVANTECH,
READ CYCLE NO. 1(8, 9)
READ CYCLE NO. 2(7, 8, 10, 12)
ADDR VALID
tRC
DATA VALID
tOH
tAA
PREVIOUS DATA VALID
Q
Note: BE0#, BE1# and BE2# are available for GVT73128S24 only.
CE#
CE1#
t
RC
DATA VALID
t
LZCE
t
ACE
OE#
HIGH Z
t
AOE
t
LZOE
t
HZCE
t
HZOE
BE0#
BE1#
BE2#
Q
UNDEFINED
DON'T CARE
t
HZBE
t
LZBE
t
ABE
CE2
August 31, 199910 Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GVT73128A24/GVT73128S24
128K X 24 ASYNCHRONOUS SRAM
GALVANTECH,
WRITE CYCLE NO. 1(7, 12, 13)
(Write Enable Controlled with Output Enable OE# active LOW))
WRITE CYCLE NO. 2(12, 13)
(Write Enable Controlled with Output Enable OE# inactive HIGH)
ADDR
tWC
tAH
tDS
DATA VALID
WE#
D
Q
tDH
tWP2
tAS
tAW
tCW
HIGH Z
tHZWE tLZWE
BE0#
BE1#
BE2#
tBW
CE#
CE1#
CE2
Note: BE0#, BE1# and BE2# are available for GVT73128S24 only.
ADDR
tWC
tAH
tDS
DATA VALID
HIGH Z
CE#
CE1#
WE#
D
Q
tDH
tWP1
tAS
tAW
tCW
UNDEFINED
DON'T CARE
BE0#
BE1#
BE2#
tBW
CE2
August 31, 199911 Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GVT73128A24/GVT73128S24
128K X 24 ASYNCHRONOUS SRAM
GALVANTECH,
WRITE CYCLE NO. 3(12, 13)
(Chip Enable Controlled)
WRITE CYCLE NO. 4(12, 13)
(Byte Enable Controlled)
ADDR
t
WC
t
AH
t
DS
DON'T CARE
DATA VALID
CE#
CE1#
WE#
D
Q
t
DH
t
WP1
t
AW
t
CW
HIGH Z
BE0#
BE1#
BE2#
t
BW
t
AS
CE2
Note: BE0#, BE1# and BE2# are available for GVT73128S24 only.
ADDR
tWC
tAH
tDS
DON'T CARE
DATA VALID
CE2
WE#
D
Q
tDH
tWP1
tAW tBW
HIGH Z
BE0#
BE1#
BE2#
tCW
tAS
CE#
CE1#
August 31, 199912 Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GVT73128A24/GVT73128S24
128K X 24 ASYNCHRONOUS SRAM
GALVANTECH,
100 Pin TQFP Package Dimensions
20.00 + 0.10
22.00 + 0.10
14.00 + 0.10
16.00 + 0.10
# 1
Note: All dimensions in Millimeters
0.30 + 0.080.65 Basic
1.40 + 0.05
1.60 Max 0.60 + 0.15
August 31, 199913 Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GVT73128A24/GVT73128S24
128K X 24 ASYNCHRONOUS SRAM
GALVANTECH,
7 x 17 (119-lead) BGA Dimensions
Note: All dimensions in Millimeters
0.60 + 0.10
0.90 + 0.10
ABCDEFGHJKLMNPRTU
1
2
3
4
5
6
7
20.32
1.27
22.00 + 0.20
7.62
1.27
14.00 + 0.20
BOTTOM VIEW
19.50 + 0.10
12.00 + 0.10
TOP VIEW
PIN 1A CORNER
0.70 REF.
2.40 MAX.
0.56 REF.
30 TYP.
SIDE VIEW
o 0.75+0.15 (119X)
August 31, 199914 Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GVT73128A24/GVT73128S24
128K X 24 ASYNCHRONOUS SRAM
GALVANTECH,
Ordering Information for 128K x 24
GVT 73128A24 XX - XX X X
GVT 73128S24 XX - XX X
Galvantech Prefix
Part Number
Package (T = 100 PIN TQFP,
12 = 12ns, 15 = 15ns)
Speed ( 9 = 9ns, 10 = 10ns,
B = 119 BUMP PBGA)
Temperature (Blank = Commercial
I = Industrial)
(No Byte Enable Controls)
Galvantech Prefix
Part Number
Package (T = 100 PIN TQFP,
12 = 12ns, 15 = 15ns)
Speed ( 9 = 9ns, 10 = 10ns,
B = 119 BUMP PBGA)
Temperature (Blank = Commercial
I = Industrial)
(With Byte Enable Controls)
