GALVANTECH, INC. GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM ASYNCHRONOUS SRAM 128K x 24 SRAM +3.3V SUPPLY, THREE MEGABIT THREE CHIP ENABLES FEATURES GENERAL DESCRIPTION * * * * * * * The GVT73128A24 and GVT73128S24 are organized as a 131,072 x 24 SRAM using a four-transistor memory cell with a high performance, silicon gate, low-power CMOS process. Galvantech SRAMs are fabricated using triple-layer polysilicon, double-layer metal technology. This device offers multiple power and ground pins for improved performance and noise immunity. For increased system flexibility and eliminating bus contention problems, this device offers multiple chip enables (CE#, CE1# and CE2), and output enable (OE#) with this organization. For GVT73128S24 device in 100-pin TQFP package, separate byte enables (BE0#, BE1#, and BE2#) are also available to control individual bytes. Writing to the device is accomplished by bringing Chip Enables (CE# and CE1#) and Write Enable (WE#) inputs LOW and CE2 HIGH. Reading from the device is accomplished by bringing Chip Enables (CE# and CE1#) LOW and bringing CE2 and Write Enable (WE#) inputs HIGH, along with Output Enable (OE#) being asserted LOW. The device offers a low power standby mode when chip is not selected. This allows system designers to meet low standby power requirements. * * * * Fast access times: 9, 10, 12 and 15ns Fast OE# access times: 4, 5, 6 and 7ns Single +3.3V+0.3V power supply Fully static -- no clock or timing strobes necessary All inputs and outputs are TTL-compatible Three state outputs Easy memory expansion with CE#, CE1#, CE2 and OE# options Automatic chip deselect power down High-performance, low-power consumption, CMOS, double-metal process Low profile 100 pin TQFP and 119 bump, 14mm x 22mm PBGA (Ball Grid Array) packages Multiple Ground and VCC pins for maximum noise immunity OPTIONS * * * MARKING Timing 9ns access 10ns access 12ns access 15ns access -9 -10 -12 -15 Packages 100-pin TQFP 119-lead BGA T B Temperature Commercial Industrial None I (0C to 70C) (-40C to 85C) Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051 Tel (408) 566-0688 Fax (408) 566-0699 Web Site www.galvantech.com Rev. 8/99 Galvantech, Inc. reserves the right to chang e products or specifications without notice. GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM GALVANTECH, FUNCTIONAL BLOCK DIAGRAM VCC VSS A16 MEMORY ARRAY 128K X 24 I/O BUFFER ROW DECODER DQ0 ADDRESS BUFFER A0 DQ23 COLUMN DECODER CONTROL CE# CE1# CE2 BE0# BE1# BE2# WE# OE# Note: BE0#, BE1# and BE2# are available for GVT73128S24 only. August 31, 1999 Rev. 8/99 2 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM GALVANTECH, 1 A NC B NC 2 3 4 5 A11 A14 A15 A16 A12 A13 CE# A5 6 7 A4 NC A3 DQ16 NC D DQ17 VCC VSS VSS VSS VCC DQ1 NC CE1# NC DQ0 E DQ18 VSS F DQ19 VCC VSS VSS VSS VCC DQ3 H J K L M N P R DQ20 VSS VCC VSS VCC VSS DQ2 VSS VCC VSS DQ4 DQ21 VCC VSS VSS VSS VCC DQ5 VCC VSS VCC VSS VCC VSS VCC DQ22 VCC VSS VSS VSS VCC DQ6 DQ23 VSS VCC VSS VCC VSS DQ7 DQ12 VCC VSS VSS VSS VCC DQ8 DQ13 VSS VCC VSS VCC VSS DQ9 DQ14 VCC VSS VSS VSS VCC DQ10 DQ15 NC NC NC NC NC DQ11 T NC A10 A8 WE# A0 A1 NC U NC A9 A7 OE# A6 A2 NC 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 100-pin TQFP 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 NC VCC VSS DQ0 DQ1 VSS VCC DQ2 DQ3 VSS VCC DQ4 DQ5 VCC NC NC VSS DQ6 DQ7 VCC VSS DQ8 DQ9 VCC VSS DQ10 DQ11 VCC VSS NC 50 NC NC NC NC A10 A9 A8 A7 OE# VSS VCC WE# A6 A0 A1 A2 BE0# BE1# BE2# NC G VCC 100 99 NC VCC VSS DQ16 DQ17 VSS VCC DQ18 DQ19 VSS VCC DQ20 DQ21 VCC NC NC VSS DQ22 DQ23 VCC VSS DQ12 DQ13 VCC VSS DQ14 DQ15 VCC VSS NC NC C CE2 128Kx24, 100-PIN TQFP (Top View) NC NC A11 A12 A13 A14 A15 CE2 VCC VSS CE1# CE# A16 A5 A4 A3 NC NC NC NC 128Kx24, 119-Bump PBGA (Top View) Note: BE0#, BE1# and BE2# are available for GVT73128S24 in 100-pin TQFP package only. For GVT73128A24 in 100-pin TQFP package, pin# 47, 48 and 49 are NC. August 31, 1999 Rev. 8/99 3 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM GALVANTECH, PIN DESCRIPTIONS TQFP PINS GVT73128A24 44, 87, 35, 94, 45, 46, 85, 86, 43, 38, 37, 36, 98, 97, 96, 95, 88 TQFP PINS GVT73128S24 44, 87, 35, 94, 45, 46, 85, 86, 43, 38, 37, 36, 98, 97, 96, 95, 88 BGA PINS 5T, 6T, 6U, 6A, 5B, 5U, 3T, 2U, 2T, 2B, 3B, 3A, 5A 6B, 3U, 2A, 4A, SYMBOL TYPE DESCRIPTION A0-A16 Input Address Inputs: These inputs determine which cell is addressed. 42 42 4T WE# Input Write Enable: This input determines if the cycle is a READ or WRITE cycle. WE# is LOW for a WRITE cycle and HIGH for a READ cycle. 89, 90, 93 89, 90, 93 4B, 5C, 3C CE#, CE1#, CE2 Input Chip Enable: These inputs are used to enable the device. When CE# and CE1# are LOW and CE2 is HIGH, the chip is selected. When CE# or CE1# are HIGH or CE2 is LOW, the chip is disabled and automatically goes into standby power mode . - 47, 48,49 - BE0#, BE1#, BE2# Input Byte Enable: These active LOW inputs are available for GVT73128A24 in 100-pin TQFP package only. These active LOW inputs allow individual bytes to be written or read. When BE0# is LOW, the data is written to or read from the lower byte (DQ0-DQ7). When BE1# is LOW, the data is written to or read from the middle byte (DQ8-DQ15). When BE2# is LOW, the data is written to or read from the higher byte (DQ16-DQ23). 39 39 4U OE# Input Output Enable: This active LOW input enables the output drivers . 77, 76, 73, 72, 69, 68, 63, 62, 59, 58, 55, 54, 22, 23, 26, 27, 4, 5, 8, 9, 12, 13, 18, 19 77, 76, 73, 72, 69, 68, 63, 62, 59, 58, 55, 54, 22, 23, 26, 27, 4, 5, 8, 9, 12, 13, 18, 19 7C, 7D, 7E, 7F, 7G, 7H, 7K, 7L, 7M, 7N, 7P, 7R, 8M, 8N, 8P, 8R, 8C, 8D, 8E, 8F, 8G, 8H, 8K, 8L DQ0-DQ23 2, 7, 11, 14, 20, 24, 2, 7, 11, 14, 20, 24, 28, 41, 53, 57, 61, 28, 41, 53, 57, 61, 67, 70, 74, 79, 92 67, 70, 74, 79, 92 1J, 2D, 2F, 2H, 2K, 2M, 2P, 3E, 3G, 3J, 3L, 3N 5E, 5G, 5J, 5L, 5N, 6D, 6F, 6H, 6K, 6M, 6P, 7J V CC Supply Power Supply: 3.3V 3, 6, 10, 17, 21, 25, 3, 6, 10, 17, 21, 25, 29, 40, 52, 56, 60, 29, 40, 52, 56, 60, 64, 71, 75, 78, 91 64, 71, 75, 78, 91 2E, 2G, 2J, 2L, 2N, 3D, 3F, 3H, 3K, 3M, 3P, 4D, 4E, 4F, 4G, 4H, 4J, 4K, 4L, 4M, 4N, 4P, 5D, 5F, 5H, 5K, 5M, 5P, 6E, 6G, 6J, 6L, 6N VSS Groun d Ground 1, 15, 16, 30, 31, 32, 33, 34, 47, 48, 49, 50, 51, 65, 66, 80, 81, 82, 83, 84, 99, 100 1A, 1B, 1T, 1U, 2C, 2R, 3R, 4C, 4R, 5R, 6C, 6R, 7A, 7B, 7T, 7U NC - August 31, 1999 Rev. 8/99 1, 15, 16, 30, 31, 32, 33, 34, 50, 51, 65, 66, 80, 81, 82, 83, 84, 99, 10 0 Input/Output SRAM Data I/O: Data inputs and data outputs . 4 + 0.3V No Connect: These signals are not internally connected. User can connect them to VCC, VSS, or any signal lines or simply leave them floating. Galvantech, Inc. reserves the right to change products or specifications without notice. GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM GALVANTECH, TRUTH TABLE MODE STANDBY STANDBY STANDBY BYTE 0 READ (DQ0-DQ7) BYTE 1 READ (DQ8-DQ15) BYTE 2 READ (DQ16-DQ23) WORD READ (DQa-DQd) WORD WRITE (DQa-DQd) BYTE 0 WRITE (DQ0-DQ7) BYTE 1 WRITE (DQ8-DQ15) BYTE 2 WRITE (DQ16-DQ23) OUTPUT DISABLE CE # CE1# CE 2 WE# OE# BE0# BE1# BE2# DQ0DQ7 DQ8DQ15 DQ16DQ23 H X X L X H X L X X L H X X X H X X X L X X X L X X X H X X X H HIGH-Z HIGH-Z HIGH-Z Q HIGH-Z HIGH-Z HIGH-Z HIGH-Z L L H H L H L H HIGH-Z Q HIGH-Z ACTIVE L L H H L H H L HIGH-Z HIGH-Z Q ACTIVE L L H H L L L L Q Q Q ACTIVE L L H L X L L L D D D ACTIVE L L H L X L H H D HIGH-Z HIGH-Z ACTIVE L L H L X H L H HIGH-Z D HIGH-Z ACTIVE L L H L X H H L HIGH-Z HIGH-Z D ACTIVE L L L L H H X H X H H X H X H X HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z HIGH-Z ACTIVE ACTIVE POWER HIGH-Z STANDBY HIGH-Z STANDBY HIGH-Z STANDBY HIGH-Z ACTIVE Note: BE0#, BE1# and BE2# are available for GVT73128S24 in 100-pin TQFP package only. August 31, 1999 Rev. 8/99 5 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM GALVANTECH, ABSOLUTE MAXIMUM RATINGS* *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VCC Supply Relative to VSS........-0.5V to +4.6V VIN ...........................................................-0.5V to VCC+1.0V Storage Temperature (plastic) ..........................-65 oC to +150o Ambient Temperature ......................................-55o C to +125o Junction Temperature .................................................. +125 o Power Dissipation ...........................................................1.0W Short Circuit Output Current .........................................50mA DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (All Temperature Ranges; VCC = 3.3V +0.3V unless otherwise noted) DESCRIPTION CONDITIONS Input High (Logic 1) Voltage SYMBOL MIN MAX UNITS NOTES Data Inputs (DQx ) V I HD 2.2 VCC+0.5 V 1, 2 All Other Inputs V IH 2.2 4.6 V 1, 2 V Il -0.5 0.8 V 1, 2 Input Low (Logic 0) Voltage Input Leakage Current 0V < V IN < VCC IL I -5 5 uA Output Leakage Current Output(s) disabled, 0V < V OUT < VCC IL O -5 5 uA Output High Voltage IOH = -4.0mA V OH 2.4 Output Low Voltage IOL = 8.0mA V OL Supply Voltage VCC DESCRIPTION CONDITIONS Power Supply Current: Operating 3.0 V 1 0.4 V 1 3.6 V 1 SYM TYP -9 -10 -12 -15 Device selected; CE# < V IL ; VCC =MAX; f= fMAX ; outputs open Ic c 80 165 150 130 110 mA 3, 14 TTL Standby CE# >V IH; VCC = MAX; f=fMAX ISB1 30 55 50 45 40 mA 14 CMOS Standby CE1# >VCC -0.2; VCC = MAX; all other inputs < VSS +0.2 or >VCC -0.2; all inputs static; f= 0 ISB2 5 10 10 10 10 mA 14 UNIT S NOTES CAPACITANCE DESCRIPTION CONDITIONS Input Capacitance TA = 25 o C; f = 1 MHz VCC = 3.3V Input/Output Capacitance (DQ) August 31, 1999 Rev. 8/99 SYMBOL MAX UNITS NOTES CI 6 pF 4 CI/O 8 pF 4 6 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM GALVANTECH, AC ELECTRICAL CHARACTERISTICS (Note 5) (All Temperature Ranges; VCC = 3.3V +0.3V) DESCRIPTION -9 - 10 MAX MIN - 12 MAX MIN - 15 SY M MIN MAX MIN MAX UNIT S NOTES READ cycle tim e t RC 9 Address access time tA A 9 10 12 15 ns t ACE 9 10 12 15 ns READ Cycle Chip Enable access time 10 12 15 t OH 3 3 3 3 Chip Enable to output in Low- Z tLZC E 3 3 3 3 Chip disable to output in High-Z tHZC E Output hold from address chang e Output Enable access time 4 tAO E 5 4 6 5 6 ns ns ns 4, 7 7 ns 4, 6, 7 7 ns Output Enable to output in Low- Z t LZOE Output Enable to output in High-Z t HZOE 5 5 6 7 ns t ABE 5 5 6 7 ns Byte Enable access tim e Byte Enable to output in Low-Z tLZBE Byte disable to output in High-Z tHZB E Chip Enable to power-up time tPU Chip disable to power-down tim e tPD 0 0 0 0 0 0 5 0 0 5 0 0 6 0 9 10 ns 7 0 12 15 4, 6 ns 4, 7 ns 4, 6, 7 ns 4 ns 4 WRITE Cycle WRITE cycle tim e t WC 9 10 12 15 ns Chip Enable to end of write t CW 7 7 8 9 ns Address valid to end of write, with OE# HIGH tAW 7 7 8 9 ns Address setup time tA S 0 0 0 0 ns Address hold from end of write tAH 0 0 0 0 ns WRITE pulse width tWP2 9 9 10 11 ns WRITE pulse width, with OE# HIGH tWP1 7 7 8 9 ns Data setup tim e tDS 5.5 6 6 7 ns Data hold tim e t DH 0 0 0 0 ns Write disable to output in Low-Z t LZWE 3 3 4 5 Write Enable to output in High-Z t HZW E Byte Enable to end of write August 31, 1999 Rev. 8/99 tBW 5 7 5 7 6 8 7 7 9 ns 4, 7 ns 4, 6, 7 ns Galvantech, Inc. reserves the right to change products or specifications without notice. GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM GALVANTECH, OUTPUT LOADS AC TEST CONDITIONS Input pulse levels DQ 0V to 3.0V Input rise and fall times 1.5ns Input timing reference levels 1.5V Output reference levels 1.5V Output load Z0 = 50 50 30 pF Vt = 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT See Figures 1 and 2 3.3v 317 DQ 351 5 pF Fig. 2 OUTPUT LOAD EQUIVALENT NOTES 8. WE# is HIGH for READ cycle. 1. All voltages referenced to VSS (GND). 9. 2. Overshoot: Undershoot: Device is continuously selected. Chip enable and output enables are held in their active state. VIH +6.0V for t t RC /2. VIL -2.0V for t t RC /2 3. Ic c is given with no output current. Ic c increases with greater output loading and faster cycle times. 4. This parameter is sampled. 5. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. 6. 7. 10. Address valid prior to, or coincident with, latest occurring chip enable. 11. tRC = Read Cycle Time. 12. Chip Enable and Write Enable can initiate and terminate a WRITE cycle. 13. Capacitance derating applies to capacitance different from the load capacitance shown in Fig. 1. Output loading is specified with CL =5pF as in Fig. 2. Transition is measured +500mV from steady state voltage. 14. Typical values are measured at 3.3V, 25o C and 15ns cycle time. At any given temperature and voltage condition, t HZCE is less than t LZCE and t HZWE is less than tLZWE. August 31, 1999 Rev. 8/99 8 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM GALVANTECH, READ CYCLE NO. 1(8, 9 ) tRC ADDR VALID tAA t OH Q PREVIOUS DATA VALID DATA VALID READ CYCLE NO. 2(7, 8, 10, 12 ) t RC CE# CE1# CE2 t t ABE BE0# BE1# BE2# t t AOE t HZCE HZBE LZOE OE# t LZBE t ACE t Q tHZOE LZCE HIGH Z DATA VALID DON'T CARE UNDEFINED Note: BE0#, BE1# and BE2# are available for GVT73128S24 only. August 31, 1999 Rev. 8/99 9 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM GALVANTECH, WRITE CYCLE NO. 1(7, 12, 13) (Write Enable Controlled with Output Enable OE# active LOW)) t WC ADDR tAW tAH t CW CE# CE1# CE2 tBW BE0# BE1# BE2# t AS t WP2 WE# tDS D tDH DATA VALID tHZWE tLZWE Q HIGH Z WRITE CYCLE NO. 2(12, 13) (Write Enable Controlled with Output Enable OE# inactive HIGH) tWC ADDR tAW tAH t CW CE# CE1# CE2 t BW BE0# BE1# BE2# tAS tWP1 WE# tDS D Q tDH DATA VALID HIGH Z DON'T CARE UNDEFINED Note: BE0#, BE1# and BE2# are available for GVT73128S24 only. August 31, 1999 Rev. 8/99 10 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM GALVANTECH, WRITE CYCLE NO. 3(12, 13) (Chip Enable Controlled) t WC ADDR t t AW AH t t AS CW CE# CE1# CE2 t BE0# BE1# BE2# BW t WP1 WE# t t DS DH DATA VALID D HIGH Z Q DON'T CARE WRITE CYCLE NO. 4(12, 13) (Byte Enable Controlled) t WC ADDR t AW BE0# BE1# BE2# tAH t AS t BW CE2 t CW CE# CE1# t WP1 WE# t t DS D Q DH DATA VALID HIGH Z DON'T CARE Note: BE0#, BE1# and BE2# are available for GVT73128S24 only. August 31, 1999 Rev. 8/99 11 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM GALVANTECH, 100 Pin TQFP Package Dimensions 16.00 + 0.10 14.00 + 0.10 #1 22.00 + 0.10 20.00 + 0.10 1.40 + 0.05 1.60 Max 0.65 Basic 0.30 + 0.08 0.60 + 0.15 Note: All dimensions in Millimeters August 31, 1999 Rev. 8/99 12 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM GALVANTECH, 7 x 17 (119-lead) BGA Dimensions 22.00 + 0.20 20.32 7 6 5 4 3 1.27 7.62 14.00 + 0.20 1.27 2 1 U T R P N M L K J o 0.75+0.15 (119X) H G F E D C B A BOTTOM VIEW 0.70 REF. PIN 1A CORNER TOP VIEW 2.40 MAX. 0.90 + 0.10 12.00 + 0.10 19.50 + 0.10 30 TYP. 0.56 REF. 0.60 + 0.10 SIDE VIEW Note: All dimensions in Millimeters August 31, 1999 Rev. 8/99 13 Galvantech, Inc. reserves the right to change products or specifications without notice. GVT73128A24/GVT73128S24 128K X 24 ASYNCHRONOUS SRAM GALVANTECH, Ordering Information for 128K x 24 GVT 73128A24 XX - XX X X Galvantech Prefix Temperature (Blank = Commercial I = Industrial) Part Number (No Byte Enable Controls) Speed ( 9 = 9ns, 10 = 10ns, 12 = 12ns, 15 = 15ns) Package (T = 100 PIN TQFP, B = 119 BUMP PBGA) GVT 73128S24 XX - XX X Galvantech Prefix Temperature (Blank = Commercial I = Industrial) Part Number (With Byte Enable Controls) Speed ( 9 = 9ns, 10 = 10ns, 12 = 12ns, 15 = 15ns) Package (T = 100 PIN TQFP, B = 119 BUMP PBGA) August 31, 1999 Rev. 8/99 14 Galvantech, Inc. reserves the right to change products or specifications without notice.