1
File Number
1570.4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207 |Copyright © Intersil Corporation 1999
IRF330
5.5A, 400V, 1.000 Ohm, N-Channel
Power MOSFET
This N-Channel enhancement mode silicon gate power field
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of
energy in the breakdown avalanche mode of operation. All of
these power MOSFETs are designed for applications such
as switching regulators, switching convertors, motor drivers,
relay drivers, and drivers for high power bipolar switching
transistors requiring high speed and low gate drive power.
These types can be operated directly from integrated
circuits.
Formerly developmental type TA17414.
Features
5.5A, 400V
•r
DS(ON) = 1.000
Single Pulse Avalanche Energy Rated
SOA is Power Dissipation Limited
Nanosecond Switching Speeds
Linear Transfer Characteristics
High Input Impedance
Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
JEDEC TO-204AA
Ordering Information
PART NUMBER PACKAGE BRAND
IRF330 TO-204AA IRF330
NO TE: When ordering, use the entire part number . G
D
S
DRAIN
(FLANGE)
SOURCE (PIN 2)
GATE (PIN 1)
Data Sheet March 1999
2
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
IRF330 UNITS
Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS 400 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 400 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
TC= 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID5.5
3.5 A
A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 22 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS ±20 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD75 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 W/oC
Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS 300 mJ
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ,T
STG -55 to 150 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg 300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ= 25oC to 125oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 10) 400 - - V
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2.0 - 4.0 V
Zero Gate Voltage Drain Current IDSS VDS = Rated BVDSS, VGS = 0V - - 25 µA
VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ= 125oC - - 250 µA
On-State Drain Current (Note 2) ID(ON) VDS > ID(ON) x rDS(ON)MAX, VGS = 10V 5.5 - - A
Gate to Source Leakage Current IGSS VGS = ±20V ±100 nA
Drain to Source On Resistance (Note 2) rDS(ON) ID = 3.0A, VGS = 10V (Figures 8, 9) - 0.8 1.0
Forward Transconductance (Note 2) gfs VDS 10V, ID = 3.3A (Figure 12) 2.9 4.0 - S
Turn-On Delay Time td(ON) VDD = 200V, ID 5.5A, RG = 12, RL = 36,
VGS = 10V (Figures 17, 18) MOSFET Switching
Times are Essentially Independent of Operating
Temperature
-1117ns
Rise Time tr-2029ns
Turn-Off Delay Time td(OFF) -3556ns
Fall Time tf-1524ns
Total Gate Charge
(Gate to Source + Gate to Drain) Qg(TOT) VGS = 10V, ID = 5.5A, VDS = 0.8 x Rated BVDSS,
IG(REF) = 1.5mA (Figures 14, 19, 20) Gate Charge is
Essentially Independent of Operating Temperature
-2135nC
Gate to Source Charge Qgs -4-nC
Gate to Drain “Miller” Charge Qgd -17-nC
Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) - 700 - pF
Output Capacitance COSS - 150 - pF
Reverse Transfer Capacitance CRSS -40-pF
Internal Drain Inductance LDMeasured between the
Contact Screw on the
Flange that is Closer to
Source and Gate Pins and
the Center of Die
Modified MOSFET
Symbol Showing the
Internal Devices
Inductances
- 5.0 - nH
Internal Source Inductance LSMeasured from the Source
Lead, 6mm (0.25in) from
the Flange and the Source
Bonding Pad
- 12.5 - nH
Thermal Resistance Junction to Case RθJC - - 1.67 oC/W
Thermal Resistance Junction to Ambient RθJA Free Air Operation - - 30 oC/W
LD
LS
D
S
G
IRF330
3
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to Drain Current ISD Modified MOSFET Symbol
Showing the Integral
Reverse P-N Junction Diode
- - 5.5 A
Pulse Source to Drain Current (Note 3) ISDM - - 22 A
Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = 5.5A, VGS = 0V (Figure 13) - - 1.6 V
Reverse Recovery Time trr TJ = 25oC, ISD = 5.5A, dISD/dt = 100A/µs 140 400 660 ns
Reverse Recovery Charge QRR TJ = 25oC, ISD = 5.5A, dISD/dt = 100A/µs 0.93 2.4 4.3 µC
NOTES:
2. Pulse test: pulse width 300µs, duty cycle 2%.
3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 50V, starting TJ= 25oC, L = 17.75mH, RG= 25Ω,peak IAS = 6.5A. See Figures 15, 16.
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE
G
D
S
0 50 100 150
0
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0.2
0.4
0.6
0.8
1.0
1.2
2
0050 100
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
10
150
8
75 125
4
6
ZθJC, NORMALIZED TRANSIENT
0.5
0.05
10-2
10-5 10-4 10-3 1.0 10
t1, RECTANGULAR WAVE PULSE DURATION (s)
10-1
PDM
t1t2
SINGLE PULSE DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
NOTES:
2
1.0
0.2
0.1
0.02
0.01
THERMAL IMPEDANCE
0.01
0.05
0.5
0.2
0.1
0.02
IRF330
4
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS
FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS
NOTE: Heating effect of 2µs pulse is minimal.
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Typical Performance Curves
Unless Otherwise Specified (Continued)
100
10
1
500
110
100
OPERATION IN THIS
AREA IS LIMITED
BY rDS(ON)
0.1
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
TC = 25oC
10µs
100µs
1ms
DC
TJ = MAX RATED
SINGLE PULSE
10ms
100ms
VDS, DRAIN TO SOURCE VOLTAGE (V)
100 150 200 2500 300
8
6
4
0
3
ID, DRAIN CURRENT (A)
4.5V
2
10V 80µs PULSE TEST
VGS = 5.5V
4V
5V
7
5
1
50
ID, DRAIN CURRENT (A)
02468
1
2
3
4
5
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
80µs PULSE TEST
VGS = 4.5V
VGS = 5V
VGS = 4V
VGS = 6V
VGS = -10V
0234 71
0
3
4
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
5
2
1
80ms PULSE TEST
VDS 50V
56
125oC
-55oC
25oC
ID, DRAIN CURRENT (A)
5101520025
3
2
0
rDS(ON), DRAIN TO SOURCE
VGS = 20V
1
VGS = 10V
30
ON RESISTANCE ()
2.2
1.4
0.6
0
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
ID = 2.0A
1.8
1.0
0.2 -40 40 80 120
VGS = 10V
ON RESISTANCE
IRF330
5
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Typical Performance Curves
Unless Otherwise Specified (Continued)
1.25
1.05
0.85
0 160
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
ID = 250µA
1.15
0.95
0.75
-40 40 80 120
BREAKDOWN VOLTAGE
VDS, DRAIN TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
2000
1600
1200
800
400
0
CISS
COSS
CRSS
010 20 30 40 50
VGS = 0V
f = 1MHz CISS = CGS + CGD
CRSS = CGD
COSS CDS + CGD
VGS = 0V, f = 1MHz
ID, DRAIN CURRENT (A)
2468
010
10
8
6
0
4
gfs, TRANSCONDUCTANCE (S)
80µs PULSE TEST
2
TJ = 125oC
TJ = 25oC
TJ = -55oC
ISD, SOURCE TO DRAIN CURRENT (A)
VSD, SOURCE TO DRAIN VOLTAGE (V)
100
10
0.101234
TJ = 25oC
TJ = 150oC
TJ = 25oC
80µs PULSE TEST
TJ = 150oC
Qg(TOT), TOTAL GATE CHARGE (nC)
8162432040
20
16
12
0
8
VGS, GATE TO SOURCE VOLTAGE (V)
VDS = 320V
4
VDS = 200V
VDS = 80V
ID = 5.5A
IRF330
6
Test Circuits and Waveforms
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
FIGURE 19. GATE CHARGE TEST CIRCUITS FIGURE 20. GATE CHARGE WAVEFORMS
tP
VGS
0.01
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS
RL
RG
DUT
+
-VDD
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
0.3µF
12V
BATTERY 50k
VDS
S
DUT
D
G
IG(REF)
0
(ISOLATED
VDS
0.2µF
CURRENT
REGULATOR
ID CURRENT
SAMPLING
IG CURRENT
SAMPLING
SUPPLY)
RESISTOR RESISTOR
SAME TYPE
AS DUT Qg(TOT)
Qgd
Qgs
VDS
0
VGS
VDD
IG(REF)
0
IRF330
7
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is gr anted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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IRF330