VW Type 5.0 x 3.2 mm SMD PECL/LVDS Voltage Controlled Crystal Oscillator Actual Size PECL Parameter Supply Voltage Variation (VDD) 5% Frequency Range Standard Frequency Absolute Pulling Range (APR) Control Voltage Range Supply Current 60MHz F0 175 MHz Output Level Output High (Logic "1") Output Low (Logic "0") + Transition Time : Rise/ Fall Time Start Time Tri-State(Input to Pin 2 ) Enable(High voltage or floating) Disable(Low voltage or GND) Linearity Modulation Bandwidth (BW) Input Impedance RMS Phase Jitter F0 < 100MHz 100 MHz F0 < 125 MHz 125 MHz F0 < 150 MHz 150 MHz F0 175MHz Phase Noise @122.88 MHz 100 Hz 1 KHz 10 KHz Aging ( @25oC 1st year) Storage Temp. Range LVDS 3.3V Min. 3.135 60 50 0.3 Unit 3.3V Max. Min. 3.465 3.135 175 60 153.6,155.52,156.25 50 3.0 0.3 100 Max. 3.465 175 3.0 75 2.275 - 1.68 1.0 3 0.9 - 1.6 1.0 3 0.7VDD 20 5 0.3VDD 10 - 0.7VDD 20 5 0.3VDD 10 - -55 1.0 0.7 0.5 0.3 -85 -115 -130 3 125 -55 1.0 0.7 0.5 0.3 -85 -115 -130 3 125 V MHz ppm V mA V nSec mSec V % KHz M pSec dBc/Hz ppm Rev(3)01/2013 www.taitien.com sales@taitien.com.tw Specifications subject to change without notice