ISL88708IP829Z - Intersil Corporation

FN8092.5

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL88705, ISL88706, ISL88707,

ISL88708, ISL88716, ISL88813

µP Supervisor with Watchdog Timer,

Power-Fail Comparator , Manual Reset and

Adjustable Power-On Reset

Designed with high reset threshold accuracy and low power

consumption, the ISL88705, ISL88706, ISL88707,

ISL88708, ISL88716 and ISL88813 devices are

microprocessor supervisors that are designed to monitor

power-supply and battery functions in microprocessor

systems. They can help to lower system cost, reduce board

space requirements and increase the reliability of systems.

These devices provide essential fu nctions such as supply

voltage supervision by asserting a reset output during

power-up and power-down as well as duri ng brownout

conditions. An auxiliary voltage monitor is provided for

detecting power failures warning the system of low battery

conditions or presence detecti on. In addition, an

independent watchdog timer helps to monitor

microprocessor activity every 1.6s (typical). An active-low

manual reset is offered and reset signals remain asserted

until VDD returns to proper operating levels.

Users can increase the nominal 200ms power-o n reset

time-out delay by adding an external capacitor to the CPOR

pin on the ISL88707 and ISL88708.

Features

• Fixed-Voltage Options Allow Precise Monitoring of +3.0V,

+3.3V, and +5.0V Power Supplies

• Additional Voltage Monitor for Power-Fail Detection or

Low-Battery Warning

- Moni tors Voltages Down to 1.25V

- Adjustable Power-Fail Input Threshold

• Watchdog T imer Capability With 1.6s Time-out

• Both RST and RST Outputs Available

• 140ms Minimum Reset Pulse Width with Option to

Customize Using an External Capacitor

• Manual Reset Input on all Devices

• Reset Signal Valid Down to VDD = 1V

• Accurate ±1.8% Voltage Threshold

• Immune to Power-Supply Transient s

• Ultra Low 10µA Maximum Supply Current at 3V

• Pb-Free (RoHS Compliant)

Applications

• Portable/Battery Powered Equipment

• Notebook/Desktop Computer Systems

• Designs Using DSPs, Microcontrollers or Microprocessors

• Controllers

• Intelligent Instruments

• Communications Systems

• Industrial Equipment

Pinouts ISL88705, ISL88706

(8 LD PDIP/SOIC)

TOP VIEW

ISL88716, ISL88813

(8 LD PDIP/SOIC)

TOP VIEW

ISL88707, ISL88708

(8 LD PDIP/SOIC)

TOP VIEW

VDD

GND

PFI

WDO

RST

WDI

PFO

MR 1

VDD

GND

PFI

WDO

RST

WDI

PFO

MR 1

VDD

GND

PFI

RST

CPOR

PFO

Data Sheet January 12, 2009

2FN8092.5

January 12, 2009

Ordering Information

PART NUMBER

(Note) PART

MARKING VTH

TEMP RANGE

(°C) PACKAGE

(Pb-Free) PKG. DWG. #

ISL88705IP846Z 88705 I46Z 4.64V -40 to +85 8 Ld PDIP** MDP0031

ISL88813IP846Z 88813 I46Z 4.64V -40 to +85 8 Ld PDIP** MDP0031

ISL88707IP846Z 88707 I46Z 4.64V -40 to +85 8 Ld PDIP** MDP0031

ISL88706IP844Z 88706 I44Z 4.38V -40 to +85 8 Ld PDIP** MDP0031

ISL88708IP844Z 88708 I44Z 4.38V -40 to +85 8 Ld PDIP** MDP0031

ISL88706IP831Z 88706 I31Z 3.09V -40 to +85 8 Ld PDIP** MDP0031

ISL88708IP831Z 88708 I31Z 3.09V -40 to +85 8 Ld PDIP** MDP0031

ISL88706IP829Z 88706 I29Z 2.92V -40 to +85 8 Ld PDIP** MDP0031

ISL88708IP829Z 88708 I29Z 2.92V -40 to +85 8 Ld PDIP** MDP0031

ISL88706IP826Z 88706 I26Z 2.63V -40 to +85 8 Ld PDIP** MDP0031

ISL88716IP826Z 88716 I26Z 2.63V -40 to +85 8 Ld PDIP** MDP0031

ISL88708IP826Z 88708 I26Z 2.63V -40 to +85 8 Ld PDIP** MDP0031

ISL88705IB846Z* 88705 I46Z 4.64V -40 to +85 8 Ld SOIC (Tape and Reel) M8.15

ISL88813IB846Z* 88813 I46Z 4.64V -40 to +85 8 Ld SOIC (Tape and Reel) M8.15

ISL88707IB846Z* 88707 I46Z 4.64V -40 to +85 8 Ld SOIC (Tape and Reel) M8.15

ISL88706IB844Z* 88706 I44Z 4.38V -40 to +85 8 Ld SOIC (Tape and Reel) M8.15

ISL88708IB844Z* 88708 I44Z 4.38V -40 to +85 8 Ld SOIC (Tape and Reel) M8.15

ISL88706IB831Z* 88706 I31Z 3.09V -40 to +85 8 Ld SOIC (Tape and Reel) M8.15

ISL88708IB831Z* 88708 I31Z 3.09V -40 to +85 8 Ld SOIC (Tape and Reel) M8.15

ISL88706IB829Z* 88706 I29Z 2.92V -40 to +85 8 Ld SOIC (Tape and Reel) M8.15

ISL88708IB829Z* 88708 I29Z 2.92V -40 to +85 8 Ld SOIC (Tape and Reel) M8.15

ISL88706IB826Z* 88706 I26Z 2.63V -40 to +85 8 Ld SOIC (Tape and Reel) M8.15

ISL88716IB826Z* 88716 I26Z 2.63V -40 to +85 8 Ld SOIC (Tape and Reel) M8.15

ISL88708IB826Z* 88708 I26Z 2.63V -40 to +85 8 Ld SOIC (Tape and Reel) M8.15

ISL88705EVAL1 Evaluation Board

*Add “-TK” suffix for Tape and Reel Packaging. Please refer to TB347 for details on reel specifications.

**Pb-free PDIPs can be used for through-hole wave solder processing only . They are not intended for use in Reflow solder processing applications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die att ach materials, and 100%

matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).

Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J

STD-020.

ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813

3FN8092.5

January 12, 2009

Functional Block Diagrams

±VREF

VDD

POR

GND

WDT

VREF

PFI

WDI

WDO

PF PFO

RST

ISL88705, ISL88706

VREF

VDD

POR

GND

WDT

VREF

PFI

WDI

WDO

PF PFO

RST

ISL88716, ISL88813

VREF

VDD

POR

GND

VREF

PFI

PF PFO

ISL88707, ISL88708

RST

CPOR

OSC

ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813

4FN8092.5

January 12, 2009

Pin Descriptions

ISL88705,

ISL88706 ISL88716,

ISL88813 ISL88707,

ISL88708 NAME DESCRIPTION

111MR

Manual Reset Input. A reset signal is generated when this input is pulled low. The MR input is an

active low debounced input to which a user can connect a push-button to add manual reset capability

or drive with a signal. The MR pin has an internal 20kΩ pull-up.

222V

DD Power Supply T erminal. The voltage at this pin is compared against an internal factory-programmed

voltage trip point, VTH1. A reset is first asserted when the device is initially powered up to ensure that

the power supply has stabilized. Thereafter , reset is again asserted whenever VDD falls below VTH1.

The device is designed with hysteresis to help prevent chattering due to noise and is immune to brief

power-supply transients. The voltage threshold VTH1 is specified in the part number suffix.

333GNDGround Connection

444PFIPower-Fail Input This is an auxiliary monitored voltage input with a 1.25V threshold that causes PFO

state to follow the PFI input state.

555PFO

Power-Fail Output. This output goes high if the voltage on PFI is greater than 1.25V , otherwise PFO

stays low.

POR Adjustable POR Time-out Delay Input. Connecting an external capacitor from CPOR to ground

allows the user to increase the Power-On Reset time-out (tPOR) from the nominal 200ms.

66 WDIWatchdog Input. The Watchdog Input takes an input from a microprocessor and ensures that it

periodically toggles the WDI pin, otherwise the internal nominal 1.6s watchdog timer runs out, then

reset is asserted and WDO is pulled low . The internal Watchdog T imer is cleared whenever the WDI

sees a rising or falling edge or the device is manually reset. Floating WDI or connecting WDI to a

high-impedance three- state buffer disables the watchdog feature.

77RST

Active-Low Reset Output. The RST output is an active low output with an internal PMOS pull-up

that is pulled low to GN D when reset is asserted. Reset is asserted whenever:

1. The device is first powered up

2. VDD falls below its minimum voltage sense level or

3. MR is asserted.

The reset output continues to be asserted for typically 200ms after VDD rises above the reset

threshold or MR input goes from low to high. A watchdog time-out will not trigger a reset unless WDO

is connected to MR.

78RSTActive-High Reset Output. The RST pin functions identically to its complementary RST output but

is an active high push-pull output. RST is set high to VDD when reset is asserted. See the RST in “Pin

Descriptions” on page 4 for more details on conditions that cause a reset.

88 WDO

W atchdog Output. This output is pulled low when the nominal 1.6s internal Watchdog T imer expires

and periodically resets until the watchdog is cleared. WDO also goes low during low VDD conditions.

Whenever VDD is below the reset threshold, WDO stays low. However, unlike RESET, WDO does

not have a minimum pulse width. As soon as VDD rises above the reset threshold, WDO goes high

with no delay.

ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813

5FN8092.5

January 12, 2009

Absolute Maximum Ratings Thermal Information

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage on any Pin with Respect to GND . . . . . . . . . . .-1.0V to +7V

DC Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA

Recommended Operating Conditions

Temperature Range ( Industrial). . . . . . . . . . . . . . . . .-40°C to +85°C

Thermal Resistance (Typical, Note 1) θJA (°C/W)

PDIP Package* (4-layer test board). . . . . . . . . . . . . 83

SOIC Package (4-layer test board) . . . . . . . . . . . . . 110

Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

*Pb-free PDIPs can be used for through hole wave solder processing

only. They are not intended for use in Reflow solder processing

applications.

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTE:

1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

Electrical Specifications Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX

limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VDD Supply Voltage Range 2.0 5.5 V

IDD VDD = 5V, WDT Inactive 10 19 µA

VDD = 3V, WDT Inactive 8 10 µA

ILI Input Leakage Current (PFI) 100 nA

ILO Output Leakage Current 100 nA

VOLTAGE THRESHOLDS

VTH1 Fixed VDD Voltage Trip Point 4.556 4.640 4.724 V

4.301 4.380 4.459 V

3.034 3.090 3.146 V

2.867 2.920 2.973 V

2.583 2.630 2.677 V

VTH1HYST Hysteresis at VTH1 Input

Temperature = +25°C VTH1 = 4.64V 46 mV

VTH1 = 4.38V 44 mV

VTH1 = 3.09V 37 mV

VTH1 = 2.92V 29 mV

VTH1 = 2.63V 31 mV

RST AND RST

VOL Reset Output Voltage Low VDD ≥ 3.3V, Sinking 2.5mA 0.05 0.40 V

VDD < 3.3V, Sinking 1.5mA 0.05 0.40 V

VOH RST Output Voltage High VDD ≥ 3.3V, Sourcing 2.5mA VDD - 0.6 VDD - 0.4 V

VDD < 3.3V, Sourcing 1.5mA VDD - 0.6 VDD - 0.4 V

RST Output Voltage High VDD ≥ 3.3V, Sourcing 0.8mA VDD - 0.6 VDD - 0.4 V

VDD < 3.3V, Sourcing 0.5mA VDD - 0.6 VDD - 0.4 V

tRPD VTH to Reset Asserted Delay 45 µs

tPOR POR Time-Out Delay CPOR is open 140 200 260 ms

CLOAD Load Capacitance on Reset Pins 5 pF

ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813

6FN8092.5

January 12, 2009

Principles of Operation

The ISL88705, ISL88706, ISL88707, ISL88708, ISL88716,

ISL88813 devices provide those functions needed for

monitoring critical voltages such as power-supply and battery

functions in microprocessor systems. Features of these

supervisors include Power-On Reset control, Supply Volt age

Supervision, Power-Fail Detection and Manual Reset

Assertion. The integration of all these features along with high

reset threshold accuracy and low power consumption make

these devices ideal for portable or battery-powered equipment.

Power-On Reset (POR)

Applying power to the device activates a POR circuit which

asserts reset (i.e. RST goes high while RST goes low). These

signals provide several benefits:

• It prevents the system microprocessor from starting to

operate with insufficient voltage.

• It prevents the processor from operating prior to stabilization

of the oscillator .

• It ensures that the monitored device is held out of operation

until internal registers are properly loaded.

• It allows time for an FPGA to download its configuration prior

to initialization of the circuit.

The reset signals remain active until VDD rises above the

minimum voltage sense level for time period tPOR. This

ensures that the supply voltage has stabilized to sufficient

operating levels.

MANUAL RESET

VMRL MR Input Voltage Low 0.8 V

VMRH MR Input Voltage High VDD - 0.6 V

tMR MR Minimum Pulse Width 550 ns

RPU Internal MR Pull-Up Resistor 20 kΩ

WATCHDOG TIMER (Note 2)

tWDT Watchdog Time-out Period 1.0 1.6 2.0 s

tWDPS WDI Minimum Pulse Width 100 ns

VIL Watchdog Input Voltage Low 0.3 x VDD V

VIH Watchdog Input Voltage High 0.7 x VDD V

VWDOL WDO Output Voltage Low VDD ≥ 3.3V, Sinking 2.5mA 0.05 0.40 V

VDD < 3.3V, Sinking 1.5mA 0.05 0.40 V

VWDOH WDO Output Voltage High VDD ≥ 3.3V, Sourcing 2.5mA VDD - 0.6 VDD - 0.4 V

VDD < 3.3V, Sourcing 1.5mA VDD - 0.6 VDD - 0.4 V

IWDT Watchdog Input Current 1µA

POWER-FAIL DETECTION

VTHPFI PFI Input Threshold Voltage MR = Open 1.20 1.25 1.30 V

PFIVTHHYST Hysteresis Voltage 20 mV

VPFOL PFO Output Voltage Low VDD ≥ 3.3V, Sinking 2.5mA 0.05 0.40 V

VDD < 3.3V, Sinking 1.5mA 0.05 0.40 V

VPFOH PFO Output Voltage High VDD ≥ 3.3V, Sourcing 2.5mA VDD - 0.6 VDD - 0.4 V

VDD < 3.3V, Sourcing 1.5mA VDD - 0.6 VDD - 0.4 V

NOTE:

2. Applies to ISL88705, ISL88706, ISL88716, and ISL88813.

Electrical Specifications Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX

limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested. (Continued)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813

7FN8092.5

January 12, 2009

Low Voltage Monitoring

These devices monitor both the voltage level of VDD and an

auxiliary voltage on PFI.

When IC is initially biased reset is asserted until the VDD

voltage is greater than the specific IC fixed-voltage trip point

for the tPOR duration of 200ms. At any subsequent time that

VDD does not exceed its voltage threshold, reset is once

again asserted, i.e. RST is high and RST is low (see

Figure 1).

Power Failure Monitor

These devices also have a Power-Failure Monitor that helps

to monitor an additional critical voltage on the Power-Fail

Input (PFI) pin. For example, the PFI pin could be used to

provide an early power-fail warning, detect a low-battery

condition, presence detection or simply monitor a power

supply othe r th an +5 V. The 1.25V th resh o l d detector can be

adjusted using an external resistor divider network to provide

custom voltage monitoring of voltages greater than 1.25V,

according to Equation 1 (see Figure 2).

PFO goes low whenever PFI is less than the 1.25V (or

user-set) threshold voltage.

If using a voltage divider on the PFI input to critique an

external voltage and intending to use the MR input to initiate

resets then avoid having the PFI voltage less than PFI Vth

+2.2V as unintended PFO transiti on may occur when MR is

transitioning high.

Adjusting tPOR

On the ISL88707 and ISL88708, users can adjust the

Power-On Reset time-out delay (tPOR) to many times the

nominal tPOR of 200ms. To do this, connect a capacitor

between CPOR and ground (see Figure 3). For example,

connecting a 50pF capacitor to CPOR will increase tPOR from

200ms to ~1.4s. Care should be taken in PCB layout and

capacitor placement in order to reduce stray capacita nce as

much as possible, which contributes to tPOR error .

FIGURE 1. POWER-SUPPLY MONITORING TIMING DIAGRAM (WDI TRI-STATED)

VDD

RST

tPOR

VTH1

tPOR tPOR

>tMR

tRPD

RST

PFIV

TH 1.25 R1R2

---------------------

⎝⎠

⎜⎟

⎛⎞

=(EQ. 1)

FIGURE 2. CUSTOM VTH WITH RESISTOR DIVIDER ON PFI

VIN

PFI

ISL8870x

ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813

8FN8092.5

January 12, 2009

Manual Reset

The manual-res et input (MR ) allows the user to trigger a

reset by using a push-button switch . The MR input is an

active low debounced input. By connecting a push-button

directly from MR to ground, the designer adds manual

system reset capability (see Figure 4). Reset is asserted if

the MR pin is pulled low to less than 100mV for the minimum

MR pulse width or longer while the push-button is closed.

After MR is released, the reset outputs remain asserted for

tPOR (200ms) and then released.

Watchdog Timer

The Watchdog Timer circuit checks microprocessor activity

by monitoring the WDI input pin. The mi croprocessor must

periodically toggle the WDI pin within tWDT (typically ~1.6s),

otherwise the WDO pin pulls low (see Fig ure 5). The WDO

then signals reset periodically (typically ~1.9s) for ~220ms

until the WDI is again toggled. Internally, the 1.6s timer is

cleared by either a reset or by toggling the WDI input, which

can detect pulses longer than 50ns.

Whenever there is a low-voltage VDD condition, WDO goes

low. Unlike the reset outputs, however, WDO does not have

a minimum reset pulse width (tPOR). WDO goes high as

soon as VDD rises above its voltage trip point (see Figure 5).

With WDI open or connected to a tristated high impedance

input, the Watchdog Timer is disabled and only pulls low

when VDD < VTH1.

ISL88707, ISL88708

FIGURE 3. ADJUSTING tPOR WITH A CAPACITOR

CPOR (pF)

CPOR

0102030405060708090100

NORMALIZED tPOR vs CPOR (pF)

OPEN = 200ms

20k

FIGURE 4. CONNECTING A MANUAL RESET PUSH-BUTTON

ISL8870x

ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813

9FN8092.5

January 12, 2009

FIGURE 5. WATCHDOG TIMING DIAGRAM

VDD

WDI

WDO

VTH1

tWDT

>tWDPS

< tWDT

< tWDT < tWDT

tPOR

tRPD

RST

tPOR

tWDT

tPOR

Typical Performance Curves

FIGURE 6. IDD vs TEMPERATURE FIGURE 7. VTH1 vs TEMPERATURE FOR 5V SUPPLY

FIGURE 8. VTH1 vs TEMPERATURE < 5V SUPPLY FIGURE 9. VTHPFI vs TEMPERATURE

6.00

6.50

7.00

7.50

8.00

8.50

9.00

9.50

10.0

10.5

-40-30-20-10 0 1020304050607090

TEMPERATURE (°C)

IDD (µA)

11.0

VDD = 3.3V

VDD = 5V

4.20

4.25

4.30

4.36

4.40

4.45

4.50

4.55

4.60

4.65

-40-30-20-10 0 1020304050607090

TEMPERATUR E (°C)

VTH1 (V)

4.70

VTH = 4.64V

VTH = 4.38V

-40-30-20-100 1020304050607090

TEMPERATURE (°C)

VTH1 (V)

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

VTH = 2.92V

VTH = 3.09V

VTH = 2.63V

TEMPERATURE (°C)

1.2530

1.2525

1.2520

1.2515

1.2510

1.2505

1.2500

VTHPFI (V)

-40-30-20-10 0 1020304050607090

ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813

10 FN8092.5

January 12, 2009

FIGURE 10. RESET AND RESET ASSERTION FIGURE 11. RESET ASSERTION vs CPOR

FIGURE 12. RESET AND RESET DEASSERTION FIGURE 13. 5V PFI TO PFO RESPONSE

Typical Performance Curves (Continued)

VDD

RESET

CPOR = OPEN

tPOR = 213ms

VDD

RESET

50pF

1.5s

OPEN

172ms

4.7pF

312ms

15pF

588ms

33pF

1.1s

VDD

RESET

PFO

PFI PFI VTH

ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813

11 FN8092.5

January 12, 2009

ISL88705EVAL1 and Applications

The ISL88705EVAL1 supports all six of the ISL88705,

ISL88706, ISL88707, ISL88708, ISL88716, ISL88813

devices, enabling evaluation of basic functional operation

and common application implem entations. Figures 15 and

17 illustrate the ISL88705EVAL1 in photographic and

schematic forms respectively.

The ISL88705EVAL1 is divided into two banks; each bank

having one each of the three available pinouts. The top bank

is fully populated and immedia tely usable whereas the

bottom bank is unpopulated. Samples of other sample

variants can be evaluated singularly or in combination with

any other variant to provide a specific voltage monitoring

solution. The left position has the ISL88705IB846Z

monitoring the VDD rail voltage for a minimum of 4.64V with

reset signaling. In addition, the power fail input (PFI) is being

compared to the internal PFI voltage reference of 1.25V and

the power fail output (PFO) will report the PFI condition. This

feature can be used for monitoring an auxilia ry voltage,

providing an early warning of a brown-out or power failure or

presence detection in a system.

The middle position has the ISL88813IB846Z installed and is

set-up as a 5V window detector with jumper J1 installed. The

VDD monitors for UV and the PFI for OV via the R3, R4

divider. The PFO output is inverted and connected to the

manual reset input (MR) via U4. Hence, a reset si gnal is

generated when 4.64V < VDD > 5.38V. With J1 removed, the

PFO will be an OV indicator but no reset signal will be

generated. Both of these positi ons share a common

Watchdog input (WDI) signal although each has its own

Watchdog output (WDO).

The right position has the ISL8870 7IB846Z and is set-up as

a +12V and +5V UV monitor with reset signa l. The PFI

allows monitoring of any voltage above the 1.25V PFI

reference and with a resistor divider this is used to monitor

the 12V. The ISL88707 and ISL88708 have the unique

feature of an adjustable time to reset (tPOR) signal

generation capability via the CPOR pi n with an external

capacitor to GND. This evaluation platform has an adjustable

SMD capacitor , C4 (8pF to 45pF) that allows easy evaluation

of this feature. Also unique to the ISL88707 and ISL88708

are both the RESET and RESET outputs, all other variants

having only one or the other.

Figures 10, 11, 12, 13 and 14 illustrate the basic IC functions

and performance of the 3 implementations.

FIGURE 14. 5V OV/UV MONITORING

Typical Performance Curves (Continued)

RESET

VDD

5.5V OV

FIGURE 15. ISL88705EVAL1

ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813

12 FN8092.5

January 12, 2009

Bipolar Voltage Sensing

Any of the ISL88705, ISL88706, ISL88707, ISL88708,

ISL88716, ISL88813 devices can be used to sense and

report the presence of both a positive and negative voltage

via the PFI and PFO, as shown in Figure 16. The VDD

monitors the positive voltage as normal and the PFI monitors

the presence of the negative supply. As the differential

voltage across the R1, R2 divider is increased, the resistor

values must be chosen such that the PFI node is <1.25V

when the -V supply is satisfactory and the positive supply is

at its maximum specified value. This allows the positive

supply to fluctuate within its acceptable range without

signaling a reset. Driving the MR with the inverted PFO

signal as shown provides for reset generation when -V is not

satisfactorily present. Reset will remain asserted as long as

PFO is high.

Special Application Considerations

Using good decoupling practices will prevent transients

(i.e., due to switching noises and short duration droops in the

supply voltage) from causing unwanted resets.

When using the CPOR pin, avoid stray capacitance during

layout as much as possible in order to minimize its effect on

the tPOR timing.

If using a voltage resistor divider on the PFI input to critique

an external voltage and intending to use the MR input to

initiate resets then avoid having the PFI voltage less than

PFI Vth +2.2V as unintended PFO transition may occur

when MR is transitioning high.

FIGURE 16. ±5V MONITORING

+5V

ISL8870x, ISL88716, ISL88813

-5V

100k

100k 2N3904

RST

PFO

PFI

V+

V-

RESET

VDD

ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813

13 FN8092.5

January 12, 2009

FIGURE 17. ISL88705EVAL1 SCHEMATIC (TOP BANK)

ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813

14 FN8092.5

January 12, 2009

ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813

Plastic Dual-In-Line Packages (PDIP)

MDP0031

PLASTIC DUAL-IN-LINE PACKAGE

SYMBOL

INCHES

TOLERANCE NOTESPDIP8 PDIP14 PDIP16 PDIP18 PDIP20

A 0.210 0.210 0.210 0.210 0.210 MAX

A1 0.015 0.015 0.015 0.015 0.015 MIN

A2 0.130 0.130 0.130 0.130 0.130 ±0.005

b 0.018 0.018 0.018 0.018 0.018 ±0.002

b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015

c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002

D 0.375 0.750 0.750 0.890 1.020 ±0.010 1

E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010

E1 0.250 0.250 0.250 0.250 0.250 ±0.005 2

e 0.100 0.100 0.100 0.100 0.100 Basic

eA 0.300 0.300 0.300 0.300 0.300 Basic

eB 0.345 0.345 0.345 0.345 0.345 ±0.025

L 0.125 0.125 0.125 0.125 0.125 ±0.010

N 8 14 16 18 20 Reference

Rev. C 2/07

NOTES:

1. Plastic or metal protrusions of 0.010” maximum per side are not included.

2. Plastic interlead protrusions of 0.010” maximum per side are not included.

3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.

4. Dimension eB is measured with the lead tips unconstrained.

5. 8 and 16 lead packages have half end-leads as shown.

NOTE 5

SEATING

PLANE

PIN #1

INDEX

12 N/2

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent right s of Int ersi l or it s sub sidi aries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8092.5

January 12, 2009

ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813

Small Outline Plastic Packages (SOIC)

INDEX

AREA E

123

-B-

0.25(0.010) C AMBS

-A-

-C-

SEATING PLANE

0.10(0.004)

h x 45°

H0.25(0.010) BM M

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.0532 0.0688 1.35 1.75 -

A1 0.0040 0.0098 0.10 0.25 -

B 0.013 0.020 0.33 0.51 9

C 0.0075 0.0098 0.19 0.25 -

D 0.1890 0.1968 4.80 5.00 3

E 0.1497 0.1574 3.80 4.00 4

e 0.050 BSC 1.27 BSC -

H 0.2284 0.2440 5.80 6.20 -

h 0.0099 0.0196 0.25 0.50 5

L 0.016 0.050 0.40 1.27 6

N8 87

α0° 8° 0° 8° -

Rev. 1 6/05