STK11C68 STK11C68-M SMD#5962-92324 8K x 8 nvSRAM QuantumTrapTM CMOS Nonvolatile Static RAM FEATURES DESCRIPTION * 25ns, 35ns, 45ns and 55ns Access Times The Simtek STK11C68 is a fast static RAM with a nonvolatile element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in the Nonvolatile Elements. Data transfers from the SRAM to the Nonvolatile Elements (the STORE operation), or from Nonvolatile Elements to SRAM (the RECALL operation), take place using a software sequence. Transfers from the Nonvolatile Elements to the SRAM (the RECALL operation) also take place automatically on restoration of power. * STORE to Nonvolatile Elements Initiated by Software * RECALL to SRAM Initiated by Software or Power Restore * 10mA Typical ICC at 200ns Cycle Time * Unlimited READ, WRITE and RECALL Cycles * 1,000,000 STORE Cycles to Nonvolatile Elements (Industrial/Commercial) * 100-Year Data Retention (Industrial/Commercial) * Commercial, Industrial and Military Temperatures The STK11C68 is pin-compatible with industrystandard SRAMs. MIL-STD-883 device is also available (STK11C68-M). * 28-Pin DIP, SOIC and LCC Packages BLOCK DIAGRAM PIN CONFIGURATIONS NC A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS QUANTUM TRAP 128 x 512 A6 A7 A8 A9 A11 ROW DECODER A5 STORE STATIC RAM ARRAY 128 x 512 RECALL A12 SOFTWARE DETECT INPUT BUFFERS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 STORE/ RECALL CONTROL 28 - LCC 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VCC W NC A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 28 - DIP 28 - SOIC COLUMN I/O PIN NAMES COLUMN DEC A0 A1 A2 A3 A4 A10 G E W March 2006 A0 - A12 1 1 A0 - A12 Address Inputs W Write Enable DQ0 - DQ7 Data In/Out E Chip Enable G Output Enable VCC Power (+ 5V) VSS Ground Document Control # ML0007 rev 0.2 STK11C68 ABSOLUTE MAXIMUM RATINGSa Note a: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on Input Relative to Ground . . . . . . . . . . . . . .-0.5V to 7.0V Voltage on Input Relative to VSS . . . . . . . . . . -0.6V to (VCC + 0.5V) Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . -0.5V to (VCC + 0.5V) Temperature under Bias . . . . . . . . . . . . . . . . . . . . . -55C to 125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA (VCC = 5.0V 10%) DC CHARACTERISTICS SYMBOL COMMERCIAL INDUSTRIAL/ MILITARY MIN MIN PARAMETER ICC1b Average VCC Current ICC2c ICC3b ISB1d Average VCC Current (Standby, Cycling TTL Input Levels) ISB2d VCC Standby Current (Standby, Stable CMOS Input Levels) IILK MAX UNITS NOTES MAX 90 75 65 N/A 90 75 65 55 mA mA mA mA tAVAV = 25ns tAVAV = 35ns tAVAV = 45ns tAVAV = 55ns Average VCC Current during STORE 3 3 mA All Inputs Don't Care, VCC = max Average VCC Current at tAVAV = 200ns 5V, 25C, Typical 10 10 mA W (V CC - 0.2V) All Others Cycling, CMOS Levels 27 23 20 N/A 28 24 21 20 mA mA mA mA tAVAV = 25ns, E VIH tAVAV = 35ns, E VIH tAVAV = 45ns, E VIH tAVAV = 55ns, E VIH 750 1500 A E (V CC - 0.2V) All Others VIN 0.2V or (VCC - 0.2V) Input Leakage Current 1 1 A VCC = max VIN = VSS to VCC IOLK Off-State Output Leakage Current 5 5 A VCC = max VIN = VSS to VCC, E or G VIH VIH Input Logic "1" Voltage 2.2 VCC + .5 2.2 VCC + .5 V All Inputs VIL Input Logic "0" Voltage VSS - .5 0.8 VSS - .5 0.8 V All Inputs VOH Output Logic "1" Voltage V IOUT = - 4mA VOL Output Logic "0" Voltage 0.4 V IOUT = 8mA TA Operating Temperature 85 C 2.4 2.4 0.4 0 70 -40 Note b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. Note c: ICC is the average current required for the duration of the STORE cycle (tSTORE ) . 2 Note d: E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. 5.0V AC TEST CONDITIONS Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 CAPACITANCEe SYMBOL PARAMETER 480 Ohms OUTPUT 255 Ohms (TA = 25C, f = 1.0MHz) MAX UNITS CONDITIONS CIN Input capacitance 8 pF V = 0 to 3V COUT Output Capacitance 7 pF V = 0 to 3V Figure 1: AC Output Loading Note e: These parameters are guaranteed but not tested. March 2006 30 pF INCLUDING SCOPE AND FIXTURE 2 Document Control # ML0007 rev 0.2 STK11C68 SRAM READ CYCLES #1 & #2 (VCC = 5.0V + 10%) SYMBOLS NO. STK11C68-25 STK11C68-35 STK11C68-45 STK11C68-55 PARAMETER #1, #2 1 tELQV 2 tAVAV f 3 tAVQVg 4 tGLQV UNITS Alt. MIN MAX MIN MIN MAX tRC Read Cycle Time tAA Address Access Time 25 35 45 55 ns tOE Output Enable to Data Valid 10 15 20 25 ns 5 tAXQXg tOH Output Hold after Address Change 5 5 5 5 ns 6 tELQX tLZ Chip Enable to Output Active 5 5 5 5 ns 7 tEHQZh tHZ Chip Disable to Output Inactive 8 tGLQX tOLZ Output Enable to Output Active 9 tGHQZh tOHZ Output Disable to Output Inactive tPA Chip Enable to Power Active tPS Chip Disable to Power Standby 10 tELICCH 11 tEHICCLd, e 35 10 0 0 55 15 0 0 15 0 45 ns ns 25 0 35 ns ns 25 0 13 25 55 45 13 10 0 45 MAX Chip Enable Access Time 25 35 MIN tACS e 25 MAX ns ns 55 ns Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles. Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected. Note h: Measured 200mV from steady state output voltage. SRAM READ CYCLE #1: Address Controlledf, g 2 tAVAV ADDRESS 3 tAVQV 5 tAXQX DQ (DATA OUT) DATA VALID SRAM READ CYCLE #2: E Controlledf 2 tAVAV ADDRESS 1 11 tELQV tEHICCL 6 tELQX E 7 tEHQZ G 9 tGHQZ 4 8 tGLQV tGLQX DQ (DATA OUT) DATA VALID 10 tELICCH ICC March 2006 ACTIVE STANDBY 3 Document Control # ML0007 rev 0.2 STK11C68 SRAM WRITE CYCLES #1 & #2 (VCC = 5.0V + 10%) SYMBOLS STK11C68-25 NO. STK11C68-35 STK11C68-45 STK11C68-55 PARAMETER UNITS #1 #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX 12 tAVAV tAVAV tWC Write Cycle Time 25 35 45 55 ns 13 tWLWH tWLEH tWP Write Pulse Width 20 25 30 45 ns 14 tELWH tELEH tCW Chip Enable to End of Write 20 25 30 45 ns 15 tDVWH tDVEH tDW Data Set-up to End of Write 10 12 15 30 ns 16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 0 0 ns 17 tAVWH tAVEH tAW Address Set-up to End of Write 20 25 30 45 ns 18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 0 ns 19 tWHAX tEHAX tWR Address Hold after End of Write 0 0 0 0 ns 20 tWLQZh, i tWZ Write Enable to Output Disable 21 tWHQX tOW Output Active after End of Write Note i: Note j: 10 13 5 5 15 5 35 5 ns ns If W is low when E goes low, the outputs remain in the high-impedance state. E or W must be VIH during address transitions. SRAM WRITE CYCLE #1: W Controlledj 12 tAVAV ADDRESS 19 tWHAX 14 tELWH E 17 tAVWH 18 tAVWL 13 tWLWH W 15 tDVWH DATA IN DATA OUT 16 tWHDX DATA VALID 20 tWLQZ HIGH IMPEDANCE PREVIOUS DATA 21 tWHQX SRAM WRITE CYCLE #2: E Controlledj 12 tAVAV ADDRESS 14 tELEH 18 tAVEL 19 tEHAX E 17 tAVEH W 13 tWLEH 15 tDVEH DATA IN DATA OUT March 2006 16 tEHDX DATA VALID HIGH IMPEDANCE 4 Document Control # ML0007 rev 0.2 STK11C68 STORE INHIBIT/POWER-UP RECALL (VCC = 5.0V + 10%) SYMBOLS STK11C68 NO. PARAMETER UNITS NOTES Standard MIN 22 tRESTORE Power-up RECALL Duration 23 tSTORE STORE Cycle Duration 24 VSWITCH Low Voltage Trigger Level 25 VRESET Low Voltage Reset Level 4.0 MAX 550 s 10 ms 4.5 V 3.6 V k Note k: tRESTORE starts from the time VCC rises above VSWITCH. STORE INHIBIT/POWER-UP RECALL VCC 5V 24 VSWITCH 25 VRESET STORE INHIBIT POWER-UP RECALL 22 tRESTORE DQ (DATA OUT) POWER-UP RECALL March 2006 BROWN OUT STORE INHIBIT BROWN OUT STORE INHIBIT BROWN OUT STORE INHIBIT NO RECALL (VCC DID NOT GO BELOW VRESET) NO RECALL (VCC DID NOT GO BELOW VRESET) RECALL WHEN VCC RETURNS ABOVE VSWITCH 5 Document Control # ML0007 rev 0.2 STK11C68 SOFTWARE STORE/RECALL MODE SELECTION E L L Note l: W A12 - A0 (hex) MODE I/O NOTES H 0000 1555 0AAA 1FFF 10F0 0F0F Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Output Data Output Data Output Data Output Data Output Data Output High Z l H 0000 1555 0AAA 1FFF 10F0 0F0E Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL Output Data Output Data Output Data Output Data Output Data Output High Z l The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle. SOFTWARE STORE/RECALL CYCLEm, n NO. 26 SYMBOLS tAVAV m 27 tAVEL 28 tELEHm 29 tELAXm 30 tRECALL m (VCC = 5.0V 10%) STK11C68-25 STK11C68-35 STK11C68-45 STK11C68-55 MIN MIN MIN MIN PARAMETER UNITS MAX MAX MAX MAX STORE/RECALL Initiation Cycle Time 25 35 45 55 ns Address Set-up Time 0 0 0 0 ns Clock Pulse Width 20 25 30 35 ns Address Hold Time 20 20 20 20 ns RECALL Duration 20 20 20 20 s Note m: The software sequence is clocked with E controlled reads. Note n: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive cycles. SOFTWARE STORE/RECALL CYCLE: E Controlledn 26 26 tAVAV ADDRESS tAVAV ADDRESS #1 27 tAVEL ADDRESS #6 28 tELEH E 29 tELAX 23 tSTORE DQ (DATA March 2006 DATA VALID DATA VALID 6 30 / tRECALL HIGH IMPEDANCE Document Control # ML0007 rev 0.2 STK11C68 DEVICE OPERATION SOFTWARE NONVOLATILE STORE The STK11C68 is a versatile memory chip that provides several modes of operation. The STK11C68 can operate as a standard 8K x 8 SRAM. It has an 8K x 8 Nonvolatile Elements shadow to which the SRAM information can be copied or from which the SRAM can be updated in nonvolatile mode. The STK11C68 software STORE cycle is initiated by executing sequential READ cycles from six specific address locations. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. The program operation copies the SRAM data into nonvolatile memory. Once a STORE cycle is initiated, further input and output are disabled until the cycle is completed. NOISE CONSIDERATIONS Note that the STK11C68 is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1F connected between Vcc and Vss, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, normal careful routing of power, ground and signals will help prevent noise problems. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted and no STORE or RECALL will take place. SRAM READ To initiate the software STORE cycle, the following READ sequence must be performed: The STK11C68 performs a READ cycle whenever E and G are low and W is high. The address specified on pins A0-12 determines which of the 8,192 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ cycle #1). If the READ is initiated by E or G, the outputs will be valid at tELQV or at tGLQV, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought high. 1. 2. 3. 4. 5. 6. 0000 (hex) 1555 (hex) 0AAA (hex) 1FFF (hex) 10F0 (hex) 0F0F (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE cycle The software sequence must be clocked with E controlled READs. Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence, although it is not necessary that G be low for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation. SRAM WRITE A WRITE cycle is performed whenever E and W are low. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. SOFTWARE NONVOLATILE RECALL A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of READ operations must be performed: It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left low, internal circuitry will turn off the output buffers tWLQZ after W goes low. March 2006 Read address Read address Read address Read address Read address Read address 1. 2. 3. 4. 5. 6. 7 Read address Read address Read address Read address Read address Read address 0000 (hex) 1555 (hex) 0AAA (hex) 1FFF (hex) 10F0 (hex) 0F0E (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL cycle Document Control # ML0007 rev 0.2 STK11C68 HARDWARE PROTECT Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation in no way alters the data in the Nonvolatile Elements. The nonvolatile data can be recalled an unlimited number of times. The STK11C68 offers hardware protection against inadvertent STORE operation during low-voltage conditions. When VCC < VSWITCH, software STORE operations are inhibited. LOW AVERAGE ACTIVE POWER The STK11C68 draws significantly less current when it is cycled at times longer than 50ns. Figure 2 shows the relationship between ICC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Figure 3 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK11C68 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the Vcc level; and 7) I/O loading. POWER-UP RECALL During power up, or after any low-power condition (VCC < VRESET), an internal RECALL request will be latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tRESTORE to complete. If the STK11C68 is in a WRITE state at the end of power-up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10K Ohm resistor should be connected either between W and system VCC or between E and system VCC. 100 Average Active Current (mA) Average Active Current (mA) 100 80 60 40 TTL 20 80 60 TTL 40 CMOS 20 CMOS 0 0 50 100 150 Cycle Time (ns) 50 200 Figure 2: ICC (max) Reads March 2006 100 150 Cycle Time (ns) 200 Figure 3: ICC (max) Writes 8 Document Control # ML0007 rev 0.2 STK11C68 Commercial/Industrial Ordering Information STK11C68 - S F 45 I Temperature Range Blank = Commercial (0 to 70C) I = Industrial (-40 to 85C) Access Time 25 = 25ns 35 = 35ns 45 = 45ns Lead Finish F = 100% Sn (Matte Tin) Package S = Plastic 28-pin 350 mil SOIC March 2006 9 Document Control # ML0007 rev 0.2 STK11C68 Millitary Ordering Information STK11C68 - 5 C 45 M Temperature Range M = Military (-55 to 125C) Access Time 35 = 35ns 45 = 45ns 55 = 55ns Package C = Ceramic 28-pin 300 mil DIP (gold lead finish) K = Ceramic 28-pin 300 mil DIP (solder dip finish) L = Ceramic 28 pin LCC Retention / Endurance 5 = Military (10 years/105cycles) 5962-92324 04 MX X Lead Finish A = Solder DIP lead finish C = Gold lead DIP finish X = Lead finish "A" or "C" is acceptable Package MX = Ceramic 28 pin 300-mil DIP MY = Ceramic 28 pin LCC Access Time 04 = 55ns 05 = 45ns 06 = 35ns March 2006 10 Document Control # ML0007 rev 0.2 STK11C68 Document Revision History Revision Date Summary 0.0 December 2002 Combined commercial, industrial and military data sheets. Removed 20 nsec device. 0.1 September 2003 Added lead-free lead finish 0.2 March 2006 Removed leaded lead finish for all Commercial/Industrial Parts, Removed "P" package. March 2006 11 Document Control # ML0007 rev 0.2 STK11C68 March 2006 12 Document Control # ML0007 rev 0.2