March 2006 1 Document Control # ML0007 rev 0.2
STK11C68
STK11C68-M SMD#5962-92324
8K x 8 nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
FEATURES
• 25ns, 35ns, 45ns and 55ns Access Times
•STORE to Nonvolatile Elements Initiated by
Software
•RECALL to SRAM Initiated by Software or
Power Restore
• 10mA Typical ICC at 200ns Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to Nonvolatile Ele-
ments (Industrial/Commercial)
• 100-Year Data Retention (Industrial/Commer-
cial)
• Commercial, Industrial and Military Tempera-
tures
• 28-Pin DIP, SOIC and LCC Packages
DESCRIPTION
The Simtek STK11C68 is a fast static RAM with a
nonvolatile element incorporated in each static
memory cell. The SRAM can be read and written an
unlimited number of times, while independent non-
volatile data resides in the Nonvolatile Elements.
Data transfers from the SRAM to the Nonvolatile Ele-
ments (the STORE operation), or from Nonvolatile
Elements to SRAM (the RECALL operation), take
place using a sof tware s equence. Transfers from the
Nonvolatile Elements to the SRAM (the RECALL
operation) also take place automatically on restora-
tion of power.
The STK11C68 is pin-compatible with industry-
standard SRAMs. MIL-STD-883 device is also
available (STK11C68-M).
BLOCK DIAGRAM
COLUM N I/O
COLUMN DEC
STATIC RAM
ARRAY
128 x 512
ROW DECODER
INPUT BUFFERS
QUANTUM TRAP
128 x 512
STORE/
RECALL
CONTROL
STORE
RECALL
A
5
A
6
A
9
A
11
A
12
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
SOFTWARE
DETECT A
0
-
A
12
G
E
W
A
8
A
7
A
10
A
3
A
2
A
0
A
1
A
4
PIN CONFIGURATIONS
NC
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
1
DQ
2
V
SS
V
CC
NC
A
8
A
9
A
11
G
W
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
28 - LCC 28 - DIP
28 - SOIC
PIN NAMES
A0 - A12 Address Inputs
WWrite Enable
DQ0 - DQ7Data In/Out
EChip Enab le
GOutput Enable
VCC Power (+ 5V)
VSS Ground
STK11C68
March 2006 2 Document Control # ML0007 rev 0.2
ABSOLUTE MAXIMUM RATINGSa
Voltage on Input Relative to Ground. . . . . . . . . . . . . .–0.5V to 7.0V
Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Tem perature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration). . . . . . . .15mA
DC CHARACTERISTICS (VCC = 5.0V ± 10%)
Note b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: ICC2 is the average current required for the duration of the STORE cycle (tSTORE ) .
Note d: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CON DITIONS
CAPACITANCEe(TA = 25°C, f = 1.0MHz)
Note e: These parameters are guaranteed but not tested.
SYMBOL PARAMETER COMMERCIAL INDUSTRIAL/
MILITARY UNITS NOTES
MIN MAX MIN MAX
ICC1bAverag e V CC Current 90
75
65
N/A
90
75
65
55
mA
mA
mA
mA
tAVAV = 25ns
tAVAV = 35 ns
tAVAV = 45ns
tAVAV = 55ns
ICC2cAverag e V CC Current during STORE 3 3 mA All Inputs Don’t Care, VCC = max
ICC3bAverag e V CC Current at tAVAV = 200ns
5V, 25°C, Typical 10 10 mA W ≥ (VCC – 0.2V)
All Others Cycling, CMOS Lev els
ISB1dAverage VCC Current
(Standby, Cycling TTL Input Lev els) 27
23
20
N/A
28
24
21
20
mA
mA
mA
mA
tAVAV = 25 ns , E ≥ VIH
tAVAV = 35ns, E ≥ VIH
tAVAV = 45ns, E ≥ VIH
tAVAV = 55ns, E ≥ VIH
ISB2dVCC Standby Current
(Standby, Stable CMOS Input Lev els) 750 1500 μAE ≥ (VCC - 0.2V )
All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V)
IILK Input Leakage Current ±1±1μAVCC = max
VIN = VSS to VCC
IOLK Off-State Output Leakage Current ±5±5μAVCC = max
VIN = VSS to VCC, E or G ≥ VIH
VIH Input Logic “1” Voltage 2.2 VCC + .5 2.2 VCC + .5 VAll In p u ts
VIL Input Logic “0” Voltage VSS – .5 0.8 VSS – .5 0.8 VAll In p u ts
VOH Output Logic “1” V oltage 2.4 2.4 V IOUT = –4mA
VOL Output Logic “0” V oltage 0.4 0.4 V IOUT = 8mA
TAOperating Temper ature 070 –40 85 °C
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Level s . . . . . . . . . . . . . . . 1.5V
Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
SYMBOL PARAMETER MAX UNITS CONDITIONS
CIN Input capacitance 8pF ΔV = 0 to 3V
COUT Output Capacitance 7pF ΔV = 0 to 3V Figure 1: AC Output Loading
480 Ohms
30 pF
255 Ohms
5.0V
INCLUDING
OUTPUT
SCOPE AND
FIXTURE
Note a: Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at condi-
tions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
STK11C68
March 2006 3 Document Control # ML0007 rev 0.2
SRAM READ CYCLES #1 & #2 (VCC = 5.0V + 10%)
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected.
Note h: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledf, g
SRAM READ CYCLE #2: E Controlledf
NO.
SYMBOLS PARAMETER STK11C68-25 STK11C68-35 STK11C68-45 STK11C68-55 UNITS
#1, #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
1 tELQV tACS Chip Enable Access Time 25 35 45 55 ns
2 tAVAVftRC Read Cycle Time 25 35 45 55 ns
3 tAVQVgtAA Address Access Time 25 35 45 55 ns
4 tGLQV tOE Output Enable to Data V alid 10 15 20 25 ns
5 tAXQXgtOH Output Hold after Address Change 5 5 5 5 ns
6 tELQX tLZ Chip Enable to Output Active 5 5 5 5 ns
7 tEHQZhtHZ Chip Disable to Output Inactive 10 13 15 25 ns
8 tGLQX tOLZ Output Enable to Output Active 0 0 0 0 ns
9 tGHQZhtOHZ Output D i s a ble t o Outp ut Inactiv e 10 13 15 25 ns
10 tELICCHetPA Chip Enable to Power Active 0 0 0 0 ns
11 tEHICCLd, e tPS Chip Disable to Power Standby 25 35 45 55 ns
DATA VALID
5
tAXQX
3
tAVQV
DQ (DATA OUT)
ADDRESS
2
tAVAV
6
tELQX
STANDBY
DATA VALID
8
tGLQX
4
tGLQV
DQ (DATA OUT)
E
ADDRESS
2
tAVAV
G
ICC
ACTIVE
1
tELQV
10
tELICCH
11
tEHICCL
7
tEHQZ
9
tGHQZ
STK11C68
March 2006 4 Document Control # ML0007 rev 0.2
SRAM WRITE CY CLES #1 & # 2 (VCC = 5.0V + 10%)
Note i: If W is low when E goes low, the outputs remain in the high-impedance state.
Note j: E or W must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledj
SRAM WRITE CYCLE #2: E Controlledj
NO. SYMBOLS PARAMETER STK11C68-25 STK11C68-35 STK11C68-45 STK11C68-55 UNITS
#1 #2 Alt. MIN MAX MIN MAX MIN MAX MIN MAX
12 tAVAV tAVAV tWC Write Cy c l e Time 25 35 45 55 ns
13 tWLWH tWLEH tWP Write Pulse Width 20 25 30 45 ns
14 tELWH tELEH tCW Chip Enable to End of Write 20 25 30 45 ns
15 tDVWH tDVEH tDW Data Set-up to End of Write 10 12 15 30 ns
16 tWHDX tEHDX tDH Data Hold after End of Write 0 0 0 0 ns
17 tAVWH tAVEH tAW Address Set-up to End of Write 20 25 30 45 ns
18 tAVWL tAVEL tAS Address S et-up to Start of Write 0 0 0 0 ns
19 tWHAX tEHAX tWR Address Ho ld after End o f Write 0 0 0 0 ns
20 tWLQZh, i tWZ Wr ite Enable to Output Disable 10 13 15 35 ns
21 tWHQX tOW Output Active after End of Write 5 5 5 5 ns
PREVIOUS DATA
DATA OUT
E
ADDRESS
12
tAVAV
W
16
tWHDX
DATA IN
19
tWHAX
13
tWLWH
18
tAVWL
17
tAVWH
DATA VALID
20
tWLQZ
15
tDVWH
HIGH IMPEDANCE
21
tWHQX
14
tELWH
DATA OUT
E
ADDRESS
12
tAVAV
W
DATA IN
13
tWLEH
17
tAVEH
DATA VALID
HIGH IMPEDANCE
14
tELEH
18
tAVEL
15
tDVEH
19
tEHAX
16
tEHDX
STK11C68
March 2006 5 Document Control # ML0007 rev 0.2
STORE INHIBIT/POWER- UP RECALL (VCC = 5.0V + 10%)
Note k: tRESTORE starts from the time VCC rises above VSWITCH.
STORE INHIBIT/POWER- UP RECALL
NO. SYMBOLS PARAMETER STK11C68 UNITS NOTES
Standard MIN MAX
22 tRESTORE Power-up RECALL Duration 550 μs k
23 tSTORE STORE Cycle Duration 10 ms
24 VSWITCH Low Voltage Trigger Level 4.0 4.5 V
25 VRESET Low Voltage Reset Level 3.6 V
V
CC
V
SWITCH
V
RESET
POWER-UP RECALL
DQ (DATA OUT)
STORE INHIBIT
5V
22
tRESTORE
24
25
POWER-UP
RECALL BROWN OUT
STORE INHIB I T
NO RECALL
(VCC DID NOT GO
BELOW VRESET)
BROWN OUT
STORE INHIBIT
NO RECALL
(VCC DID NOT GO
BELOW VRESET)
BROWN OU T
STORE INHI BIT
RECALL WHEN
VCC RETURNS
ABOVE VSWITCH
STK11C68
March 2006 6 Document Control # ML0007 rev 0.2
SOFTWARE STORE/RECALL MODE SELECTION
Note l: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
SOFTWARE STORE/RECALL CYCLEm, n(VCC = 5.0V ± 10%)
Note m: The software sequence is clocked with E controlled reads.
Note n: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0000, 1555, 0AAA, 1FFF,
10F0, 0F0F) for a STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive
cycles.
SOFTWARE STORE/RECALL CYCLE: E Controlledn
E W A12 - A0 (hex) MODE I/O NOTES
L H
0000
1555
0AAA
1FFF
10F0
0F0F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
l
L H
0000
1555
0AAA
1FFF
10F0
0F0E
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
l
NO. SYMBOLS PARAMETER STK11C68-25 STK11C68-35 STK11C68-45 STK11C68-55 UNITS
MIN MAX MIN MAX MIN MAX MIN MAX
26 tAVAV STORE/RECALL Initiatio n Cy c le Time 25 35 45 55 ns
27 tAVELmAddress S et-up Time 0 0 0 0 ns
28 tELEHmClock Pulse Width 20 25 30 35 ns
29 tELAXmAddress Hold Time 20 20 20 20 ns
30 tRECALLmRECALL Dura t i on 20 20 20 20 μs
HIGH IMPEDANCE
ADDRESS #6ADDRESS #1
DATA VALID
26
tAVAV
DATA VALID
DQ (DATA
E
ADDRESS
23 30
tSTORE / tRECALL
26
tAVAV
27
tAVEL 28
tELEH
29
tELAX
STK11C68
March 2006 7 Document Control # ML0007 rev 0.2
The STK11C68 is a versatile memory chip that pro-
vides several modes of operation. The STK11C68
can operate as a standard 8K x 8 SRAM. It has an
8K x 8 Nonvolatile Elements shadow to which the
SRAM information can be copied or from which the
SRAM can be updated in nonvolatile mode.
NOISE CONSIDERATIONS
Note that the STK11C68 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1μF connected between Vcc
and Vss, using leads and traces that are as short as
possible. As with all high-speed CMOS ICs, normal
careful routing of power, ground and signals will
help prevent noise problems.
SRAM READ
The STK11C68 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A0-12 determines which of the 8,192 data
bytes will be accessed. When the READ is initiated
by an address transition, the outputs will be valid
after a delay of tAVQV (READ cycle #1). If the READ is
initiated by E or G, the outputs will be valid at tELQV or
at tGLQV, whichever is later (READ cycle #2). The data
outputs will repeatedly respond to address changes
within the tAVQV access time without the need for tran-
sitions on any control input pins, and will remain valid
until another address change or until E or G is
brought high.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ0-7 will be writ-
ten into the memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an
E controlled WRITE.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the comm on I/ O lin es. I f G is le ft low, in tern al ci rcui try
will turn off the output buffers tWLQZ after W goes low.
SOFTWARE NONVOLATILE STORE
The STK11C68 software STORE cycle is initiated by
executing sequential READ cycles from six specific
address locations. During the STORE cycle an erase
of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements.
The program operation copies the SRAM data into
nonvolatile memory. Once a STORE cycle is initi-
ated, further input and output are disabled until the
cycle is completed.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is impor-
tant that no other READ or WRITE accesses inter-
vene in the sequence or the sequence will be
aborted and no STORE or RECALL will take place.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1. Read address 0000 (hex) Valid READ
2. Read address 1555 (hex) Valid READ
3. Read address 0AAA ( hex) Valid READ
4. Read address 1FFF (he x) Valid READ
5. Read address 10F0 (hex) Valid READ
6. Read address 0F0F (hex) Initiate STORE cycle
The software sequence must be clocked with E con-
trolled READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the tSTORE cycle time has
been fulfilled, the SRAM will again be activated for
READ and WRITE operation.
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiate d with a sequence
of READ operations in a manner similar to the soft-
ware STORE initiation. To initiate the RECALL cycle,
the following sequence of READ operations must be
performed:
1. Read address 0000 (hex) Valid READ
2. Read address 1555 (hex) Valid READ
3. Read address 0AAA ( hex) Valid READ
4. Read address 1FFF (he x) Valid READ
5. Read address 10F0 (hex) Valid READ
6. Read address 0F0E (hex) Init iate RECALL cycle
DEVICE OPERATION
STK11C68
March 2006 8 Document Control # ML0007 rev 0.2
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvola-
tile information is transferred into the SRAM cells.
After the tRECALL cycle time the SRAM will once again
be ready for READ and WRITE operations. The
RECALL operation in no way alters the data in the
Nonvolatile Elements. The nonvolatile data can be
recalled an unlimited number of times.
POWER-UP RECALL
During power up, or after any low-power condition
(VCC < VRESET), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the STK11C68 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
VCC or between E and system VCC.
HARDWARE PROTECT
The STK11C68 offers hardware protection against
inadvertent STORE operation during low-voltage
conditions. When VCC < VSWITCH, software STORE
operations are inhibited.
LOW AVERAGE ACTIVE POWER
The STK11C68 draws significantly less current
when it is cycled at times longer than 50ns. Figure 2
shows the relationship between ICC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
perature range, VCC = 5.5V, 100% duty cycle on chip
enable). Figure 3 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK11C68 depends on the following items:
1) CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of READs to WRITEs; 5) the operating
temperature; 6) the Vcc level; and 7) I/O loading.
Figure 2: ICC (max) Reads
0
20
40
60
80
100
50 100 150 200
Cycle Time (ns)
TTL
CMOS
A verage Active Current (mA)
Figure 3: ICC (max) Writes
0
20
40
60
80
100
50 100 150 200
Cycle T ime (ns)
TTL
CMOS
Average Active Current (mA)
STK11C68
March 2006 9 Document Control # ML0007 rev 0.2
Commercial/Industrial Ordering Information
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C)
Access Time
25 = 25ns
35 = 35ns
45 = 45ns
Lead Finish
F = 100% Sn (Matte Tin)
Package
S = Plastic 28-pin 350 mil SOIC
- S F 45 I
STK11C68
STK11C68
March 2006 10 Document Control # ML0007 rev 0.2
Millit
ary
O
r
d
er
i
ng
I
n
f
orma
ti
on
Temperature Range
M = Military (–55 to 125°C)
Access Time
35 = 35ns
45 = 45ns
55 = 55ns
Package
C = Ceramic 28-pin 300 mil DIP (gold lead finish)
K = Ceramic 28-pin 300 mil DIP (solder dip finish)
L = Ceramic 28 pin LCC
Retention / Endurance
5 = Military (10 years/105cycles)
Lead Finish
A = Solder DIP lead finish
C = Gold lead DIP finish
X = Lead finish “A” or “C” is acceptable
Package
MX = Ceramic 28 pin 300-mil DIP
MY = Ceramic 28 pin LCC
Access Time
04 = 55ns
05 = 45ns
06 = 35ns
- 5 C 45 M
STK11C68
5962-92324 04 MX X
STK11C68
March 2006 11 Document Control # ML0007 rev 0.2
Document Revision History
Revision Date Summary
0.0 December 2002 Combined commercial, industrial and mil itary data sheet s. Rem oved 20 nsec device.
0.1 September 2003 Added lead-free lead finish
0.2 March 2006 Removed leaded lead finish for all Commerci al/In dustri al Parts, Removed “P” package .
STK11C68
March 2006 12 Document Control # ML0007 rev 0.2
