MILITARY SPECIFICATION
MICROCIRCUIT , DIGITAL, 4096-BIT SCHOTTKY, BIPOLAR, PROGRAMMABLE READ-ONLY MEMORY (PROM),
MONOLITHIC SILIC ON
This specif ication is approved for use by all Department sand Agencies of the Department of Defense.
The requireme nts for acquiring the product herein shall c onsist of this s pecification sheet and MIL-PRF 38535.
1. SCOPE
1.1 Scope. T his s pec i fication covers the detail requirements for monolith i c silicon, pr ogrammable read-only memory
(PROM) microcircuits which employ thin film nichrom e (NiCr) resistors, titanium-tungsten ( TiW), or zapped vertical emit ter
(ZVE) as the fusible link or program ming element. Two product assurance c lasses and a choice of case outlines and lead
finishes are provided and are reflected in th e complete part number. For this product, the requireme nts of MIL-M-38510
have been superseded by MIL-PRF-38535, (see 6.4).
1.2 Part or Identifying Number (PIN). The PIN is in accorda nc e with MIL-PRF-38535, and as specif ied herein.
1.2.1 Device types. The devi c e types are as foll ows:
Device type Circuit
01 512 word/8 bits per word PROM with uncomm itted collector
02 512 word/8 bits per word PROM with active pull-up and a ch oi c e
third high-imped ance state output
03 512 word/8 bits per word PROM with active pull-up and a third
high-impedance state output
04 512 word/8 bits per word PROM with uncomm itted collector
05 512 word/8 bits per word PROM with active pull-up and a third
high-impedance stat e output
1.2.2 Device class. The device c lass is the prod uc t assurance level as defi ned in MIL-PRF-38535.
1.2.3 Case outli nes . The case outl ines are as designated in MIL-STD-1835 and as follo ws:
Outline letter Descriptive designator Terminals Package style
J GDIP1-T24 or CDIP2-T24 24 Dual-in-line
K GDFP2-F24 or CDFP3-F24 24 Flat pack
X See figure 1 24 Flat pack
Y See figure 2 20 Dual-in-line
Z CQCC1-N24 24 Square le adless chip carr ier
Comments, suggestions, or questions on this document should be addressed to: Commander, Defense
Supply Cent er C olumbus, ATTN: DLA LAND AND MARITIME-VAS, P. O. Box 3990, Col um bus, OH 43218-
3990, or emailed to Memory@dla.mil. Since contact inform ation can change, you may want to ver ify the
currency of this address information using the ASSIST Online database at https://assist.dla.mil
AMSC N/A FSC 5962
INCH-POUND
MIL-M-38510/208F
21 August 2013
SUPERSEDING
MIL-M-38510/208E
12 October 2010
Inactive for new design after 24 July 1995
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MIL-M-38510/208F
2
1.3 Absolute maximum ratings.
Supply voltage range ............................................................................. -0.5 V dc to +7.0 V dc
Input volta ge range ................................................................................ -1.5 V dc at -10 mA to +5.5 V dc
Storage temperature range .................................................................... -65° to +150°C
Lead temperature (soldering, 10 seconds) .............................................. +300°C
Thermal resis tance, junction to case (θJC) 1/:
Cases J, K, and Y ............................................................................. 30°C/W
Case X and Z ................................................................................... 36° C/W
Output voltage applied ............................................................................ -0.5 V dc dc to +VCC
Output sink current ............................................................................ 100 mA
Maximum power dissipation (PD) 2/ ........................................................ 1.02 W
Maximum, junction temper ature (T J) ....................................................... +175°C
1.4 Recommende d operating c ondi tions.
Supply voltage ....................................................................................... +4.5 V dc minimum to
+5.5 V dc maximum
Minimum high-lev el input voltage .......................................................... 2.0 V dc
Maximum low-level input volt age .......................................................... 0.8 V dc
Normalized fanout (each output) .......................................................... 8 mA 3/
Case operating temperature range (T C) .................................................. -55 °C t o +125 °C
2. APPLICABLE DOCUMENTS
2.1 General. The documents li s ted in this sect i on ar e specified in sections 3, 4, or 5 of this specification. This
section does n ot include documents cited in other sections of this specification or recommended for addi tional
information or as examples. While every effort has been m ade to ensure the c om pleteness of this list, doc um ent
users are cautioned that they must meet all specified requirements of documents cited in sections 3, 4, or 5 of
this specification, whether or not they are listed.
2.2 Government documents.
2.2.1 Specifications and Standards. The f ol lowing specifications and st andards form a part of this
specificat ion to the extent s pecified herein. Unless otherwise specif ied, the i s sues of these documents are those
cited in the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATIONS
MIL-PRF-38535 - Integrated Circuits (Mi c rocircuits) M anufacturing, General Specif ication for .
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 - Test Met hod Standard for Mic roelectronic s.
MIL-STD-1835 - Interface St andard Electro nic Component C ase Outline
(Copies of these documents are availabl e online at http://quicksearch.dla.mil or from the S tandardization
Document Order Desk, 700 Robbins Avenue, Bui lding 4D, Phil adelphia, PA 19111-5094.)
2.3 Order of precedence. Unless otherwise noted herein or i n the contract, in the event of a c onflict between
the text of this doc ument and the references cited herein (except for related s pec i fication sheets), the text of this
document takes precedenc e. Nothing in thi s document, however, supersedes applicabl e laws and regulations
unless a specific exemption has been obtained.
_____
1/ Heat sinking is recommended to reduce the junction temperature.
2/ Must withst and the added PD due to short circ uit test (e.g. IOS).
3/ 16 mA for circuit F devices.
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MIL-M-38510/208F
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3. REQUIREMENTS
3.1 Qualification. Microcircuits furnished under this s pecificati on s hall be prod ucts that are manuf ac tured by
a manufacturer authorized by the qualif ying activity for listing on t he applicable qualified manuf acturers list before
contract award (see 4.3 and 6.3).
3.2 Item requirements. The individual item requirements shall be in accordance with MI L-PRF-38535 and as
specified herein or as modified in the device manufactur ers Quality Management (QM) plan. The modification in
the QM plan shall not affect the form, fit, or function as described herein.
3.3 Design, construction, and physical di m ensions. The design, const r uction, and physical dimens ions shall
be as specified in MIL-PRF-38535 a nd herein.
3.3.1 Term inal c onnections. The terminal conn ec tions shall be as specified on figures 3.
3.3.2 Truth table
3.3.2.1 Unprogrammed devi ces. The truth table f or unprogrammed devices for c ontracts involving no altered
item drawing shall be as specified on figure 4. When required in groups A, B, or C (see 4.4), the devices shall be
programmed by the manufactur er prior to test in a checkerboard pattern (a minimum of 50 percent of the total
number of bits programmed) or to any altere d item drawing pat tern which incl udes at leas t 25 percent of t he total
number of bits programmed.
3.3.2.2 Programmed devices. The truth table for programm ed devices shall be as specif i ed by the altered
item drawing.
3.3.3 Logic diagram. The logic diagram shall be as specifie d on figure 5.
3.3.4 Case outli nes . The case outl ines shall be as s pecified in 1.2.3.
3.4 Lead material and finish. The lead material and finis h shall be in accordance with MIL-PRF-38535 (see
6.6).
3.5 Electrical performance characteristics. The electric al performance characterist i c s are as specified in
table I, and apply over the ful l recommended case operating temperature range, unless otherwise specifi ed.
3.6 Electrical test requir ements. The el ec trical test requirements shall be as specified in table II, and where
applicable, the altered it em drawing. The electrical tests for each subgroup are described in table III.
3.7 Marking. Mar k i ng shall be in acc ordance with MIL-PRF-38535.
3.8 Processing options. Sin ce the PROM is an unprogrammed mem ory capable of being programmed by
either the manufacturer or the user to result in a wide variety of configurations, two processing options are
provided for selection in the contract, using an altered it em drawing.
3.8.1 Unprogrammed PROM delivered to the us er. All test i ng s hall be verified through group A testing as
defined in 3.3.2.1, table II, and table III. It i s recom mended that user s perform subgroups 7 and 9 after
programming to verify the specific program configuration.
3.8.2 Manufacturer-programmed PROM delivered to the user. All testing requirements and qualit y assurance
provisions h er ein, includi ng the requirements of the alter ed item dra wing, shall be satisf ied by the manufacturer
prior to delivery.
3.9 Microcircuit group assignment. The devices covered by this spec ification sh all be in microcircuit group
number 14 (see A ppendix A MIL-PRF-38535.)
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MIL-M-38510/208F
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TABLE I. Electrical per formance characteristics.
Test
Symbol
Conditions 1/ 2/
Device
type
Limits
Min
Max
High-level outp ut voltage
V
OH
V
CC
= 4.5 V,
IOH = -2 mA
02,03,05
2.4
---
Low-level output voltage
V
OL
V
CC
= 4.5 V,
IOL = 8 mA 3/
All
---
0.5
Input clamp voltage
V
IC
V
CC
= 4.5 V,
IIN = -10 mA,
TC = 25
°
C
All
---
-1.5
Maximum collector cut-off
current
I
CEX
V
CC
= 5.5 V,
VO = 5.2 V
01,04
---
100
High-impedance ( off-state)
output high current
I
OHZ
V
CC
= 5.5 V
VO = 5.2 V
02,03,05
---
100
High-impedance ( off-state)
output low curr ent
I
OLZ
V
CC
= 5.5 V,
VO = 0.5 V
02,03,05
-100
High-level input current
I
IH1
V
CC
= 5.5 V,
VIN = 5.5 V
All
---
50
I
IH2
V
CC
= 5.5 V,
VIN = 4.5 V,
special progr am-
ming pin
All
---
100
Low-level inp ut current
I
IL1
V
CC
= 5.5 V,
VIN = 0.5 V
All
-1.0
-250
I
IL2
V
CC
= 5.5 V,
VIN = 0.5 V,
for CE3 and CE4
01,02
-1.0
-1000
Short circuit output
current
I
OS
V
CC
= 5.5 V,
VO = 0.0 V 4/
02,03,05
-10
-100
Supply current
I
CC
V
CC
= 5.5 V,
VIN = 0, out-
puts = open
01,02,03
---
185
04,05
---
155
Propagation delay time,
high-to-low level logic,
address to output
t
PHL1
V
CC
= 4.5 V and
5.5 V,
CL = 30 pF
(see figure 6)
01,02,03
---
90
04,05
---
80
Propagation delay time,
low-to-high level logic,
address to output
t
PLH1
01,02,03
---
90
04,05
---
80
Propagation delay time,
high-to-low level logic,
enable to output
t
PHL2
V
CC
= 4.5 V and
5.5 V,
CL = 30 pF
(see figure 6)
01,02,03
---
50
04,05
---
40
Propagation delay time,
low-to-high level logic,
enable to output
t
PLH2
01,02,03
---
50
04,05
40
1/ Complete term inal conditi ons shall be as sp ecified on table III.
2/ For device type 03, the fusing pins FE1 and FE2 may be grounded or floating during operation.
3/ IOL = 16 mA for circuit F devices.
4/ Not more than one output shall be grounded at one tim e. Output shall be at high logic l ev el pr ior
to test.
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MIL-M-38510/208F
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FIGURE 1. Case outline X.
Dimension
Symbol
Inches
Millimeters
Notes
Min
Max
Min
Max
A
.045
.090
1.14
2.29
b
.015
.019
.38
.48
5
c
.003
.006
.08
.15
5
D
----
.400
----
10.16
3
E
.340
.385
8.64
9.78
E1
----
.400
----
10.16
3
E2
.125
----
3.18
----
E3
.030
----
.76
----
14
e
.050 BSC
1.27 BSC
4, 6
k
.008
.015
.20
.38
10
L
.250
.370
6.35
9.40
Q
.010
.040
.25
1.02
2
S1
.005
----
.13
----
7, 8
S2
.005
---
.13
----
11
α
30°
90°
30°
90°
12, 13
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MIL-M-38510/208F
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NOTES:
1. Index area; a notch or a pin o ne identification mark shall be located adjac ent to pin one a nd s hall be within
the shaded area shown. The manufacturer’s identificat i on shall not be us ed as a pin one identi fication mark.
Alternately, a tab (dimension k) may be used to identify p in one.
2. Dimensio n Q shall be measured at the point of exit of the le ad from the body.
3. This dimens ion allows for off-center lid, meniscus and glass overrun.
4. The basic pin spacing is .050 (1.25 mm) between centerlines. Each pin centerline shall be located withi n
±.005 (0.13 mm) of its exact long i tudinal position relative to pins relative to pins 1 and 24.
5. All leads increase maximum li m i t by .003 (0.08mm) measured at t he c enter of the flat, when lead fi nish A
is applied.
6. Twenty-two spaces.
7. Applies to all four corners (leads number 3, 10, 15, and 22).
8. Dimensio n S1 may be .000 (0.00 mm) if leads number 3, 10, 15, and 22 bend toward the cavit y of the
package withi n one lead width from the point of entry of the lead, into the body or if the leads are br az ed to
the metallized ceramic bod y (see MIL-STD-1835) .
9. Optional configuration: if this configuration is us ed, no organic or polymeric materials shall be molded t o the
bottom of the package to cover the leads.
10. Optional, see note 1. If a pin one identification mark is used in addition to this tab, t he minimum limit of
dimension k does not apply.
11. Applies to leads number 2, 11, 14, and 23.
12. Lead configuration is opt ional within dimension E except dimensions b and c apply (see MIL-STD-1835).
13. Applies to lead numbers 1, 2, 11, 12, 13, 14, 23, and 24.
14. Applies to all edges.
FIGURE 1. Case outline XContinued.
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MIL-M-38510/208F
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FIGURE 2. Case outline Y.
Dimension
Symbol
Inches
Millimeters
Notes
Min
Max
Min
Max
A
----
.175
----
4.44
b
.016
.020
.41
.51
11, 8
b1
.040
.060
1.02
1.52
8, 2
C
.008
.012
.20
.30
11, 8
D
.970
1.010
24.64
25.65
4
E
.280
.300
7.11
7.62
4
E1
.290
.320
7.37
8.13
7
e
.090
.110
2.29
2.79
5, 9
L
.125
.180
3.18
4.58
L1
.150
----
3.81
----
Q
.020
.060
.51
1.52
3
S
----
.098
----
2.49
6
S1
.005
----
.13
----
6
S2
.005
----
.13
----
8
α
0°
15°
0°
15°
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NOTES:
1. Index area; a notch or a pin one ide ntification mar k shall be located adjacent to pin one and shall be
located within the shaded area shown. The manufact urer’s identification s hall not be used as a pi n one
identificat ion mark.
2. The minimum limit for dimens ion b1 may be .020 (. 51 m m) for leads num ber 1, 10, 11, and 20 only.
3. Dimensio n Q shall be measured from the seating plane to the base plane.
4. This dimens ion allows for off-center lid, meniscus and glass overrun.
5. The basic pin spacing is .100 (2.54 mm) between centerlines. Each pin centerline shall be located
within ±.010 (. 25 mm) of its exact longitudina l position relat i ve to pins 1 and 20.
6. Applies to all four corners (leads number 1, 10, 11, and 20) (see MIL-STD-1835).
7. Lead center when α is 0°. E1 shall be measured at the centerline of leads (see MIL-STD-1835).
8. All leads Inc rease maximum limit by .003 (.08 mm) measured at the center of the flat, when lead finish
A is applied.
9. Eighteen spaces.
10. No organic or polymeric materials sh al l be molded to the bottom of the pack age.
11. Applies to all leads.
FIGURE 2. Case outline YContinued.
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9
Device type
01 and 02
03
04 and 05
Case outline
J, K, X, and Z
J, K, and X
Y
Terminal number
Terminal symbol
1
A7
A3
A0
2
A6
A4
A1
3
A5
A5
A2
4
A4
A6
A3
5
A3
A7
A4
6
A2
A8
O1
7
A1
O1
O2
8
A0
O2
O3
9
O1
O3
O4
10
O2
O4
GND
11
O3
FE2
O5
12
GND
GND
O6
13
O4
FE1
O7
14
O5
O5
O8
15
O6
O6
CE
1
16
O7
O7
A5
17
O8
O8
A6
18
CE4
STROBE
A7
19
CE3
CE2
A8
20
CE
2
CE
1
V
CC
21
CE
1
A0
----
22
NC
A1
----
23
A8
A2
----
24
VCC
VCC
----
NOTE: Case Z: option A with active terminals on plane 1.
FIGURE 3. Terminal connections.
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Device types 01 and 02
Device type 03
Device types 04 and 05
WORD
NO.
ENABLE
ADDRESS
DATA
CE
1
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
O
8
NA
H
X
X
X
X
X
X
X
X
X
OC
OC
OC
OC
OC
OC
OC
OC
NA
L
X
X
X
X
X
X
X
X
X
4/
4/
4/
4/
4/
4/
4/
4/
NOTES:
1. NA = Not applicable.
2. X = Input may be high level, low level, or open ci r cuit.
3. OC = Open cir cuit (high resistance output).
4. The outputs for an unprogrammed device shall be high for circuits A, B, D, and F, and low for c i r cuit C, G and H.
FIGURE 4. Truth table (unprogram med).
WORD
NO.
ENABLE
ADDRESS
DATA
CE
1
CE
2
CE
3
CE
4
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
O
8
NA
L
L
L
L
X
X
X
X
X
X
X
X
X
OC
OC
OC
OC
OC
OC
OC
OC
NA
H
L
L
L
X
X
X
X
X
X
X
X
X
OC
OC
OC
OC
OC
OC
OC
OC
NA
L
H
L
L
X
X
X
X
X
X
X
X
X
OC
OC
OC
OC
OC
OC
OC
OC
NA
H
H
L
L
X
X
X
X
X
X
X
X
X
OC
OC
OC
OC
OC
OC
OC
OC
NA
L
L
H
L
X
X
X
X
X
X
X
X
X
OC
OC
OC
OC
OC
OC
OC
OC
NA
H
L
H
L
X
X
X
X
X
X
X
X
X
OC
OC
OC
OC
OC
OC
OC
OC
NA
L
H
H
L
X
X
X
X
X
X
X
X
X
OC
OC
OC
OC
OC
OC
OC
OC
NA
H
H
H
L
X
X
X
X
X
X
X
X
X
OC
OC
OC
OC
OC
OC
OC
OC
NA
L
L
L
H
X
X
X
X
X
X
X
X
X
OC
OC
OC
OC
OC
OC
OC
OC
NA
H
L
L
H
X
X
X
X
X
X
X
X
X
OC
OC
OC
OC
OC
OC
OC
OC
NA
L
H
L
H
X
X
X
X
X
X
X
X
X
OC
OC
OC
OC
OC
OC
OC
OC
NA
H
H
L
H
X
X
X
X
X
X
X
X
X
OC
OC
OC
OC
OC
OC
OC
OC
NA
L
L
H
H
X
X
X
X
X
X
X
X
X
4/
4/
4/
4/
4/
4/
4/
4/
NA
H
L
H
H
X
X
X
X
X
X
X
X
X
OC
OC
OC
OC
OC
OC
OC
OC
NA
L
H
H
H
X
X
X
X
X
X
X
X
X
OC
OC
OC
OC
OC
OC
OC
OC
NA
H
H
H
H
X
X
X
X
X
X
X
X
X
OC
OC
OC
OC
OC
OC
OC
OC
WORD
NO.
ADDRESS
DATA
CE
1
CE
2
STROBE
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
O
8
NA
L
L
H
X
X
X
X
X
X
X
X
X
OC
OC
OC
OC
OC
OC
OC
OC
NA
H
L
H
X
X
X
X
X
X
X
X
X
OC
OC
OC
OC
OC
OC
OC
OC
NA
L
H
H
X
X
X
X
X
X
X
X
X
4/
4/
4/
4/
4/
4/
4/
4/
NA
H
H
H
X
X
X
X
X
X
X
X
X
OC
OC
OC
OC
OC
OC
OC
OC
NA
L
H
L
X
X
X
X
X
X
X
X
X
Last data is latched
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MIL-M-38510/208F
11
LOGIC CIRCUIT A
(Device types 01 and 02)
FIGURE 5. Logic diagr am s.
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MIL-M-38510/208F
12
LOGIC CIRCUIT B
(Device types 01, 02, 04, & 05) and
LOGIC CIRCUIT F
(Device type 05)
FIGURE 5. Logic diagr am sContinued.
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MIL-M-38510/208F
13
LOGIC CIRCUIT C
(Device types 01 and 02) and
LOGIC CIRCUIT H
(Device type 02)
FIGURE 5. Logic diagramsContinued.
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MIL-M-38510/208F
14
LOGIC CIRCUIT C
(Device type 03)
FIGURE 5. Logic diagr am sContinued.
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MIL-M-38510/208F
15
LOGIC CIRCUIT D
(Device types 01 and 02)
FIGURE 5. Logic diagr am s - Continued
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MIL-M-38510/208F
16
LOGIC CIRCUIT G
(Device type 01)
FIGURE 5. Logic diagr am sContinued.
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MIL-M-38510/208F
17
LOGIC CIRCUIT G
(Device type 02)
FIGURE 5. Logic diagramsContinued.
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MIL-M-38510/208F
18
LOGIC CIRCUIT G
(Device types 04 and 05)
FIGURE 5. Logic diagramsContinued.
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MIL-M-38510/208F
19
Device types 01 and 02
NOTES:
1. Test table f or devices progra mmed in accordance with an alter ed item drawing may be replac ed by the equival ent
tests which apply to the specific program configuration for the result ing read-onl y memory
2. CL = 30 pF minimum, inc l uding jig and probe capacitance, R1 =330 ±25%, and R2 = 680 ±20%.
3. Outputs may be under load si m ul taneously.
FIGURE 6. Switching time test circuit.
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MIL-M-38510/208F
20
Device type 03
NOTES:
1. Test table f or devices progra mmed in accordance with an alter ed item drawing may be replac ed by the equival ent
tests which apply to t he specific pro gram configur ation for the resulting read-only memor y
2. CL = 30 pF minimum, inc l uding jig and probe capacitance, R1 =330 ±25%, and R2 = 680 ±20%.
3. Outputs may be under load si m ul taneously.
FIGURE 6. Switching time test circ uitContinued.
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MIL-M-38510/208F
21
Device types 04 and 05
NOTES:
1. Test table f or devices progra mmed in accordance with an alter ed item drawing may be replac ed by the equival ent
tests which apply to t he specific pro gram configur ation for the resul ting read-only memory
2. CL = 30 pF minimum, inc l uding jig and probe capacitance, R1 =330 ±25%, and R2 = 680 ±20%.
3. Outputs may be under load si m ul taneously.
FIGURE 6. Switching time test circ uitContinued.
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MIL-M-38510/208F
22
NOTES:
1. Disregar d for devices with no chip enable inputs.
2. All other waveforms characteristics shall be as specified in table IVA.
FIGURE 7a. Programming v oltage wavefor ms during programming for circuit A.
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MIL-M-38510/208F
23
NOTES:
1. Output loa d is 0.2 mA and 12 mA during 7.0 V and 4.0 V ch eck, respectively.
2. All other waveform characteristic s shall be as speci fied in table IVB.
3.
1
CE
is the programming pin for de v i c e types 04 and 05.
FIGURE 7b. Programming vo ltage wavefor ms during pro gramming for cir cuit B.
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MIL-M-38510/208F
24
Device types 01 and 02
Device type 03
NOTE: All other wa v eform charact er i s tics shall be as specified in table IVC.
NOTE: All other waveform characterist ics shall be as specified in table IVC.
FIGURE 7c. Programmi ng voltage wavef or ms during programming for ci r cuits C and H.
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MIL-M-38510/208F
25
NOTE: All other waveform characteristics shall be as specified in table IVD.
FIGURE 7d Programming voltage waveforms dur i ng programm ing for circuit D .
NOTES:
1. Output loa d is 0.2 mA and 12 mA during 7.0 V and 4.0 V ch eck, respectively.
2. All other waveform characteristics s hal l be as specified in table IVF.
FIGURE 7f. Progr am ming voltage waveforms duri ng programm ing for circuit F.
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MIL-M-38510/208F
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FIGURE 7g. Programming voltage waveforms dur i ng programming for circuit G.
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MIL-M-38510/208F
27
4. VERIFICATION
4.1 Sampling and inspection. Sampling an d inspection procedures s hall be in accor dance with MIL-PRF-
38535 or as modif ied in the devi c e manufactur er's Quality Management (Q M) plan. The modification in the QM
plan shall not affect the f orm, fit, or function as described h erein.
4.2 Screening. Screening shall be in accordance with MIL-PRF-38535 and shall be conducted on all devices
prior to qualification and quality conformance inspection. The following additional criteria shall appl y:
a. The burn-in test duration, t est condition, and test temperature, or approved alternat ives shall be as
specified in the device manufacturer's QM plan in accorda nce with MIL-PRF-38535. The burn-in test
circuit shall be maintained under doc ument control by the device manufacturer's Technology Review
Board (TRB) in accordance with MIL-PRF-38535 a nd shall be made av ailable to the acquiring or
preparing act i v ity upon request. The test circuit shall specify the inputs, outputs, bias es , and power
dissipatio n, as applicable, in accordanc e with the intent s pecified in tes t method 1015 of M IL-STD-
883.
b. Interim and fi nal electrical test parameters shall be as specified i n table II, except i nterim electrical
parameters t est prior to burn-in is optional at the discretion of the manufactur er.
c. Additional s c reening for space level produc t shall be as specified in MIL-PRF-38535, appendix B.
d. Class B devices processe d to an altered item drawing may be programmed eit her before or after
burn-in at the m anufacturer’s discretion. The required electrical testing shall include, as a
minimum, the final electrical tests for pr ogrammed devices as specified in table II herein. Cl as s S
devices processed by the manuf ac turer to an altered item drawing shall b e programmed prior to burn-
in.
TABLE II. Elect r i c al test requirements.
Subgroups (s ee table III)
1/, 2/, 3/
MIL-PRF-38535
test requirements
Class S
devices
Class B
devices
Interim electr i cal parameters 1 1
Final electrical te s t parameters
for unprogrammed devices
1*, 2, 3, 7*,
8
1*, 2, 3,
7*, 8
Final electrical test parameters
for programmed devices
1*, 2, 3, 7*
8, 9, 10, 11
1*, 2, 3, 7*,
8, 9,
Group A test requi rements
1, 2, 3, 7, 8,
9, 10, 11
1, 2, 3, 7, 8
9, 10, 11
Group B end-point electrical parameters
when using the method 5005 QCI option
1, 2, 3, 7, 8,
9, 10, 11
N/A
Group C end-point electrical
parameters
1, 2, 3, 7, 8,
9, 10, 11
1, 2, 3, 7, 8
Group D test requirements
1, 2, 3, 7, 8 1, 2, 3, 7, 8
1/ * indicates PDA applies to subgr oups 1 and 7.
2/ Any or all subgroups may be combined when usin g high-speed testers.
3/ Subgroups 7 and 8 shall consist of verifying t he pattern specified.
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MIL-M-38510/208F
28
4.3 Qualification inspection. Qualification inspection shall be in accordance with MIL-PRF-38535.
4.4 Technology Conformance inspection (TCI). Technology conformance inspec tion shall be in accordanc e
with MIL-PRF-38535 and as specified h er ein for groups A, B, C, and D inspec tions (see 4.4.1 through 4.4.4).
4.4.1 Group A inspection. Group A i nspection shall be in accordance with table III of MIL-PRF-38535 and as
follows:
a. Electrical test requir em ents shall be as s pecified i n table II herein.
b. Subgroups 4, 5, and 6 shall be omi tted.
c. For unprogrammed devices, a sample shall be selected to sat isfy programmabi lity requirements prior
to performing subgroups 9, 10, and 11. T welve dev i ces shall be submitted to pr ogr amming (see
3.3.2.1). I f more than 2 devices fail to program, the lot shall be rejected. At the m anufacturer’s
option, the sample may be increased to 24 total devices with no m ore than 4 tot al device failures
allowed.
d. For unprogrammed devices, 10 devices f r om the programmability sample shall be submitted to the
requirement s of group A, subgr oups 9, 10, and 11. If more than two total devices fail in all three
subgroups, the lot shall be rejected. At the m anufacturer’s option, the sa m pl e m ay be increased to 20
total devices with no more that 4 total devic e failures allowed.
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TABLE III. Group A inspection for device t yp e 01.
Terminal conditions: Outputs not designated are open or r esistive cou pled to GND or v oltage; input not designated are high 2.0 V, low 0.8 V, or open.
Subgroup
Symbol
MIL-
STD-
883
method
Cases
J,K,
X,Z
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Measured
terminal
Test limits
Unit
Test
no.
A7
A6
A5
A4
A3
A2
A1
A0
O1
O2
O3
GND
O4
O5
O6
O7
O8
CE
4
CE
3
CE
2
CE
1
NC
A8
V
CC
Min
Max
1
TC=25°C
V
IC
1
2
3
4
5
6
7
8
9
10
11
12
13
-10mA
-10mA
-10mA
-10mA
-10mA
-10mA
-10mA
-10mA
GND
-10mA
-10mA
-10mA
-10mA
-10mA
4.5V
A7
A6
A5
A4
A3
A2
A1
A0
CE4
CE3
CE2
CE1
A8
-1.5
V
V
OL
3007
14
15
16
17
18
19
20
21
1/ 2/
13/ 14/
1/ 3/
13/ 14/
1/
13/ 14/
1/
13/ 14/
1/
13/ 14/
1/
13/ 14/
1/
13/ 14/
1/ 2/
13/ 14/
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
2.4V
2.4V
0.5V
0.5V
1/2/4/
13/14/
O1
O2
O3
O4
O5
O6
O7
O8
0.5
V
I
IL1
3009
22
23
24
25
26
27
28
29
30
31
32
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
5.5V
A7
A6
A5
A4
A3
A2
A1
A0
CE2
CE1
A8
-1.0
-250
µA
I
IL2
33
34
0.5V
0.5V
CE
4
CE3
-1000
-1000
µA
I
IH1
3010
35
36
37
38
39
40
41
42
43
44
45
46
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
A7
A6
A5
A4
A3
A2
A1
A0
CE4
CE3
CE1
A8
50
µA
I
IH2
47
4.5V
CE
2
100
See footnotes at end of table.
29
MIL-M-38510/208F
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TABLE III. Group A inspection for device t yp e 01 Continued.
Terminal conditions: Outputs not designated are open or r esistive cou pled to GND or v oltage; input not designated are high 2.0 V, low 0.8 V, or open.
Subgroup
Symbol
MIL-
STD-
883
method
Cases
J,K,
X,Z
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Measured
terminal
Test limits
Unit
Test
no.
A7
A6
A5
A4
A3
A2
A1
A0
O1
O2
O3
GND
O4
O5
O6
O7
O8
CE
4
CE
3
CE
2
CE
1
NC
A8
V
CC
Min
Max
1
TC=+25°C
I
CEX
48
49
50
51
52
53
54
55
15/
1/
15/
1/
15/
1/
15/
1/
15/
1/
15/
1/
15/
1/
15/
1/
5.2V
5.2V
5.2V
GND
5.2V
5.2V
5.2V
5.2V
5.2V
15/
1/
5.5V
O1
O2
O3
O4
O5
O6
O7
O8
100
µA
ICC
3005
56
GND
GND
GND
GND
GND
GND
GND
GND
5/
5/
GND
GND
GND
VCC
185
mA
2
Same tests, terminal conditions, and limits as for subgroup 1, except TC = 125°C and VIC tests are omitted.
3
Same tests, terminal conditions, and limits as for subgroup 1, except TC = -55°C and VIC tests are omitted.
7
TC=25°C
Func-
tional
test
3014
57
6/
6/
6/
6/
6/
6/
6/
6/
6/
6/
6/
GND
6/
6/
6/
6/
6/
6/
6/
6/
6/
6/
6/
Outputs
6/
8
Same tests, terminal conditions, and limits as for subgroup 7, except TC = 125°C.
9
TC=25°C
t
PLH1
tPHL1
tPLH2
tPHL2
GALPAT
Fig. 6
GALPAT
Fig. 6
Sequen-
tial
Fig. 6
Sequen-
tial
Fig. 6
58
59
60
61
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
9/
9/
9/
GND
9/
9/
9/
9/
9/
5.5V
5.5V
8/
8/
5.5V
5.5V
8/
8/
GND
GND
8/
8/
GND
GND
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
Outputs
90
90
50
50
ns
10
Same tests, terminal conditions, and limits as for subgroup 9, except TC = 125°C.
11
Same tests, terminal conditions, and limits as for subgroup 9, except TC = -55°C.
See footnotes at end of table.
MIL-M-38510/206D
30
MIL-M-38510/208F
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TABLE III. Group A inspection for device t yp e 02.
Terminal conditions: Outputs not designated are open or r esistive cou pled to GND or v oltage; input not designated are high 2.0 V, low 0.8 V, or open.
Subgroup
Symbol
MIL-
STD-
883
method
Cases
J,K,
X,Z
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Measured
terminal
Test limits
Unit
Test
no.
A7
A6
A5
A4
A3
A2
A1
A0
O1
O2
O3
GND
O4
O5
O6
O7
O8
CE
4
CE
3
CE
2
CE
1
NC
A8
V
CC
Min
Max
1
TC=25°C
V
IC
1
2
3
4
5
6
7
8
9
10
11
12
13
-10mA
-10mA
-10mA
-10mA
-10mA
-10mA
-10mA
-10mA
GND
-10mA
-10mA
-10mA
-10mA
-10mA
4.5V
A7
A6
A5
A4
A3
A2
A1
A0
CE4
CE3
CE2
CE1
A8
-1.5
V
V
OL
3007
14
15
16
17
18
19
20
21
1/ 2/
16/
13/
1/ 3/
16/
13/
1/
16/
13/
1/
16/
13/
1/
16/
13/
1/
16/
13/
1/
16/
13/
1/ 2/
16/
13/
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
2.4V
2.4V
0.5V
0.5V
1/ 4/
16/
13/
O1
O2
O3
O4
O5
O6
O7
O8
0.5
V
V
OH
3006
22
23
24
25
26
27
28
29
17/
1/ 10/
17/
1/
17/
1/ 25/
17/
1/
17/
1/
17/
1/
17/
1/
17/
-2mA
-2mA
-2mA
-2mA
-2mA
-2mA
-2mA
-2mA
1/ 10/
17/
O1
O2
O3
O4
O5
O6
O7
O8
2.4
V
I
IL1
3009
30
31
32
33
34
35
36
37
38
39
40
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
5.5V
A7
A6
A5
A4
A3
A2
A1
A0
CE2
CE1
A8
-1.0
-250
µA
I
IL2
24/
41
42
0.5V
0.5V
CE
4
CE3
-1000
-1000
µA
I
IH1
3010
43
44
45
46
47
48
49
50
51
52
53
54
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
A7
A6
A5
A4
A3
A2
A1
A0
CE4
CE3
CE1
A8
50
µA
I
IH2
23/
55
4.5V
CE 2
100
µA
See footnotes at end of table.
31
MIL-M-38510/208F
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TABLE III. Group A inspection for device t yp e 02 Continued.
Terminal conditions: Outputs not designated are open or r esistive cou pled to GND or v oltage; input not designated are high 2.0 V, low 0.8 V, or open.
Subgroup
Symbol
MIL-
STD-
883
method
Cases
J,K,
X,Z
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Measured
terminal
Test limits
Unit
Test
no.
A7
A6
A5
A4
A3
A2
A1
A0
O1
O2
O3
GND
O4
O5
O6
O7
O8
CE
4
CE
3
CE
2
CE
1
NC
A8
V
CC
Min
Max
1
TC=25°C
I
OHZ
56
57
58
59
60
61
62
63
5.2V
5.2V
5.2V
GND
5.2V
5.2V
5.2V
5.2V
5.2V
GND
GND
5.5V
5.5V
5.5V
O1
O2
O3
O4
O5
O6
O7
O8
100
µA
I
OLZ
64
65
66
67
68
69
70
71
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
O1
O2
O3
O4
O5
O6
O7
O8
-100
µA
ICC
3005
72
GND
GND
GND
GND
GND
GND
GND
GND
5/
5/
GND
GND
GND
VCC
185
mA
I
OS
3011
73
74
75
76
77
78
79
80
1/
18/
1/ 10/
18/
1/
18/
1/
18/
1/
18/
1/
18/
1/
18/
1/
18/
GND
GND
GND
GND
GND
GND
GND
GND
5.5V
5.5V
1/ 10/
18/
O1
O2
O3
O4
O5
O6
O7
O8
-10
-100
mA
2
Same tests, terminal conditions, and limits as for subgroup 1, except TC = 125°C and VIC tests are omitted.
3
Same tests, terminal conditions, and limits as for subgroup 1, except TC = -55°C and VIC tests are omitted.
7
TC=25°C
Func-
tional
test
3014
81
6/
6/
6/
6/
6/
6/
6/
6/
6/
6/
6/
GND
6/
6/
6/
6/
6/
6/
6/
6/
6/
6/
6/
Outputs
6/
ns
8
Same tests, terminal conditions, and limits as for subgroup 7, except TC = 125°C and TC = -55°C.
9
TC=25°C
tPLH1
tPHL1
tPLH2
tPHL2
GALPAT
Fig. 6
GALPAT
Fig. 6
Sequen-
tial
Fig. 6
Sequen-
tial
Fig. 6
82
83
84
85
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
9/
9/
9/
GND
9/
9/
9/
9/
9/
5.5V
5.5V
8/
8/
5.5V
5.5V
8/
8/
GND
GND
8/
8/
GND
GND
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
Outputs
90
90
50
50
ns
10
Same tests, terminal conditions, and limits as for subgroup 9, except TC = 125°C.
11
Same tests, terminal conditions, and limits as for subgroup 9, except TC = -55°C.
See footnotes at end of table.
33
MIL-M-38510/208E
32
MIL-M-38510/208F
Source: https://assist.dla.mil -- Downloaded: 2018-06-19T19:20Z
Check the source to verify that this is the current version before use.
TABLE III. Group A inspection for device t yp e 03.
Terminal conditions: Outputs not designated are open or r esistive cou pled to GND or v oltage; inputs not designated are high 2.0 V, low 0.8 V , or open.
Subgroup
Symbol
MIL-
STD-
883
method
Cases
J,K,X
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Measured
terminal
Test limits
Unit
Test
no.
A3
A4
A5
A6
A7
A8
O1
O2
O3
O4
FE2
GND
FE1
O5
O6
O7
O8
Strobe
CE
2
CE
1
A0
A1
A2
V
CC
Min
Max
1
TC=25°C
V
IC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
-10mA
-10mA
-10mA
-10mA
-10mA
-10mA
-10mA
GND
-10mA
-10mA
-10mA
-10mA
-10mA
-10mA
-10mA
4.5V
A3
A4
A5
A6
A7
A8
FE2
FE1
Strobe
CE2
CE1
A0
A1
A2
-1.5
V
V
OL
3007
15
16
17
18
19
20
21
22
1/
1/
1/
1/
1/
1/
8mA
8mA
8mA
8mA
GND
GND
‘’
8mA
8mA
8mA
8mA
2.4V
2.4V
0.5V
1/
1/
1/
O1
O2
O3
O4
O5
O6
O7
O8
0.5
V
V
OH
3006
23
24
25
26
27
28
29
30
1/ 10/
-2mA
-2mA
-2mA
-2mA
-2mA
-2mA
-2mA
-2mA
O1
O2
O3
O4
O5
O6
O7
O8
2.4
V
I
IL1
3009
31
32
33
34
35
36
37
38
39
40
41
42
43
44
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
5.5V
A3
A4
A5
A6
A7
A8
FE2
FE1
Strobe
CE2
CE1
A0
A1
A2
-1.0
-1.0
-100
1.0
1.0
-100
µA
mA
mA
µA
I
IH1
3010
45
46
47
48
49
50
51
52
53
54
55
56
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
A3
A4
A5
A6
A7
A8
Strobe
CE2
CE1
A0
A1
A2
50
µA
See footnotes at end of table.
33
MIL-M-38510/208F
Source: https://assist.dla.mil -- Downloaded: 2018-06-19T19:20Z
Check the source to verify that this is the current version before use.
TABLE III. Group A inspection for device t yp e 03 Continued.
Terminal conditions: Outputs not designated are open or resistiv e c oupled to G ND or voltage; input not designated ar e high 2.0 V, low 0.8 V, or open.
Subgroup
Symbol
MIL-
STD-
883
method
Cases
J,K,X
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Measured
terminal
Test limits
Unit
Test
no.
A3
A4
A5
A6
A7
A8
O1
O2
O3
O4
FE
2
GND
FE
1
O5
O6
O7
O8
Strobe
CE
2
CE
1
A0
A1
A2
V
CC
Min
Max
1
TC=25°C
I
OHZ
57
58
59
60
61
62
63
64
5.2V
5.2V
5.2V
5.2V
GND
5.2V
5.2V
5.2V
5.2V
0.5V
2.4V
0.5V
5.5V
O1
O2
O3
O4
O5
O6
O7
O8
100
µA
I
OLZ
65
66
67
68
69
70
71
72
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
O1
O2
O3
O4
O5
O6
O7
O8
-100
µA
ICC
3005
73
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
185
mA
I
OS
3011
74
75
76
77
78
79
80
81
1/
1/
1/
1/ 25/
1/
1/ 10/
GND
GND
GND
GND
GND
GND
GND
GND
5.5V
1/
1/ 10/
1/
O1
O2
O3
O4
O5
O6
O7
O8
-10
-100
mA
2
Same tests, terminal conditions, and limits as for subgroup 1, except TC = 125°C and VIC tests are omitted.
3
Same tests, terminal conditions, and limits as for subgroup 1, except TC = -55°C and VIC tests are omitted.
7
TC=25°C
Func-
tional
test
3014
82
6/
6/
6/
6/
6/
6/
6/
6/
6/
6/
6/
GND
6/
6/
6/
6/
6/
6/
6/
6/
6/
6/
6/
Outputs
6/
8
Same tests, terminal conditions, and limits as for subgroup 7, except TC = 125°C and TC = -55°C.
9
TC=25°C
tPLH1
tPHL1
tPLH2
tPHL2
GALPAT
Fig. 6
GALPAT
Fig. 6
Sequen-
tial
Fig. 6
Sequen-
tial
Fig. 6
83
84
85
86
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
9/
9/
9/
9/
GND
GND
GND
9/
9/
9/
9/
GND
5.5V
GND
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
Outputs
90
90
50
50
ns
10
Same tests, terminal conditions, and limits as for subgroup 9, except TC = 125°C.
11
Same tests, terminal conditions, and limits as for subgroup 9, except TC = -55°C.
See footnotes at end of table.
34
MIL-M-38510/208F
Source: https://assist.dla.mil -- Downloaded: 2018-06-19T19:20Z
Check the source to verify that this is the current version before use.
TABLE III. Group A inspection for device t yp e 04.
Terminal conditions: Outputs not designated are open or r esistive cou pled to GND or v oltage; input not designated are high 2.0 V, low 0.8 V, or ope n.
Subgroup
Symbol
MIL-
STD-
883
method
Case Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Measured
terminal
Test limits
Unit
Test
no.
A0
A1
A2
A3
A4
O1
O2
O3
O4
GND
O5
O6
O7
O8
CE
1
A5
A6
A7
A8
V
CC
Min
Max
1
TC=25°C
V
IC
1
2
3
4
5
6
7
8
9
10
-10mA
-10mA
-10mA
-10mA
-10mA
GND
-10mA
-10mA
-10mA
-10mA
-10mA
4.5V
A0
A1
A2
A3
A4
CE1
A5
A6
A7
A8
-1.5
V
V
OL
3007
11
12
13
14
15
16
17
18
2.4V
19/
1/ 3/
19/
1/
19/
1/
19/
1/
19/
8mA
8mA
8mA
8mA
8mA
8mA
8mA
8mA
0.5V
19/
1/
19/
1/
19/
1/
19/
1/
19/
19/
O1
O2
O3
O4
O5
O6
O7
O8
0.5
V
I
IL
3009
19
20
21
22
23
24
25
26
27
28
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
5.5V
A0
A1
A2
A3
A4
CE1
A5
A6
A7
A8
-1.0
-250
µA
I
IH1
3010
29
30
31
32
33
34
35
36
37
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
A0
A1
A2
A3
A4
A5
A6
A7
A8
50
µA
I
IH2
38
4.5V
CE
1
100
µA
I
CEX
39
40
41
42
43
44
45
46
5.2V
5.2V
5.2V
5.2V
5.2V
5.2V
5.2V
5.2V
5.5V
O1
O2
O3
O4
O5
O6
O7
O8
µA
ICC
3005
47
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
155
mA
See footnotes at end of table.
35
MIL-M-38510/208F
Source: https://assist.dla.mil -- Downloaded: 2018-06-19T19:20Z
Check the source to verify that this is the current version before use.
TABLE III. Group A inspection for device t yp e 04 Continued.
Terminal conditions: Outputs not designated are open or r esistive cou pled to GND or voltage; input not designated are high 2.0 V, low 0.8 V, or open.
Subgroup
Symbol
MIL-STD-
883
method
Case Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Measured
terminal
Test limits
Unit
Test
no.
A0
A1
A2
A3
A4
O1
O2
O3
O4
GND
O5
O6
O7
O8
CE
1
A5
A6
A7
A8
V
CC
Min
Max
2
Same tests, terminal conditions, and limits as for subgroup 1, except TC = 125°C and VIC t e st s are omitted.
3
Same tests, terminal conditions, and limits as for subgroup 1, except TC = -55°C and VIC tests are omitted.
7
TC=25°C
Func-
tional
test
3014
48
6/
6/
6/
6/
6/
6/
6/
6/
6/
GND
6/
6/
6/
6/
6/
6/
6/
6/
6/
6/
Outputs
6/
8
Same tests, terminal conditions, and limits as for subgroup 7, except TC = 125°C and TC = -55°C.
9
TC=25°C
tPLH1
tPHL1
tPLH2
tPHL2
GALPAT
Fig. 6
GALPAT
Fig. 6
Sequential
Fig. 6
Sequential
Fig. 6
49
50
51
52
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
9/
9/
9/
9/
GND
9/
9/
9/
9/
GND
GND
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
Outputs
80
80
50
50
ns
10
Same tests, terminal conditions, and limits as for subgroup 9, except TC = 125°C.
11
Same tests, terminal conditions, and limits as for subgroup 9, except TC = -55°C.
See footnotes at end of table.
36
MIL-M-38510/208F
Source: https://assist.dla.mil -- Downloaded: 2018-06-19T19:20Z
Check the source to verify that this is the current version before use.
TABLE III. Group A inspection for device t yp e 05.
Terminal conditions: O utputs not designated are open or r esistive cou pl ed to GND or vol tage; input not designated are high 2.0 V, low 0.8 V, or open.
Subgroup
Symbol
MIL-
STD-
883
method
Case Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Measured
terminal
Test limits
Unit
Test
no.
A0
A1
A2
A3
A4
O1
O2
O3
O4
GND
O5
O6
O7
O8
CE
1
A5
A6
A7
A8
V
CC
Min
Max
1
TC=25°C
V
IC
1
2
3
4
5
6
7
8
9
10
-10mA
-10mA
-10mA
-10mA
-10mA
GND
-10mA
-10mA
-10mA
-10mA
-10mA
4.5V
A0
A1
A2
A3
A4
CE1
A5
A6
A7
A8
-1.5
V
V
OL
3007
11
12
13
14
15
16
17
18
2.4V
20/
1/ 3/
20/
1/ 11/
20/
1/ 11/
20/
1/ 11/
20/
12/
12/
12/
12/
12/
12/
12/
12/
0.5V
1/
20/
1/
20/
1/
20/
1/
20/
O1
O2
O3
O4
O5
O6
O7
O8
0.5
V
V
OH
3006
19
20
21
22
23
24
25
26
1/
21/
1/
21/
1/
21/
1/
21/
1/
21/
-2mA
-2mA
-2mA
-2mA
-2mA
-2mA
-2mA
-2mA
1/
21/
1/
21/
1/
21/
1/
21/
O1
O2
O3
O4
O5
O6
O7
O8
2.4
V
I
IL
3009
27
28
29
30
31
32
33
34
35
36
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
5.5V
A0
A1
A2
A3
A4
CE1
A5
A6
A7
A8
-1.0
-250
µA
I
IH1
3010
37
38
39
40
41
42
43
44
45
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
A0
A1
A2
A3
A4
A5
A6
A7
A8
50
µA
I
IH2
46
4.5V
CE
1
100
See footnotes at end of table.
37
MIL-M-38510/208F
Source: https://assist.dla.mil -- Downloaded: 2018-06-19T19:20Z
Check the source to verify that this is the current version before use.
TABLE III. Group A inspection for device t yp e 05 Continued.
Terminal conditions: Outputs not designated are open or r esistive cou pled to GND or v oltage; input not designated are high 2.0 V, low 0.8 V, or ope n.
Subgroup
Symbol
MIL-STD-
883
method
Case Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Measured
terminal
Test limits
Unit
Test
no.
A0
A1
A2
A3
A4
O1
O2
O3
O4
GND
O5
O6
O7
O8
CE
1
A5
A6
A7
A8
V
CC
Min
Max
1
TC=25°C
I
OHZ
47
48
49
50
51
52
53
54
5.2V
5.2V
5.2V
5.2V
GND
5.2V
5.2V
5.2V
5.2V
5.5V
5.5V
O1
O2
O3
O4
O5
O6
O7
O8
100
µA
I
OLZ
55
56
57
58
59
60
61
62
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
0.5V
O1
O2
O3
O4
O5
O6
O7
O8
-100
µA
ICC
3005
63
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
-10
-100
mA
I
OS
3011
64
65
66
67
68
69
70
71
1/
22/
1/
22/
1/
22/
1/
22/
1/
22/
GND
GND
GND
GND
GND
GND
GND
GND
0.5V
1/
22/
1/
22/
1/
22/
1/
22/
O1
O2
O3
O4
O5
O6
O7
O8
mA
2
Same tests, terminal conditions, and limits as for subgroup 1, except TC = 125°C and VIC t e st s are omitted.
3
Same tests, terminal conditions, and limits as for subgroup 1, except TC = -55°C and VIC test s are omitted.
7
TC=25°C
Func-
tional
test
3014
72
6/
6/
6/
6/
6/
6/
6/
6/
6/
GND
6/
6/
6/
6/
GND
6/
6/
6/
6/
6/
Outputs
6/
8
Same tests, terminal conditions, and limits as for subgroup 7, except TC = 125°C and TC = -55°C.
9
TC=25°C
t
PLH1
tPHL1
tPLH2
tPHL2
GALPAT
Fig. 6
GALPAT
Fig. 6
Sequential
Fig. 6
Sequential
Fig. 6
73
74
75
76
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
9/
9/
9/
9/
GND
9/
9/
9/
9/
GND
GND
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
7/
7/
8/
8/
Outputs
80
80
40
40
ns
10
Same tests, terminal conditions, and limits as for subgroup 9, except TC = 125°C.
11
Same tests, terminal conditions, and limits as for subgroup 9, except TC = -55°C.
See footnotes at end of table.
38
MIL-M-38510/208F
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1/ For unprogrammed devices, s elect an appro pr i ate address t o ac qui re the desired output state.
2/ For unprogrammed devices (circuit D), apply 12.0 V on pin 8 ( A0) and pin 1 (A 7).
3/ For unprogrammed device t ypes 01 and 02 (circ ui t B), apply 12.0 V on pin 2 (A6); for unprogrammed device types
04 and 05 (circui t B), apply 12 .0 V on pin 2 (A1).
4/ For unprogrammed devices (circuit A), apply 11.0 V on pin 2 3 (A8).
5/ CE4 and CE3 may be “GND” or “2.4 V”.
6/ The functional test shall veri fy that no fus es are blown for unprogrammed devices or that the alt ered item drawing
pattern exists for programme d devices (see table II and 3.3. 2.2). All bits shall be tested. The functional t ests shall
be performed with VCC = 4.5 V and VCC = 5.5 V. Terminal c onditions shall be as follows:
a. Inputs: H = 3.0 V, L = 0.0 V.
b. Outputs: Output voltage shall be either:
(1) H = 2.4 V minimum and L = 0.5 V maximum when using a high-speed checker double
comparator, or
(2) H 1.0 V and L < 1.0 V when using a high-speed checker single comparator.
7/ GALPAT (PROGRAMMED PROM). This program will t est all bits in t he array, the addressing and interaction
between bits for ac performan c e, tPLH1 and tPHL1. Each bit in the pattern is fixed by being programmed with an “H”
or “L”. The GALPAT tests shall be p er formed with VCC = 4. 5 V and 5.5 V.
Description:
Step 1. Word 0 is read.
Step 2. Word 1 is read.
Step 3. Word 0 is read.
Step 4. Word 2 is read.
Step 5. Word 0 is read.
Step 6. The reading procedure con tinues back and forth between word 0 and the next higher numbered
word until word 511 is reached, t hen i ncrements to t he next word and reads back and fort h as i n
step 1 through step 6 and shall include all words.
Step 7. Pass execution time = (n2 + n) x cycle time. n = 512.
8/ SEQUENTIAL (PROGRAMMED PROM). This program will test all bits in the array for tPLH2 and tPHL2. The
SEQUENT IAL tests shall be performed wit h VCC = 4.5 V and 5.5 V.
Description:
Step 1. Each word in the pattern is t es ted from the enable lines to the output lines for recovery.
Step 2. Word 0 is addressed. Enable li ne i s pulled high to low and low to high. tPHL2 and tPLH2 are
Step 3. Word 1 is addressed. Same ena bl e sequence as above.
Step 4. The r eading procedure c ontinues until word 511 is reached.
Step 5. Pass execution time = 512 x cycle t i me.
9/ The outputs ar e loaded per figure 6.
10/ For uprogrammed dev ice types 01 and 02 (circuit C), apply 10.0 V on pi n 23 (A8); 0. 5 V on pin 2 (A6); and 5.0 V
on all other address pins. For unprogram m ed device t ype 03 (circuit C), apply 10.0 V on pin 6 (A8); 0.5 V on pin
22 (A1); and 5.0 V on all ot her address pins.
11/ For unprogrammed dev ices (circuit F), apply 12.0 V on pin 3 (A2) and 0.0 V on pin 4 (A3).
12/ IOL = 8 mA for circuit B devices; IOL = 16 mA for circuit F devices.
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13/ For unprogrammed dev ice types 01, 02, 04, and 05 (circ uit G) select an appropriate a ddr ess to obtain the
desired output state.
14/ For programmed device type 02 (c ircuit G) apply 4.5 V to pin 24; 10.5 V to pin 1; 3.0 V to pins 23, 19, 18, 8, 7, 6,
4, 3, and 2; and 0.0 V to pins 21, 20, 12, and 5.
15/ For unprogrammed dev ice type 01 (circuit G) apply 1 0.5 V to pins 6 and 1; 5.5 V to pin 24; 3.0 V to pins 23, 19,
18, 8, 7, 6, 4, 3, and 2; 0.0 V to pins 21, 20, 12, and 5.
16/ For progr ammed device type 02 (circuit G) apply 10.5 V to pin 1; 4.5 V to pin 2 4; 3.0 V to pins 23, 1 9, 18, 8, 7, 6,
4, 3, and 2; and 0.0 V to pins 21, 20, 5, and 12.
17/ For unprogrammed dev ice type 02 (circuit G) apply 1 0.5 V to pins 6 and 1; 4.5 V to pin 24; 3.0 V to pins 23, 19,
18, 8, 7, 4, and 2; 2.0 V to pin 3; 0.0 V to pins 21, 20, 12, and 5.
18/ For unpr ogrammed dev i c e type 02 (circuit G) apply 10.5 V to pins 1 and 6; 5.5 V to pin 24; 3.0 V to pins 23, 19,
18, 8, 7, 4, 3 and 2; 0.0 V to pins 5, 12, 20, and 21.
19/ For progr ammed device type 04 (circuit G) apply 10.5 V to pin 16; 4.5 V to pin 20; 3.0 V to pins 1, 2, 3, 4, 5, 18,
and 19; 0.0 V to pins 10 and 1 5.
20/ For progr ammed device type 05 (circuit G) apply 10.5 V to pin 16; 4.5 V to pi n 20; 3.0 V to pins 1, 2, 3, 4, 5, 18,
and 19; 0.0 V to pins 10 and 1 5.
21/ For unprogrammed dev ice type 05 (circuit G) apply 1 0.5 V to pins 17 and 3; 4.5 V to pin 20; 3.0 V to pins 2, 4, 5,
16, 18, and 19; 0.0 V to pins 1, 10, and 15.
22/ For unprogrammed dev ice type 05 (circuit G) apply 1 0.5 V to pins 3 and 17; 5.5 V to pin 20; 3.0 V to pins 2, 4, 5,
16, 18, and 19; 0.0 V to pins 1, 10, and 15.
23/ At the manufac turer’s option, this may be pr epared with VIH = 5.5 and test limits of 50 µA maximum.
24/ At the manufac turer’s option, this may be per formed with VIO = 0.5 V and test limit s of -1 µA minimum to -250 µA
maximum.
25/ For unprogrammed device type 02 (circuit H) apply 5.0V to pi n 24; 0.0V to pins 3, 5, 6, 7, 8, 20, and 21; 3.0V to
pins 1, 2, 18, 19, and 23; 9.0V to pin 4.
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4.4.2 Group B inspection. Group B i nspection shall be in accordance with table II MIL-PRF-38535.
4.4.3 Group C inspect ion. Group C i ns pection shall be in accordance with table IV of MIL-PRF-38535 and as
follows:
a. End-point e lectrical par ameters shall b e as specified in table II herein.
b. The steady-state life test duration, test condition, and test temperature, or appr ov ed alternativ es shall be
as specified in the device man ufacturer's Q M pl an in accordanc e with MIL-PRF-38535. The burn-in test
circuit shall be maintained under document control by the dev i ce manufacturer's Technology Review
Board (TRB) in accordance with M IL-PRF-38535 and shall be made available to the acquiring or
preparing act i v ity upon request. The test circuit shall specify the inputs, outputs, bias es , and power
dissipatio n, as applicable, in accordanc e with the intent s pecified in tes t method 1005 of MIL-STD-883.
c. For qualification, at least 25 percent of the sample selected for life testing shall be programmed (see
3.3.2). For quali ty conformance inspection, the programm ability sampl e ( see 4.4.1c) shall be includ ed i n
the life test.
4.4.4 Group D inspection. G r oup D inspection shall be in accordance with table V of MIL-PRF-38535 and as
follows:
a. End-point el ectrical tests s hal l be as specified in table I I herein.
b. Subgroup 2 s hall be omitted f or devices in package Z.
c. For moist ure res i s tance and salt atmosphere of subgroups 3 and 5, om i t initial conditioning for
devices in package Z .
4.5 Methods of inspection. Methods of inspection shall be as specified and as follows:
4.5.1 Voltage and c urrent. All v oltages given are r eferenced to the microcircuit ground term i nal. Currents given
are conventi onal and positi v e when flowing into the referenced terminal.
4.6 Programming procedure identif i c ation. The programming procedure to be utiliz ed shall be ide ntified by the
manufacturer s circuit designator.
4.7 Programming procedure for circuit A. The waveforms on figure 7a, t he programming characteristic s in table
IVA and the following proced ures shall app ly:
a. Connect the device in t he electrical configurati on for programm i ng.
b. Addres s the PROM with the binary addr ess of the selected word to be programmed. Address inputs are
TTL compatible.
c. Disable the ch ip by applying VIH to the
CE
1 and
CE
2 inputs and VIL to the CE3 and CE4 i nputs. The CE
inputs are TTL compatible.
d. Disable the program ming circuitry by applyin g a v ol tage of VOPD to t he outputs of the PRO M .
e. Raise VCC to V PH as s pec i fied on the wavef orms on figure 7a.
f. After a delay of tD, apply only one VOPE pulse with dur ation of tp t o the output select ed for programming.
Note that the PROM is supplied with fuses generating a high-level log ic output. Programming a fuse will
cause the output to go to a low-level logic in the verify mode.
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g. Other bits in the same word may be programmed s equentially while the VCC input is at the VPH level by
applying VOPE pulses to each output t o be programmed allowing a delay of tD between pulses as shown on
figure 7a.
h. Repeat steps 4.7b t hrough 4.7g for all other bits to be programmed.
i. Lower VCC to 4.5 vol ts following a delay of tD from the l as t programmi ng pulse applie d to an output.
j. Enable the chip by applying VIL to the
CE
1 and
CE
2 inputs and VIH to the CE3 and CE4 input s and verify the
program.
k. For class S an d B devices, if any bit does not verify as programmed, i t shall be considered a program m ing
reject.
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TABLE IVA. Programming characteristics for circuit A.
Parameter Symbol Limits 1/ Unit
Min Recommended Max
Address input voltage 2/
V
IH
VIL
2.4
0.0
5.0
0.4
5.0
0.8
V
V
V
CC
required durin g
programming
V
PH
VPL
12.0
4.5
12.0
4.5
12.5
5.5
V
V
Programming input low
current
I
ILP
----
-300
-600
µA
Programming voltage
transition time
t
TLH
tTHL
1
1
1
1
10
10
µs
µs
Programming del a y
t
D
10
10
100
µs
Programming puls e width
tP
90
100
110
µs
Programming duty cycle
D.C.
----
50
90
%
Output voltage
Enable 3/
Disable 4/
VOPE
VOPD
10.5
4.5
10.5
5.0
11.0
5.5
V
V
Output voltage enable
current
I
OPE
----
----
10
mA
1/ TA = +25°C.
2/ Address and c hi p enable shal l not be left open for VIH.
3/ VOPE supply shall be c apable of sourcing 10 mA.
4/ Disable condit ion can be met wit h output open circuit.
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4.8 Programm i ng procedure for circuit B. The waveforms o n figure 7b, the pr ogramming charac teristics of table
IVB, and the foll owing procedures shall apply:
a. Connect the device in the electrical configuration for programming.
b. Raise VCC to 5.5 volts .
c. Address the PROM with the binary addres s of the select ed word to be pro grammed. Address i nputs are
TTL compatible.
d. Disable the chip by appl ying VIH to the
CE
1 and
CE
2 and VIL to the CE3 and CE4 input s (device types 01
and 02) or VIH to the CE i nput (device types 04 and 05). The CE input is TTL c om patible.
e. Apply the VPP pulse to the programming pin
CE
2 (device types 01 and 02) or
CE
(device types 04 and
05). In order to ins ure that the output transis tor is off before inc reasing th e voltage on the out put pin, the
programming pin’s voltage pulse shall prec ede the output pin’s program ming pulse by TD1 and leav e after
the output pin’s programming pulse by TD2 (see figure 7b).
f. Apply only one V OUT pulse with duration of tP to the out put selected for pr ogramming. The outputs shall be
programmed one output at a time, since internal decoding c ircuitry is ca pable of sinking only one unit of
programming current at a time. Note that the P R OM is supplied with fuses generating a high-l ev el logic
output. Programming a fuse will c ause the output to go to a low-level logic i n the verify mode.
g. Other bits i n the same word may be programmed seq uentially b y applying VPP pulses to each output to be
programmed.
h. Repeat 4.8c through 4.8g for all other bit s to be programmed.
i. Enable the chip by applying VIL to the
CE
1 and
CE
2 and VIH to the CE3 and CE4 inputs (device types 01
and 02) or VIL to the
CE
inputs (device types 04 and 05) and verify the program. Verification may check
for a low output by requiring t he device to sink 12 m A at VCC = 4.0 V and 0.2 mA at VCC = 7.0 V at
TA = 25°C.
j. For class S and B devices, if any bit does not verify as programmed, it shall be considered a programming
reject. .
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TABLE IVB. Programming characteristics for circuit B.
Parameter Symbol Conditions Limits 1/ Unit
Min Recommended
Max
V
CC
required durin g
programming
V
CCP
5.4
5.5
5.6
V
Rise time of
programming pulse to
data out or programming
pin
t
TLH
0.34
0.40
0.46
V/µs
Programming voltage on
programming pin
V
PP
32.5
33
33.5
V
Output progr amming
voltage
V
OUT
25.6
26
26.5
V
Programming pin pulse
width (
CE
2) 2/
t
PP
Chip disabled,
VCC = 5.5 V
100
180
ns
Pulse width of
programming voltage
t
P
Chip disabled,
VCC = 5.5 V
1
40
µs
Required curr ent limit of
power supply feeding
programming pin and
output durin g
programming
I
L
V
PP
= 33 V, V
OUT
= 26 V,
VCC = 5.5 V
240
mA
Required tim e delay
between disabling
memory output and
application of output
programming pulse
T
D1
Measured at 1 0% l evels
70
80
90
µs
Required tim e delay
between remov al of
programming pulse and
enabling mem ory output
T
D2
Measured at 1 0% l evels
100
ns
Output current during
verification
I
OLV1
Chip enabled,
VCC = 4.0 V
11
12
13
mA
I
OLV2
Chip enabled,
VCC = 7.0 V
0.19
0.2
0.21
mA
Address input voltage
V
IH
2.4
5.0
5.5
V
V
IL
0.0
0.4
0.8
V
Maximum duty cycle
during automatic
programming of program
pin and output pin
D.C.
t
P
/ t
C
----
----
25
%
1/ TA = +25°C.
2/
CE
1 is the programm i ng pin for device types 04 and 05.
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4.9 Programming procedures for circuits C and H. The wavefor ms on figure 7c, the programming ch aracteristics
in table IVC, and the follo win g procedures shall be used for pr ogramming the dev ice:
4.9.1 Device types 01 and 02.
a. Connect the dev ice in the elect r i c al c onfiguration for programm ing.
b. Terminat e al l device outputs with a 10 k resistor to VCC. Apply
CE
1 = VIH,
CE
2 = VIL, CE3 = VIH, and
CE4 = VIH.
c. Address the PROM with the binary addres s of the select ed word to be pro grammed. Rais e VCC to VCCP.
d. After a tD delay (10µs), apply only one VOUT puls e to the output t o be pr ogrammed. Program one output at
a time.
e. After a tD delay (10µs), pulse CE1 input to lo gic “0” for a durat ion of tP.
f. After a tD delay (10µs), remove the VOUT pulse from the pr ogrammed output. Programming a fuse will
cause the output to go to a high-level logic in t he v erify mode.
g. Other bits i n the same word may be programmed seq uentially while the VCC input is at the VCCP l evel by
applying VOUT pulses to each output to be programmed allowing a delay of tD between puls es as shown on
figure 7c.
h. Repeat 4.9. 1c through 4.9.1 g for all other bits to be programmed.
i. To verif y programming, after tD (10 µs) delay, lower VCC to VCCH and apply a logic “0” level to both
CE
1 and
CE
2 inputs. The program m ed output should remain in the “1” state. Again, l ower VCC to V CCL and verify
that the progr ammed output r em ains in the “1” s tate.
j. For class S and B devices, if any bit does not v erify as programmed i t shall be considered a program ming
reject.
4.9.2 Device type 03.
a. Connect the device in the electrical configuration for programming.
b. Terminat e al l device outputs with a 10 k resistor to VCC. Apply
CE
1 = VIL,
CE
2 = VIH, and strobe = VIH.
c. Address the PROM with the binary addres s of the select ed word to be pr ogrammed. Raise VCC to VCCP.
d. After a tD delay (10µs), apply t o FE1 (pin 13) a voltage source of +5. 0 ± 0.5 V, with 10 mA sour c ing current
capability.
e. After a tD delay (10µs), apply only one VOUT puls e to the output t o be pr ogrammed. Program one output at
a time.
f. After a tD delay (10µs), raise FE2 (pin 11) from GND to +5.0 ± 0.5 V for 1 ms, and ret ur n to GND.
g. After a tD delay (10 µs), remov e the VOUT pulse from the programmed output.
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h. Programmi ng a fuse will cause the output to go to a high level logic in the verify mode. Other bits in the
same word may be programmed s equentially while the VCC input is at the VCCP level by applying VOUT
pulses to each output to be programmed allowing a delay to tD between puls es as shown on figure 7c.
i. Repeat 4.9.2c through 4.9.2h for all other bits to be progr am med.
j. To verif y programming aft er a tD (10 µs) delay, return F E1 to GND. Raise VCC to VCCH. The programmed
output shoul d r emain in the hi gh s tate. Again lower VCC to VCCL and verify that the programmed output
remains in the high state.
k. For class S and B devices, if any bit does not verify as programmed it shall be consi dered a programming
reject.
TABLE IVC. Programming characteristics for circuits C and H.
Parameter Symbol Conditions Limits Unit
Min Recommended
Max
Programming voltage to
VCC
V
CCP
1/
I
CCP
= 375 ±75 mA
Transient or steady-state
8.5
8.75
9.0
V
Verification upper limit
V
CCH
5.3
5.5
5.7
V
Verification lower limit
VCCL
4.3
4.5
4.7
V
Verify threshold
V
S
2/
1.4
1.5
1.6
V
Programming supply
current
I
CCP
V
CCP
= 8.75 ±0.25 V
300
450
mA
Input voltage , high level
“1”
V
IH
2.4
5.5
V
Input voltage , l ow level
“0”
V
IL
0
0.4
0.8
V
Input current
IIH
VIH = 5.5 V
50
µA
Input current
IIL
VIL = 0.4 V
-500
µA
Output progr amming
voltage
V
OUT
3/
I
OUT
= 200 ±20 mA
Transient or steady-state
16
17
18
V
Output progr amming
current
I
OUT
V
OUT
= 17 ±1 V
180
200
220
mA
Programming voltage
transition time
t
TLH
10
50
µs
CE
programming puls e
width
t
P
300
400
500
µs
Pulse sequence delay
t
D
10
µs
1/ Bypass VCC to GND with a 0.01 µF capacitor to reduce v oltage spikes.
2/ VS is the sensing t hr eshold of the P R OM output voltag e for a programmed bit. It normall y constitutes the
reference voltage applied to a comparator circuit to verify a successful fusing att em pt.
3/ Care should be taken to insure t he 17 ±1 V output voltage is maintained during the entire fusing c ycl e. The
recommended s upply is a constant current source clamped at the specified voltage limit.
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4.10 Programming procedure for circuit D. The waveforms on figure 7d, the programming characteris tics of table
IVD, and the following procedures shall apply:
a. Connect the device in the electrical configuration for programming.
b. Address the PROM with the binary address of the selected word to be programmed. Address inputs are
TTL compatible.
c. Disable the chip b y applying VIH to the
CE
1 and
CE
2 inputs and VIL to the CE3 and CE4 i nputs. The chip
enable input is TTL compatible.
d. After a dela y of tD, apply only one VOUT pulse with a duration of tp to the ouput selec ted for progr am ming.
The other outputs may be left open or tied to VIH. The outputs shall be programmed one output at a time.
Note that the PROM is supplied with fuses generating a high-level log ic output. Pr ogramming a fuse will
cause the output to go to a low-level logic in the verify mode.
e. Other bits i n the same word may be programmed seq uentially by applying VOUT pulses to each out put to be
programmed.
f. Repeat 4.10b through 4.10e for all ot her bits to be programmed.
g. Enable the chip by applying VIL to the
CE
1 and
CE
2 inputs and VIH to the C E3 and CE4 inputs and verify
the program.
h. For class S and B devices, if any bit does not v erify as program m ed, it shall be co nsidered a programming
reject.
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TABLE IVD. Programming characteristics for circuit D.
Parameter Symbol Conditions 1/ Limits Unit
Min Recommended
Max
V
CC
required durin g
programming
V
CCP
4.75
5.0
5.25
V
Verificati on V
CC
read
V
CCL
Programming read verif y
4.2
4.4
5.0
V
Input voltage , high level
“1”
V
IH
Do not leave inputs
open
2.4
5.0
5.0
V
Input voltage , l ow level
“0”
V
IL
Do not leave inputs open
0
0
0.4
V
Output progr amming
voltage
V
OUT
Applied to output to be
programmed
20
20.5
21
V
Output progr amming
current
I
OUT
If pulse generator is
used, set current limit to
the max value
100
mA
Programming voltage
transition time
t
TLH
0.5
1.0
3.0
µs
Programming puls e
width
t
P
50
100
180
µs
Programming duty cycle
D. C.
Maximum duty cycle to
maintain TA < +85°C
20
20
%
Required delay between
disabling memory output
and application of output
programming pulse
t
D
30
ns
1/ Recommended TA = +25°C; maximum TA = +85°C.
4.11 Programming procedure for circuit F. The waveforms on figure 7f, the programming charact er i s tics on tabl e
IVF, and the following procedures shall apply:
a. Connect the device in the electrical configuration for programming.
b. Raise VCC to 5.5 Volts .
c. Address the PROM with the binary addres s of the select ed word to be pro grammed. Address i nputs are
TTL compatible.
d. Disable the chip by appl ying VIH to the
CE
inputs and VIL to the CE inputs. The chi p enable inputs ar e TTL
compatible.
e. Apply the VPP pulse to the programm ing pin
CE
2. In order to insure that the output transistor is off before
increasing v oltage on the output pin, the programming pi n’s voltage pulse shall precede the output pin’s
programming pulse by TD1 and l eave after the programming pin’ s programming pulse by T D2
(see figure 7f).
f. Apply only one V OUT pulse with duration of tP to the output selected f or programming. The outputs sh all be
programmed one output at a time, since internal decoding c ircuitry is ca pable of sinking only one unit of
programming current at a time. Note that the P R OM is supplied with fuses generating a high-l ev el logic
output. Programming a fuse will c ause the output to go to a low-level logi c i n the verify mode.
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MIL-M-38510/208F
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g. Other bits i n the same word may be programmed seq uentially by applying VOUT pulses to each output to be
programmed.
h. Repeat steps 4.11c through 4.11g for al l other bits to be programmed.
i. Enable the chip by applying VIL to the
CE
inputs and VIH to the C E i nputs, and verify the program.
Verificati on may check for a low output by re quiring the device to sink 12 mA at VCC = 4.0 V and 0.2 mA at
VCC = 7.0 V at TA = 25°C.
j. For class S and B devices, if any bit does not v er i fy as programmed, it shall be co ns i dered a program m ing
reject.
TABLE IVF. Programming characteristics for circuit FContinued.
Parameter Symbol Conditions Limits 1/ Unit
Min Recommended
Max
V
CC
required durin g
programming
V
CCP
5.4
5.5
5.6
V
Rise time of pr ogramming
pulse data out or
programming pin
t
TLH
0.34
0.40
0.46
V/µs
Programming voltage on
programming pin
V
PP
32.5
33
33.5
V
Output progr amming
voltage
V
OUT
25.5
26
26.5
V
Programming pin pulse
width (
CE
)
t
PP
Chip disabled,
VCC = 5.5 V
100
180
ns
Pulse width of pr ogramming
voltage
t
P
Chip disabled,
VCC = 5.5 V
1
40
µs
Required curr ent limit of
power supply feeding
programming pin and output
during programming
I
L
V
PP
= 33 V, V
OUT
= 26 V,
VCC = 5.5 V
240
mA
Required tim e delay
between disabling memory
output and application of
output programming pulse
T
D1
Measured at 1 0% l evels
70
80
90
µs
Required tim e delay
between remov al of
programming pulse and
enabling mem ory output
T
D2
Measured at 1 0% l evels
100
----
----
ns
Output current during
verification
I
OLV1
Chip enabled,
VCC = 4.0 V
11
12
13
mA
I
OLV2
Chip enabled,
VCC = 7.0 V
0.19
0.2
0.21
mA
Address input voltage
V
IH
2.4
5.0
5.5
V
V
IL
0.0
0.4
0.8
V
Maximum duty cycle during
automatic programming of
program pin and output pin
D. C.
t
P
/ t
C
----
----
25
%
1/ TA = +25°C.
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MIL-M-38510/208F
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4.12 Programming procedur e for circuit G. The programming c haracteristics on table IVG and the following
procedures shall be used for programming:
a. Connect the device in the electrical configuration for programming. The waveforms on figure 7g and the
programming characterist i c s of table IVG shall apply to these procedures.
b. Select the d esired word b y applying high or low levels to the appropriate a ddr ess inputs. Dis able the
device by applying a high level to one or more ‘active low’ chip Enable in puts. NOTE: Addres s and enable
inputs must be driven with TTL l ogic levels d ur i ng programm ing and verification.
c. Increase VCC from nominal to VCCP (10.5 ±0.5 V) with a slew rate limit of IRR (1.0 to 10.0 V/µs). Since VCC is
the source of the current requir ed to program t he fuse as well as the ICC for the device at the progr am ming
voltage, it must be capable of supplying 75 0 m A at 11.0 volts.
d. Select the o utput where a logical high is desired by raising that output voltage to VOP (10.5 ±0.5 V). Lim it
the slew rate to IRR (1.0 to 10.0 V/µs). This voltage c hange may occur s imultaneous ly with the V CC
increase to VCCP, but must not precede it. It is critical that only one out put at a time be programmed since
the internal cir cuits can only supply programming current to one bit at a ti me. Outputs not bei ng
programmed m ust be left open or c onnected to a high impedance source of 20 k minimum (remember
that the outputs of the device ar e di sabled at this time).
e. Enable the d evice by takin g the chip Enab le(s) to a low level. This is done with a pulse PW E for 10 µs. The
10 µs duration refers to the time t hat the circuit (dev ice) is ena bled. Normal input levels are used and rise
and fall times are not critical.
f. Verify that the bit has been programmed by first removing the progr am ming voltage from the output and
then reducing VCC to 5.0 (±0.25 V). The device must be enabled to sense the state of the outputs. Dur i ng
verificati on, the loading of the output must be within specified IOL and IOH limit s .
g. If the device i s not to be tested for VOH over the entire operating r ange subsequent to programm ing, the
verification of Step f is t o be per formed at a VCC level of 4.0 vol ts (±0.2 V). VOH, during the 4 volt
verificati on, must be at leas t 2.0 volts. The 4 volt VCC verification assures minimum VOH l evels over the
entire operating range.
h. Repeat steps 4.12b through 4.12f for each bit to be program m ed to a high level. If the procedure is
performed on a n automatic program mer, the duty cycle of VCC at the programmi ng v ol tage must be limited
to a maximum of 25 percent. This is necessary to minimize device junction temperatures. After all
selected bits are programmed, the entire c ontents of the m em ory should be veri fied.
i. For class S and B devices, if any bit does not v er i fy as programmed, it shall be co ns i dered a program m ing
reject.
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MIL-M-38510/208F
52
TABLE IVG. Programming characteristics for circuit G.
Parameter Symbol Conditions Limits 1/ Unit
Min Recommended
Max
Required V
CC
during
programming
V
CCP
10.0
10.5
11.0
V
I
CC
during programming
I
CCP
V
CC
= 11 V
750
mA
Required output voltage
for programmi ng
V
OP
10.0
10.5
11.0
V
Output current wh ile
programming
I
OP
V
OUT
= 11 V
20
mA
Rate of voltage change
of VCC or output
I
RR
1.0
10.0
V/µs
Programming puls e
width (Enabl ed)
PWE
9
10
11
µs
Required V
CC
for
verification
V
CCV
3.8
4.0
4.2
V
Maximum duty cycle for
VCC at VCCP
MDC
25
25
%
Address set-up time
t1
100
ns
V
CCP
set-up time
t
2
2/
5
µs
VCCP hold time
t5
100
ns
VOP set-up time
t3
100
ns
VOP hold time
t4
100
ns
1/ TA = +25°C.
2/ VCCP set-up time may be greater than 0 if VCCP rises at the same rate or f aster than VOP.
5. PACKAGING
5.1 Packaging requirements. For acquisiti on purposes, t he pac kaging requir em ents shall be as specifie d i n the
contract or order (see 6.2). W hen packaging of materiel is to be performed by Do D or in-house contractor pers onnel,
these person nel need to contact the responsible packaging activity to ascertain p ac kaging requir ements. P ac kaging
requirement s are maintained by the Inventory Control Point's packaging activity with in the Militar y Ser vice or Defens e
Agency, or within the military service's system command. P ackaging dat a retrieval is available from the managing
Military Depar tment's or Defense Agency's automated packaging fi les, CD-ROM products, or by contacting the
responsible packaging activity.
6. NOTES
(This section contains information of a general or explan atory nature which may be helpf ul, but is not
mandatory.)
6.1 Intended u se. Microcircuits conforming to this specif i cation are i ntended for logistic support of existing
equipment.
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MIL-M-38510/208F
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6.2 Acquisiti on requirements. Acquisition d ocuments should specify the f ollowing:
a. Title, number, and date of t he specification.
b. PIN and compl iance identifier, if applic able (see 1.2).
c. Requirements for deliver y of one copy of the c onformance inspection data pertinent to the device
inspection l ot to be supplied with each ship m ent by the device manufacturer , if applicable.
d. Requirements for certif i c ate of compli anc e, if applicable.
e. Requirements for notification of change of product or pr ocess to contr ac ting activity in addition to
notificati on to the qualifying activity, if applicabl e.
f. Requirements f or failure anal y sis (including required test condition of m ethod 5003 of MIL-STD-883),
corrective act ion, and repor ting of results , if applicable.
g. Requirements for product assurance options.
h. Requirements for special l ead lengths, or lead forming, i f applicable. Unless otherwise specified, these
requirement s will not apply to direct purchase by or direct shipment to t he Government.
i. Requirement for programmi ng the device, including proc essing optio n. The device may be pr ogrammed
pre- or post-burn-in, if applic able.
j. Requirements for "JA N" m arking.
k. Packaging Requirements (s ee 5.1)
6.3 Qualification. With respe c t to products requiring qualification, awards will be mad e only for produc ts which
are, at the time of award of contr act, qualified for inclusion in Qualified Manufacturers List QML-38535 whether or not
such products have actually been so listed by that date. The attention of t he contractor s is called to these
requirement s, and manufacturers are urged to arrange to have the produc ts that they propos e to offer to the Federal
Government tested for qualification in order that the y may be eligible t o be awarded contracts or purcha se orders for
the products covered by this specification. Information pertaining to qualification of products may be obtained from
DLA LAND AND MARITIME-VQ, 3990 E. Broad Street, Col um bus, Ohio 43218-3990.
6.4 Supersedi ng i nformation. T he r equi r ements of MIL-M-38510 have b een superseded to take advantage of the
available Qualified Manufacturer Listing (QML) system provided b y MIL-PRF-38535. Previous references to MIL-M-
38510 in this document have been replaced by appropriate references to M IL-PRF-38535. All technical requirements
now consist of this specific ation and MIL-PRF-38535. The MIL-M-38510 specification sheet number and PIN have
been retained to avoid adver sely impact i ng existing gover nment logisti c s systems and contractor's par ts lists.
6.5 Abbreviations, symbols , and defini tions. The abbrev iations, symbols, and definitions us ed herein are def ined
in MIL-PRF-38535, MIL-HDBK-1331, and as f oll ows:
GND ............................................ Ground zero voltage potent i al.
VIN ............................................... Volt age level at an inp ut terminal
VIC ................................................ Input clamp voltage
IIN ................................................. Current flowing into an input terminal
6.6 Logistic s upport. Lead m aterials and fi nishes (see 3.4) are intercha ngeable. Unless otherwise specified,
microcircui ts acquired for Government logistic support will be acquire d to device class B (see 1.2.2), le ad material
and finish C (see 3.4). Longer length leads and lead forming sho uld not affect the part number. It is intended that
spare devices for logistic s upport be acquired in the unprogrammed condition (see 3.8.1) and programmed b y the
maintenance activity, e xcept where use q uantities for dev ices with a specific program or pattern justify stocking of
preprogramm ed devices.
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MIL-M-38510/208F
54
6.7 Substitutability. The cross-reference informat i on below is pres ented for the convenience of us er s.
Microcircuits covere d by this specification will f unc tionally replace the listed generic-industry type. Generic-industry
microcircui t types may not have equivalent operational performance characterist i c s across milit ary temperatur e
ranges or reli ability factor s equivalent t o M IL-M-38510 devic e types and may have s light physical variations in relation
to case size. T he pr esence of this information should not be deemed as permitting substitution of generic-industry
types for MIL-M-38510 types or as a waiver of any of the provisions of MIL-PRF-38535.
Military
device type
Generic-industry
Type
Circuit
Designator
Fusible
Links
Symbol/
FSCM no.
01
7640/Harris Corporation
A
NiCr
CDWO/34371
01
5340-1/Monolithic Memories, Inc.
B
NiCr
CECD/50364
01
82S140/Signetics Corporation
C
NiCr
CDKB/18324
01
82S140/ e2v aer ospace & defense, inc.
C
ZVE
0C7V7
01
93438/Fairchild Corporat ion
D
NiCr
CFJ/07263
01
54S475/Nat ional Semicond uctor
G
TiW
CCXP/27014
02
7641/Harris Corporation
A
NiCr
----
02
5341-1/Monol ithic Memories, Inc.
B
NiCr
----
02
82S141/Signetics Corpor ation
C
NiCr
----
02
82S141/e2v aerospace & defense, inc.
H
ZVE
0C7V7
02
93448/Fairchild Corporat ion
D
NiCr
----
02
54S474/Nat ional Semicond uctor
G
TiW
----
03
82S115/Signetics Corpor ation
C
NiCr
----
03
82S115/ e2v aerospace & defense, i nc .
C
ZVE
0C7V7
04
5348-1/Monolithic Memories, Inc.
B
NiCr
----
04
54S473/Nat ional Semicond uctor
G
TiW
----
05
5349-1/Monolithic Memories, Inc.
B
NiCr
----
05
29621/Rayt heon Company
F
NiCr
CRP/07933
05
54S472/Nat ional Semiconductor
G
TiW
----
6.8 Change f r om previous issue. Marginal notations are not used in this revision to ident i fy changes with r espect to
the previous issue due to the extent of the changes.
Custodians: Preparing activity:
Army - CR DLA - CC
Navy - EC
Air Force - 85
DLA - CC
Review activities: (Project 5962-2013-005)
Army – SM, MI
Navy - AS, CG, MC, SH
Air Force 03, 19, 99
NOTE: The activ i ties listed a bov e were interested in this d oc ument as of the dat e of this document. Since
organization and responsibilities can c hange, you should verify the currency of the information above using the
ASSIST Onl ine database at https://assist.dla.mil.
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