SPC584Gx, SPC58EGx, SPC58NGx 32-bit Power Architecture(R) microcontroller for automotive ASIL-D applications Datasheet - production data eTQFP144 (20 x 20 x 1.0 mm) eLQFP176 (24 x 24 x 1.4 mm) FPBGA292 (17 x 17 x 1.8 mm) * Crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC Features * AEC-Q100 qualified * High performance e200z4 triple core: - 32-bit Power Architecture technology CPU - Core frequency as high as 180 MHz - Variable Length Encoding (VLE) - Floating Point, End-to-End Error Correction * 6582 KB (6144 KB code flash+ 256 KB data flash) on-chip flash memory: - supports read during program and erase operations, and multiple blocks allowing EEPROM emulation - Supports read while read between the two code Flash partitions. * 608 KB on-chip general-purpose SRAM (in addition to 160 KB core local data RAM): 64KB in CPU_0, 64 KB in CPU_1 and 32 KB in CPU_2 * 182 KB HSM dedicated flash memory (144 KB code + 32 KB data) * Multi-channel direct memory access controller (eDMA) - one eDMA with 64 channels - one eDMA with 32 channels * 1 interrupt controller (INTC) * Comprehensive new generation ASIL-D safety concept: - ASIL-D of ISO 26262 - One CPU channel in lockstep February 2019 This is information on a product in full production. - Logic BIST - FCCU for collection and reaction to failure notifications - Memory BIST - Cyclic redundancy check (CRC) unit - Memory Error Management Unit (MEMU) for collection and reporting of error events in memories * Body cross triggering unit (BCTU) - Triggers ADC conversions from any eMIOS channel - Triggers ADC conversions from up to 2 dedicated PIT_RTIs * Enhanced modular IO subsystem (eMIOS): up to 64 timed IO channels with 16-bit counter resolution * Enhanced analog-to-digital converter system with: - 4 independent fast 12-bit SAR analog converters - One supervisor 12-bit SAR analog converter - One standby 10-bit SAR analog converter * Communication interfaces: - 18 LINFlexD modules - 10 deserial serial peripheral interface (DSPI) modules - 8 MCAN interfaces with advanced shared memory scheme and ISO CAN-FD support - Dual-channel FlexRay controller - Two independent Ethernet controllers 10/100Mbps compliant IEEE 802.3-2008 * Low power capabilities - Versatile low power modes - Ultra low power standby with RTC - Smart Wake-up Unit for contact monitoring DS11758 Rev 5 1/131 www.st.com SPC584Gx, SPC58EGx, SPC58NGx - Fast wakeup schemes * Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell * Nexus development interface (NDI) per IEEEISTO 5001-2003 standard, with some support for 2010 standard * Boot assist Flash (BAF) supports factory programming using a serial bootload through the asynchronous CAN or LIN/UART * Junction temperature range -40 C to 150 C Table 1. Device summary Part number Package 4 MB Single core Dual core 6 MB Triple core Single core Dual core Triple core eTQFP144 SPC584G80E5 SPC58EG80E5 SPC58NG80E5 SPC584G84E5 SPC58EG84E5 SPC58NG84E5 eLQFP176 SPC584G80E7 SPC58EG80E7 SPC58NG80E7 SPC584G84E7 SPC58EG84E7 SPC58NG84E7 FPBGA292 SPC584G80C3 SPC58EG80C3 SPC58NG80C3 SPC584G84C3 SPC58EG84C3 SPC58NG84C3 2/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Table of contents Table of contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 Device feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 12 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.1 Power domains and power up/down sequencing . . . . . . . . . . . . . . . . . 19 3.4 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5 Electromagnetic compatibility characteristics . . . . . . . . . . . . . . . . . . . . . . 21 3.6 Temperature profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.7 Device consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.8 I/O pad specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.8.1 I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.8.2 I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.8.3 I/O pad current specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.9 Reset pad (PORST, ESR0) electrical characteristics . . . . . . . . . . . . . . . . 37 3.10 PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.11 3.12 3.10.1 PLL0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.10.2 PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.11.1 Crystal oscillator 40 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.11.2 Crystal Oscillator 32 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.11.3 RC oscillator 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.11.4 Low power RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 ADC system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 DS11758 Rev 5 3/131 4 Table of contents 3.12.1 ADC input description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.12.2 SAR ADC 12 bit electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.12.3 SAR ADC 10 bit electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.13 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.14 LFAST pad electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.15 4 SPC584Gx, SPC58EGx, SPC58NGx 3.14.1 LFAST interface timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.14.2 LFAST and MSC/DSPILVDS interface electrical characteristics . . . . . . 57 3.14.3 LFAST PLL electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.15.1 Power management integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.15.2 Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.15.3 Voltage monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 3.16 Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.17 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.17.1 Debug and calibration interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.17.2 DSPI timing with CMOS pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 3.17.3 Ethernet timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.17.4 FlexRay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 3.17.5 CAN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 3.17.6 UART timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 3.17.7 I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4.1 eTQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.2 eLQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4.3 FPBGA292 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 4.4 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 4.4.1 eTQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.4.2 LQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.4.3 BGA292 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4.4.4 General notes for specifications at maximum junction temperature . . 116 5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx 1 Introduction 1.1 Document overview Introduction This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. To ensure a complete understanding of the device functionality, refer also to the device reference manual and errata sheet. 1.2 Description The SPC584Gx, SPC58EGx, SPC58NGx microcontroller belongs to a family of devices superseding the SPC56x family. SPC584Gx, SPC58EGx, SPC58NGx builds on the legacy of the SPC5x family, while introducing new features coupled with higher throughput to provide substantial reduction of cost per feature and significant power and performance improvement (MIPS per mW). 1.3 Device feature summary Table 2 lists a summary of major features for the SPC584Gx, SPC58EGx, SPC58NGx device. The feature column represents a combination of module names and capabilities of certain modules. A detailed description of the functionality provided by each on-chip module is given later in this document. Table 2. SPC584Gx, SPC58EGx, SPC58NGx features summary Feature Description SPC58 family 40 nm Computing Shell 0 Number of Cores up to 2 Number of checker cores up to 1 16 KB Instruction Local RAM 64 KB Data Single Precision Floating Point Yes SIMD (LSP) No VLE Yes 8 KB Instruction Cache 4 KB Data Computing Shell 1 Number of Cores 1 Number of checker cores 0 DS11758 Rev 5 5/131 11 Introduction SPC584Gx, SPC58EGx, SPC58NGx Table 2. SPC584Gx, SPC58EGx, SPC58NGx features summary (continued) Feature Description 16 KB Instruction Local RAM 32 KB Data Single Precision Floating Point Yes SIMD (LSP) Yes VLE Yes Cache 8 KB Instruction Other Core MPU: 24 per CPU MPU System MPU: 24 per XBAR Semaphores Yes CRC Channels 2x4 Software Watchdog Timer (SWT) 4 Core Nexus Class 3+ 4 x SCU Event Processor 4 x PMC Run control Module Yes System SRAM 608 KB (including 256KB of standby RAM) Flash 6144 KB code / 256 KB data Flash fetch accelerator 2 x 2 x 4 x 256-bit DMA channels 96 DMA Nexus Class 3 LINFlexD 18 M_CAN supporting CAN-FD according to ISO 11898-1 2015 8 DSPI 10 I2C 1 FlexRay 1 x Dual channel Ethernet 2 MAC with Time stamping, AVB and VLAN support SIPI / LFAST Interprocessor bus High Speed 8 PIT channels System Timers 4 AUTOSAR(R) (STM) RTC/API 6/131 eMIOS 2 x 32 channels BCTU 64 channels Interrupt controller > 710 sources DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Introduction Table 2. SPC584Gx, SPC58EGx, SPC58NGx features summary (continued) Feature Description ADC (SAR) 6 Temp. sensor Yes Self Test Controller Yes PLL Dual PLL with FM Integrated linear voltage regulator Yes External Power Supplies 3.3 V - 5 V Stop Mode Low Power Modes Halt Mode Smart Standby with output controller, analog and digital inputs Standby Mode DS11758 Rev 5 7/131 11 Introduction 1.4 SPC584Gx, SPC58EGx, SPC58NGx Block diagram The figures below show the top-level block diagrams. Figure 1. Block diagram 8/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Introduction Figure 2. Periphery allocation DS11758 Rev 5 9/131 11 Introduction 1.5 SPC584Gx, SPC58EGx, SPC58NGx Features On-chip modules within SPC584Gx, SPC58EGx, SPC58NGx include the following features: * * 10/131 Three main CPUs, dual issue, 32-bit CPU core complexes (e200z4), one paired in lock-step. - Power Architecture embedded specification compliance - Instruction set enhancement allowing variable length encoding (VLE), encoding a mix of 16-bit and 32-bit instructions, for code size footprint reduction - Single-precision floating point operations - Lightweight signal processing auxiliary processing unit (LSP APU) instruction support for digital signal processing (DSP) on Core_2 - 16 KB Local instruction RAM and 64 KB local data RAM for Core_0 and Core_1, 16 KB Local instruction RAM and 32 KB local data RAM for Core_2 - 8 KB I-Cache and 4 KB D-Cache for Core_0 and Core_1, 8kB I-Cache for Core_2 6400 KB (6144 KB code flash + 256 KB data flash) on-chip Flash memory - Supports read during program and erase operations, and multiple blocks allowing EEPROM emulation - Supports read while read between the two code Flash partitions. * 608 KB on-chip general-purpose SRAM (+ 160 KB data RAM included in the CPUs) * 182 KB HSM dedicated flash memory (144 KB code + 32 KB data) * Multi channel direct memory access controllers (eDMA paired in lock-step) - One eDMA with 64 channels - One eDMA with 32 channels * One interrupt controller (INTC) in lock-step * Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell * Dual crossbar switch architecture for concurrent access to peripherals, Flash, or RAM from multiple bus masters with end-to-end ECC * Hardware security module (HSM) to provide robust integrity checking of Flash memory * System integration unit lite (SIUL) * Boot assist Flash (BAF) supports factory programming using a serial bootload through the asynchronous CAN or LIN/UART. * Hardware support for motor control and safety related applications * Enhanced modular IO subsystem (eMIOS): up to 64 (2 x 32) timed I/O channels with 16-bit counter resolution - Buffered updates - Support for shifted PWM outputs to minimize occurrence of concurrent edges - Supports configurable trigger outputs for ADC conversion for synchronization to channel output waveforms - Shared or independent time bases - DMA transfer support available DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx * * Introduction Body cross triggering unit (BCTU) - Triggers ADC conversions from any eMIOS channel - Triggers ADC conversions from up to 2 dedicated PIT_RTIs - One event configuration register dedicated to each timer event allows to define the corresponding ADC channel - Synchronization with ADC to avoid collision Enhanced analog-to-digital converter system with - Four independent fast 12-bit SAR analog converters - One supervisor 12-bit SAR analog converter - One 10-bit SAR analog converter with STDBY mode support * Ten deserial serial peripheral interface (DSPI) modules * Eighteen LIN and UART communication interface (LINFlexD) modules - LINFlexD_0 is a Master/Slave - All others are Masters * Eight modular controller area network (MCAN) modules, all supporting flexible data rate (CAN-FD) * Dual-channel FlexRay controller * Two ethernet controllers 10/100 Mbps, compliant IEEE 802.3-2008 - IEEE 1588-2008 Time stamping (internal 64-bit time stamp) - IEEE 802.1AS and IEEE 802.1Qav (AVB-Feature) - IEEE 802.1Q VLAN tag detection - IPv4 and IPv6 checksum modules * Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some support for 2010 standard. * Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1) * Standby power domain with smart wake-up sequence DS11758 Rev 5 11/131 11 Package pinouts and signal descriptions 2 SPC584Gx, SPC58EGx, SPC58NGx Package pinouts and signal descriptions Please refer to the SPC584Gx, SPC58EGx, SPC58NGx IO_ definition document. It includes the following sections: 12/131 1. Package pinouts 2. Pin descriptions a) Power supply and reference voltage pins b) System pins c) LVDS pins d) Generic pins DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics 3 Electrical characteristics 3.1 Introduction The present document contains the target Electrical Specification for the 40 nm family 32-bit MCU SPC584Gx, SPC58EGx, SPC58NGx products. In the tables where the device logic provides signals with their respective timing characteristics, the symbol "CC" (Controller Characteristics) is included in the "Symbol" column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol "SR" (System Requirement) is included in the "Symbol" column. The electrical parameters shown in this document are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 3 are used and the parameters are tagged accordingly in the tables where appropriate. Table 3. Parameter classifications Classification tag Tag description P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design validation on a small sample size from typical devices. D Those parameters are derived mainly from simulations. DS11758 Rev 5 13/131 13 Electrical characteristics 3.2 SPC584Gx, SPC58EGx, SPC58NGx Absolute maximum ratings Table 4 describes the maximum ratings for the device. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Stress beyond the listed maxima, even momentarily, may affect device reliability or cause permanent damage to the device. Table 4. Absolute maximum ratings Value Symbol VDD_LV C SR Parameter Conditions Unit Min Typ Max D Core voltage operating life range(1) -- -0.3 -- 1.4 V -- -0.3 -- 1.5 V VDD_LV_BD SR D Buddy device voltage operating life range(2) VDD_HV_IO_MAIN VDD_HV_IO_FLEX VDD_HV_OSC VDD_HV_FLA SR D I/O supply voltage(3) -- -0.3 -- 6.0 V VSS_HV_ADV SR D ADC ground voltage Reference to digital ground -0.3 -- 0.3 V VDD_HV_ADV SR D ADC Supply voltage(3) Reference to VSS_HV_ADV -0.3 -- 6.0 V VSS_HV_ADR_S SR D SAR ADC ground reference -- -0.3 -- 0.3 V VDD_HV_ADR_S SR D SAR ADC voltage reference(3) Reference to VSS_HV_ADR_S -0.3 -- 6.0 V VSS-VSS_HV_ADR_S SR D VSS_HV_ADR_S differential voltage -- -0.3 -- 0.3 V VSS-VSS_HV_ADV SR D VSS_HV_ADV differential voltage -- -0.3 -- 0.3 V -- -0.3 -- 6.0 Relative to Vss -0.3 -- -- Relative to VDD_HV_IO and VDD_HV_ADV -- -- 0.3 -- -- -- 1 VIN TTRIN 14/131 SR SR D D I/O input voltage range(3)(4) (5) Digital Input pad transition time(6) DS11758 Rev 5 V ms SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Table 4. Absolute maximum ratings (continued) Value Symbol IINJ TSTG TPAS C SR SR SR Parameter Conditions Unit Min Typ Max T Maximum DC injection current for each analog/digital PAD(7) -- -5 -- 5 mA T Maximum nonoperating Storage temperature range -- -55 -- 125 C C Maximum nonoperating temperature during passive lifetime -- -55 -- 150(8) C No supply; storage temperature in range -40 C to 60 C -- -- 20 years TSTORAGE SR -- Maximum storage time, assembled part programmed in ECU TSDR SR T Maximum solder temperature Pbfree packaged(9) -- -- -- 260 C MSL SR T Moisture sensitivity level(10) -- -- -- 3 -- Maximum cumulated XRAY dose Typical range for X-rays source during inspection:80 / 130 KV; 20 / 50 A -- -- 1 grey TXRAY dose SR T 1. VDD_LV: allowed 1.335 V - 1.400 V for 60 seconds cumulative time at the given temperature profile. Remaining time allowed 1.260 V - 1.335 V for 10 hours cumulative time at the given temperature profile. Remaining time as defined in Section 3.3: Operating conditions. 2. VDD_LV_BD: allowed 1.450 V - 1.500 V for 60 seconds cumulative time at the given temperature profile. Remaining time allowed 1.375 V - 1.450 V for 10 hours cumulative time at maximum TJ = 125 C. Remaining time as defined in Section 3.3: Operating conditions. 3. VDD_HV: allowed 5.5 V - 6.0 V for 60 seconds cumulative time at the given temperature profile, for 10 hours cumulative time with the device in reset at the given temperature profile. Remaining time as defined in Section 3.3: Operating conditions. 4. The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current condition on a pin, the voltage will be equal to the supply plus the voltage drop across the internal ESD diode from I/O pin to supply. The diode voltage varies greatly across process and temperature, but a value of 0.3 V can be used for nominal calculations. 5. Relative value can be exceeded if design measures are taken to ensure injection current limitation (parameter IINJ). DS11758 Rev 5 15/131 16 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx 6. This limitation applies to pads with digital input buffer enabled. If the digital input buffer is disabled, there are no maximum limits to the transition time. 7. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in Section 3.8.3: I/O pad current specifications. 8. 175C are allowed for limited time. Mission profile with passive lifetime temperature >150C have to be evaluated by ST to confirm that are granted by product qualification. 9. Solder profile per IPC/JEDEC J-STD-020D. 10. Moisture sensitivity per JDEC test method A112. 16/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx 3.3 Electrical characteristics Operating conditions Table 5 describes the operating conditions for the device, and for which all the specifications in the data sheet are valid, except where explicitly noted. The device operating conditions must not be exceeded or the functionality of the device is not guaranteed. Table 5. Operating conditions Value(1) Symbol C Parameter Conditions Unit Min Typ Max FSYS SR P Operating system clock frequency(2) -- -- -- 180 MHz TA_125 Grade(3) SR D Operating Ambient temperature -- -40 -- 125 C TJ_125 Grade(3) SR P Junction temperature under bias TA = 125 C -40 -- 150 C TA_105 Grade(3) SR D Ambient temperature under bias -- -40 -- 105 C TJ_105 Grade(3) SR D Operating Junction temperature TA = 105 C -40 -- 130 C VDD_LV SR P Core supply voltage(4) -- 1.14(5) 1.20 1.26(6) (7) V VDD_HV_IO_MAIN VDD_HV_IO_FLEX VDD_HV_FLA VDD_HV_OSC SR P IO supply voltage -- 3.0 -- 5.5 V VDD_HV_ADV SR P ADC supply voltage -- 3.0 -- 5.5 V VSS_HV_ADVVSS SR D ADC ground differential voltage -- -25 -- 25 mV VDD_HV_ADR_S SR P SAR ADC reference voltage -- 3.0 -- 5.5 V -- 2.0 -- 3.0 -- -- 25 C VDD_HV_ADR_SVDD_HV_ADV SR D SAR ADC reference differential voltage -- VSS_HV_ADR_S SR P SAR ADC ground reference voltage -- DS11758 Rev 5 VSS_HV_ADV mV V 17/131 19 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Table 5. Operating conditions (continued) Value(1) Symbol C Parameter Conditions Unit Min Typ Max VSS_HV_ADR_SVSS_HV_ADV SR D VSS_HV_ADR_S differential voltage -- -25 -- 25 mV VRAMP_HV SR D Slew rate on HV power supply -- -- -- 100 V/ms VIN SR P I/O input voltage range -- 0 -- 5.5 V IINJ1 SR T Injection current (per pin) without performance degradation(8) Digital pins and analog pins -3.0 -- 3.0 mA Dynamic Injection current (per pin) with performance degradation(10) Digital pins and analog pins -10 -- 10 mA (9) (10) IINJ2 SR D (11) 1. The ranges in this table are design targets and actual data may vary in the given range. 2. Maximum operating frequency is applicable to the cores and platform of the device. See the Clock Chapter in the Microcontroller Reference Manual for more information on the clock limitations for the various IP blocks on the device. 3. In order to evaluate the actual difference between ambient and junction temperatures in the application, refer to Section 4.4: Package thermal characteristics. 4. Core voltage as measured on device pin to guarantee published silicon performance. 5. In the range [1.14-1.08]V, the device functionality and specifications are granted and the device is expected to receive a flag by the internal LVD100 monitors to warn that the regulator (internal or external), providing the VDD_LV supply, exited the expected operating conditions. If the internal LVD100 monitors are disabled by the application, then an external voltage monitor with minimum threshold of VDD_LV(min) = 1.08 V measured at the device pad, has to be implemented. Please refer to Section 3.15.3: Voltage monitors for the list of available internal monitors and to the Reference Manual for the configurability of the monitors. 6. Core voltage can exceed 1.26 V with the limitations provided in Section 3.2: Absolute maximum ratings, provided that HVD134_C monitor reset is disabled. 7. 1.260 V - 1.290 V range allowed periodically for supply with sinusoidal shape and average supply value below or equal to 1.236 V at the given temperature profile. 8. Full device lifetime. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See Section 3.2: Absolute maximum ratings for maximum input current for reliability requirements. 9. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pins is above the supply rail, current will be injected through the clamp diode to the supply rails. For external RC network calculation, assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature. 10. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in Section 3.8.3: I/O pad current specifications. 11. Positive and negative Dynamic current injection pulses are allowed up to this limit. I/O and ADC specifications are not granted. See the dedicated chapters for the different specification limits. See the Absolute Maximum Ratings table for maximum input current for reliability requirements. Refer to the following pulses definitions: Pulse1 (ISO 7637-2:2011), Pulse 2a(ISO 7637-2:2011 5.6.2), Pulse 3a (ISO 7637-2:2011 5.6.3), Pulse 3b (ISO 7637-2:2011 5.6.3). 18/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Table 6. PRAM wait states configuration 3.3.1 PRAMC WS Clock Frequency (MHz) 1 < 180 0 < 120 Power domains and power up/down sequencing The following table shows the constraints and relationships for the different power domains. Supply1 (on rows) can exceed Supply2 (on columns), only if the cell at the given row and column is reporting `ok'. This limitation is valid during power-up and power-down phases, as well as during normal device operation. Table 7. Device supply relation during power-up/power-down sequence Supply2 VDD_HV_IO_MAIN VDD_LV VDD_HV_IO_ VDD_HV_FLA VDD_HV_ADV VDD_HV_ADR not allowed ok ok ok ok ok ok ok VDD_HV_OSC VDD_HV_IO_ Supply1 VDD_LV ok (1) ok VDD_HV_IO_MAIN VDD_HV_FLA VDD_HV_OSC ok ok VDD_HV_ADV ok ok not allowed VDD_HV_ADR ok ok not allowed ok not allowed 1. VDD_LV can be higher than VDD_HV supplies only during power-up/down transient ramps, in case of external LV regulator and if VDD_HV supply voltage level is lower than VDD_LV allowed max operating condition. During power-up, all functional terminals are maintained in a known state as described in the device pinout IO definition excel file. DS11758 Rev 5 19/131 19 Electrical characteristics 3.4 SPC584Gx, SPC58EGx, SPC58NGx Electrostatic discharge (ESD) The following table describes the ESD ratings of the device. Table 8. ESD ratings(1),(2) Parameter ESD for Human Body Model (HBM)(3) ESD for field induced Charged Device Model (CDM) (4) C Conditions Value Unit T All pins 2000 V T All pins 500 V T Corner Pins 750 V 1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2. Device failure is defined as: "If after exposure to ESD pulses, the device does not meet the device specification requirements, which includes the complete DC parametric and functional testing at room temperature and hot temperature. Maximum DC parametrics variation within 10% of maximum specification". 3. This parameter tested in conformity with ANSI/ESD STM5.1-2007 Electrostatic Discharge Sensitivity Testing. 4. This parameter tested in conformity with ANSI/ESD STM5.3-1990 Charged Device Model - Component Level. 20/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx 3.5 Electrical characteristics Electromagnetic compatibility characteristics EMC measurements at IC-level IEC standards are available from STMicroelectronics on request. DS11758 Rev 5 21/131 21 Electrical characteristics 3.6 SPC584Gx, SPC58EGx, SPC58NGx Temperature profile The device is qualified in accordance to AEC-Q100 Grade1 requirements, such as HTOL 1,000 h and HTDR 1,000 hrs, TJ = 150 C. 22/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx 3.7 Electrical characteristics Device consumption Table 9. Device consumption Value Symbol(1) IDD_LKG(2),(3) C CC Parameter Conditions Unit Min Typ Max C Leakage current on the VDD_LV supply D TJ = 40 C -- -- 26 TJ = 25 C -- -- 18 D TJ = 55 C -- -- 36 D TJ = 95 C -- -- 90 D TJ = 120 C -- -- 160 P TJ = 150 C -- -- 320 mA IDD_LV(3) CC P Dynamic current on the VDD_LV supply, very high consumption profile(4) -- -- -- 400 mA IDD_HV CC P Total current on the VDD_HV supply(4) fMAX -- -- 85 mA IDD_LV_GW CC T Dynamic current on the VDD_LV supply, gateway profile(5) -- -- -- 310 mA IDD_HV_GW CC T Dynamic current on the VDD_HV supply, gateway profile(5) -- -- -- 46 mA IDD_LV_BCM CC T Dynamic current on the VDD_LV supply, body profile(6) -- -- -- 280 mA IDD_HV_BCM CC T Dynamic current on the VDD_HV supply, body profile(6) -- -- -- 49 mA IDD_MAIN_CORE_AC CC T Main Core dynamic current(7) fMAX -- -- 50 mA IDD_CHKR_CORE_AC CC T Checker Core dynamic operating current fMAX -- -- 30 mA IDD_HSM_AC CC T HSM platform dynamic operating current(8) fMAX/2 -- -- 20 mA IDDHALT(9) CC T Dynamic current on the VDD_LV supply +Total current on the VDD_HV supply -- -- 110 180 mA IDDSTOP(10) CC T Dynamic current on the VDD_LV supply +Total current on the VDD_HV supply -- -- 21 40 mA DS11758 Rev 5 23/131 25 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Table 9. Device consumption (continued) Value Symbol(1) IDDSTBY8 C CC Max TJ = 25 C -- 145 380 TJ = 40 C -- -- 550 TJ = 55 C -- -- 820 D TJ = 120 C -- -- 4 P TJ = 150 C -- -- 8 TJ = 25 C -- 170 530 TJ = 40 C -- -- 790 TJ = 55 C -- -- 1.2 D TJ = 120 C -- -- 5.5 P TJ = 150 C -- -- 11 TJ = 25 C -- 200 680 A TJ = 40 C -- -- 1.0 mA TJ = 55 C -- -- 1.5 mA D TJ = 120 C -- -- 7 P TJ = 150 C -- -- 14 D D C D IDDSTBY256 CC Unit Typ D CC Conditions Min C IDDSTBY128 Parameter D C D Total standby mode current on VDD_LV and VDD_HV supply, 8 KB RAM(11) Total standby mode current on VDD_LV and VDD_HV supply, 128 KB RAM(11) Total standby mode current on VDD_LV and VDD_HV supply, 256 KB RAM(11) A mA A mA IDDSSWU1 CC D SSWU running over all STANDBY period with OPC/TU commands execution and keeping ADC off(12) TJ = 40 C -- 1.0 3.5 mA IDDSSWU2 CC D SSWU running over all STANDBY period with OPC/TU/ADC commands execution and keeping ADC on(13) TJ = 40 C -- 3.5 5.0 mA IDD_LV_BD CC P Buddy Device Consumption on VDD_LV supply(14) TJ = 150 C -- -- 500 mA IDD_HV_BD CC T Buddy Device Consumption on VDD_HV supply(14) -- -- -- 130 mA 1. The ranges in this table are design targets and actual data may vary in the given range. 2. The leakage considered is the sum of core logic and RAM memories. The contribution of analog modules is not considered, and they are computed in the dynamic IDD_LV and IDD_HV parameters. 3. IDD_LKG (leakage current) and IDD_LV (dynamic current) are reported as separate parameters, to give an indication of the consumption contributors. The tests used in validation, characterization and production are verifying that the total consumption (leakage+dynamic) is lower or equal to the sum of the maximum values provided (IDD_LKG+IDD_LV). The two parameters, measured separately, may exceed the maximum reported for each, depending on the operative conditions and the software profile used. 24/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics 4. Use case: 3 x e200Z4 @180 MHz with all locksteps on (main core + dma + irq), HSM @90 MHz, all IPs clock enabled, Flash access with prefetch disabled, Flash consumption includes parallel read and program/erase, 1xSARADC in continuous conversion, DMA continuously triggered by ADC conversion, 5xDSPI / 7xCAN / 12xLINFlex / FlexRay, 1xEMIOS running (5 channels in OPWMT mode), FIRC, SIRC, FXOSC, PLL0-1 running. The switching activity estimated for dynamic consumption does not include I/O toggling, which is highly dependent on the application. Details of the software configuration are available separately. The total device consumption is IDD_LV + IDD_HV + IDD_LKG for the selected temperature. 5. Gateway use case: Two cores running at 160 MHz, no lockstep, DMA, PLL, FLASH read only 25%, 8xCAN, 1xEthernet, HSM, 4xSARADC. 6. BCM use case: One Core running at 160 MHz, no lockstep, DMA, PLL, FLASH read only 25%, 2xCAN, HSM, 5xSARADC. 7. Dynamic consumption of one core, including the dedicated I/D-caches and I/D-MEMS contribution. 8. Dynamic consumption of the HSM module, including the dedicated memories, during the execution of Electronic Code Book crypto algorithm on 1 block of 16 byte of shared RAM. 9. Flash in Low Power. Sysclk at 160 MHz, PLL0_PHI at 160 MHz, XTAL at 40 MHz, FIRC 16 MHz ON, RCOSC1M off. MCAN: instances: 0, 1, 2, 3, 4, 5, 6, 7 ON (configured but no reception or transmission), Ethernet ON (configured but no reception or transmission), ADC ON (continuously converting). All others IPs clock-gated. 10. Sysclk = RC16 MHz, RC16 MHz ON, RC1 MHz ON, PLL OFF. All possible peripherals off and clock gated. Flash in power down mode. 11. STANDBY mode: device configured for minimum consumption, RC16 MHz off, RC1 MHz on. 12. SSWU1 mode adder: FIRC = ON, SSWU clocked at 8 MHz and running over all STANDBY period, ADC off. The total standby consumption can be obtained by adding this parameter to the IDDSTBY parameter for the selected memory size and temperature. 13. SSWU2 mode adder: FIRC = ON, SSWU clocked at 8 MHz and running over all STANDBY period, ADC on in continuous conversion. The total standby consumption can be obtained by adding this parameter to the IDDSTBY parameter for the selected memory size and temperature. 14. Worst case usage (data trace, data overlay, full Aurora utilization). If Aurora and JTAGM/LFAST not used, VDD_LV_BD current is reduced by ~20mA. DS11758 Rev 5 25/131 25 Electrical characteristics 3.8 SPC584Gx, SPC58EGx, SPC58NGx I/O pad specification The following table describes the different pad type configurations. Table 10. I/O pad specification descriptions Pad type Description Weak configuration Provides a good compromise between transition time and low electromagnetic emission. Medium configuration Strong configuration Provides transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission. Provides fast transition speed; used for fast interface. Very strong configuration Provides maximum speed and controlled symmetric behavior for rise and fall transition. Used for fast interface including Ethernet and FlexRay interfaces requiring fine control of rising/falling edge jitter. Differential configuration A few pads provide differential capability providing very fast interface together with good EMC performances. Input only pads Standby pads Note: These low input leakage pads are associated with the ADC channels. Some pads are active during Standby. Low Power Pads input buffer can only be configured in TTL mode. When the pads are in Standby mode, the Pad-Keeper feature is activated: if the pad status is high, the weak pull-up resistor is automatically enabled; if the pad status is low, the weak pull-down resistor is automatically enabled. Each I/O pin on the device supports specific drive configurations. See the signal description table in the device reference manual for the available drive configurations for each I/O pin. PMC_DIG_VSIO register has to be configured to select the voltage level (3.3 V or 5.0 V) for each IO segment. Logic level is configurable in running mode while it is TTL not-configurable in STANDBY for LP (low power) pads, so if a LP pad is used to wakeup from STANDBY, it should be configured as TTL also in running mode in order to prevent device wrong behavior in STANDBY. 3.8.1 I/O input DC characteristics The following table provides input DC electrical characteristics, as described in Figure 3. 26/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Figure 3. I/O input electrical characteristics VIN VDD VIH VHYS VIL VINTERNAL (SIUL register) Table 11. I/O input electrical characteristics Value Symbol C Parameter Conditions Unit Min Typ Max TTL Vihttl SR P Input high level TTL -- 2 -- VDD_HV_IO + 0.3 V Vilttl SR P Input low level TTL -- -0.3 -- 0.8 V Vhysttl CC C Input hysteresis TTL -- 0.3 -- -- V CMOS Vihcmos SR P Input high level CMOS -- 0.65 * VDD -- VDD_HV_IO + 0.3 V Vilcmos SR P Input low level CMOS -- -0.3 -- 0.35 * VDD V Vhyscmos CC C Input hysteresis CMOS -- 0.10 * VDD -- -- V COMMON ILKG CC P Pad input leakage INPUT-ONLY pads TJ = 150 C -- -- 200 nA ILKG CC P Pad input leakage MEDIUM pads TJ = 150 C -- -- 360 nA ILKG CC P Pad input leakage STRONG pads TJ = 150 C -- -- 1,000 nA DS11758 Rev 5 27/131 36 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Table 11. I/O input electrical characteristics (continued) Value Symbol C Parameter Conditions Unit Min Typ Max ILKG CC P Pad input leakage VERY STRONG pads, TJ = 150 C -- -- 1,000 nA CP1 CC D Pad capacitance -- -- -- 10 pF Vdrift CC D Input Vil/Vih temperature drift In a 1 ms period, with a temperature variation <30 C -- -- 100 mV WFI SR C Wakeup input filtered pulse(1) -- -- -- 20 ns WNFI SR C Wakeup input not filtered pulse(1) -- 400 -- -- ns 1. In the range from WFI (max) to WNFI (min), pulses can be filtered or not filtered, according to operating temperature and voltage. Refer to the device pinout IO definition excel file for the list of pins supporting the wakeup filter feature. Table 12. I/O pull-up/pull-down electrical characteristics Value Symbol IWPU C CC T P Parameter Conditions Unit Min Typ Max Weak pull-up current absolute value VIN = 1.1 V(1) -- -- 130 VIN = 0.69 * VDD_HV_IO(2) 15 -- -- A RWPU CC D Weak Pull-up resistance VDD_HV_IO = 5.0 V 10% 33 -- 93 K RWPU CC D Weak Pull-up resistance VDD_HV_IO = 3.3 V 10% 19 -- 62 K IWPD CC T Weak pulldown current absolute value VIN = 0.69 * VDD_HV_IO(1) -- -- 130 A VIN = 0.9 V(2) 15 -- -- P RWPD CC D Weak Pulldown resistance VDD_HV_IO = 5.0 V 10% 29 -- 60 K RWPD CC D Weak Pulldown resistance VDD_HV_IO = 3.3 V 10% 19 -- 60 K 1. Maximum current when forcing a change in the pin level opposite to the pull configuration. 2. Minimum current when keeping the same pin level state than the pull configuration. Note: 28/131 When the device enters into standby mode, the LP pads have the input buffer switched-on. As a consequence, if the pad input voltage VIN is VSS<VIN<VDD_HV, an additional consumption can be measured in the VDD_HV domain. The highest consumption can be DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics seen around mid-range (VIN ~=VDD_HV/2), 2-3mA depending on process, voltage and temperature. This situation may occur if the PAD is used as a ADC input channel, and VSS<VIN<VDD_HV. The applications should ensure that LP pads are always set to VDD_HV or VSS, to avoid the extra consumption. Please refer to the device pinout IO definition excel file to identify the low-power pads which also have an ADC function. 3.8.2 I/O output DC characteristics Figure 4 provides description of output DC electrical characteristics. Figure 4. I/O output DC electrical characteristics definition VINTERNAL (SIUL register) VHYS tSKEW20-80 Vout 90% 80% 20% 10% tR20-80 tF20-80 tR10-90 tF10-90 tTR(max) = MAX(tR10-90; tF10-90) tTR20-80(max) = MAX(tR20-80; tF20-80) tTR(min) = MIN(tR10-90; tF10-90) tTR20-80(min) = MIN(tR20-80; tF20-80) tSKEW20-80 = |tR20-80-tF20-80| tSKEW10-90 = |tR10-90-tF10-90| The following tables provide DC characteristics for bidirectional pads: Note: Table 13 provides output driver characteristics for I/O pads when in WEAK/SLOW configuration. Table 14 provides output driver characteristics for I/O pads when in MEDIUM configuration. Table 15 provides output driver characteristics for I/O pads when in STRONG/FAST configuration. Table 16 provides output driver characteristics for I/O pads when in VERY STRONG/VERY FAST configuration. 10%/90% is the default condition for any parameter if not explicitly mentioned differently. DS11758 Rev 5 29/131 36 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Table 13. WEAK/SLOW I/O output characteristics Value Symbol C Parameter Conditions Unit Min Typ Max Vol_W CC D Output low Iol = 0.5 mA voltage for Weak VDD = 5.0 V 10% type PADs VDD = 3.3 V 10% -- -- 0.1*VDD V Voh_W CC D Output high Ioh = 0.5 mA voltage for Weak VDD = 5.0 V 10% type PADs VDD = 3.3 V 10% 0.9*VDD -- -- V R_W CC P Output VDD = 5.0 V 10% impedance for VDD = 3.3 V 10% Weak type PADs 380 -- 1040 250 -- 700 Maximum output CL = 25 pF frequency for VDD = 5.0 V 10% Weak type PADs V = 3.3 V 10% DD -- -- 2 MHz CL = 50 pF VDD = 5.0 V 10% VDD = 3.3 V 10 % -- -- 1 MHz Transition time output pin weak configuration, 10%-90% CL = 25 pF VDD = 5.0 V + 10% VDD = 3.3 V + 10% 25 -- 120 ns CL = 50 pF VDD = 5.0 V 10 % VDD = 3.3 V 10 % 50 -- 240 ns Fmax_W tTR_W CC CC T T |tSKEW_W| CC T Difference between rise and fall time, 90%-10% -- -- -- 25 % IDCMAX_W CC D Maximum DC current VDD = 5.0 V 10% VDD = 3.3 V 10% -- -- 0.5 mA Table 14. MEDIUM I/O output characteristics Value Symbol C Parameter Conditions Unit Min Typ Max Vol_M CC D Output low voltage for Medium type PADs Iol = 2.0 mA VDD =5.0 V 10 % VDD =3.3 V 10 % -- -- 0.1*VDD V Voh_M CC D Output high voltage for Medium type PADs Ioh=2.0 mA VDD = 5.0 V 10% VDD = 3.3 V 10% 0.9*VDD -- -- V 30/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Table 14. MEDIUM I/O output characteristics (continued) Value Symbol R_M Fmax_M tTR_M C CC CC CC P T T Parameter Conditions Unit Min Typ Max VDD = 5.0 V 10% 90 -- 260 VDD = 3.3 V 10% 60 -- 170 Maximum output CL = 25 pF frequency for VDD = 5.0 V 10% Medium type VDD = 3.3 V 10% PADs CL = 50 pF VDD = 5.0 V 10 % VDD = 3.3 V 10 % -- -- 12 MHz -- -- 6 MHz Output impedance for Medium type PADs Transition time output pin MEDIUM configuration, 10%-90% CL = 25 pF VDD = 5.0 V 10% VDD = 3.3 V 10% 8 -- 30 ns CL = 50 pF VDD = 5.0 V 10% VDD = 3.3 V 10% 12 -- 60 ns |tSKEW_M| CC T Difference between rise and fall time, 90%-10% -- -- -- 25 % IDCMAX_M CC D Maximum DC current VDD = 5.0 V 10% VDD = 3.3 V 10% -- -- 2 mA Table 15. STRONG/FAST I/O output characteristics Value Symbol Vol_S Voh_S R_S C CC CC CC D D P Parameter Conditions Unit Min Typ Max Output low voltage for Strong type PADs Iol = 8.0 mA VDD = 5.0 V 10% -- -- 0.1*VDD V Iol = 5.5 mA VDD =3 .3 V 10% -- -- 0.15*VDD V Output high voltage for Strong type PADs Ioh = 8.0 mA VDD = 5.0 V 10% 0.9*VDD -- -- V Ioh = 5.5 mA VDD = 3.3 V 10% 0.85*VDD -- -- V Output impedance for Strong type PADs VDD = 5.0 V 10% 20 -- 65 VDD = 3.3 V 10% 28 -- 90 DS11758 Rev 5 31/131 36 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Table 15. STRONG/FAST I/O output characteristics (continued) Value Symbol Fmax_S tTR_S IDCMAX_S |tSKEW_S| C CC CC CC CC T T D T Parameter Maximum output frequency for Strong type PADs Transition time output pin STRONG configuration, 10%-90% Maximum DC current Difference between rise and fall time, 90%-10% Conditions Unit Min Typ Max CL = 25 pF VDD=5.0 V 10% -- -- 50 MHz CL = 50 pF VDD=5.0 V 10% -- -- 25 MHz CL = 25 pF VDD = 3.3 V 10% -- -- 25 MHz CL = 50 pF VDD = 3.3 V 10% -- -- 12.5 MHz CL = 25 pF VDD = 5.0 V 10% 3 -- 10 ns CL = 50 pF VDD = 5.0 V 10% 5 -- 16 CL = 25 pF VDD = 3.3 V 10% 1.5 -- 15 CL = 50 pF VDD = 3.3 V 10% 2.5 -- 26 VDD = 5 V 10% -- -- 8 VDD = 3.3 V 10% -- -- 5.5 -- -- -- 25 mA % Table 16. VERY STRONG/VERY FAST I/O output characteristics Value Symbol Vol_V Voh_V R_V 32/131 C CC CC CC D D P Parameter Conditions Unit Min Typ Max Output low voltage for Very Strong type PADs Iol = 9.0 mA VDD =5.0 V 10% -- -- 0.1*VDD V Iol = 9.0 mA VDD =3.3 V 10% -- -- 0.15*VDD V Output high voltage for Very Strong type PADs Ioh = 9.0 mA VDD = 5.0 V 10% 0.9*VDD -- -- V Ioh = 9.0 mA VDD = 3.3 V 10% 0.85*VDD -- -- V Output impedance for Very Strong type PADs VDD = 5.0 V 10% 20 -- 60 VDD = 3.3 V 10% 18 -- 50 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Table 16. VERY STRONG/VERY FAST I/O output characteristics (continued) Value Symbol Fmax_V tTR_V tTR20-80_V C CC CC CC T T T Parameter Conditions Unit Min Typ Max Maximum output CL = 25 pF frequency for VDD = 5.0 V 10% Very Strong type CL = 50 pF PADs VDD = 5.0 V 10% -- -- 50 MHz -- -- 25 MHz CL = 25 pF VDD = 3.3 V 10% -- -- 50 MHz CL = 50 pF VDD = 3.3 V 10% -- -- 25 MHz CL = 25 pF VDD = 5.0 V 10% 1 -- 6 ns CL = 50 pF VDD = 5.0 V 10% 3 -- 12 CL = 25 pF VDD = 3.3 V 10% 1.5 -- 6 CL = 50 pF VDD = 3.3 V 10% 3 -- 11 CL = 25 pF VDD = 5.0 V 10% 0.8 -- 4.5 CL = 15 pF VDD = 3.3 V 10% 1 -- 4.5 10-90% threshold transition time output pin VERY STRONG configuration 20-80% threshold transition time output pin VERY STRONG configuration (Flexray Standard) ns tTRTTL_V CC T TTL threshold transition time for output pin in VERY STRONG configuration (Ethernet standard) CL = 25 pF VDD = 3.3 V 10% 0.88 -- 5 ns tTR20-80_V CC T Sum of transition time 20-80% output pin VERY STRONG configuration CL = 25 pF VDD = 5.0 V 10% -- -- 9 ns CL = 15 pF VDD = 3.3 V 10% -- -- 9 |tSKEW_V| CC T Difference between rise and fall delay CL = 25 pF VDD = 5.0 V 10% 0 -- 1.2 ns IDCMAX_V CC D Maximum DC current VDD = 5.0 V10% VDD = 3.3 V 10% -- -- 9 mA DS11758 Rev 5 33/131 36 Electrical characteristics 3.8.3 SPC584Gx, SPC58EGx, SPC58NGx I/O pad current specifications The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as described in the device pinout IO definition excel file. Table 17 provides I/O consumption figures. In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IRMSSEG maximum value. In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain below the IDYNSEG maximum value. Pad mapping on each segment can be optimized using the pad usage information provided on the I/O Signal Description table. Table 17. I/O consumption Value Symbol(1) C Parameter Conditions Unit Min Typ Max Average consumption(2) IRMSSEG SR D Sum of all the DC I/O current within a supply segment -- -- -- 80 mA IRMS_W CC D RMS I/O current for WEAK configuration CL = 25 pF, 2 MHz, VDD = 5.0 V 10 % -- -- 1.1 mA CL = 50 pF, 1 MHz, VDD = 5.0 V 10 % -- -- 1.1 CL = 25 pF, 2 MHz, VDD = 3.3 V 10 % -- -- 1.0 CL = 25 pF, 1 MHz, VDD = 3.3 V 10% -- -- 1.0 CL = 25 pF, 12 MHz, VDD = 5.0 V 10% -- -- 5.5 CL = 50 pF, 6 MHz, VDD = 5.0 V 10% -- -- 5.5 CL = 25 pF, 12 MHz, VDD = 3.3 V 10% -- -- 4.2 CL = 25 pF, 6 MHz, VDD = 3.3 V 10% -- -- 4.2 CL = 25 pF, 50 MHz, VDD = 5.0 V 10% -- -- 21 CL = 50 pF, 25 MHz, VDD = 5.0 V 10% -- -- 21 CL = 25 pF, 25 MHz, VDD = 3.3 V 10% -- -- 10 CL = 25 pF, 12.5 MHz, VDD = 3.3 V 10% -- -- 10 IRMS_M IRMS_S 34/131 CC CC D D RMS I/O current for MEDIUM configuration RMS I/O current for STRONG configuration DS11758 Rev 5 mA mA SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Table 17. I/O consumption Symbol(1) (continued) IRMS_V CC Value C D Parameter Conditions RMS I/O current for VERY STRONG configuration Unit Min Typ Max CL = 25 pF, 50 MHz, VDD = 5.0 V 10% -- -- 23 CL = 50 pF, 25 MHz, VDD = 5.0 V 10% -- -- 23 CL = 25 pF, 50 MHz, VDD = 3.3 V 10% -- -- 16 CL = 25 pF, 25 MHz, VDD = 3.3 V 10% -- -- 16 mA Dynamic consumption(3) IDYN_SEG IDYN_W IDYN_M IDYN_S SR CC CC CC D D D D Sum of all the dynamic and DC I/O current within a supply segment VDD = 5.0 V 10% -- -- 195 VDD = 3.3 V 10% -- -- 150 Dynamic I/O current for WEAK configuration CL = 25 pF, VDD = 5.0 V 10% -- -- 16.7 CL = 50 pF, VDD = 5.0 V 10% -- -- 16.8 CL = 25 pF, VDD = 3.3 V 10% -- -- 12.9 CL = 50 pF, VDD = 3.3 V 10% -- -- 12.9 CL = 25 pF, VDD = 5.0 V 10% -- -- 18.2 CL = 50 pF, VDD = 5.0 V 10% -- -- 18.4 CL = 25 pF, VDD = 3.3 V 10% -- -- 14.3 CL = 50 pF, VDD = 3.3 V 10% -- -- 16.4 CL = 25 pF, VDD = 5.0 V 10% -- -- 57 CL = 50 pF, VDD = 5.0 V 10% -- -- 63.5 CL = 25 pF, VDD = 3.3 V 10% -- -- 31 CL = 50 pF, VDD = 3.3 V 10% -- -- 33.5 Dynamic I/O current for MEDIUM configuration Dynamic I/O current for STRONG configuration DS11758 Rev 5 mA mA mA mA 35/131 36 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Table 17. I/O consumption Symbol(1) (continued) IDYN_V CC Value C D Parameter Conditions Dynamic I/O current for VERY STRONG configuration Unit Min Typ Max CL = 25 pF, VDD = 5.0 V 10% -- -- 62 CL = 50 pF, VDD = 5.0 V 10% -- -- 70 CL = 25 pF, VDD = 3.3 V 10% -- -- 52 CL = 50 pF, VDD = 3.3 V 10% -- -- 55 1. I/O current consumption specifications for the 4.5 V VDD_HV_IO 5.5 V range are valid for VSIO_[VSIO_xx] = 1, and VSIO[VSIO_xx] = 0 for 3.0 V VDD_HV_IO 3.6 V. 2. Average consumption in one pad toggling cycle. 3. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition. When possible (timed output) it is recommended to delay transition between pads by few cycles to reduce noise and consumption. 36/131 DS11758 Rev 5 mA SPC584Gx, SPC58EGx, SPC58NGx 3.9 Electrical characteristics Reset pad (PORST, ESR0) electrical characteristics The device implements dedicated bidirectional reset pins as below specified. PORST pin does not require active control. It is possible to implement an external pull-up to ensure correct reset exit sequence. Recommended value is 4.7 K. Figure 5. Startup Reset requirements VDD VDDMIN VDD_POR PORST VIH VIL device start-up phase PORST undriven device reset PORST driven low device reset by by internal power-on reset forced by external circuitry internal power-on reset Figure 6 describes device behavior depending on supply signal on PORST: 1. PORST low pulse has too low amplitude: it is filtered by input buffer hysteresis. Device remains in current state. 2. PORST low pulse has too short duration: it is filtered by low pass filter. Device remains in current state. 3. PORST low pulse is generating a reset: a) PORST low but initially filtered during at least WFRST. Device remains initially in current state. b) PORST potentially filtered until WNFRST. Device state is unknown. It may either be reset or remains in current state depending on extra condition (temperature, voltage, device). c) PORST asserted for longer than WNFRST. Device is under reset. DS11758 Rev 5 37/131 39 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Figure 6. Noise filtering on reset signal VPORST, VESR0 VDD VIH VHYS VIL internal reset filtered by hysteresis filtered by lowpass filter WFRST 1 2 filtered by lowpass filter WFRST unknown reset state device under hardware reset WNFRST 3a 3b 3c Table 18. Reset PAD electrical characteristics Value Symbol C Parameter Conditions Unit Min Typ Max VIHRES SR P Input high level TTL VDD_HV = 5.0 V 10% VDD_HV = 3.3 V 10% 2 -- VDD_HV_IO +0.3 V VILRES SR P Input low level TTL VDD_HV = 5.0 V 10% -0.3 -- 0.8 V VDD_HV = 3.3 V 10% -0.3 -- 0.6 Input hysteresis TTL VDD_HV = 5.0 V 10% 0.3 -- -- VDD_HV = 3.3 V 10% 0.2 -- -- Minimum supply for strong pulldown activation VDD_HV = 5.0 V 10% -- -- 1.6 VDD_HV = 3.3 V 10% -- -- 1.05 VHYSRES VDD_POR 38/131 CC CC C D DS11758 Rev 5 V V SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Table 18. Reset PAD electrical characteristics (continued) Value Symbol IOL_R IWPU C CC CC WFRST CC CC CC Unit Typ Max 12 -- -- 8 -- -- VIN = 1.1 V VDD_HV = 5.0 V 10% -- -- 130 VIN = 1.1 V VDD_HV = 3.3 V 10% -- -- 70 P VIN = 0.69 * VDD_HV_IO(3) VDD_HV = 5.0 V 10% 15 -- -- P VIN = 0.69 * VDD_HV_IO VDD_HV = 3.3 V 10% 15 -- -- VIN = 0.69 * VDD_HV_IO(2) VDD_HV = 5.0 V 10% -- -- 130 P VIN = 0.69 * VDD_HV_IO(2) VDD_HV = 3.3 V 10% -- -- 80 P VIN = 0.9 V VDD_HV = 5.0 V 10% 15 -- -- P VIN = 0.9 V VDD_HVDD_HV = 3.3 V 10% 15 -- -- Input filtered pulse VDD_HV = 5.0 V 10% -- -- 500 VDD_HV = 3.3 V 10% -- -- 600 Input not filtered pulse VDD_HV = 5.0 V 10% 2000 -- -- VDD_HV = 3.3 V 10% 3000 -- -- P P P P P WNFRST Conditions Min P IWPD Parameter P P Strong pull-down VDD_HV = 5.0 V 10% current (1) VDD_HV = 3.3 V 10% Weak pull-up current absolute value Weak pull-down current absolute value (2) mA A A ns ns 1. Iol_r applies to PORST: Strong Pull-down is active on PHASE0 for PORST. A dedicated Reset Pad for ESR0, with the specifications reported in this table, is implemented. Refer to the device pinout IO definition excel file for details regarding pin usage. 2. Maximum current when forcing a change in the pin level opposite to the pull configuration. 3. Minimum current when keeping the same pin level state than the pull configuration. Table 19. Reset Pad state during power-up and reset PAD POWER-UP State RESET state DEFAULT state(1) STANDBY state PORST Strong pull-down Weak pull-down Weak pull-down Weak pull-up ESR0 Strong pull-down Strong pull-down Weak pull-up Weak pull-up 1. Before SW Configuration. Please refer to the Device Reference Manual, Reset Generation Module (MC_RGM) Functional Description chapter for the details of the power-up phases. DS11758 Rev 5 39/131 39 Electrical characteristics 3.10 SPC584Gx, SPC58EGx, SPC58NGx PLLs Two phase-locked loop (PLL) modules are implemented to generate system and auxiliary clocks on the device. Figure 7 depicts the integration of the two PLLs. Please, refer to device Reference Manual for more detailed schematic. Figure 7. PLLs integration IRCOSC PLL0_PHI PLL0 PLL0_PHI1 XOSC PLL1_PHI PLL1 3.10.1 PLL0 Table 20. PLL0 electrical characteristics Value Symbol C Parameter Conditions Unit Min Typ Max -- 8 -- 44 MHz fPLL0IN SR -- PLL0 input clock(1) PLL0IN SR -- PLL0 input clock duty cycle(1) -- 40 -- 60 % fINFIN SR PLL0 PFD (Phase -- Frequency Detector) input clock frequency -- 8 -- 20 MHz fPLL0VCO CC P -- 600 -- 1400 MHz -- FSYS(2) MHz MHz CC fPLL0PHI0 D PLL0 VCO frequency PLL0 output frequency -- 4.762 fPLL0PHI1 CC D PLL0 output clock PHI1 -- 20 -- 175(3) tPLL0LOCK CC P PLL0 lock time -- -- -- 100 s D PLL0_PHI0 single period jitter fPLL0IN = 20 MHz (resonator) fPLL0PHI0 = 400 MHz, 6-sigma pk-pk -- -- 200 ps |PLL0PHI0SPJ 40/131 |(4) CC DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Table 20. PLL0 electrical characteristics (continued) Value Symbol |PLL0PHI1SPJ| PLL0LTJ IPLL0 (4) (4) C CC CC CC T T T Parameter Conditions PLL0_PHI1 single period jitter fPLL0IN = 20 MHz (resonator) PLL0 output long term jitter(5) fPLL0IN = 20 MHz (resonator), VCO frequency = 800 MHz PLL0 consumption Unit Min Typ Max fPLL0PHI1 = 40 MHz, 6-sigma pk-pk -- -- 300(5) ps 10 periods accumulated jitter (80 MHz equivalent frequency), 6-sigma pk-pk -- -- 250 ps 16 periods accumulated jitter (50 MHz equivalent frequency), 6-sigma pk-pk -- -- 300 ps long term jitter (< 1 MHz equivalent frequency), 6-sigma pk-pk) -- -- 500 ps FINE LOCK state -- -- 6 mA 1. PLL0IN clock retrieved directly from either internal RCOSC or external FXOSC clock. Input characteristics are granted when using internal RCOSC or external oscillator is used in functional mode. 2. Please refer to for the maximum operating frequency. 3. If the PLL0_PHI1 is used as an input for PLL1, then the PLL0_PHI1 frequency shall obey the maximum input frequency limit set for PLL1 (87.5 MHz, according to Table 21). 4. Jitter values reported in this table refer to the internal jitter, and do not include the contribution of the divider and the path to the output CLKOUT pin. 5. VDD_LV noise due to application in the range VDD_LV = 1.20 V5%, with frequency below PLL bandwidth (40 kHz) will be filtered. DS11758 Rev 5 41/131 42 Electrical characteristics 3.10.2 SPC584Gx, SPC58EGx, SPC58NGx PLL1 PLL1 is a frequency modulated PLL with Spread Spectrum Clock Generation (SSCG) support. Table 21. PLL1 electrical characteristics Value Symbol C Parameter Conditions Unit Min Typ Max fPLL1IN SR -- PLL1 input clock(1) -- 37.5 -- 87.5 MHz PLL1IN SR -- PLL1 input clock duty cycle(1) -- 35 -- 65 % fINFIN SR -- PLL1 PFD (Phase Frequency Detector) input clock frequency -- 37.5 87.5 MHz fPLL1VCO CC P PLL1 VCO frequency -- 600 -- 1400 MHz MHz fPLL1PHI0 CC D PLL1 output clock PHI0 -- 4.762 -- FSYS(2) tPLL1LOCK CC P PLL1 lock time -- -- -- 50 s fPLL1MOD CC T PLL1 modulation frequency -- -- -- 250 kHz |PLL1MOD| CC T PLL1 modulation depth (when enabled) Center spread(3) 0.25 -- 2 % Down spread 0.5 -- 4 % |PLL1PHI0SPJ| (4) CC T PLL1_PHI0 single period peak to peak jitter fPLL1PHI0 = 200 MHz, 6-sigma -- -- 500(5) ps IPLL1 CC T PLL1 consumption FINE LOCK state -- -- 5 mA 1. PLL1IN clock retrieved directly from either internal PLL0 or external FXOSC clock. Input characteristics are granted when using internal PPL0 or external oscillator is used in functional mode. 2. Please refer to Section 3.3: Operating conditions for the maximum operating frequency. 3. The device maximum operating frequency FSYS (max) includes the frequency modulation. If center modulation is selected, the FSYS must be below the maximum by MD (Modulation Depth Percentage), such that FSYS(max)=FSYS(1+MD%). Please refer to the Reference Manual for the PLL programming details. 4. Jitter values reported in this table refer to the internal jitter, and do not include the contribution of the divider and the path to the output CLKOUT pin. 5. 1.25 V5%, application noise below 40 kHz at VDD_LV pin - no frequency modulation. 42/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics 3.11 Oscillators 3.11.1 Crystal oscillator 40 MHz Table 22. External 40 MHz oscillator electrical specifications Value Symbol fXTAL C CC D Parameter Conditions Max 4(2) 8 >8 20 >20 40 TJ = 150 C -- 5 ms Crystal Frequency Range(1) -- (3),(4) Unit Min MHz tcst CC T Crystal start-up time trec CC D Crystal recovery time(5) -- -- 0.5 ms VIHEXT CC D EXTAL input high voltage(6) (External Reference) VREF = 0.29 * VDD_HV_IO_JTAG VREF + 0.75 -- V VILEXT CC D EXTAL input low voltage(6) (External Reference) VREF = 0.29 * VDD_HV_IO_JTAG -- VREF 0.75 V CS_EXTAL CC D Total on-chip stray capacitance on EXTAL pin(7) -- 3 7 pF CS_XTAL CC D Total on-chip stray capacitance on XTAL pin(7) -- 3 7 pF gm CC P Oscillator Transconductance fXTAL = 4 - 8 MHz freq_sel[2:0] = 000 3.9 13.6 mA/V D fXTAL = 5 - 10 MHz freq_sel[2:0] = 001 5 17.5 D fXTAL = 10 - 15 MHz freq_sel[2:0] = 010 8.6 29.3 P fXTAL = 15 - 20 MHz freq_sel[2:0] = 011 14.4 48 D fXTAL = 20 - 25 MHz freq_sel[2:0] = 100 21.2 69 D fXTAL = 25 - 30 MHz freq_sel[2:0] = 101 27 86 D fXTAL = 30 - 35 MHz freq_sel[2:0] = 110 33.5 115 P fXTAL = 35 - 40 MHz freq_sel[2:0] = 111 33.5 115 0.5 1.8 VEXTAL CC D Oscillation Amplitude on the EXTAL pin after startup(8) TJ = -40 C to 150 C DS11758 Rev 5 V 43/131 46 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Table 22. External 40 MHz oscillator electrical specifications (continued) Value Symbol VHYS C CC IXTAL CC D D Parameter Conditions Comparator Hysteresis (8),(9) XTAL current Unit Min Max TJ = -40 C to 150 C 0.1 1.0 V TJ = -40 C to 150 C -- 14 mA 1. The range is selectable by UTEST miscellaneous DCF client XOSC_FREQ_SEL. 2. The XTAL frequency, if used to feed the PPL0 (or PLL1), shall obey the minimum input frequency limit set for PLL0 (or PLL1). 3. This value is determined by the crystal manufacturer and board design, and it can potentially be higher than the maximum provided. 4. Proper PC board layout procedures must be followed to achieve specifications. 5. Crystal recovery time is the time for the oscillator to settle to the correct frequency after adjustment of the integrated load capacitor value. 6. Applies to an external clock input and not to crystal mode. 7. See crystal manufacturer's specification for recommended load capacitor (CL) values.The external oscillator requires external load capacitors when operating from 8 MHz to 16 MHz. Account for on-chip stray capacitance (CS_EXTAL/CS_XTAL) and PCB capacitance when selecting a load capacitor value. When operating at 20 MHz/40 MHz, the integrated load capacitor value is selected via S/W to match the crystal manufacturer's specification, while accounting for on-chip and PCB capacitance. 8. Amplitude on the EXTAL pin after startup is determined by the ALC block, that is the Automatic Level Control Circuit. The function of the ALC is to provide high drive current during oscillator startup, but reduce current after oscillation in order to reduce power, distortion, and RFI, and to avoid over driving the crystal. The operating point of the ALC is dependent on the crystal value and loading conditions. 9. IXTAL is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. This is the maximum current during startup of the oscillator. 3.11.2 Crystal Oscillator 32 kHz Table 23. 32 kHz External Slow Oscillator electrical specifications Value Symbol C Parameter Conditions Unit Min Typ Max fsxosc SR T Slow external crystal oscillator frequency -- -- 32768 -- Hz gmsxosc CC P Slow external crystal oscillator transconductance -- 9.5 -- 32 A/V Vsxosc CC T Oscillation Amplitude -- 0.5 -- 1.7 V Isxoosc CC D Oscillator consumption -- -- -- 9 A Tsxosc CC T Start up time -- -- -- 2 s 44/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx 3.11.3 Electrical characteristics RC oscillator 16 MHz Table 24. Internal RC oscillator electrical specifications Value Symbol C Parameter Conditions Unit Min Typ Max fTarget CC D IRC target frequency -- -- 16 -- MHz fvar_noT CC P IRC frequency variation without temperature compensation T < 150 C -5 -- 5 % fvar_T CC T IRC frequency variation with temperature compensation T < 150 C -3 -- 3 % T IRC software trimming accuracy Trimming temperature -0.5 +0.3 0.5 % fvar_SW Tstart_noT CC T Startup time to reach within fvar_noT Factory trimming already applied -- -- 5 s Tstart_T CC T Startup time to reach within fvar_T Factory trimming already applied -- -- 120 s IFIRC CC T Current consumption on HV power supply(1) After Tstart_T -- -- 600 A 1. The consumption reported considers the sum of the RC oscillator 16 MHz IP, and the core logic clocked by the IP during Standby mode. DS11758 Rev 5 45/131 46 Electrical characteristics 3.11.4 SPC584Gx, SPC58EGx, SPC58NGx Low power RC oscillator Table 25. 1024 kHz internal RC oscillator electrical characteristics Value Symbol C Parameter Conditions Unit Min Typ Max Fsirc CC T Slow Internal RC oscillator frequency -- -- 1024 -- kHz fvar_T CC P Frequency variation across temperature -40 C < T < 150 C -9 -- +9 % fvar_V CC P Frequency variation across voltage -40 C < T < 150 C -5 -- +5 % Isirc CC T Slow Internal RC oscillator current T = 55 C -- -- 6 A Tsirc CC T Start up time, after switching ON the internal regulator. -- -- -- 12 S 46/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx 3.12 ADC system 3.12.1 ADC input description Electrical characteristics Figure 8 shows the input equivalent circuit for SARn and SARB channels. Figure 8. Input equivalent circuit (Fast SARn and SARB channels) INTERNAL CIRCUIT SCHEME VDD CP1 RSW1: Channel Selection Sampling RSW1 RAD CP2 Channel Selection Switch Impedance RAD: Sampling Switch Impedance CP : Pin Capacitance (two contributions, CP1 and CP2) CS : Sampling Capacitance CS RCMSW Common mode switch RCMRL Common mode resistive ladder RCMSW: Common mode switch VCM RCMRL: Common mode resistive ladder VCM : Common mode voltage (~0.5 VDD) The above figure can be used as approximation circuitry for external filtering definition. Table 26. ADC pin specification(1) Value Symbol R20K C CC Parameter Conditions D Internal voltage reference source impedance. -- Unit Min Max 16 30 K ILKG CC -- Input leakage current, two ADC channels on input-only pin. See IO chapter Table 11: I/O input electrical characteristics, parameter ILKG IINJ1,2 SR -- Injection current on analog input preserving functionality at full or degraded performances. See Operating Conditions chapter Table 5: Operating conditions, IINJ1 and IINJ2 parameter. CHV_ADC SR D VDD_HV_ADV external capacitance. See Power Management chapter Table 34: External components integration, CADC parameter. CP1 CC D Pad capacitance CP2 CC D Internal routing capacitance See IO chapter Table 11: I/O input electrical characteristics, parameter CP1 SARB channels -- 2 SARn 10bit channels -- 0.5 SARn 12bit channels -- 1 DS11758 Rev 5 pF 47/131 54 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Table 26. ADC pin specification(1) (continued) Value Symbol CS C CC RSWn CC CC RAD Parameter Conditions -- 5 SARn 10bit -- 2 SARB channels 0 1.8 SARn 10bit channels 0 0.8 SARn 12bit channels 0 1.8 SARn 12bit -- 0.8 SARn 10bit -- 3.2 sum of the two resistances -- 9 VDD_HV_IO = 5.0 V 10% -- 300 VDD_HV_IO = 3.3 V 10% -- 500 -1.5 +1.5 % D ADC input analog switches resistance D Common mode switch resistance RCMRL CC D Common mode resistive ladder RSAFEPD(2) CC D Discharge resistance for ADC input-only pins (strong pull-down for safety) CC SARn 12bit D Analog switches resistance CC ABGAP Max D SAR ADC sampling capacitance RCMSW Unit Min pF k k k k D ADC digital bandgap accuracy 1. All specifications in this table valid for the full input voltage range for the analog inputs. 2. It enables discharge of up to 100 nF from 5 V every 300 ms. Please refer to the device pinout IO definition excel file for the pads supporting it. 3.12.2 SAR ADC 12 bit electrical specification The SARn ADCs are 12-bit Successive Approximation Register analog-to-digital converters with full capacitive DAC. The SARn architecture allows input channel multiplexing. Table 27. SARn ADC electrical specification(1) Value Symbol fADCK C SR P Parameter Conditions Clock frequency Standard frequency mode T High frequency mode Unit Min Max 7.5 13.33 >13.33 16.0 MHz tADCINIT SR -- ADC initialization time -- 1.5 -- s tADCBIASINIT SR -- ADC BIAS initialization time -- 5 -- s tADCPRECH SR T ADC decharge time Fast SAR 1/fADCK -- s Slow SAR (SARDAC_B) 2/fADCK -- 0 0.25 V 16 30 K VPRECH SR D Decharge voltage precision R20K CC D Internal voltage reference source impedance 48/131 TJ < 150 C -- DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Table 27. SARn ADC electrical specification(1) (continued) Value Symbol C Parameter Conditions Unit Min Max -0.20 0.20 V -- s s VINTREF CC P Internal reference voltage precision Applies to all internal reference points (VSS_HV_ADR, 1/3 * VDD_HV_ADR, 2/3 * VDD_HV_ADR, VDD_HV_ADR) tADCSAMPLE SR P ADC sample time(2) Fast SAR - 12-bit configuration 6/fADCK Fast SAR - 10-bit configuration mode 1(3) (Standard frequency mode only) 6/fADCK Fast SAR - 10-bit configuration mode 2(4) (Standard frequency mode only) 5/fADCK Fast SAR - 10-bit configuration mode 3(5) (High frequency mode only) 6/fADCK Slow SAR (SARADC_B) - 12-bit configuration 12/fADCK Slow SAR (SARADC_B) - 10-bit configuration mode 1(3) (Standard frequency mode only) 12/fADCK Slow SAR (SARADC_B) - 10-bit configuration mode 2(4) (Standard frequency mode only) 10/fADCK Slow SAR (SARADC_B) - 10-bit configuration mode 3(5) (High frequency mode only) 12/fADCK Conversion of BIAS test channels through 20 k input. 40/fADCK 12-bit configuration 12/fADCK -- 10-bit configuration 10/fADCK -- Run mode (average across all codes) -- 7 Power Down mode -- 1 D tADCEVAL SR P ADC evaluation time D IADCREFH (6),(7) CC T ADC high reference current DS11758 Rev 5 A 49/131 54 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Table 27. SARn ADC electrical specification(1) (continued) Value Symbol IADCREFL(7) IADV_S(7) C CC CC TUE10 50/131 CC CC Conditions Unit Min Max Run mode VDD_HV_ADR_S 5.5 V -- 15 Power Down mode VDD_HV_ADR_S 5.5 V -- 1 Run mode -- 4.0 Power Down mode -- 0.04 Total unadjusted error TJ < 150 C, in 12-bit VDD_HV_ADV > 3 V, VDD_HV_ADR_S > 3 V configuration(8) -4 4 P TJ < 150 C, VDD_HV_ADV > 3 V, VDD_HV_ADR_S > 3 V -6 6 T TJ < 150 C, VDD_HV_ADV > 3 V, 3 V > VDD_HV_ADR_S > 2 V -6 6 D High frequency mode, TJ < 150 C, VDD_HV_ADV > 3 V, VDD_HV_ADR_S > 3 V -12 12 -1.5 1.5 D P D TUE12 Parameter T D ADC low reference current VDD_HV_ADV power supply current Total unadjusted error Mode 1, TJ < 150 C, in 10-bit VDD_HV_ADV > 3 V configuration(8) VDD_HV_ADR_S > 3 V mA LSB (12b) LSB (10b) D Mode 1, TJ < 150 C, VDD_HV_ADV > 3 V, 3 V > VDD_HV_ADR_S > 2 V -2.0 2.0 C Mode 2, TJ < 150 C, VDD_HV_ADV > 3 V VDD_HV_ADR_S > 3 V -3.0 3.0 C Mode 3, TJ < 150 C, VDD_HV_ADV > 3 V VDD_HV_ADR_S > 3 V -4.0 4.0 DS11758 Rev 5 A SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Table 27. SARn ADC electrical specification(1) (continued) Value Symbol TUE12 DNL(8) C CC CC D P T Parameter Conditions Unit Min Max TUE degradation due VIN < VDD_HV_ADV to VDD_HV_ADR offset VDD_HV_ADR - VDD_HV_ADV with respect to [0:25 mV] VDD_HV_ADV VIN < VDD_HV_ADV VDD_HV_ADR - VDD_HV_ADV [25:50 mV] -1 1 -2 2 VIN < VDD_HV_ADV VDD_HV_ADR - VDD_HV_ADV [50:75 mV] -4 4 VIN < VDD_HV_ADV VDD_HV_ADR - VDD_HV_ADV [75:100 mV] -6 6 VDD_HV_ADV < VIN < VDD_HV_ADR VDD_HV_ADR - VDD_HV_ADV [0:25 mV] -2.5 2.5 VDD_HV_ADV < VIN < VDD_HV_ADR VDD_HV_ADR - VDD_HV_ADV [25:50 mV] -4 4 VDD_HV_ADV < VIN < VDD_HV_ADR VDD_HV_ADR - VDD_HV_ADV [50:75 mV] -7 7 VDD_HV_ADV < VIN < VDD_HV_ADR VDD_HV_ADR - VDD_HV_ADV [75:100 mV] -12 12 Standard frequency mode, VDD_HV_ADV > 4 V VDD_HV_ADR_S > 4 V -1 2 High frequency mode, VDD_HV_ADV > 4 V VDD_HV_ADR_S > 4 V -1 Differential nonlinearity LSB (12b) LSB (12b) 2 1. Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2. Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB within the sampling window. Please refer to Figure 8 for models of the internal ADC circuit, and the values to use in external RC sizing and calculating the sampling window duration. 3. Mode1: 6 sampling cycles + 10 conversion cycles at 13.33 MHz. 4. Mode2: 5 sampling cycles + 10 conversion cycles at 13.33 MHz. 5. Mode3: 6 sampling cycles + 10 conversion cycles at 16 MHz. DS11758 Rev 5 51/131 54 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx 6. IADCREFH and IADCREFL are independent from ADC clock frequency. It depends on conversion rate: consumption is driven by the transfer of charge between internal capacitances during the conversion. 7. Current parameter values are for a single ADC. 8. TUE and DNL are granted with injection current within the range defined in Table 26, for parameters classified as T and D. 3.12.3 SAR ADC 10 bit electrical specification The ADC comparators are 10-bit Successive Approximation Register analog-to-digital converters with full capacitive DAC. The SARn architecture allows input channel multiplexing. Table 28. ADC-Comparator electrical specification(1) Value Symbol fADCK C SR Parameter Conditions P Clock frequency Standard frequency mode T High frequency mode Unit Min Max 7.5 13.33 >13.33 16.0 MHz tADCINIT SR -- ADC initialization time -- 1.5 -- s tADCBIASINIT SR -- ADC BIAS initialization time -- 5 -- s tADCINITSBY SR -- ADC initialization time in standby 8 -- s tADCPRECH SR T ADC precharge time 1/fADCK -- s VPRECH SR D Precharge voltage precision TJ < 150 C 0 0.25 V tADCSAMPLE SR P ADC sample time(2) 10-bit ADC mode 5/fADCK -- s ADC comparator mode 2/fADCK -- s P ADC evaluation time 10-bit ADC mode 10/fADCK -- s D ADC comparator mode 2/fADCK -- Run mode (average across all codes) -- 7 Power Down mode -- 1 ADC comparator mode -- 19.5 Run mode VDD_HV_ADR_S 5.5 V -- 15 Power Down mode VDD_HV_ADR_S 5.5 V -- 1 ADC comparator mode -- 20.5 Run mode -- 4 Power Down mode -- 0.04 tADCEVAL IADCREFH(3),(4) IADCREFL(5) IADV_S(5) 52/131 SR CC CC CC T ADC high reference current D ADC low reference current P VDD_HV_ADV power supply current D Standby Mode -- DS11758 Rev 5 A A mA SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Table 28. ADC-Comparator electrical specification(1) (continued) Value Symbol TUE10 TUE10 C CC CC Parameter Conditions Unit Min Max Total unadjusted error TJ < 150 C, in 10-bit configuration(6) VDD_HV_ADV > 3 V, VDD_HV_ADR_S > 3 V -2 2 P TJ < 150 C, VDD_HV_ADV > 3 V, VDD_HV_ADR_S > 3 V -3 3 T TJ < 150 C, VDD_HV_ADV > 3 V, 3 V > VDD_HV_ADR_S > 2 V -3 3 D High frequency mode, TJ < 150 C, VDD_HV_ADV > 3 V, VDD_HV_ADR_S > 3 V -3 3 D TUE degradation due to VDD_HV_ADR offset with respect to VDD_HV_ADV VIN < VDD_HV_ADV VDD_HV_ADR - VDD_HV_ADV [0:25 mV] -1.0 1.0 VIN < VDD_HV_ADV VDD_HV_ADR - VDD_HV_ADV [25:50 mV] -2.0 2.0 VIN < VDD_HV_ADV VDD_HV_ADR - VDD_HV_ADV [50:75 mV] -3.5 3.5 VIN < VDD_HV_ADV VDD_HV_ADR - VDD_HV_ADV [75:100 mV] -6.0 6.0 VDD_HV_ADV < VIN < VDD_HV_ADR VDD_HV_ADR - VDD_HV_ADV [0:25 mV] -2.5 2.5 VDD_HV_ADV < VIN < VDD_HV_ADR VDD_HV_ADR - VDD_HV_ADV [25:50 mV] -4.0 4.0 VDD_HV_ADV < VIN < VDD_HV_ADR VDD_HV_ADR - VDD_HV_ADV [50:75 mV] -7.0 7.0 VDD_HV_ADV < VIN < VDD_HV_ADR VDD_HV_ADR - VDD_HV_ADV [75:100 mV] -12.0 12.0 T DS11758 Rev 5 LSB (10b) LSB (10b) 53/131 54 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Table 28. ADC-Comparator electrical specification(1) (continued) Value Symbol DNL(6) C CC Parameter Conditions Unit Min Max P Differential non-linearity Standard frequency mode, std. mode VDD_HV_ADV > 4 V VDD_HV_ADR_S > 4 V -1 2 T -1 High frequency mode, VDD_HV_ADV > 4 V VDD_HV_ADR_S > 4 V LSB (10b) 2 1. Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device. 2. Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB within the sampling window. Please refer to Figure 8 for models of the internal ADC circuit, and the values to use in external RC sizing and calculating the sampling window duration. 3. IADCREFH and IADCREFL are independent from ADC clock frequency. It depends on conversion rate: consumption is driven by the transfer of charge between internal capacitances during the conversion. 4. Current parameter values are for a single ADC. 5. All channels of all SAR-ADC12bit and SAR-ADC10bit are impacted with same degradation, independently from the ADC and the channel subject to current injection. 6. TUE and DNL are granted with injection current within the range defined in Table 26, for parameters classified as T and D. 54/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx 3.13 Electrical characteristics Temperature Sensor The following table describes the temperature sensor electrical characteristics. Table 29. Temperature sensor electrical characteristics Value Symbol C Parameter Conditions Unit Min Typ Max -- CC -- Temperature monitoring range -- -40 -- 150 C TSENS CC T Sensitivity -- -- 5.18 -- mV/C TACC CC P Accuracy TJ < 150 C -3 -- 3 C DS11758 Rev 5 55/131 55 Electrical characteristics 3.14 SPC584Gx, SPC58EGx, SPC58NGx LFAST pad electrical characteristics The LFAST(LVDS Fast Asynchronous Serial Transmission) pad electrical characteristics apply to high-speed debug serial interfaces on the device. 3.14.1 LFAST interface timing diagrams Figure 9. LFAST and MSC/DSPI LVDS timing definition Signal excursions above this level NOT allowed Max. common mode input at RX 1743 mV 1600 mV |VOD| Max Differential Voltage = 285 mV (LFAST) 400 mV (MSC/DSPI) PAD_P Minimum Data Bit Time Opening = 0.55 * T (LFAST)0.50 * T (MSC/DSPI) |VOD| Min Differential Voltage = 100 mV (LFAST) (MSC/DSPI) "No-Go" VOS = 1.2 V +/- 10% TX common mode VICOM PAD_N PEREYE PEREYE Data Bit Period T = 1 /FDATA Min. common mode input at RX Signal excursions below this level NOT allowed 56/131 DS11758 Rev 5 150 mV 0V SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Figure 10. Power-down exit time H lfast_pwr_down L tPD2NM_TX Differential Data Lines TX pad_p/pad_n Data Valid Figure 11. Rise/fall time VIH Differential Data Lines TX |VOD(min)| |VOD(min)| pad_p/pad_n VIL tTR tTR 3.14.2 LFAST and MSC/DSPILVDS interface electrical characteristics The following table contains the electrical characteristics for the LFAST interface. Table 30. LVDS pad startup and receiver electrical characteristics(1),(2) Value Symbol C Parameter Conditions Unit Min Typ Max STARTUP(3),(4) tSTRT_BIAS CC T Bias current reference startup time(5) -- -- 0.5 4 s tPD2NM_TX CC T Transmitter startup time (power down to normal mode)(6) -- -- 0.4 2.75 s DS11758 Rev 5 57/131 61 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Table 30. LVDS pad startup and receiver electrical characteristics(1),(2) (continued) Value Symbol C Parameter Conditions Unit Min Typ Max tSM2NM_TX CC T Transmitter startup time (sleep mode to normal mode)(7) Not applicable to the MSC/DSPI LVDS pad -- 0.4 0.6 s tPD2NM_RX CC T Receiver startup time (power down to normal mode)(8) -- -- 20 40 ns tPD2SM_RX CC T Receiver startup time (power down to sleep mode)(9) Not applicable to the MSC/DSPI LVDS pad -- 20 50 ns ILVDS_BIAS CC D LVDS bias current consumption Tx or Rx enabled -- -- 0.95 mA TRANSMISSION LINE CHARACTERISTICS (PCB Track) Z0 SR D Transmission line characteristic impedance -- 47.5 50 52.5 ZDIFF SR D Transmission line differential impedance -- 95 100 105 (10) -- 1.6(11) V RECEIVER 0.15 VICOM SR T Common mode voltage -- |VI| SR T Differential input voltage(12) -- 100 -- -- mV VHYS CC T Input hysteresis -- 25 -- -- mV RIN CC D Terminating resistance VDD_HV_IO = 5.0 V 10% -40 C < TJ< 150 C 80 -- 150 VDD_HV_IO = 3.3 V 10% -40 C < TJ < 150 C 80 -- 175 -- -- 3.5 6.0 pF CIN CC D Differential input capacitance(13) ILVDS_RX CC C Receiver DC current consumption Enabled -- -- 1.6 mA IPIN_RX CC D Maximum consumption on receiver input pin VI = 400 mV, RIN = 80 -- -- 5 mA 1. The LVDS pad startup and receiver electrical characteristics in this table apply to both the LFAST & High-speed Debug (HSD) LVDS pad. 2. All LVDS pad electrical characteristics are valid from -40 C to 150 C. 3. All startup times are defined after a 2 peripheral bridge clock delay from writing to the corresponding enable bit in the LVDS control registers (LCR) of the LFAST and High-speed Debug modules. The value of the LCR bits for the LFAST/HSD modules don't take effect until the corresponding SIUL2 MSCR ODC bits are set to LFAST LVDS mode. Startup times for MSC/DSPI LVDS are defined after 2 peripheral bridge clock delay after selecting MSC/DSPI LVDS in the corresponding SIUL2 MSCR ODC field. 4. Startup times are valid for the maximum external loads CL defined in both the LFAST/HSD and MSC/DSPI transmitter electrical characteristic tables. 5. Bias startup time is defined as the time taken by the current reference block to reach the settling bias current after being enabled. 6. Total transmitter startup time from power down to normal mode is tSTRT_BIAS + tPD2NM_TX + 2 peripheral bridge clock periods. 7. Total transmitter startup time from sleep mode to normal mode is tSM2NM_TX + 2 peripheral bridge clock periods. Bias block remains enabled in sleep mode. 58/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics 8. Total receiver startup time from power down to normal mode is tSTRT_BIAS + tPD2NM_RX + 2 peripheral bridge clock periods. 9. Total receiver startup time from power down to sleep mode is tPD2SM_RX + 2 peripheral bridge clock periods. Bias block remains enabled in sleep mode. 10. Absolute min = 0.15 V - (285 mV/2) = 0 V 11. Absolute max = 1.6 V + (285 mV/2) = 1.743 V 12. Value valid for LFAST mode. The LXRXOP[0] bit in the LFAST LVDS Control Register (LCR) must be set to one to ensure proper LFAST receive timing. 13. Total internal capacitance including receiver and termination, co-bonded GPIO pads, and package contributions. For bare die devices, subtract the package value given in Figure 12. Table 31. LFAST transmitter electrical characteristics(1),(2),(3) Value Symbol fDATA SR VOS C Parameter D Conditions Unit Min Typ Max Data rate -- -- -- 320 Mbps CC P Common mode voltage -- 1.08 -- 1.32 V |VOD| CC P Differential output voltage swing (terminated)(4),(5) -- 110 -- 285 mV tTR CC T Rise time from -|VOD(min)| to +|VOD(min)|. Fall time from +|VOD(min)| to -|VOD(min)| -- 0.26 -- 1.25 ns CL SR External lumped differential load capacitance4 VDD_HV_IO = 4.5 V -- -- 6.0 VDD_HV_IO = 3.0 V -- -- 4.0 -- 3.6 mA 2.85 mA D ILVDS_TX CC C Transmitter DC current consumption Enabled -- IPIN_TX CC D Transmitter DC current sourced through output pin -- 1.1 pF 1. This table is applicable to LFAST LVDS pads used in LFAST configuration (SIUL2_MSCR_IO_n.ODC=101). 2. The LFAST and High-Speed Debug LFAST pad electrical characteristics are based on worst case internal capacitance values shown in Figure 12. 3. All LFAST and High-Speed Debug LVDS pad electrical characteristics are valid from -40 C to 150 C. 4. Valid for maximum data rate fDATA. Value given is the capacitance on each terminal of the differential pair, as shown in Figure 12. 5. Valid for maximum external load CL. DS11758 Rev 5 59/131 61 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Figure 12. LVDS pad external load diagram Die PCB Package GPIO Driver CL 1pF 2.5pF 100 terminator LVDS Driver GPIO Driver CL 1pF 2.5pF 3.14.3 LFAST PLL electrical characteristics The following table contains the electrical characteristics for the LFAST PLL. Table 32. LFAST PLL electrical characteristics(1) Value Symbol C Parameter Conditions Unit Min Typ Max fRF_REF SR D PLL reference clock frequency (CLKIN) -- 10(2) -- 30 MHz ERRREF CC D -- -1 -- 1 % -- 30 -- 70 % DCREF PLL reference clock frequency error CC D PLL reference clock duty cycle (CLKIN) PN CC D Integrated phase noise (single side band) fRF_REF = 20 MHz -- -- -58 dBc fVCO CC P PLL VCO frequency -- 312 -- 320(3) MHz -- 150(4) s tLOCK 60/131 CC D PLL phase lock -- DS11758 Rev 5 -- SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Table 32. LFAST PLL electrical characteristics(1) (continued) Value Symbol C Parameter Conditions T PERREF SR Input reference clock jitter (peak to peak) T PEREYE CC T Unit Min Typ Max Single period, fRF_REF = 20 MHz -- -- 350 ps Long term, fRF_REF = 20 MHz -500 -- 500 ps -- -- -- 400 ps Output Eye Jitter (peak to peak)(5) 1. The specifications in this table apply to both the interprocessor bus and debug LFAST interfaces. 2. If the input frequency is lower than 20 MHz, it is required to set a input division factor of 1. 3. The 320 MHz frequency is achieved with a 20 MHz reference clock. 4. The total lock time is the sum of the coarse lock time plus the programmable lock delay time 2 clock cycles of the peripheral bridge clock that is connected to the PLL on the device (to set the PLL enable bit). 5. Measured at the transmitter output across a 100 termination resistor on a device evaluation board. See Figure 12. DS11758 Rev 5 61/131 61 Electrical characteristics 3.15 SPC584Gx, SPC58EGx, SPC58NGx Power management The power management module monitors the different power supplies as well as it generates the required internal supplies. The device can operate in the following configurations: Table 33. Power management regulators Device SPC584Gx SPC58EGx SPC58NGx External regulator Internal SMPS regulator Internal linear regulator external ballast Internal linear regulator internal ballast Auxiliary regulator Clamp regulator Internal standby regulator(1) -- -- X -- X X X(2) 1. Standby regulator is automatically activated when the device enters standby mode. Standby mode is not supported if the device operates in External regulator mode. Emulation Device calibration and trace features are not supported in standby mode. 2. Emulation Device calibration and trace features are not supported in standby mode. 3.15.1 Power management integration Use the integration schemes provided below to ensure the proper device function, according to the selected regulator configuration. The internal regulators are supplied by VDD_HV_IO_MAIN supply and are used to generate VDD_LV supply. Place capacitances on the board as near as possible to the associated pins and limit the serial inductance of the board to less than 5 nH. It is recommended to use the internal regulators only to supply the device itself. 62/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Figure 13. Internal regulator with external ballast mode &)/$ 966 &( 966 %&75/ (;75(*B6(/ &% 9''B+9B,2 4(;7 &%9 9''B+9B)/$ 9''B+9 9''B+9B,2 &+9Q 0DLQ5HJ 966 9''B/9 $X[5HJ &/9Q 966 &ODPS5HJ 966B+9B$'9 9''B+9B$'9 &$'& DS11758 Rev 5 63/131 70 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Figure 14. Standby regulator with external ballast mode &)/$ 966 9''B+9 &%9 &( 966 9''B+9B,2 (;75(*B6(/ %&75/ &% 9''B+9B)/$ 4(;7 9''B+9B,2 &+9Q 6WDQGE\UHJ 966 9''B/9 &/9Q 966 966B+9B$'9 9''B+9B$'9 &$'& Table 34. External components integration Symbol C Value Conditions(1) Parameter Unit Min Typ Max -- 2x2.2 -- F Common Components CE SR D Internal voltage regulator stability external capacitance.(2) (3) RE SR D Stability capacitor equivalent serial resistance Total resistance including board track -- -- 50 m CLVn SR D Internal voltage regulator decoupling external capacitance(2) (4) (5) Each VDD_LV/VSS pair -- 47 -- nF 64/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Table 34. External components integration (continued) Symbol C Value Conditions(1) Parameter Unit Min Typ Max RLVn SR D Stability capacitor equivalent serial resistance -- -- -- 50 m CBV SR D Bulk capacitance for HV supply(2) -- -- 4.7 -- F CHVn SR D Decoupling capacitance for ballast and IOs(2) on all VDD_HV_IO/VSS and VDD_HV_ADR/VSS pairs -- 100 -- nF CFLA SR D Decoupling capacitance for Flash supply(6) -- -- 10 -- nF CADC SR D ADC supply external capacitance(2) VDD_HV_ADV/VSS_HV_ADV pair. -- 2.2 -- F VDD_ V Internal Linear Regulator with External Ballast Mode QEXT SR D Recommended external NPN transistors VQ SR D External NPN transistor collector voltage NJD2873T4, BCP68, 2SCR574D -- 2.0 -- HV_IO _MAIN CB SR D Internal voltage regulator stability external capacitance on ballast base(5) (7) RB SR D Stability capacitor equivalent serial resistance -- -- 2.2 -- F Total resistance including board track -- -- 50 m 1. VDD = 3.3 V 10% / 5.0 V 10%, TJ = -40 / 150 C, unless otherwise specified. 2. Recommended X7R or X5R ceramic -50% / +35% variation across process, temperature, voltage and after aging. 3. CE capacitance is required both in internal and external regulator mode. 4. For noise filtering, add a high frequency bypass capacitance of 10 nF. 5. For applications it is recommended to implement at least 5 CLV capacitances. 6. Recommended X7R capacitors. For noise filtering, add a high frequency bypass capacitance of 100 nF. 7. CB capacitance is required if only the external ballast is implemented. DS11758 Rev 5 65/131 70 Electrical characteristics 3.15.2 SPC584Gx, SPC58EGx, SPC58NGx Voltage regulators Table 35. Linear regulator specifications Value Symbol VMREG IDDMREG C Parameter Conditions Unit Min Typ Max CC P Main regulator output voltage Power-up, before trimming, no load 1.12 1.20 1.28 CC P After trimming, maximum load 1.08 1.18 1.23 -- -- 700 mA -- -- 400 mA -100 -- 100 mA IMREG = max -- -- 22 mA IMREG = 0 mA -- -- -- CC T Main regulator current provided to VDD_LV domain -- V The maximum current required by the device (IDD_LV) may exceed the maximum current which can be provided by the internal linear regulator. In this case, the internal regulator mode cannot be used. IDDCLAMP CC D Main regulator rush current sinked from VDD_HV_IO_MAIN domain during VDD_LV domain loading Power-up condition IDDMREG CC 20 s observation window IMREGINT T Main regulator output current variation CC D Main regulator current consumption D Table 36. Auxiliary regulator specifications Value Symbol C Parameter Conditions Unit Min Typ Max CC P Aux regulator output voltage After trimming, internal regulator mode 1.08 1.18 1.21 CC P After trimming, external regulator mode 1.03 1.12 1.16 IDDAUX CC T Aux regulator current provided to VDD_LV domain -- -- -- 250 mA IDDAUX CC T Aux regulator current variation 20 s observation window --100 -- 100 mA IAUXINT CC D Aux regulator current consumption D IMREG = max -- -- 1.1 mA IMREG = 0 mA -- -- 1.1 VAUX 66/131 DS11758 Rev 5 V SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Table 37. Clamp regulator specifications Value Symbol VCLAMP C Parameter Conditions Typ Max CC P Clamp regulator output voltage After trimming, internal regulator mode 1.17 1.21 1.32 CC P After trimming, external regulator mode 1.24 1.28 1.39 --100 -- 100 mA -- -- 0.7 mA IDDCLAMP CC T Clamp regulator current variation ICLAMPINT Unit Min CC D Clamp regulator current consumption 20 s observation window IMREG = 0 mA V Table 38. Standby regulator specifications Value Symbol VSBY IDDSBY 3.15.3 C Parameter Conditions CC P Standby regulator output voltage After trimming, maximum load CC T Standby regulator current provided to VDD_LV domain -- Unit Min Typ Max 1.02 1.06 1.26 V -- -- 50 mA Voltage monitors The monitors and their associated levels for the device are given in Table 39. Figure 15 illustrates the workings of voltage monitoring threshold. DS11758 Rev 5 67/131 70 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Figure 15. Voltage monitor threshold definition VDD_xxx VHVD VLVD TVMFILTER TVMFILTER HVD TRIGGER (INTERNAL) TVMFILTER TVMFILTER LVD TRIGGER (INTERNAL) Table 39. Voltage monitor electrical characteristics Value(1) Symbol C Supply/Parameter Conditions Unit Min Typ Max 1.80 2.18 2.40 V PowerOn Reset HV VPOR200_C CC P VDD_HV_IO_MAIN -- Minimum Voltage Detectors HV VMVD270_C CC P VDD_HV_IO_MAIN -- 2.71 2.76 2.80 V VMVD270_F CC P VDD_HV_FLA -- 2.71 2.76 2.80 V CC P VDD_HV_IO_MAIN (in Standby) -- 2.71 2.76 2.80 V VMVD270_SBY Low Voltage Detectors HV VLVD290_C CC P VDD_HV_IO_MAIN -- 2.89 2.94 2.99 V VLVD290_F CC P VDD_HV_FLA -- 2.89 2.94 2.99 V VLVD290_AD CC P VDD_HV_ADV (ADCSD pad) -- 2.89 2.94 2.99 V VLVD290_AS CC P VDD_HV_ADV (ADCSAR pad) -- 2.89 2.94 2.99 V VLVD290_IJ CC P VDD_HV_IO_JTAG -- 2.89 2.94 2.99 V 68/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Table 39. Voltage monitor electrical characteristics (continued) Value(1) Symbol C Supply/Parameter Conditions Unit Min Typ Max VLVD290_IF CC P VDD_HV_IO_FLEX -- 2.89 2.94 2.99 V VLVD400_AD CC P VDD_HV_ADV (ADCSD pad) -- 4.15 4.23 4.31 V VLVD400_AS CC P VDD_HV_ADV (ADCSAR pad) -- 4.15 4.23 4.31 V VLVD400_IM CC P VDD_HV_IO_MAIN -- 4.15 4.23 4.31 V VLVD400_IJ CC P VDD_HV_IO_JTAG 4.15 4.23 4.31 V VLVD400_IF CC P VDD_HV_IO_FLEX 4.15 4.23 4.31 V -- High Voltage Detectors HV VHVD400_C CC P VDD_HV_IO_MAIN 3.68 3.75 3.82 V VHVD400_IJ CC P VDD_HV_IO_JTAG 3.68 3.75 3.82 V VHVD400_IF CC P VDD_HV_IO_FLEX 3.68 3.75 3.82 V 5.72 5.82 5.92 V -- Upper Voltage Detectors HV VUVD600_C CC P VDD_HV_IO_MAIN VUVD600_F CC P VDD_HV_FLA -- 5.72 5.82 5.92 V VUVD600_IJ CC P VDD_HV_IO_JTAG -- 5.72 5.82 5.92 V VUVD600_IF CC P VDD_HV_IO_FLEX -- 5.72 5.82 5.92 V -- 0.29 0.60 0.97 V PowerOn Reset LV VPOR031_C CC P VDD_LV Minimum Voltage Detectors LV VMVD082_C CC P VDD_LV -- 0.85 0.88 0.91 V VMVD082_B CC P VDD_LV_BD -- 0.85 0.88 0.91 V VMVD094_C CC P VDD_LV -- 0.98 1.00 1.02 V VMVD094_FA CC P VDD_LV (Flash) -- 1.00 1.02 1.04 V VMVD094_FB CC P VDD_LV (Flash) -- 1.00 1.02 1.04 V Low Voltage Detectors LV VLVD100_C CC P VDD_LV -- 1.06 1.08 1.11 V VLVD100_SB CC P VDD_LV (In Standby) -- 0.99 1.01 1.03 V VLVD100_F CC P VDD_LV (Flash) -- 1.08 1.10 1.12 V 1.28 1.31 1.33 V High Voltage Detectors LV VHVD134_C CC P VDD_LV -- Upper Voltage Detectors LV VUVD140_C CC P VDD_LV -- 1.34 1.37 1.39 V VUVD140_F CC P VDD_LV (Flash) -- 1.34 1.37 1.39 V DS11758 Rev 5 69/131 70 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Table 39. Voltage monitor electrical characteristics (continued) Value(1) Symbol C Supply/Parameter Conditions Unit Min Typ Max 5 -- 25 Common TVMFILTER (2) CC D Voltage monitor filter -- s 1. The values reported are Trimmed values, where applicable. 2. See Figure 15. Transitions shorter than minimum are filtered. Transitions longer than maximum are not filtered, and will be delayed by TVMFILTER time. Transitions between minimum and maximum can be filtered or not filtered, according to temperature, process and voltage variations. 70/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx 3.16 Electrical characteristics Flash memory The following table shows the Wait State configuration. Table 40. Wait State configuration APC RWSC Frequency range (MHz) 0 f<30 1 f<60 2 f<90 3 f<120 4 f<150 5 f<180 0 f<30 1 f<60 2 f<90 3 f<120 4 f<150 5 f<180 2 55<f<80 3 55<f<120 4 55<f<160 5 55<f<180 000(1) 100(2) 001(3) 1. STD pipelined. 2. No pipeline. 3. Pipeline with 1 Tck address anticipation. The following table shows the Program/Erase Characteristics. Table 41. Flash memory program and erase specifications Value Symbol Characteristics(1)(2) Lifetime Initial max Typ(3) C (6) All temp C 25 C (7) Typical end of life(4) max(5) <1K cycles < 250 K cycles Unit C tdwprogram Double Word (64 bits) program time EEPROM (partitions 2, 3, 4) [Packaged part] 55 C 130 -- -- 140 500 C s tpprogram Page (256 bits) program time 76 C 240 -- -- 255 1000 C s DS11758 Rev 5 71/131 74 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Table 41. Flash memory program and erase specifications (continued) Value Symbol Characteristics Lifetime Initial max (1)(2) Typ(3) C (6) All temp C 25 C (7) Typical end of life(4) max(5) <1K cycles < 250 K cycles Unit C Page (256 bits) program time EEPROM (partitions 2, 3, 4) [Packaged part] 90 C 300 -- -- 315 1000 C s Quad Page (1024 bits) program time 220 C 840 1200 P 850 2000 C s tqprogrameep Quad Page (1024 bits) program time EEPROM (partitions 2, 3, 4) [Packaged part] 306 C 1200 1800 P 1270 2000 C s t16kpperase 16 KB block pre-program and erase time 190 C 450 500 P 250 1000 -- C ms t32kpperase 32 KB block pre-program and erase time 250 C 520 600 P 310 1200 -- C ms t64kpperase 64 KB block pre-program and erase time 360 C 700 750 P 420 1600 -- C ms t256kpperase 256 KB block pre-program and erase time 1050 C 1800 2400 P 1600 4000 -- C ms t16kprogram 16 KB block program time 25 C 45 50 P 40 1000 -- C ms t32kprogram 32 KB block program time 50 C 90 100 P 75 1200 -- C ms t64kprogram 64 KB block program time 102 C 175 200 P 150 1600 -- C ms t256kprogram 256 KB block program time 410 C 700 850 P 590 4000 -- C ms 120 C 200 300 P 330 1750 C ms Erase 64 KB Data Flash EEPROM (partition 2,3) [Packaged part] 530 C 910 1150 P 1040 3600 C ms Program rate(8) 1.7 C 2.8 3.40 C 2.4 -- C s/MB 4.8 C 7.2 9.6 C 6.4 -- C s/MB 1.12 C 1.4 1.6 C -- -- C s/MB 4.0 C 5.2 5.8 C -- -- C s/MB 12.0 C 17.8 22.0 P 15.4 -- -- C s 25.0 C 40.0 50.0 P 40.0 -- -- C s 200 T -- -- -- -- tpprogrameep tqprogram Program 64 KB Data Flash t64kprogrameep EEPROM (partition 2,3) [Packaged part] t64keraseeep tprr terr tprfm terfm tffprogram (8) Erase rate Program rate Factory Erase rate Factory Mode(8) Mode(8) Full flash programming time(9) time(9) tfferase Full flash erasing tESRT Erase suspend request rate(10) 72/131 DS11758 Rev 5 -- -- s SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Table 41. Flash memory program and erase specifications (continued) Value Symbol Characteristics Lifetime Initial max (1)(2) Typ(3) C (6) All temp C 25 C (7) Typical end of life(4) max(5) <1K cycles < 250 K cycles Unit C tPSRT Program suspend request rate(10) 30 T -- -- -- -- -- -- s tAMRT Array Integrity Check - Margin Read suspend request rate 15 T -- -- -- -- -- -- s tPSUS Program suspend latency(11) -- -- -- -- -- -- 12 T s -- -- -- -- -- -- 22 T s latency(11) tESUS Erase suspend tAIC0S Array Integrity Check (6.0 MB, sequential)(12) 40 T -- -- -- -- -- -- -- ms tAIC256KS Array Integrity Check (256 KB, sequential)(12) 1.5 T -- -- -- -- -- -- -- ms tAIC0P Array Integrity Check (6.0 MB, proprietary)(12) 4.0 T -- -- -- -- -- -- -- tMR0S Margin Read (6.0 MB, sequential)(12) 120 T -- -- -- -- -- -- -- ms tMR256KS Margin Read (256 KB, sequential)(12) 4.0 T -- -- -- -- -- -- -- ms s 1. Characteristics are valid both for Data Flash and Code Flash, unless specified in the characteristics column. 2. Actual hardware operation times; this does not include software overhead. 3. Typical program and erase times assume nominal supply values and operation at 25 C. 4. Typical End of Life program and erase times represent the median performance and assume nominal supply values. Typical End of Life program and erase values may be used for throughput calculations. These values are characteristic, but not tested. 5. Lifetime maximum program & erase times apply across the voltages and temperatures and occur after the specified number of program/erase cycles. These maximum values are characterized but not tested or guaranteed. 6. Initial factory condition: < 100 program/erase cycles, 25 C typical junction temperature and nominal ( 5%) supply voltages. 7. Initial maximum "All temp" program and erase times provide guidance for time-out limits used in the factory and apply for less than or equal to 100 program or erase cycles, -40 C < TJ < 150 C junction temperature and nominal ( 5%) supply voltages. 8. Rate computed based on 256 KB sectors. 9. Only code sectors, not including EEPROM. 10. Time between suspend resume and next suspend. Value stated actually represents Min value specification. 11. Timings guaranteed by design. 12. AIC is done using system clock, thus all timing is dependant on system frequency and number of wait states. Timing in the table is calculated at max frequency. All the Flash operations require the presence of the system clock for internal synchronization. About 50 synchronization cycles are needed: this means that the timings of the previous table can be longer if a low frequency system clock is used. DS11758 Rev 5 73/131 74 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Table 42. Flash memory Life Specification Symbol Value Characteristics(1) (2) Unit Min C Typ C NCER16K 16 KB CODE Flash endurance 10 -- 100 -- Kcycles NCER32K 32 KB CODE Flash endurance 10 -- 100 -- Kcycles NCER64K 64 KB CODE Flash endurance 10 -- 100 -- Kcycles 1 -- 100 -- Kcycles 10 -- 100 -- Kcycles 64 KB DATA EEPROM Flash endurance 250 -- -- -- Kcycles tDR1k Minimum data retention Blocks with 0 - 1,000 P/E cycles 25 -- -- -- Years tDR10k Minimum data retention Blocks with 1,001 - 10,000 P/E cycles 20 -- -- -- Years tDR100k Minimum data retention Blocks with 10,001 - 100,000 P/E cycles 15 -- -- -- Years tDR250k Minimum data retention Blocks with 100,001 - 250,000 P/E cycles 10 -- -- -- Years NCER256K NDER64K 256 KB CODE Flash endurance 256 KB CODE Flash endurance (3) 1. Program and erase cycles supported across specified temperature specs. 2. It is recommended that the application enables the core cache memory. 3. 10K cycles on 4-256 KB blocks is not intended for production. Reduced reliability and degraded erase time are possible. 74/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx 3.17 Electrical characteristics AC Specifications All AC timing specifications are valid up to 150 C, except where explicitly noted. 3.17.1 Debug and calibration interface timing 3.17.1.1 JTAG interface timing Table 43. JTAG pin AC electrical characteristics # Symbol(1),(2) Value C Characteristic Unit Min Max 1 tJCYC CC D TCK cycle time 100 -- ns 2 tJDC CC T TCK clock pulse width 40 60 % 3 tTCKRISE CC D TCK rise and fall times (40%-70%) -- 3 ns 4 tTMSS, tTDIS CC D TMS, TDI data setup time 5 -- ns 5 tTMSH, tTDIH CC D TMS, TDI data hold time 5 -- ns ns 6 tTDOV CC D TCK low to TDO data valid -- 15(3) 7 tTDOI CC D TCK low to TDO data invalid 0 -- ns 8 tTDOHZ CC D TCK low to TDO high impedance -- 15 ns 9 tJCMPPW CC D JCOMP assertion time 100 -- ns 10 tJCMPS CC D JCOMP setup time to TCK low 40 -- ns ns 11 tBSDV CC D TCK falling edge to output valid -- 600(4) 12 tBSDVZ CC D TCK falling edge to output valid out of high impedance -- 600 ns 13 tBSDHZ CC D TCK falling edge to output high impedance -- 600 ns 14 tBSDST CC D Boundary scan input valid to TCK rising edge 15 -- ns 15 tBSDHT CC D TCK rising edge to boundary scan input invalid 15 -- ns 1. These specifications apply to JTAG boundary scan only. See Table 44 for functional specifications. 2. JTAG timing specified at VDD_HV_IO_JTAG = 4.0 to 5.5 V and max. loading per pad type as specified in the I/O section of the datasheet. 3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay. 4. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay. DS11758 Rev 5 75/131 103 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Figure 16. JTAG test clock input timing TCK 2 3 2 1 3 Figure 17. JTAG test access port timing TCK 4 5 TMS, TDI 6 8 7 TDO 76/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Figure 18. JTAG JCOMP timing TCK 10 JCOMP 9 DS11758 Rev 5 77/131 103 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Figure 19. JTAG boundary scan timing TCK 11 13 Output Signals 12 Output Signals 14 15 Input Signals 3.17.1.2 Nexus interface timing Table 44. Nexus debug port timing(1) Value # Symbol C Characteristic CC D EVTI pulse width 7 tEVTIPW 8 tEVTOPW CC D EVTO pulse width Unit Min Max 4 -- tCYC(2) 40 -- ns 2(3),(4) -- tCYC(2) ns 9 tTCYC CC D TCK cycle time 9 tTCYC CC D Absolute minimum TCK cycle time(5) (TDO sampled on posedge of TCK) 40(6) -- Absolute minimum TCK cycle time(7) (TDO sampled on negedge of TCK) 20(6) -- 5 -- 11 78/131 tNTDIS CC D TDI data setup time DS11758 Rev 5 ns SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Table 44. Nexus debug port timing(1) (continued) Value # Symbol C Characteristic Unit Min Max 12 tNTDIH CC D TDI data hold time 5 -- ns 13 tNTMSS CC D TMS data setup time 5 -- ns 14 tNTMSH CC D TMS data hold time 5 -- ns -- 16 ns 2.25 -- ns (8) 15 -- CC D TDO propagation delay from falling edge of TCK 16 -- CC D TDO hold time with respect to TCK falling edge (minimum TDO propagation delay) 1. Nexus timing specified at VDD_HV_IO_JTAG = 3.0 V to 5.5 V, and maximum loading per pad type as specified in the I/O section of the data sheet. 2. tCYC is system clock period. 3. Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual peripheral frequency being used. To ensure proper operation TCK frequency should be set to the peripheral frequency divided by a number greater than or equal to that specified here. 4. This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the Absolute minimum TCK period specification. 5. This value is TDO propagation time 36 ns + 4 ns setup time to sampling edge. 6. This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency being used. 7. This value is TDO propagation time 16n s + 4 ns setup time to sampling edge. 8. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay. Figure 20. Nexus output timing 1 2 MCKO 3 4 6 MDO MSEO EVTO Output Data Valid DS11758 Rev 5 79/131 103 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Figure 21. Nexus event trigger and test clock timings TCK EVTI EVTO 9 TCK EVTI EVTO 9 7 7 8 8 Figure 22. Nexus TDI, TMS, TDO timing TCK 11 13 12 14 TMS, TDI 15 16 TDO 80/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx 3.17.1.3 Electrical characteristics External interrupt timing (IRQ pin) Table 45. External interrupt timing Characteristic IRQ Pulse Width Low IRQ Pulse Width High (1) IRQ Edge to Edge Time Symbol Min Max Unit tIPWL 3 -- tcyc tIPWH 3 -- tcyc tICYC 6 -- tcyc 1. Applies when IRQ pins are configured for rising edge or falling edge events, but not both. Figure 23. External interrupt timing IRQ 2 1 3 Figure 24. External interrupt timing D_CLKOUT 4 IRQ 2 1 3 3.17.2 DSPI timing with CMOS pads DSPI channel frequency support is shown in Table 46. Timing specifications are shown in tables below. DS11758 Rev 5 81/131 103 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Table 46. DSPI channel frequency support(1) Max usable frequency (MHz)(2),(3) DSPI use mode CMOS (Master mode) Full duplex - Classic timing (Table 47) Full duplex - Modified timing (Table 48) DSPI_0, DSPI_3, DSPI_5, DSPI_7 12 DSPI_8 5 DSPI_1, DSPI_2, DSPI_4, DSPI_6, DSPI_9 17 DSPI_0, DSPI_3, DSPI_5, DSPI_7 12 DSPI_8 5 DSPI_1, DSPI_2, DSPI_4, DSPI_6, DSPI_9 30 Output only mode (SCK/SOUT/PCS) (Table 47 and Table 48) -- 30 Output only mode TSB mode (SCK/SOUT/PCS) -- 30 -- 16 CMOS (Slave mode Full duplex) (Table 49) 1. Each DSPI module can be configured to use different pins for the interface. Please see the device pinout IO definition excel file for the available combinations. It is not possible to reach the maximum performance with every possible combination of pins. 2. Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads. 3. Maximum usable frequency does not take into account external device propagation delay. 3.17.2.1 DSPI master mode full duplex timing with CMOS pads 3.17.2.1.1 DSPI CMOS master mode -- classic timing Table 47. DSPI CMOS master classic timing (full duplex and output only) MTFE = 0, CPHA = 0 or 1(1) Value(2) Condition # 1 Symbol tSCK 82/131 C Characteristic CC D SCK cycle time Unit Pad drive(3) Load (CL) Min Max SCK drive strength Very strong 25 pF 59.0 -- Strong 50 pF 80.0 -- Medium 50 pF 200.0 -- DS11758 Rev 5 ns SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Table 47. DSPI CMOS master classic timing (full duplex and output only) MTFE = 0, CPHA = 0 or 1(1) (continued) Value(2) Condition # 2 3 4 Symbol tCSC tASC tSDC C Characteristic CC D PCS to SCK delay CC D After SCK delay CC D SCK duty cycle(7) Unit Pad drive(3) Load (CL) Min Max SCK and PCS drive strength Very strong 25 pF (N(4) x tSYS(5)) - 16 -- Strong 50 pF (N(4) x tSYS(5)) - 16 -- Medium 50 pF (N(4) x tSYS(5)) - 16 -- PCS medium and SCK strong PCS = 50 pF SCK = 50 pF (N(4) x tSYS(5)) - 29 -- ns SCK and PCS drive strength Very strong PCS = 0 pF SCK = 50 pF (M(6) x tSYS(5)) - 35 -- Strong PCS = 0 pF SCK = 50 pF (M(6) x tSYS(5)) - 35 -- Medium PCS = 0 pF SCK = 50 pF (M(6) x tSYS(5)) - 35 -- PCS medium and SCK strong PCS = 0 pF SCK = 50 pF (M(6) x tSYS(5)) - 35 -- ns SCK drive strength Very strong Strong Medium 0 pF 1/ 0 pF 1/ 0 pF 1/ 2tSCK 2tSCK 2tSCK -2 1/ 2tSCK +2 -2 1/ 2tSCK +2 -5 1/ 2tSCK +5 ns PCS strobe timing 5 tPCS C 6 tPAS C CC D PCSx to PCSS time(8) PCS and PCSS drive strength CC D PCSS to PCSx time(8) PCS and PCSS drive strength Strong Strong 25 pF 25 pF 16.0 -- ns 16.0 -- ns 25.0 -- ns SIN setup time 7 tSUI CC D SIN setup time to SCK drive strength SCK(9) Very strong 25 pF Strong 50 pF 31.0 -- Medium 50 pF 52.0 -- DS11758 Rev 5 83/131 103 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Table 47. DSPI CMOS master classic timing (full duplex and output only) MTFE = 0, CPHA = 0 or 1(1) (continued) Value(2) Condition # Symbol C Characteristic Unit Pad drive(3) Load (CL) Min Max SIN hold time 8 tHI CC D SIN hold time from SCK(9) SCK drive strength Very strong 0 pF -1.0 -- Strong 0 pF -1.0 -- Medium 0 pF -1.0 -- ns SOUT data valid time (after SCK edge) 9 tSUO CC D SOUT data valid time from SCK(10) SOUT and SCK drive strength Very strong 25 pF -- 7.0 Strong 50 pF -- 8.0 Medium 50 pF -- 16.0 ns SOUT data hold time (after SCK edge) 10 tHO CC D SOUT data hold time after SCK(10) SOUT and SCK drive strength Very strong 25 pF -7.7 -- Strong 50 pF -11.0 -- Medium 50 pF -15.0 -- ns 1. All output timing is worst case and includes the mismatching of rise and fall times of the output pads. 2. All timing values for output signals in this table are measured to 50% of the output voltage. 3. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation. 4. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 5. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min tSYS = 10 ns). 6. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 7. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time. 8. PCSx and PCSS using same pad configuration. 9. Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL voltage thresholds. 10. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value. 84/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Figure 25. DSPI CMOS master mode -- classic timing, CPHA = 0 tCSC tASC PCSx tSCK tSDC SCK Output (CPOL = 0) SCK Output (CPOL = 1) tSDC tSUI tHI First Data SIN Data Last Data tSUO SOUT tHO Data First Data Last Data Figure 26. DSPI CMOS master mode -- classic timing, CPHA = 1 3&6[ 6&.2XWSXW &32/ 6&.2XWSXW &3 2/ W68, 6,1 W+, )LUVW'DWD 'DWD W682 6287 )LUVW'DWD DS11758 Rev 5 'DWD /DVW'DWD W+2 /DVW'DWD 85/131 103 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Figure 27. DSPI PCS strobe (PCSS) timing (master mode) tPCSC tPASC PCSS PCSx 3.17.2.1.2 DSPI CMOS master mode -- modified timing Table 48. DSPI CMOS master modified timing (full duplex and output only) MTFE = 1, CPHA = 0 or 1(1) Value(2) Condition # 1 2 Symbol tSCK tCSC C Characteristic CC D SCK cycle time CC D PCS to SCK delay Pad drive(3) Unit Load (CL) Very strong 25 pF 33.0 -- Strong 50 pF 80.0 -- Medium 50 pF 200.0 -- (N(4) x tSYS(5)) - 16 -- 25 pF 50 pF Medium 50 pF PCS PCS = 50 pF medium and SCK = 50 pF SCK strong 4 tSDC CC D After SCK delay (4) - 16 -- x tSYS ) - 16 -- (N(4) x tSYS(5)) - 29 -- (N (4) (N x tSYS (5)) (5) ns SCK and PCS drive strength Very strong PCS = 0 pF SCK = 50 pF (M(6) x tSYS(5)) - 35 -- Strong PCS = 0 pF SCK = 50 pF (M(6) x tSYS(5)) - 35 -- Medium PCS = 0 pF SCK = 50 pF (M(6) x tSYS(5)) - 35 -- PCS PCS = 0 pF medium and SCK = 50 pF SCK strong (M(6) x tSYS(5)) - 35 -- ns CC D SCK duty cycle(7) SCK drive strength Very strong 0 pF 1/ 2tSCK -2 1/ t 2 SCK +2 Strong 0 pF 1/ 2tSCK -2 1/ t 2 SCK +2 0 pF 1/ -5 1/ t 2 SCK +5 Medium 86/131 ns SCK and PCS drive strength Strong tASC Max SCK drive strength Very strong 3 Min DS11758 Rev 5 2tSCK ns SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Table 48. DSPI CMOS master modified timing (full duplex and output only) MTFE = 1, CPHA = 0 or 1(1) (continued) Value(2) Condition # Symbol C Characteristic Pad drive(3) Unit Load (CL) Min Max 16.0 -- ns 16.0 -- ns -- ns PCS strobe timing 5 tPCSC CC D PCSx to PCSS time(8) PCS and PCSS drive strength Strong 6 tPASC CC D PCSS to PCSx time(8) 25 pF PCS and PCSS drive strength Strong 25 pF SIN setup time 7 tSUI CC D SIN setup time to SCK drive strength SCK Very strong 25 pF CPHA = 0(9) Strong 50 pF Medium 50 pF 25 - (P(10) x tSYS(5)) 31 - (P (10) -- 52 - (P(10) x tSYS(5)) -- 25.0 -- 31.0 -- 52.0 -- SIN setup time to SCK drive strength SCK Very strong 25 pF CPHA = 1(9) Strong 50 pF Medium x tSYS(5)) 50 pF ns SIN hold time 8 tHI CC D SIN hold time from SCK CPHA = 09 SCK drive strength Very strong Strong 0 pF Medium SIN hold time from SCK CPHA = 19 0 pF 0 pF -1 + (P(9) x tSYS(4)) (4) x tSYS ) -- (P(9) (4)) -- -1 + (P -1 + -- (9) x tSYS ns SCK drive strength Very strong 0 pF -1.0 -- Strong 0 pF -1.0 -- Medium 0 pF -1.0 -- DS11758 Rev 5 ns 87/131 103 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Table 48. DSPI CMOS master modified timing (full duplex and output only) MTFE = 1, CPHA = 0 or 1(1) (continued) Value(2) Condition # Symbol C Characteristic Pad drive(3) Unit Load (CL) Min Max SOUT data valid time (after SCK edge) 9 tSUO CC D SOUT data valid time from SCK CPHA = 0(10) SOUT data valid time from SCK CPHA = 1(10) SOUT and SCK drive strength Very strong 25 pF -- 7.0 + tSYS(5) tSYS(5) Strong 50 pF -- 8.0 + Medium 50 pF -- 16.0 + tSYS(5) ns SOUT and SCK drive strength Very strong 25 pF -- 7.0 Strong 50 pF -- 8.0 Medium 50 pF -- 16.0 25 pF -7.7 + tSYS(5) -- 50 pF -11.0 + tSYS(5) -- -15.0 + tSYS(5) -- ns SOUT data hold time (after SCK edge) 10 tHO CC D SOUT data hold time after SCK CPHA = 0(11) SOUT and SCK drive strength Very strong Strong Medium SOUT data hold time after SCK CPHA = 1(11) 50 pF ns SOUT and SCK drive strength Very strong 25 pF -7.7 -- Strong 50 pF -11.0 -- Medium 50 pF -15.0 -- ns 1. All output timing is worst case and includes the mismatching of rise and fall times of the output pads. 2. All timing values for output signals in this table are measured to 50% of the output voltage. 3. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation. 4. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 5. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min tSYS = 10 ns). 6. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge of DSPI_CLKn). 7. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time. 8. PCSx and PCSS using same pad configuration. 9. Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL voltage thresholds. 88/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics 10. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using DSPI_ MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set to 1. 11. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same value. Figure 28. DSPI CMOS master mode -- modified timing, CPHA = 0 tCSC tASC PCSx tSCK tSDC SCK Output (CPOL = 0) SCK Output (CPOL = 1) SIN tSDC tSUI tHI First Data Data Last Data tSUO SOUT tHO Data First Data Last Data Figure 29. DSPI CMOS master mode -- modified timing, CPHA = 1 PCSx SCK Output (CPOL = 0) SCK Output (CPOL = 1) tSUI SIN tHI tHI Data First Data tSUO SOUT First Data DS11758 Rev 5 Data Last Data tHO Last Data 89/131 103 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Figure 30. DSPI PCS strobe (PCSS) timing (master mode) tPCSC tPASC PCSS PCSx 3.17.2.2 Slave mode timing Table 49. DSPI CMOS slave timing -- full duplex -- normal and modified transfer formats (MTFE = 0/1) Condition # Symbol C Characteristic Pad Drive Load Min Max Unit 1 tSCK CC D SCK Cycle Time(1) -- -- 62 -- ns 2 tCSC SR D SS to SCK Delay(1) -- -- 16 -- ns D Delay(1) -- -- 16 -- ns -- -- 30 -- ns Very strong 25 pF -- 50 ns Strong 50 pF -- 50 ns Medium 50 pF -- 60 ns (2) (3) Very strong 25 pF -- 5 ns (SS inactive to SOUT HighZ or invalid) Strong 50 pF -- 5 ns Medium 50 pF -- 10 ns 3 tASC SR SCK to SS Cycle(1) 4 tSDC CC D SCK Duty 5 tA CC D Slave Access Time(1) (2) (3) (SS active to SOUT driven) 6 tDIS CC D Slave SOUT Disable Time(1) 9 tSUI CC D Data Setup Time for Inputs(1) -- -- 10 -- ns 10 tHI CC D Data Hold Time for Inputs(1) -- -- 10 -- ns 11 tSUO CC D SOUT Valid Time(1) (2) (3) (after SCK edge) Very strong 25 pF -- 30 ns Strong 50 pF -- 30 ns Medium 50 pF -- 50 ns Very strong 25 pF 2.5 -- ns Strong 50 pF 2.5 -- ns Medium 50 pF 2.5 -- ns 12 tHO CC D (1) (2) (3) SOUT Hold Time (after SCK edge) 1. Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL voltage thresholds. 2. All timing values for output signals in this table, are measured to 50% of the output voltage. 3. All output timing is worst case and includes the mismatching of rise and fall times of the output pads. 90/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Figure 31. DSPI slave mode -- modified transfer format timing (MFTE = 0/1) CPHA = 0 tASC tCSC SS tSCK SCK Input (CPOL = 0) tSDC tSDC SCK Input (CPOL = 1) tSUO tA First Data SOUT Data tDIS Last Data tSUI tHI Data First Data SIN tHO Last Data Figure 32. DSPI slave mode -- modified transfer format timing (MFTE = 0/1) CPHA = 1 SS SCK Input (CPOL = 0) SCK Input (CPOL = 1) tSUO tA SOUT tHO First Data tSUI SIN 3.17.3 Data Last Data Data Last Data tDIS tHI First Data Ethernet timing The Ethernet provides both MII and RMII interfaces. The MII and RMII signals can be configured for either CMOS or TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V. Please check the device pinout details to review the packages supporting MII and RMII. DS11758 Rev 5 91/131 103 Electrical characteristics 3.17.3.1 SPC584Gx, SPC58EGx, SPC58NGx MII receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK) The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency. Table 50. MII receive signal timing(1) Value Symbol C Characteristic Unit Min Max M1 CC D RXD[3:0], RX_DV, RX_ER to RX_CLK setup 5 -- ns M2 CC D RX_CLK to RXD[3:0], RX_DV, RX_ER hold 5 -- ns M3 CC D RX_CLK pulse width high 35% 65% RX_CLK period M4 CC D RX_CLK pulse width low 35% 65% RX_CLK period 1. All timing specifications are referenced from RX_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V. Figure 33. MII receive signal timing diagram M3 RX_CLK (input) M4 RXD[3:0] (inputs) RX_DV RX_ER M1 3.17.3.2 M2 MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK) The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency. The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from either the rising or falling edge of TX_CLK, and the timing is the same in either case. This option allows the use of non-compliant MII PHYs. Refer to the Microcontroller Reference Manual's Ethernet chapter for details of this option and how to enable it. 92/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Table 51. MII transmit signal timing(1) Value(2) Symbol C Characteristic Unit Min Max M5 CC D TX_CLK to TXD[3:0], TX_EN, TX_ER invalid 5 -- ns M6 CC D TX_CLK to TXD[3:0], TX_EN, TX_ER valid -- 25 ns M7 CC D TX_CLK pulse width high 35% 65% TX_CLK period M8 CC D TX_CLK pulse width low 35% 65% TX_CLK period 1. All timing specifications are referenced from TX_CLK = 1.4 V to the valid output levels, 0.8 V and 2.0 V. 2. Output parameters are valid for CL = 25 pF, where CL is the external load to the device. The internal package capacitance is accounted for, and does not need to be subtracted from the 25 pF value Figure 34. MII transmit signal timing diagram M7 TX_CLK (input) M5 M8 TXD[3:0] (outputs) TX_EN TX_ER M6 3.17.3.3 MII async inputs signal timing (CRS and COL) Table 52. MII async inputs signal timing Value Symbol M9 C Characteristic Unit CC D CRS, COL minimum pulse width Min Max 1.5 -- TX_CLK period Figure 35. MII async inputs timing diagram CRS, COL M9 DS11758 Rev 5 93/131 103 Electrical characteristics 3.17.3.4 SPC584Gx, SPC58EGx, SPC58NGx MII and RMII serial management channel timing (MDIO and MDC) The Ethernet functions correctly with a maximum MDC frequency of 2.5 MHz. Figure 36. MII serial management channel timing diagram M14 M15 MDC (output) M10 MDIO (output) M11 MDIO (input) M12 3.17.3.5 M13 MII and RMII serial management channel timing (MDIO and MDC) The Ethernet functions correctly with a maximum MDC frequency of 2.5 MHz. Table 53. MII serial management channel timing(1) Value Symbol C Characteristic Unit Min Max M10 CC D MDC falling edge to MDIO output invalid (minimum propagation delay) 0 -- ns M11 CC D MDC falling edge to MDIO output valid (max prop delay) -- 25 ns M12 CC D MDIO (input) to MDC rising edge setup 10 -- ns M13 CC D MDIO (input) to MDC rising edge hold 0 -- ns M14 CC D MDC pulse width high 40% 60% MDC period M15 CC D MDC pulse width low 40% 60% MDC period 1. All timing specifications are referenced from MDC = 1.4 V (TTL levels) to the valid input and output levels, 0.8 V and 2.0 V (TTL levels). For 5 V operation, timing is referenced from MDC = 50% to 2.2 V/3.5 V input and output levels. 94/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Table 54. RMII serial management channel timing(1) Value Symbol C Characteristic Unit Min Max M10 CC D MDC falling edge to MDIO output invalid (minimum propagation delay) 0 -- ns M11 CC D MDC falling edge to MDIO output valid (max prop delay) -- 25 ns M12 CC D MDIO (input) to MDC rising edge setup 10 -- ns M13 CC D MDIO (input) to MDC rising edge hold 0 -- ns M14 CC D MDC pulse width high 40% 60% MDC period M15 CC D MDC pulse width low 40% 60% MDC period 1. All timing specifications are referenced from MDC = 1.4 V (TTL levels) to the valid input and output levels, 0.8 V and 2.0 V (TTL levels). For 5 V operation, timing is referenced from MDC = 50% to 2.2 V/3.5 V input and output levels. Figure 37. MII serial management channel timing diagram M14 M15 MDC (output) M10 MDIO (output) M11 MDIO (input) M12 3.17.3.6 M13 RMII receive signal timing (RXD[1:0], CRS_DV) The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1%. There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency, which is half that of the REF_CLK frequency. DS11758 Rev 5 95/131 103 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Table 55. RMII receive signal timing(1) Value Symbol C Characteristic Unit Min Max R1 CC D RXD[1:0], CRS_DV to REF_CLK setup 4 -- ns R2 CC D REF_CLK to RXD[1:0], CRS_DV hold 2 -- ns R3 CC D REF_CLK pulse width high 35% 65% REF_CLK period R4 CC D REF_CLK pulse width low 35% 65% REF_CLK period 1. All timing specifications are referenced from REF_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V. Figure 38. RMII receive signal timing diagram R3 REF_CLK (input) R4 RXD[1:0] (inputs) CRS_DV R1 3.17.3.7 R2 RMII transmit signal timing (TXD[1:0], TX_EN) The transmitter functions correctly up to a REF_CLK maximum frequency of 50 MHz + 1%. There is no minimum frequency requirement. The system clock frequency must be at least equal to or greater than the TX_CLK frequency, which is half that of the REF_CLK frequency. The transmit outputs (TXD[1:0], TX_EN) can be programmed to transition from either the rising or falling edge of REF_CLK, and the timing is the same in either case. This option allows the use of non-compliant RMII PHYs. Table 56. RMII transmit signal timing(1) Value Symbol C Characteristic Unit Min Max R5 CC D REF_CLK to TXD[1:0], TX_EN invalid 2 -- ns R6 CC D REF_CLK to TXD[1:0], TX_EN valid -- 14 ns R7 CC D REF_CLK pulse width high 35% 65% REF_CLK period R8 CC D REF_CLK pulse width low 35% 65% REF_CLK period 1. All timing specifications are referenced from REF_CLK = 1.4 V to the valid output levels, 0.8 V and 2.0 V 96/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Figure 39. RMII transmit signal timing diagram R7 REF_CLK (input) R5 R8 TXD[1:0] (outputs) TX_EN R6 3.17.4 FlexRay timing This section provides the FlexRay Interface timing characteristics for the input and output signals. These are recommended numbers as per the FlexRay EPL v3.0 specification, and subject to change per the final timing analysis of the device. 3.17.4.1 TxEN Figure 40. TxEN signal TxEN 80 % 20 % dCCTxENFALL dCCTxENRISE Table 57. TxEN output characteristics(1) (2) Value Symbol C Characteristic Unit Min Max dCCTxENRISE25 CC D Rise time of TxEN signal at CC -- 9 ns dCCTxENFALL25 CC D Fall time of TxEN signal at CC -- 9 ns DS11758 Rev 5 97/131 103 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Table 57. TxEN output characteristics(1) (2) (continued) Value Symbol C Characteristic Unit Min Max dCCTxEN01 CC D Sum of delay between Clk to Q of the last FF and the final output buffer, rising edge -- 25 ns dCCTxEN10 CC D Sum of delay between Clk to Q of the last FF and the final output buffer, falling edge -- 25 ns 1. TxEN pin load maximum 25 pF. 2. Pad configured as VERY STRONG. Figure 41. TxEN signal propagation delays PE_Clk TxEN dCCTxEN10 98/131 dCCTxEN01 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx 3.17.4.2 Electrical characteristics TxD Figure 42. TxD signal TxD dCCTxD50% 80 % 50 % 20 % dCCTxDRISE dCCTxDFALL Table 58. TxD output characteristics(1),(2),(3) Value Symbol dCCTxAsym C Characteristic CC D Asymmetry of sending CC at 25 pF load (= dCCTxD50% - 100 ns) dCCTxDRISE25+dCCTxDFALL25 CC D Sum of Rise and Fall time of TxD signal at the output pin(4) D Unit Min Max -2.45 2.45 ns -- 9(5) ns -- 9(6) dCCTxD01 CC D Sum of delay between Clk to Q of the last FF and the final output buffer, rising edge -- 25 ns dCCTxD10 CC D Sum of delay between Clk to Q of the last FF and the final output buffer, falling edge -- 25 ns 1. TxD pin load maximum 25 pF. 2. Specifications valid according to FlexRay EPL 3.0.1 standard with 20%-80% levels and a 10 pF load at the end of a 50 Ohm, 1 ns stripline. Please refer to the Very Strong I/O pad specifications. 3. Pad configured as VERY STRONG. 4. Sum of transition time simulation is performed according to Electrical Physical Layer Specification 3.0.1 and the entire temperature range of the device has been taken into account. 5. VDD_HV_IO = 5.0 V 10%, Transmission line Z = 50 ohms, tdelay = 1 ns, CL = 10 pF. 6. VDD_HV_IO = 3.3 V 10%, Transmission line Z = 50 ohms, tdelay = 0.6 ns, CL = 10 pF. DS11758 Rev 5 99/131 103 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Figure 43. TxD Signal propagation delays PE_Clk* TxD dCCTxD10 dCCTxD01 * FlexRay Protocol Engine Clock 3.17.4.3 RxD Table 59. RxD input characteristics Value Symbol C Characteristic Unit Min Max CC D Input capacitance on RxD pin -- 7 pF uCCLogic_1 CC D Threshold for detecting logic high 35 70 % uCCLogic_0 CC D Threshold for detecting logic low 30 65 % dCCRxD01 CC D Sum of delay from actual input to the D input of the first FF, rising edge -- 10 ns dCCRxD10 CC D Sum of delay from actual input to the D input of the first FF, falling edge -- 10 ns C_CCRxD dCCRxAsymAccept15 CC D Acceptance of asymmetry at receiving CC with 15 pF load -31.5 44 ns dCCRxAsymAccept25 CC D Acceptance of asymmetry at receiving CC with 25 pF load -30.5 43 ns 3.17.5 CAN timing The following table describes the CAN timing. 100/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Table 60. CAN timing Value Symbol tP(RX:TX) tPLP(RX:TX) 3.17.6 C CC D CC D CC D CC D CC D CC D CC D CC D Parameter Condition CAN controller propagation delay time standard pads CAN controller propagation delay time low power pads Unit Min Typ Max Medium type pads 25pF load -- -- 70 Medium type pads 50pF load -- -- 80 STRONG, VERY STRONG type pads 25pF load -- -- 60 STRONG, VERY STRONG type pads 50pF load -- -- 65 Medium type pads 25pF load -- -- 90 Medium type pads 50pF load -- -- 100 STRONG, VERY STRONG type pads 25pF load -- -- 80 STRONG, VERY STRONG type pads 50pF load -- -- 85 ns ns UART timing UART channel frequency support is shown in the following table. Table 61. UART frequency support LINFlexD clock frequency LIN_CLK (MHz) Oversampling rate 80 16 Voting scheme Max usable frequency (Mbaud) 3:1 majority voting 8 6 5 10 Limited voting on one sample with configurable sampling point 4 100 16 5 3:1 majority voting 16 6.25 12.5 Limited voting on one sample with configurable sampling point 4 3.17.7 13.33 20 8 6 5 16.67 20 25 I2C timing The I2C AC timing specifications are provided in the following tables. DS11758 Rev 5 101/131 103 Electrical characteristics SPC584Gx, SPC58EGx, SPC58NGx Table 62. I2C input timing specifications -- SCL and SDA(1) Value No. Symbol C Parameter Unit Min Max 1 -- CC D Start condition hold time 2 -- PER_CLK Cycle(2) 2 -- CC D Clock low time 8 -- PER_CLK Cycle 3 -- CC D Bus free time between Start and Stop condition 4.7 -- s 4 -- CC D Data hold time 0.0 -- ns 5 -- CC D Clock high time 4 -- PER_CLK Cycle 6 -- CC D Data setup time 0.0 -- ns 7 -- CC D Start condition setup time (for repeated start condition only) 2 -- PER_CLK Cycle -- CC D Stop condition setup time 2 -- PER_CLK Cycle 8 2 1. I C input timing is valid for Automotive and TTL inputs levels, hysteresis enabled, and an input edge rate no slower than 1 ns (10% - 90%). 2. PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter in the device reference manual for more detail. Table 63. I2C output timing specifications -- SCL and SDA(1),(2),(3),(4) Value No. Symbol C Parameter Unit Min Max 1 -- CC D Start condition hold time 6 -- PER_CLK Cycle(5) 2 -- CC D Clock low time 10 -- PER_CLK Cycle 3 -- CC D Bus free time between Start and Stop condition 4.7 -- s 4 -- CC D Data hold time 7 -- PER_CLK Cycle 5 -- CC D Clock high time 10 -- PER_CLK Cycle 6 -- CC D Data setup time 2 -- PER_CLK Cycle 7 -- CC D Start condition setup time (for repeated start condition only) 20 -- PER_CLK Cycle 8 -- CC D Stop condition setup time 10 -- PER_CLK Cycle 1. All output timing is worst case and includes the mismatching of rise and fall times of the output pads. 2. Output parameters are valid for CL = 25 pF, where CL is the external load to the device (lumped). The internal package capacitance is accounted for, and does not need to be subtracted from the 25 pF value. 3. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may cause incorrect operation. 4. Programming the IBFD register (I2C bus Frequency Divider) with the maximum frequency results in the minimum output timings listed. The I2C interface is designed to scale the data transition time, moving it to the middle of the SCL low period. The actual position is affected by the pre-scale and division values programmed in the IBC field of the IBFD register. 5. PER_CLK is the SoC peripheral clock, which drives the I2C BIU and module clock inputs. See the Clocking chapter in the device reference manual for more detail. 102/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Electrical characteristics Figure 44. I2C input/output timing 2 5 SCL 1 4 8 6 7 3 SDA DS11758 Rev 5 103/131 103 Package information 4 SPC584Gx, SPC58EGx, SPC58NGx Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. The following table lists the case numbers for SPC584Gx, SPC58EGx, SPC58NGx. Table 64. Package case numbers 104/131 Package Type Device Type Package reference eTQFP144 Production 7386636 eLQFP176 Production 8153717 FPBGA292 Production 8537045 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx 4.1 Package information eTQFP144 package information Figure 45. eTQFP144 package outline 1/2 PACKAGE MECHANICAL DRAWINGS DS11758 Rev 5 105/131 114 Package information SPC584Gx, SPC58EGx, SPC58NGx Figure 46. eTQFP144 package outline 2/2 PACKAGE MECHANICAL DRAWINGS 106/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Package information Table 65. eTQFP144 package mechanical data Dimensions Symbol Min Typ Max Degrees 0 3.5 7 1 0 -- -- 2 10 12 14 3 10 12 14 Millimeters A(1) -- -- 1.20 A1(2) 0.05 -- 0.15 1 0.95 1.00 1.05 b(3),(4) 0.17 0.22 0.27 b14 0.17 0.20 0.23 c 0.09 -- 0.20 c14 0.09 -- 0.16 A2 4 (5) 22.00 BSC D D1(6),(7) D2(8) D3 (9) 20.00 BSC -- -- 8.96 7.30 -- -- e 0.50 BSC E5 22.00 BSC 67 20.00 BSC E1 8 -- -- 8.96 E39 7.30 -- -- L 0.45 0.60 0.75 E2 L1 1.00 REF (10) 144 N R1 0.08 -- -- R2 0.08 -- 0.20 S 0.20 -- -- 1. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude beyond that surface. 2. A1 is defined as the distance from the seating plane to the lowest point on the package body. 3. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum "b" dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages. 4. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. DS11758 Rev 5 107/131 114 Package information SPC584Gx, SPC58EGx, SPC58NGx 5. To be determined at seating datum plane C. 6. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm. 7. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is "0.25 mm" 8. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located (if present). It includes all metal protrusions from exposed pad itself. Type of exposed pad is variable depending on leadframe pad design (T1, T2, T3), as shown in the figure below. End user should verify D2 and E2 dimensions according to specific device application. 9. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of exposed pad which is guaranteed to be free from resin flashes/bleeds, bordered by internal edge of inner groove. 10. "N" is the max number of terminal positions for the specified body size. Table 66. eTQFP144 package tolerance of form and position Symbol(1) (2) (3) Dimensions aaa 0.20 bbb 0.20 ccc 0.08 ddd 0.08 1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994. 2. All Dimensions are in millimeters. 3. For Symbols, Recommended Values and Tolerances see Table below: 108/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx 4.2 Package information eLQFP176 package information Figure 47. eLQFP176 package outline 1/2 PACKAGE MECHANICAL DRAWINGS DS11758 Rev 5 109/131 114 Package information SPC584Gx, SPC58EGx, SPC58NGx Figure 48. eLQFP176 package outline 2/2 110/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Package information Table 67. eLQFP176 package mechanical data Dimensions Symbol Min Typ Max Degrees 0 3.5 7 1 0 -- -- 2 10 12 14 3 10 12 14 Millimeters A(1) -- -- 1.60 A1(2) 0.05 -- 0.15 1 1.35 1.40 1.45 b(3),(4) 0.17 0.22 0.27 b14 0.17 0.20 0.23 c 0.09 -- 0.20 c14 0.09 -- 0.16 A2 4 (5) 26.00 BSC D D1(6),(7) D2(8) D3 (9) 24.00 BSC -- -- 8.97 7.30 -- -- e 0.50 BSC E5 26.00 BSC 67 24.00 BSC E1 8 -- -- 8.97 E39 7.30 -- -- L 0.45 0.60 0.75 E2 L1 1.00 REF (10) 176 N R1 0.08 -- -- R2 0.08 -- 0.20 S 0.20 -- -- 1. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude beyond that surface. 2. A1 is defined as the distance from the seating plane to the lowest point on the package body. 3. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum "b" dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages. 4. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. DS11758 Rev 5 111/131 114 Package information SPC584Gx, SPC58EGx, SPC58NGx 5. To be determined at seating datum plane C. 6. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm. 7. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is "0.25 mm" 8. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located (if present). It includes all metal protrusions from exposed pad itself. Type of exposed pad is variable depending on leadframe pad design (T1, T2, T3), as shown in the figure below. End user should verify D2 and E2 dimensions according to specific device application. 9. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of exposed pad which is guaranteed to be free from resin flashes/bleeds, bordered by internal edge of inner groove. 10. "N" is the max number of terminal positions for the specified body size. Table 68. eTQFP176 package tolerance of form and position Symbol(1) (2) (3) Dimensions aaa 0.20 bbb 0.20 ccc 0.08 ddd 0.08 1. Dimensioning and tolerancing schemes conform to ASME Y14.5M-1994. 2. All Dimensions are in millimeters. 3. For Symbols, Recommended Values and Tolerances see Table below: 112/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx 4.3 Package information FPBGA292 package information Figure 49. FPBGA292 package outline PACKAGE MECHANICAL DRAWINGS DS11758 Rev 5 113/131 114 Package information SPC584Gx, SPC58EGx, SPC58NGx Table 69. FPBGA292 package mechanical data Dimensions REF. Millimeters Min Typ Max A(1) - - 1.8 A1 0.35 - - A2 - 0.53 - A4 - - 0.80 D 16.85 17.00 17.15 D1 - 15.20 - E 16.85 17.00 17.15 E1 - 15.20 - e - 0.80 - 0.50 0.55 0.60 Z - 0.90 - aaa - - 0.15 bbb - - 0.10 ddd - - 0.12 - - 0.15 - - 0.08 (2) b (3) eee fff(4) 1. FPBGA stands for Fine Pitch Plastic Ball Grid Array. Fine pitch: e < 1.00mm pitch. Low Profile: The total profile height (Dim A) is measured from the seating plane to the top of the component. The maximum total package height is calculated by the following methodology: Amax = A1(TYP) + A2(TYP) + A4(TYP) + (A1)2 + (A2)2 + (A4)2 (tolerance values) 2. The typical ball diameter before mounting is 0.55mm. 3. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. 4. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective zone eee above. The axis of each ball must lie simultaneously in both tolerance zones. 114/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx 4.4 Package thermal characteristics Package thermal characteristics The following tables describe the thermal characteristics of the device. The parameters in this chapter have been evaluated by considering the device consumption configuration reported in the Section 3.7: Device consumption 4.4.1 eTQFP144 Table 70. Thermal characteristics for 144 exposed pad eTQFP package(1) Symbol RJA C CC Parameter D Junction-to-Ambient, Natural Convection(2) (2) Conditions Value Unit Four layer board (2s2p) 21.4 C/W at 200 ft./min., four layer board (2s2p) 15.7 C/W RJMA CC D RJB CC D Junction-to-board(3) -- 8.5 C/W RJCtop CC D Junction-to-case top(4) -- 5.4 C/W -- 1 C/W Natural convection 1 C/W RJCbottom JT CC CC D D Junction-to-Moving-Air, Ambient Junction-to-case bottom(5) (6) Junction-to-package top 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. 3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 5. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation without any interface resistance. 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 4.4.2 LQFP176 Table 71. Thermal characteristics for 176 exposed pad LQFP package(1) Symbol C Parameter (2) Conditions Value Unit Four layer board (2s2p) 20.9 C/W RJA CC D Junction-to-Ambient, Natural Convection RJMA CC D Junction-to-Moving-Air, Ambient(2) at 200 ft./min., four layer board (2s2p) 15.3 C/W RJB CC D Junction-to-board(3) -- 9 C/W -- 7.3 C/W -- 1 C/W Natural convection 1 C/W RJCtop RJCbottom JT CC CC CC D D D Junction-to-case top Junction-to-case (4) bottom(5) Junction-to-package top(6) 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal. 3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. DS11758 Rev 5 115/131 118 Package thermal characteristics SPC584Gx, SPC58EGx, SPC58NGx 4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 5. Thermal resistance between the die and the exposed pad ground on the bottom of the package based on simulation without any interface resistance. 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 4.4.3 BGA292 Table 72. Thermal characteristics for 292-pin BGA(1) Symbol RJA C CC Parameter D Junction-to-Ambient, Natural Convection (2) Ambient(2) Conditions Value Unit Four layer board (2s2p) 21.9 C/W at 200 ft./min., four layer board (2s2p) NA C/W RJMA CC D RJB CC D Junction-to-board(3) -- 10.3 C/W RJC CC D Junction-to-case(4) -- 6.7 C/W Natural convection 1 C/W JT CC D Junction-to-Moving-Air, Junction-to-package top(5) 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-6 with the board (JESD51-9) horizontal. 3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 5. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 4.4.4 General notes for specifications at maximum junction temperature An estimation of the chip junction temperature, TJ, can be obtained from the equation: Equation 1 TJ = TA + (RJA * PD) where: TA = ambient temperature for the package (C) RJA = junction-to-ambient thermal resistance (C/W) PD = power dissipation in the package (W) The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The differences between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the: 116/131 * Construction of the application board (number of planes) * Effective size of the board which cools the component * Quality of the thermal and electrical connections to the planes * Power dissipated by adjacent components DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Package thermal characteristics Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leaves the planes virtually disconnected, the thermal performance is also greatly reduced. As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has: * One oz. (35 micron nominal thickness) internal planes * Components are well separated * Overall power dissipation on the board is less than 0.02 W/cm2 The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation: Equation 2 TJ = TB + (RJB * PD) where: TB = board temperature for the package perimeter (C) RJB = junction-to-board thermal resistance (C/W) per JESD51-8 PD = power dissipation in the package (W) When the heat loss from the package case to the air does not factor into the calculation, the junction temperature is predictable if the application board is similar to the thermal test condition, with the component soldered to a board with internal planes. The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance: Equation 3 RJA = RJC + RCA where: RJA = junction-to-ambient thermal resistance (C/W) RJC = junction-to-case thermal resistance (C/W) RCA = case to ambient thermal resistance (C/W) RJC is device related and is not affected by other factors. The thermal environment can be controlled to change the case-to-ambient thermal resistance, RCA. For example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where 90% of the heat flow is through the case to heat sink to ambient. For most packages, a better model is required. DS11758 Rev 5 117/131 118 Package thermal characteristics SPC584Gx, SPC58EGx, SPC58NGx A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple estimations and for computational fluid dynamics (CFD) thermal models. More accurate compact Flotherm models can be generated upon request. To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter (JT) to determine the junction temperature by measuring the temperature at the top center of the package case using the following equation: Equation 4 TJ = TT + (JT x PD) where: TT = thermocouple temperature on top of the package (C) JT = thermal characterization parameter (C/W) PD = power dissipation in the package (W) The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire. When board temperature is perfectly defined below the device, it is possible to use the thermal characterization parameter (JPB) to determine the junction temperature by measuring the temperature at the bottom center of the package case (exposed pad) using the following equation: Equation 5 TJ = TB + (JPB x PD) where: TT = thermocouple temperature on bottom of the package (C) JT = thermal characterization parameter (C/W) PD = power dissipation in the package (W) 118/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx 5 Ordering information Ordering information Figure 50. Ordering information scheme Example code: SPC58 N G 84 C3 Q E Product identifier Core Product Memory Package Frequency Custom version H Security 0 Y Silicon revision Packing Y = Tray X = Tape and Reel (pin1 top right) 0 = 1st version 1 = 2nd version 0 = No security and no ASIL-D C = Security HW (HSM) S = Safety (ASIL-D) H = ASIL-D + Security HW (HSM) 0 = 8x ISO CAN FD, FlexRay E = Ethernet 0 T = Ethernet 0 and 1 X = Extended feature (a) E = 120 MHz at 105 oC F = 160 MHz at 105 oC G = 180 MHz at 105 oC N = 120 MHz at 125 oC P = 160 MHz at 125 oC Q = 180 MHz at 125 oC E7 = eLQFP176 E5 = eTQFP144 C3 = FPBGA292 84 = 6 MB 80 = 4 MB G = SPC58NGx family N = Triple computing e200z4 core (CPU_2 + CPU_1 + CPU_0) 4 = Single computing e200z4 core (CPU_2) E = Dual computing e200z4 core (CPU_2 + CPU_0) SPC58 = Power Architecture in 40 nm a: 2nd checker core, additional RAM, Microsecond channel, SENT bus. Available extended features are described in a customer specific addendum. DS11758 Rev 5 119/131 121 Ordering information SPC584Gx, SPC58EGx, SPC58NGx Table 73. Code Flash options SPC58xG84 (6M) SPC58xG80 (4M) Partition Start address End address 16 16 0 0x00FC0000 0x00FC3FFF 16 16 0 0x00FC4000 0x00FC7FFF 16 16 1 0x00FC8000 0x00FCBFFF 16 16 1 0x00FCC000 0x00FCFFFF 32 32 0 0x00FD0000 0x00FD7FFF 32 32 1 0x00FD8000 0x00FDFFFF 64 64 0 0x00FE0000 0x00FEFFFF 64 64 0 0x00FF0000 0x00FFFFFF 128 128 0 0x01000000 0x0101FFFF 128 128 1 0x01020000 0x0103FFFF 256 256 0 0x01040000 0x0107FFFF 256 256 0 0x01080000 0x010BFFFF 256 256 0 0x010C0000 0x010FFFFF 256 256 0 0x01100000 0x0113FFFF 256 256 0 0x01140000 0x0117FFFF 256 256 0 0x01180000 0x011BFFFF 256 256 0 0x011C0000 0x011FFFFF 256 256 1 0x01200000 0x0123FFFF 256 256 1 0x01240000 0x0127FFFF 256 256 1 0x01280000 0x012BFFFF 256 256 1 0x012C0000 0x012FFFFF 256 256 1 0x01300000 0x0133FFFF 256 256 1 0x01340000 0x0137FFFF 256 256 1 0x01380000 0x013BFFFF 256 NA 5 0x013C0000 0x013FFFFF 256 NA 5 0x01400000 0x0143FFFF 256 NA 5 0x01440000 0x0147FFFF 256 NA 5 0x01480000 0x014BFFFF 256 NA 5 0x014C0000 0x014FFFFF 256 NA 5 0x01500000 0x0153FFFF 256 NA 5 0x01540000 0x0157FFFF 256 NA 5 0x01580000 0x015BFFFF 120/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Ordering information Table 74. RAM options(1) SPC58EGx SPC58NGx SPC584G84 SPC584G80 Type Start address End address 768 640 512 128 128 128 PRAMC_0 0x40060000 0x4007FFFF 96 96 96 PRAMC_1 0x40080000 0x40097FFF 64 64 NA PRAMC_1 0x40098000 0x400A7FFF 8 8 8 PRAMC_2 (STBY) 0x400A8000 0x400A9FFF 120 120 120 PRAMC_2 (STBY) 0x400AA000 0x400C7FFF 128 128 128 PRAMC_2 (STBY) 0x400C8000 0x400E7FFF 64 64 NA PRAMC_3 0x400E8000 0x400F7FFF 64 NA NA D-MEM CPU_0 0x50800000 0x5080FFFF 64 NA NA D-MEM CPU_1 0x51800000 0x5180FFFF 32 32 32 D-MEM CPU_2 0x52800000 0x52807FFF 1. RAM size is the sum of TCM and SRAM. DS11758 Rev 5 121/131 121 Revision history 6 SPC584Gx, SPC58EGx, SPC58NGx Revision history Table 75. Document revision history Date Revision 28-Jul-2016 1 Changes Initial release. Changed Microsoft Excel(R) workbook attached to this document (was SPC584Gx_SPC58EGx_SPC58NGx_IO_Definition_v1.xlsx dated July 26, 2016). For details, refer to the sheet Revision History of the attached file "SPC584Gx_SPC58EGx_SPC58NGx_IO_Definition_v2.xlsx". 09-Sep-2016 2 Updated Section 3.12: ADC system For ADC12 bit, "FAST SAR" updated to "Fast SAR" and "Slow SAR" updated to "Slow SAR (SARADC_B)" For ADC10 bit, instance of "Slow SAR" removed and "FAST SAR" replaced with "-". 122/131 DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Revision history Table 75. Document revision history (continued) Date Revision Changes Following are the changes for this release of the document: 06-Jul-2017 3 Updated the cover page. Section 3.1: Introduction: - Removed text "The IPs and...for the details". - Removed the two notes. Updated the Table 2: SPC584Gx, SPC58EGx, SPC58NGx features summary Updated the Figure 1: Block diagram Table 3: Parameter classifications: Updated the description of classification tag "T". Section 3.2: Absolute maximum ratings: - Added text "Exposure to absolute ... reliability" - Added text "even momentarily" Table 4: Absolute maximum ratings: - For parameter "IINJ", text "DC" removed from description. - Updated values in conditions column. - Added parameter TTRIN. - For parameter "TSTG", maximum value updated from "175" to "125" - Added new parameter "TPAS" - For parameter "IINJ", description updated from "maximum...PAD" to "maximum DC...pad" Table 5: Operating conditions: - For parameter "VDD_LV", changed the classification from "D" to "P" - Renamed the "Wait State configuration" table to "PRAM wait state configuration" - Footnote "1.260 V - 1.290 V range .. temperature profile" updated to Text "... average supply value below or equal to 1.236 V ..." - For parameter "IINJ1" description, text "DC" removed. - Added note "In the range [1.14-1.08]V, the device...." to parameter VDD_LV. - Added parameter IINJ2 - Removed note "Core voltage as ...." - Removed parameter "VRAMP_LV". - Updated the table footnote "Positive and negative Dynamic current...." Table 6: PRAM wait states configuration: Added this table. Table 9: Device consumption: - Updated the table and it's values. Table 12: I/O pull-up/pull-down electrical characteristics: - Added note "When the device enters into standby mode... an ADC function." DS11758 Rev 5 123/131 130 Revision history SPC584Gx, SPC58EGx, SPC58NGx Table 75. Document revision history (continued) Date 06-Jul-2017 124/131 Revision Changes 3 (cont') Table 13: WEAK/SLOW I/O output characteristics: - Added "10%-90% in description of parameter "tTR_W". - For parameter "Fmax_W", updated condition "25 pF load" to "CL=25pF" - For parameter "tTR_S", changed min value (25 pF load) from "4" to "3" - Changed min value (50 pF load) from "6" to "5" - For parameter "|tSKEW_W|", changed max value from "30" to "25". Table 14: MEDIUM I/O output characteristics: - Added "10%-90% in description of parameter "tTR_M". - For parameter "|tSKEW_W|", changed max value from "30" to "25". Table 15: STRONG/FAST I/O output characteristics: - Added "10%-90% in description of parameter "tTR_S". - Parameter "IDCMAX_S" updated: - Condition added "VDD=5V+10% - Condition added "VDD=3.3V+10% Max value updated to 5.5mA - For parameter "|tSKEW_W|", changed max value from "30" to "25". Table 17: I/O consumption: Updated all the max values of parameters IDYN_W and IDYN_M Section 3.8: I/O pad specification: - Replaced all occurences of "50 pF load" with "CL=50pF". - Removed note "The external ballast...." Section 3.8.2: I/O output DC characteristics: - Added note "10%/90% is the...." - "WEAK" to "WEAK/SLOW" - "STRONG" to "STRONG/FAST" - "VERY STRONG" to "VERY STRONG / VERY FAST" Table 19: Reset Pad state during power-up and reset: - Added this table. Section 3.11: Oscillators: - Removed figure "Test circuit" Table 20: PLL0 electrical characteristics: - For parameter "IPLL0", classification changed from "C" to "T". - Footnote "Jitter values...measurement" added for parameters: |PLL0PHI0SPJ| |PLL0PHI1SPJ| PLL0LTJ Table 21: PLL1 electrical characteristics: - For parameter "IPLL1", classification changed from "C" to "T". - Footnote "Jitter values...measurement" added for parameter "|PLL1PHI0SPJ|" DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Revision history Table 75. Document revision history (continued) Date 06-Jul-2017 Revision Changes 3 (cont') Table 22: External 40 MHz oscillator electrical specifications: - Classification for parameters "CS_EXTAL" and "CS_EXTAL" changed from "T" to "D". - Updated classification, conditions, min and max values for parameter "gm". - Footnote "Ixatl is the oscillator...Test circuit is shown in Figure 8" modified to "Ixatl is the oscillator...startup of the oscillator". - Minimum value of parameter "VIHEXT" updated from "VREF+0.6" to "VREF+0.75" - Maximum value of parameter "VILEXT" updated from "VREF-0.6" to "VREF-0.75" - Parameter "gm", value "D" updated to "P" for "fXTAL < 8 MHz", and "D" for others. - Footnote "This parameter is...100% tested" updated to "Applies to an...to crystal mode". Also added to parameter "VILEXT". - For parameters "VIHEXT" and "VILEXT", Condition "-" updated to "VREF = 0.29 * VDD_HV_IO_JTAG" - Parameter "gm", value "D" updated to "P" for "fXTAL < 8 MHz", and "D" for others. - Footnote "This parameter is...100% tested" updated to "Applies to an...to crystal mode". Also added to parameter "VILEXT". - For parameters "VIHEXT" and "VILEXT", Condition "-" updated to "VREF = 0.29 * VDD_HV_IO_JTAG" - Updated parameters CS_EXTAL and CS_XTAL. Renamed the section "RC oscillator 1024 kHz" to Section 3.11.4: Low power RC oscillator" Table 23: 32 kHz External Slow Oscillator electrical specifications: - For parameter "gmsxosc", changed the classification to "P". Table 24: Internal RC oscillator electrical specifications: - For parameter "IFIRC", replaced max value of 300 with 600. - Added footnote to the description. - For parameter IFIRC, changed the max value to 600 and added - Min, Typ and Max value of "fvar_SW" updated from "-1", "-", "1" to "0.5", "+0.3" and "0.5" respectively. Table 25: 1024 kHz internal RC oscillator electrical characteristics: - For parameter "fvar_T", and "fvar_V "changed the classification to "P". - For parameter "fvar_V", minimum and maximum value updated from "-0.05" and "+0.05" to "-5" and "+5" Table 26: ADC pin specification: - For ILKG, changed condition "C" to "--". - Added parameter "IINJ1" - For parameter CP2, updated the max value to "1". DS11758 Rev 5 125/131 130 Revision history SPC584Gx, SPC58EGx, SPC58NGx Table 75. Document revision history (continued) Date 06-Jul-2017 126/131 Revision Changes 3 (cont') Table 27: SARn ADC electrical specification: - Classification for parameter "IADCREFH" changed from "C" to "T". - Removed parameter "TUEINJ2" - For parameter fADCK (High frequency mode), changed min value from "7.5" to "> 13.33". - Deleted footnote "Values are subject to change (possibly improved to 2 LSB) after characterization" Table 28: ADC-Comparator electrical specification: - Classification for parameter "IADCREFH" changed from "C" to "T" - Removed table footnote "Values are subject to change (possibly improved to 2 LSB) after characterization" - Removed parameter "TUEINJ2" Updated Figure 8: Input equivalent circuit (Fast SARn and SARB channels) Table 29: Temperature sensor electrical characteristics: - For "temperature monitoring range", classification removed (was C) - Min and Max value of parameter "PERREF" for condition "Long period" updated from "TBD" to "-500" and "+500" respectively. Table 31: LFAST transmitter electrical characteristics,,: - Footnote "The transition time is measured from..." removed. Updated Figure 26: DSPI CMOS master mode -- classic timing, CPHA = 1 Table 30: LVDS pad startup and receiver electrical characteristics,: - For parameter ILVDS_BIAS, changed the characteristics to "C" Table 32: LFAST PLL electrical characteristics: - Min and Max value of parameter "ERRREF" updated from "TBD" to "-1" and "+1" respectively - Max value of parameter "PN" updated from "TBD" to "-58" - Frequency of parameter "PERREF" updated from "10MHz" to "20MHz". - Max value of parameter "PERREF" for condition "Single period" updated from "TBD" to "350" Table 33: Power management regulators: - Removed text "In parts packaged with LQFP176, the auxiliary and clamp regulators cannot be enabled" from note 2. - Removed "SMPS regulator mode" from note 2. Table 34: External components integration: - For PMOS, replaced "STT4P3LLH6" with "PMPB100XPEA" - For NMOS, replaced "STT6N3LLH6" with "PMPB55XNEA" - Added table footnote to typ value of CS2. - Removed table footnote "External components number......." DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Revision history Table 75. Document revision history (continued) Date 06-Jul-2017 Revision 3 (cont') Changes Table 35: Linear regulator specifications: - Classification of parameter "IDDMREG" changed from "P" to "T". - Classification of parameter "IDDMREG" changed from "T" to "P". - Added "After trimming, external regulator mode" Table 36: Auxiliary regulator specifications: - Classification of parameter "IDDAUX" changed from "P" to "T". - Classification of parameter "IDDAUX" changed from "T" to "P". - Added "After trimming, external regulator mode" Table 38: Standby regulator specifications: - Classification of parameter "IDDSBY" changed from "P" to "T". - Classification of parameter "IDDSBY" changed from "T" to "P". Table 39: Voltage monitor electrical characteristics: - For VPOR031_C, changed the max value from 0.85 to 0.97. - For TVMFILTER, replaced T with D. - Min value of "VPOR200_C" updated from "1.96" to "1.80" - Max value of "VPOR031_C" updated from ".85" "0.97" - Changed the min value of parameter VPOR200_C from "1.96" to "1.80" - Changed the max value of parameter VPOR031_C from "0.85" to "0.97" - Changed the condition of parameter TVMFILTER from "T" to "D" Figure 15: Voltage monitor threshold definition: Updated the figure. Updated Table 40: Wait State configuration Table 44: Nexus debug port timing: Classification of parameters "tEVTIPW" and "tEVTOPW" changed from "P" to "D". Table 46: DSPI channel frequency support: - Added column to show slower and faster frequencies. Table 47: DSPI CMOS master classic timing (full duplex and output only) MTFE = 0, CPHA = 0 or 1: - Changed the Min value of tSCK (very strong) from 33 to 59. Updated Section 3.16: Flash memory Added Section 3.17.5: CAN timing Updated Figure 47: eLQFP176 package outline 1/2 Table 70: Thermal characteristics for 144 exposed pad eTQFP package: Updated the values. Table 71: Thermal characteristics for 176 exposed pad LQFP package and Table 72: Thermal characteristics for 292-pin BGA: Updated the tables and its values. Updated Figure 50: Ordering information scheme Added Table 73: Code Flash options Added Table 74: RAM options Changed Microsoft Excel(R) workbook attached to this document. For details, refer to the sheet Revision History of the attached file "SPC584Gx_SPC58EGx_SPC58NGx_IO_Definition_v4.xlsx". DS11758 Rev 5 127/131 130 Revision history SPC584Gx, SPC58EGx, SPC58NGx Table 75. Document revision history (continued) Date 08-Feb-2018 128/131 Revision Changes 4 Table 1: Introduction Table 2: SPC584Gx, SPC58EGx, SPC58NGx features summary: Added "Flash Overlay RAM: 2x16KB Section 2: Package pinouts and signal descriptions: Added "pad characteristics" to heading. Section 3.1: Introduction: Reformated note from introduction Section 3.3: Operating conditions: Replaced reference to IO_definition excel file by "the device pin out IO definition excel file" Section Table 9.: Device consumption: Updated the following parameters: - IDD_LKG for all conditions. - IDDSTBY8 for all conditions. - IDDSTBY128 for all conditions. IDDSTBY256 for all conditions."IDD_LV": added Footnote "IDD_LKG and IDD_LV are reported as..." Section 3.8: I/O pad specification: Replaced all references to the IO_definitions excel file by "the device pinout IO definition excel file". Reformated note from introduction. Table 16: VERY STRONG/VERY FAST I/O output characteristics - "tTR20-80" replaced by "tTR20-8_V" - "tTRTTL" replaced by "tTRTTL_V" - "tTR20-80" replaced by "tTR20-80_V" Table 10: I/O pad specification descriptions: Removed latest sentence at Standby pads description. Table 15: STRONG/FAST I/O output characteristics: updated values for tTR_S for condition CL = 25 pF and CL = 50 pF Section 3.9: Reset pad (PORST, ESR0) electrical characteristics: Table 18: Reset PAD electrical characteristics: replaced reference to IO_definition excel file by "Refer to the device pin out IO definition excel file" Section 3.10: PLLs: Table 20: PLL0 electrical characteristics: Added "fINFIN" changed "C" by "--" in column "C" - |PLL0PHI0SPJ|: changed "T" by "D" and added pk-pk to Conditions value - |PLL0PHI1SPJ|: added pk-pk to Conditions value - |PLL0PHI0SPJ|: changed "T" by "D" and added pk-pk to Conditions value - |PLL0PHI1SPJ|: added pk-pk to Conditions value DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx Revision history Table 75. Document revision history (continued) Date 08-Feb-2018 Revision 4(cont') Changes Table 21: PLL1 electrical characteristics: Added "fINFIN" changed "C" by "--" in column "C" Section 3.12: ADC system: Table 26: ADC pin specification: updated Max value for CS For parameter CP2, updated the max value from "1" to "2". Added electrical specification for R20K symbol. Changed Max value = 1 by 2 for Cp2 SARB channels Table 27: SARn ADC electrical specification: added symbols tADCINIT and tADCBIASINIT column "C" splitted and added "D" for IADV_S Table 28: ADC-Comparator electrical specification: Added new parameter "tADCINITSBY". Set min = 5/fADCK s for 10-bit ADC mode, min = 2/fADCK for ADC comparator mode, at symbol tADCSAMPLE. Column "C" splitted and added "D" for IADV_S Section 3.14: LFAST pad electrical characteristics: Introduction paragraph: - 1st sentence: hidden text "both the SIPI and" - all 2nd sentence hidden: "The same LVDS.. tables" Section 3.14.2: LFAST and MSC/DSPILVDS interface electrical characteristics: title completed with "and MSC/DSPI" Section 3.15: Power management: Figure 15: Voltage monitor threshold definition: right blue line adjusted on the top figure Section 3.15.1: Power management integration: added sentence "It is recommended...device itself" for all devices Table 35: Linear regulator specifications: updated values for symbol "IDDMREG" Min: added -100 Max added 100: Section 3.17: AC Specifications Table 57: TxEN output characteristics: added table footnote " Pad configured as VERY STRONG." Table 58: TxD output characteristics,,: changed note 3 to apply to the whole table Table 60: CAN timing: added columns for "CC" and "D" Section 4: Package information: Table 69: FPBGA292 package mechanical data: updated Amax formula in table footnote 2. Section 4.4: Package thermal characteristics: Reformated note from introduction Section 5: Ordering information: Chapter title heading changed to heading 1. Figure 50: Ordering information scheme: updated for Packing DS11758 Rev 5 129/131 130 Revision history SPC584Gx, SPC58EGx, SPC58NGx Table 75. Document revision history (continued) Date 04-Feb-2019 130/131 Revision Changes 5 Table 4: Absolute maximum ratings Added a cross ref to footnote starting with "VDD_HV: allowed 5.5 V - 6.0 V for 60 seconds..." to all VDD_HV* parameters having max=6.0V. The same to VIN parameter. Section 3.5: Electromagnetic compatibility characteristicsUpdated section from Electromagnetic emission characteristics to Electromagnetic compatibility characteristics. Table 9: Device consumption Updated IDDSTBY8, IDDSTBY128, IDDSTBY256 max values and "C" column at TJ=40. Section 4.1: eTQFP144 package information Updated mechanical drawings and mechanical data. Section 4.2: eLQFP176 package information Updated mechanical drawings and mechanical data. Table 50: Ordering information scheme Updated Security and Custom Version option lists. Table 74: RAM options Updated PRAMC_1_64K and PRAMC_2_128K start address. PRAMC_2_120K and D-MEM CPU_2 end address. DS11758 Rev 5 SPC584Gx, SPC58EGx, SPC58NGx IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2019 STMicroelectronics - All rights reserved DS11758 Rev 5 131/131 131