FEATURES FUNCTIONAL BLOCK DIAGRAM VDD Reflective, 50 design Low insertion loss: 0.7 dB typical to 2.0 GHz High power handling at TCASE = 105C Long-term (>10 years) average CW power: 43 dBm Peak power: 49 dBm LTE average power (8 dB PAR): 41 dBm Single event (<10 sec) average LTE average power (8 dB PAR): 44 dBm High linearity P0.1dB: 47 dBm typical IP3: 70 dBm typical ESD ratings HBM: 4 kV, Class 3A CDM: 1.25 kV Single positive supply: 5 V Positive control, CMOS/TTL compatible 32-lead, 5 mm x 5 mm LFCSP package VCTL ADRF5160 RF1 RF2 RFC GND PACKAGE BASE GND 16518-001 Data Sheet High Power, 88 W Peak, Silicon SPDT, Reflective Switch, 0.7 GHz to 4.0 GHz ADRF5160 Figure 1. APPLICATIONS Wireless infrastructure Military and high reliability applications Test equipment Pin diode replacement GENERAL DESCRIPTION The ADRF5160 is a silicon-based, high power, 0.7 GHz to 4.0 GHz, silicon, single-pole, double-throw (SPDT) reflective switch in a leadless, surface-mount package. The switch is ideal for high power and cellular infrastructure applications, such as long-term evolution (LTE) base stations. The ADRF5160 has high power handling of 41 dBm (8 dB PAR LTE, long-term (>10 years) average typical), a low insertion loss of 0.7 dB typical Rev. 0 to 2.0 GHz, an input third-order intercept (IP3) of 70 dBm (typical), and a 0.1 dB compression point (P0.1dB) of 47 dBm. On-chip circuitry operates at a single positive supply voltage of 5 V at a typical supply current of 1.1 mA, making the ADRF5160 an ideal alternative to pin diode-based switches. The ADRF5160 comes in an RoHS compliant, compact, 32-lead, 5 mm x 5 mm LFCSP. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADRF5160 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Interface Schematics .....................................................................5 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................6 Functional Block Diagram .............................................................. 1 Theory of Operation .........................................................................8 General Description ......................................................................... 1 Applications Information .................................................................9 Revision History ............................................................................... 2 Evaluation Board ...........................................................................9 Specifications..................................................................................... 3 Typical Application Circuit ....................................................... 10 Absolute Maximum Ratings ............................................................ 4 Outline Dimensions ....................................................................... 12 Thermal Resistance ...................................................................... 4 Ordering Guide .......................................................................... 12 ESD Caution .................................................................................. 4 Pin Configuration and Function Descriptions ............................. 5 REVISION HISTORY 5/2018--Revision 0: Initial Version Rev. 0 | Page 2 of 12 Data Sheet ADRF5160 SPECIFICATIONS VDD = 5 V, VCTL = 0 V/VDD, TA = 25C, and the device is a 50 system, unless otherwise noted. Table 1. Parameter FREQUENCY RANGE INSERTION LOSS ISOLATION RFC to RF1 and RF2 (Worst Case) RF1 to RF2 RETURN LOSS RFC RF1 and RF2 (On State) SWITCHING CHARACTERISTICS Rise and Fall Time (tRISE, tFALL) On and Off Time (tON, tOFF) INPUT LINEARITY 0.1 dB Compression (P0.1dB) Third-Order Intercept (IP3) SUPPLY CURRENT DIGITAL CONTROL INPUT Low Voltage High Voltage Low and High Current RECOMMENDED OPERATING CONDITIONS Supply Voltage Range (VDD) Control Voltage Range (VCTL) RF Input Power Case Temperature (TCASE) = 105C 2 TCASE = 85C TCASE = 25C TCASE = -40C Test Conditions/Comments 2 Typ Max 4.0 Unit GHz dB dB dB 0.7 GHz to 2.0 GHz 2.0 GHz to 3.5 GHz 3.5 GHz to 4.0 GHz 0.7 0.8 0.9 0.7 GHz to 2.0 GHz 2.0 GHz to 4.0 GHz 0.7 GHz to 2.0 GHz 2.0 GHz to 4.0 GHz 53 45 51 35 dB dB dB dB 0.7 GHz to 2.0 GHz 2.0 GHz to 4.0 GHz 0.7 GHz to 2.0 GHz 2.0 GHz to 4.0 GHz 20 19 19 18 dB dB dB dB 10%/90% radio frequency output (RFOUT) 50% VCTL to 10%/90% RFOUT 0.27 1.2 s s 47 dBm 72 70 1.1 dBm dBm mA Two-tone input power = 30 dBm per tone at 1 MHz tone spacing 0.7 GHz to 2.0 GHz 2.0 GHz to 4.0 GHz 1.0 1 VDD = 4.5 V to 5.4 V, TCASE = -40C to +105C 0 1.3 0.8 5 V V A 4.5 0 5.4 VDD V V -40 43 41 44 45 41 44 47.5 41 44 49 41 44 +105 dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm C <1 Continuous wave (CW) 8 dB peak average ratio (PAR) LTE, long-term (>10 years) average 8 dB PAR LTE, single event (<10 sec) average CW 8 dB PAR LTE, long-term (>10 years) average 8 dB PAR LTE, single event (<10 sec) average CW 8 dB PAR LTE, long-term (>10 years) average 8 dB PAR LTE, single event (<10 sec) average CW 8 dB PAR LTE, long-term (>10 years) average 8 dB PAR LTE, single event (<10 sec) average TCASE Range 1 Min 0.7 Guaranteed by design for device to device and over operating temperature variation. Peak power is 49 dBm, which corresponds to a PAR of 8 dB at LTE long-term. Rev. 0 | Page 3 of 12 ADRF5160 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 2. Parameter Supply Voltage Range (VDD) Control Voltage Range (VCTL) RF Input Power1 Channel Temperature Maximum Peak Reflow Temperature (Moisture Sensitivity Level 3 (MSL3))2 Storage Temperature Range Electrostatic Discharge (ESD) Sensitivity Human Body Model (HBM) Charged Device Model (CDM) 1 2 Rating -0.3 V to +5.4 V -0.3 V to VDD + 0.3 V 49.7 dBm 135C 260C Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Table 3. Thermal Resistance Package Type HCP-32-1 -65C to +150C ESD CAUTION 4 kV (Class 3A) 1.25 kV For the recommended operating conditions, see Table 1. See the Ordering Guide for additional information. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. 0 | Page 4 of 12 JC 8.4 Unit C/W Data Sheet ADRF5160 32 31 30 29 28 27 26 25 GND GND GND VDD VCTL GND GND GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 ADRF5160 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 GND GND GND RF2 GND GND GND GND NOTES 1. EXPOSED PAD. EXPOSED PAD MUST BE CONNECTED TO RF/DC GROUND. 16518-002 GND GND GND RFC GND GND GND GND 9 10 11 12 13 14 15 16 GND GND GND RF1 GND GND GND GND Figure 2. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 to 3, 5 to 11, 13 to 20, 22 to 27, 30 to 32 Mnemonic GND 4 RF1 12 RFC 21 RF2 28 VCTL 29 VDD EPAD Description Ground. The package bottom has an exposed metal pad that must connect to the PCB RF/dc ground. RF Port 1. This pin is dc-coupled and matched to 50 . A dc blocking capacitor is required on this pin. See Figure 3 for the interface schematic. RF Common Port. This pin is dc-coupled and matched to 50 . A dc blocking capacitor is required on this pin. See Figure 3 for the interface schematic. RF Port 2. This pin is dc-coupled and matched to 50 . A dc blocking capacitor is required on this pin. See Figure 3 for the interface schematic. Control Input Pin. See Figure 4 for the VCTL interface schematic. Refer to Table 5 for the signal path and the recommended input control voltage range shown in Table 1. Supply Voltage Pin. Exposed Pad. Exposed pad must be connected to RF/dc ground. INTERFACE SCHEMATICS VDD VDD 16518-003 16518-004 VCTL RFC, RF1, RF2 Figure 3. RFC, RF1, and RF2 Interface Schematic Figure 4. Control Input (VCTL) Interface Schematic Rev. 0 | Page 5 of 12 ADRF5160 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0 0 -40C +25C +85C +105C RF1 RF2 -0.5 INSERTION LOSS (dB) -1.0 -1.5 -2.0 2 3 4 5 Figure 5. Insertion Loss for RF1 and RF2 vs. Frequency at VDD = 5 V 0 -3.0 ISOLATION (dB) -30 -40 -50 -60 4 5 -40 -50 -60 -70 -80 -80 1 2 3 4 5 FREQUENCY (GHz) 16518-006 -70 Figure 6. Isolation Between RFC and RF1 and RF2 vs. Frequency at VDD = 5 V 0 RFC RF1 RF2 -5 -10 -15 -20 -25 -30 1 2 3 4 FREQUENCY (GHz) 5 16518-007 -35 0 3 RF1 RF2 -10 -30 -40 2 0 -20 0 1 Figure 8. Insertion Loss vs. Frequency for Various Temperatures at VDD = 5 V -20 -90 0 FREQUENCY (GHz) RF1 RF2 -10 ISOLATION (dB) -2.0 16518-008 1 16518-005 0 FREQUENCY (GHz) RETURN LOSS (dB) -1.5 -2.5 -2.5 -3.0 -1.0 Figure 7. Return Loss vs. Frequency at VDD = 5 V Rev. 0 | Page 6 of 12 -90 0 1 2 3 FREQUENCY (GHz) 4 5 16518-009 INSERTION LOSS (dB) -0.5 Figure 9. Isolation Between RF1 and RF2 vs. Frequency at VDD = 5 V Data Sheet ADRF5160 80 55 -40C +25C +85C +105C 50 INPUT P0.1 dB (dBm) 70 65 60 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 16518-110 1.0 FREQUENCY (GHz) Figure 10. Input Third-Order Intercept (IP3) vs. Frequency for Various Temperatures, VDD = 5 V 1.0 1.5 2.0 2.5 FREQUENCY (GHz) 3.0 3.5 4.0 16518-112 INPUT P0.1 dB (dBm) RF1 RF2 0.5 40 35 55 50 0.5 45 Figure 11. Input 0.1dB Power Compression (P0.1dB) vs. Frequency, VDD = 5 V Rev. 0 | Page 7 of 12 30 0.5 1.0 1.5 2.0 2.5 FREQUENCY (GHz) 3.0 3.5 4.0 16518-111 INPUT IP3 (dBm) 75 -40C +25C +85C +105C Figure 12. Input 0.1dB Compression (P0.1dB) vs. Frequency for Various Temperatures, VDD = 5 V ADRF5160 Data Sheet THEORY OF OPERATION The ADRF5160 requires a single-supply voltage applied to the VDD pin. Bypassing capacitors are recommended on the supply line to minimize RF coupling. The ADRF5160 is controlled via a digital control voltage applied to the VCTL pin. A bypassing capacitor is recommended on this digital signal line to improve the RF signal isolation. The ADRF5160 is internally matched to 50 at the RF input port (RFC) and the RF output ports (RF1 and RF2). Therefore, no external matching components are required. The RFx pins are dc-coupled, and dc blocking capacitors are required on the RFx lines. The design is bidirectional, meaning that the input and outputs are interchangeable. The ideal power-up sequence is as follows: 1. 2. 3. 4. Connect GND. Power up VDD. Power up the digital control input. Power the digital control input before the VDD supply to avoid inadvertently forward biasing and damaging the ESD protection structures. Power up the RF input. Depending on the logic level applied to the VCTL pin, one RF output port (for example, RF1) is set to on mode, by which an insertion loss path is provided from the input to the output. While the other RF output port (for example, RF2) is set to off mode, by which the output is isolated from the input. Table 5. Switch Operation Mode Digital Control Input (VCTL) Low High RF1 to RFC Isolation (off ) Insertion loss (on) Rev. 0 | Page 8 of 12 Signal Path RF2 to RFC Insertion loss (on) Isolation (off ) Data Sheet ADRF5160 APPLICATIONS INFORMATION EVALUATION BOARD The ADRF5160-EVALZ can withstand high power levels and temperatures at which the device operates. The ADRF5160-EVALZ evaluation board is constructed with eight metal layers and dielectrics between each layer, as shown in Figure 13. Each metal layer has a 1 oz (1.3 mil) copper thickness, and the external layers are plated to 2 oz. The top dielectric material is 10 mil Rogers RO4350, which exhibits a low thermal coefficient, offering control over thermal rise of the board. The dielectrics between other metal layers are FR4. The overall board thickness is 62 mil. To ensure maximum heat dissipation and to reduce thermal rise on the board, some application considerations are essential. The evaluation board must be attached to a copper support plate at the bottom of the board. The ADRF5160-EVALZ comes with this support plate attachment. Attach this evaluation board with its support plate to a heat sink using thermal grease during all high power operations. Figure 14 shows the board temperature vs. the RF power input tested with the preceding conditions and precautions (the evaluation board and support plate are attached to a heat sink). The temperature rise is less than 8C up to 48 dBm of RF power input, which provides the required thermal dissipation when operating at high power levels. G = 13mil 36 W = 18mil 35 1.5oz Cu (2.1mil) RO4350 = 10mil 1.5oz Cu (2.1mil) T = 2.1 mil 34 BOARD TEMPERATURE (C) 1.5oz Cu (2.1mil) H = 10mil 1oz Cu (1.3mil) FR4 33 32 31 30 29 28 27 TOTAL THICKNESS = 60mil 1oz Cu (1.3mil) 25 43.0 FR4 43.5 44.0 44.5 45.0 45.5 46.0 46.5 47.0 47.5 48.0 RF POWER INPUT (dBm) 16518-014 26 Figure 14. ADRF5160-EVALZ Evaluation Board Temperature Rise (Oven Temperature Set to 25C) 1oz Cu (1.3mil) FR4 C1 1oz Cu (1.3mil) TP1 TP3 FR4 C4 1oz Cu (1.3mil) FR4 C2 R1 1oz Cu (1.3mil) TP2 Figure 13. ADRF5160-EVALZ Evaluation Board Cross Sectional View The top copper layer has all RF and dc traces. The other seven layers provide sufficient ground and help handle the thermal rise on the ADRF5160-EVALZ. In addition, via holes are provided around transmission lines and under the exposed pad of package, as shown in Figure 15, for proper thermal grounding. RF transmission lines on the board are of a coplanar wave guide design with a width of 18 mils and ground spacing of 13 mils. Rev. 0 | Page 9 of 12 C3 Figure 15. ADRF5160-EVALZ Evaluation Board Layout 16518-015 1.5oz Cu (2.1mil) 16518-013 FR4 ADRF5160 Data Sheet TYPICAL APPLICATION CIRCUIT impedance, and the package ground leads and backside ground slug must connect directly to the ground plane. The evaluation board shown in Figure 16 is available from Analog Devices, Inc., upon request. Generate the evaluation PCB used in the typical application circuit shown in Figure 17 with proper RF circuit design techniques. Signal lines at the RF port must have a 50 J1 GND RF1 TP3 C4 THRU CAL C2 TP1 4321 RFC J2 VDD C1 R1 4321 RF2 1234 600-01533-00-2 TP2 C3 VCTL 16518-012 J3 Figure 16. ADRF5160-EVALZ Evaluation Board Component Placement Table 6. Bill of Materials for the ADRF5160-EVALZ Evaluation Board Reference Designator C1 to C3 C4 TP1, TP2, TP3 R1 J1, J2, J3 U1 PCB 1 1 2 Description 24 pF, 200 V ultralow, effective series resistance (ESR) capacitors, 0402 package 0.3 pF, 200 V ultralow ESR capacitor, 0402 package Test point connectors 0 resistor, 0402 package PCB mount, SubMiniature Version A (SMA) connectors ADRF5160 SPDT switch ADRF5160-EVALZ 2 evaluation PCB The circuit board material is Roger 4350 or Arlon 25FR. Reference to this evaluation board number when ordering the complete evaluation board. Rev. 0 | Page 10 of 12 Data Sheet ADRF5160 VDD VCTL GND GND GND VCTL GND VDD GND GND R1 0 32 31 30 29 28 27 26 25 GND 1 GND 2 23 22 3 RF1 4 GND 5 GND 21 20 6 19 GND 7 GND 18 17 8 GND GND GND RF2 C3 RF2 GND GND GND GND GND GND GND GND RFC GND 10 11 12 13 14 15 16 GND 9 GND RF1 24 C4 C2 RFC Figure 17. Typical Application Circuit Rev. 0 | Page 11 of 12 16518-011 GND C1 ADRF5160 ADRF5160 Data Sheet OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 0.30 0.25 0.18 PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 32 25 1 24 0.50 BSC 3.80 3.70 SQ 3.60 EXPOSED PAD 17 0.45 0.40 0.35 TOP VIEW 0.90 0.85 0.80 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PKG-004898 8 16 9 BOTTOM VIEW 3.50 REF 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-4. 03-09-2017-B PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 18. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm x 5 mm Body and 0.85 mm Package Height (HCP-32-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADRF5160BCPZ ADRF5160BCPZ-R7 ADRF5160-EVALZ 1 2 Temperature Range -40C to +105C -40C to +105C MSL Rating 2 MSL3 MSL3 Package Description 32-lead Lead Frame Chip Scale Package [LFCSP] 32-lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS Compliant Part. See the Absolute Maximum Ratings section for additional information. (c)2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16518-0-5/18(0) Rev. 0 | Page 12 of 12 Package Option HCP-32-1 HCP-32-1