DS90C185
PRELIMINARY
February 7, 2012
Low Power 1.8V FPD-Link (LVDS) Serializer
General Description
The DS90C185 is a Low Power Serializer for portable battery
powered applications that reduces the size of the RGB inter-
face between the host GPU and the Display.
24-bit RGB plus three video control signals are serialized and
translated to LVDS compatible levels and sent as a 4 data +
clock (4D+C) reduced width LVDS compatible interface. The
LVDS Interface is compatible with FPD-Link (1) deserializers
and many LVDS based displays. These interfaces are com-
monly supported in LCD modules with “LVDS” or FPD-Link
single-pixel input interfaces.
Displays up to 1280 x 1024 @ 60 fps are supported with 8bpp
in color depth. 6bpp may also be supported by a dedicated
mode with a 3D+C output. Power Dissipation is minimized by
the full CMOS design and 1.8V powered core and VDDIO rails.
The DS90C185 is offered in the small 48 pin QFN package
and features single 1.8V supply operation for minimum power
dissipation (50mW typ).
Features
■Typ power 50mW @ 75 MHz pclk
■Drives up to 1280 x 1024 @ 60 Hz (SXGA+) Displays
■2.94 Gbps of throughput
■Two operating modes: 24-bit and 18-bit RGB
■25 to 105 MHz Pixel Clock support
■Single 1.8V Supply
■Sleep Mode
■Spread Spectrum Clock compatibility
■Small 6mm x 6mm x 0.8mm QFN package
Applications
■Media Tablet Devices
■Netbooks
■Portable Display Monitors
System Diagram
30151590
Ordering Information
Order Number Package Description Package ID Supplied As
DS90C185SQE/NOPB 48–pin LLP, 6.0 x 6.0 x 0.8 mm, 0.4 mm pitch SQF48A 250 units on Tape and Reel
DS90C185SQ/NOPB 48–pin LLP, 6.0 x 6.0 x 0.8 mm, 0.4 mm pitch SQF48A 1000 units on Tape and
Reel
DS90C185SQX/NOPB 48–pin LLP, 6.0 x 6.0 x 0.8 mm, 0.4 mm pitch SQF48A 2500 units on Tape and
Reel
© 2012 Texas Instruments Incorporated 301515 SNLS402 www.ti.com
DS90C185 Low Power 1.8V FPD-Link (LVDS) Serializer
Functional Block Diagram
30151501
Connection Diagram
30151591
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DS90C185
DS90C185 Pin Descriptions
Pin Name I/O No. Description
1.8 V LVCMOS VIDEO INPUTS
D27 – D21,
D20,
D19 – D14,
D13 – D9,
D8 – D1,
D0
I 22 – 16,
14,
12 – 7,
5 – 1,
47 – 40,
38
Data input pins.
This includes: 8 Red, 8 Green, 8 Blue, and 4 video control lines. Includes pull down.
CLK I 6 1.8V LVCMOS Ievel clock input
Includes pull down.
LVDS VIDEO OUTPUTS
TxOUT0 –/+,
TxOUT1 –/+,
TxOUT2 –/+,
TxOUT3 –/+,
O 36, 35
34, 33
32, 31
28, 27
LVDS Output Data — Expects 100 Ω DC load.
TxCLK OUT -/+ O 30, 29 LVDS Output Clock — Expects 100 Ω DC load.
1.8 V LVCMOS CONTROL INPUTS
R_FB I 23 LVTTL Ievel programmable strobe select
1 = Rising Edge Clock
0 = Falling Edge Clock
Includes pull down.
18B_Mode I 26 Mode Configuration Input
1 = 3D+C (18-bit RGB mode)
0 = 4D+C (24-bit RGB mode) — default
Includes pull down.
VOD_SEL I 39 VOD Select Input
1 = Reduced VOD (lower power)
0 = Normal VOD — default
Includes pull down.
PDB I 37 Power Down Bar(Sleep) Input
1 = ACTIVE
0 = Sleep State (low power idle) — default
Includes pull down.
POWER and GROUND
VDD P 48 Digital power input
VDDTX P 25 LVDS driver power input
VDDPLL P 13 PLL power input
GND G 15, 24 Ground pins
DAP G Connect DAP to ground plane
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DS90C185
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
Supply Voltage (VDD) −0.3V to +4V
LVCMOS Input Voltage −0.5V to (VDD + 0.3V)
LVDS Driver Output Voltage −0.3V to (VDD + 0.3V)
LVDS Output Short Circuit
Duration Continuous
Junction Temperature +150°C
Storage Temperature −65°C to +150°C
Lead Temperature
(Soldering, 4 sec) +260°C
Package Derating: θJA 26.6 °C/W above +22°C
ESD Ratings
(HBM, 1.5kΩ, 100pF) TBDkV
(EIAJ, 0Ω, 200 pF) TBDV
Recommended Operating
Conditions
Min Nom Max Units
Supply Voltage (VCC) 1.71 1.8 1.89 V
Operating Free Air
Temperature (TA) −10 +22 +70 °C
Supply Noise Voltage
(VDD)
90 mVPP
Differential Load
Impedance
80 100 120 Ω
Input Clock Frequency 25 105 MHz
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
LVCMOS DC SPECIFICATIONS
VIH High Level Input Voltage 0.65 *
VDD
VDD V
VIL Low Level Input Voltage GND 0.35*V
DD
V
IIN Input Current VIN = 0V or VDD = 1.71 V to 1.89 V –10 ±1 +10 μA
LVDS DC SPECIFICATIONS
VOD Differential Output Voltage RL = 100Ω VODSEL = H 160
(320)
300
(600)
450
(900)
mV
(mVP-P)
VODSEL = L 115
(230)
180
(360)
300
(600)
mV
(mVP-P)
ΔVOD Change in VOD between complimentary
output states
RL = 100Ω 50 mV
VOS Offset Voltage 0.8 0.9 1.0 V
ΔVOS Change in VOS between complimentary
output states
50 mV
IOS Output Short Circuit Current VOUT = 0V, RL = 100Ω –45 −35 −25 mA
SERIALIZER SUPPLY CURRENT
IDDT1 Serializer Supply Current
Worst Case
Checkerboard pattern, RL
= 100Ω, 18B_MODE = L,
VOD_SEL = H, VDD =
1.89
f = 105 MHz 60 85 mA
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DS90C185
Symbol Parameter Conditions Min Typ Max Units
IDDTG Serializer Supply Current
16 Grayscale
RL = 100Ω, 18B_MODE =
L, VOD_SEL = L, VDD =
1.8
16 Grayscale Pattern
f = 75 MHz 31 mA
RL = 100Ω, 18B_MODE =
L, VOD_SEL = H, VDD =
1.8
16 Grayscale Pattern
41 mA
RL = 100Ω, 18B_MODE =
H, VOD_SEL = L, VDD =
1.8
16 Grayscale Pattern
28 mA
RL = 100Ω, 18B_MODE =
H, VOD_SEL = H, VDD =
1.8
16 Grayscale Pattern
36 mA
IDDTP Serializer Supply Current
PRBS-7
RL = 100Ω, 18B_MODE =
L, VOD_SEL = L, VDD =
1.8
PRBS-7 Pattern
f = 75 MHz 33 mA
RL = 100Ω, 18B_MODE =
L, VOD_SEL = H, VDD =
1.8
PRBS-7 Pattern
45 mA
RL = 100Ω, 18B_MODE =
H, VOD_SEL = L, VDD =
1.8
PRBS-7 Pattern
29 mA
RL = 100Ω, 18B_MODE =
H, VOD_SEL = H, VDD =
1.8
PRBS-7 Pattern
38 mA
IDDZ Serializer Power Down Current 18 200 μA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for VCC = 3.3V and TA = +25C unless specified otherwise.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except VOD and ΔVOD).
Note 4: VOS previously referred as VCM.
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
TCIT TxCLK IN Transition Time (Figure 5)1.0 6.0 ns
TCIP TxCLK IN Period (Figure 6)9.52 T 40 ns
TCIH TxCLK IN High Time (Figure 6)0.35T 0.5T 0.65T ns
TCIL TxCLK IN Low Time (Figure 6)0.35T 0.5T 0.65T ns
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
LLHT LVDS Low-to-High Transition Time (Figure 4) 0.18 0.5 ns
LHLT LVDS High-to-Low Transition Time (Figure 4) 0.18 0.5 ns
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DS90C185
Symbol Parameter Min Typ Max Units
TPPOS Transmitter Output Pulse Positions Normalize f = 105 MHz TBD TBD TBD UI
TSTC Required TxIN Setup to TxCLK IN 0 ns
THTC Required TxIN Hold to TxCLK IN 2.5 ns
TCCJ Cycle to Cycle Jitter TBD TBD ns
TPLLS Transmitter Phase Lock Loop Set 1 ms
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DS90C185
Note 6: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 7: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Note 8: Recommended pin to signal mapping. Customer may choose to define differently.
30151530
FIGURE 3. DS90C185 (Transmitter) LVDS Output Load
30151506
FIGURE 4. DS90C185 (Transmitter) LVDS Transition Times
30151542
FIGURE 5. DS90C185 (Transmitter) Input Clock Transition Time
30151540
FIGURE 6. DS90C185 (Transmitter) Setup/Hold and High/Low Times with R_FB pin = GND (Falling Edge Strobe)
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DS90C185
30151512
FIGURE 7. DS90C185 Propagation Delay
30151551
FIGURE 8. DS90C185 (Transmitter) Phase Lock Loop Set Time
30151552
FIGURE 9. Transmitter Power Down Delay
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DS90C185
30151543
FIGURE 10. Transmitter LVDS Output Pulse Position Measurement - DS90C185
20 40 60 80 100 120
20
25
30
35
40
45
50
55
60
IDD (mA)
FREQUENCY (MHz)
VODSEL = L, 18B = L
VODSEL = H, 18B = L
VODSEL = L, 18B = H
VODSEL = H, 18B = H
30151556
FIGURE 11. Typ Current Draw — PRBS-7 Data Pattern
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DS90C185
LVDS Interface / TFT Color Data
recommended Mapping
Different color mapping options exist. Check with the color
mapping of the Deserializer / TCON device that is used to
ensure compatible mapping for the application. The
DS90C185 supports single pixel interfaces with either 8bpp
or 6bpp color depths.
The DS90C185 provides four LVDS data lines along with an
LVDS clock line (4D+C). The SER input interface is from
twenty five inputs and three input which are assigned to the
three video control signals (DE, VS and HS). This supports a
24 bpp interface along with the three video control signals and
one additional input. The single pixel 8bpp 4D+C LVDS in-
terface mapping is shown Figure 13. A single pixel 6bpp mode
is also supported by utilizing the 18B_MODE pin. In this con-
figuration the TxOUT3 output channel is place in TRI-
STATE® to save power. Its respective inputs are ignored.
This mapping is shown in Figure 12.
30151548
FIGURE 12. DS90C185 LVDS Map — 18B_MODE = H
30151549
FIGURE 13. DS90C185 LVDS Map — 18B_MODE = L
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DS90C185
COLOR MAPPING INFORMATION
A defacto color mapping is shown next. Different color map-
ping options exist. Check with the color mapping of the De-
serializer / TCON device that is used to ensure compatible
mapping for the application.
8bpp / MSB on CH3
DS90C187 Input Color
Mapping
Note
D22 R7 MSB
D21 R6
D5 R5
D4 R4
D3 R3
D2 R2
D1 R1
D0 R0 LSB
D24 G7 MSB
D23 G6
D11 G5
D10 G4
D9 G3
D8 G2
D7 G1
D6 G0 LSB
D26 B7 MSB
D25 B6
D17 B5
D16 B4
D15 B3
D14 B2
D13 B1
D12 B0
D20 DE Data Enable
D19 VS Vertical Sync
D18 HS Horizontal Sync
D27 GP General
Purpose
8bpp / LSB on CH3
DS90C187 Input Color
Mapping
Note
D5 R7 MSB
D4 R6
D3 R5
D2 R4
D1 R3
D0 R2
D22 R1
DS90C187 Input Color
Mapping
Note
D21 R0 LSB
D11 G7 MSB
D10 G6
D9 G5
D8 G4
D7 G3
D6 G2
D24 G1
D23 G0 LSB
D17 B7 MSB
D16 B6
D15 B5
D14 B4
D13 B3
D12 B2
D26 B1
D25 B0
D20 DE Data Enable
D19 VS Vertical Sync
D18 HS Horizontal Sync
D27 GP General Purpose
6bpp
DS90C187 Input Color
Mapping
Note
D5 R5 MSB
D4 R4
D3 R3
D2 R2
D1 R1
D0 R0 LSB
D11 G5 MSB
D10 G4
D9 G3
D8 G2
D7 G1
D6 G0 LSB
D17 B5 MSB
D16 B4
D15 B3
D14 B2
D13 B1
D12 B0
D20 DE Data Enable
D19 VS Vertical Sync
D18 HS Horizontal Sync
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DS90C185
Functional Description
DS90C185 converts a wide parallel LVCMOS input bus into
FPD-Link LVDS data. The device can be configured to sup-
port RGB-888 (24-bit color) or RGB-666 (18-bit color). The
DS90C185 has several power saving features including: se-
lectable VOD, 18-bit/24-bit mode select, and a power down
pin control.
Single Pixel Input / Single Pixel Output
In each input pixel clock cycle, data from D[27:0] is serialized
and driven out on TxOUT[3:0] +/- with TxCLKOUT +/-. If
18B_MODE is LOW, then TxOUT3 +/- is powered down and
the corresponding LVCMOS input signals are ignored.
In this configuration input pixel clock can range from 25 MHz
to 105 MHz, resulting in a total maximum payload of 700 Mbps
(28 bits * 25MHz) to 2.94 Gbps (28 bits * 105 MHz). Each
LVDS driver will operate at a speed of 7 bits per input clock
cycle, resulting in a serial line rate of 175 Mbps to 735 Mbps.
TxCLKOUT +/- will operate at the same rate as CLK with a
duty cycle ratio of 57:43.
Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the input LVCMOS
data is latched on. If RFB is HIGH, input data is latched on
the RISING EDGE of the pixel clock (CLK). If RFB is LOW,
the input data is latched on the FALLING EDGE of the pixel
clock. Note: This can be set independently of receiver’s output
clock strobe.
TABLE 1. Pixel Clock Edge
RFB Result
0 FALLING edge
1 RISING edge
Power Management
The DS90C185 has several features to assist with managing
power consumption. The device can be configured through
the MODE0 and MODE1 control pins to enable only the re-
quired number of LVDS drivers for each application. The
18B_MODE pin allows the DS90C185 to power down the un-
used LVDS driver(s) for RGB-666 (18-bit color) applications
for an additional level of power management. If no clock is
applied to the CLK pin, the DS90C185 will enter a low power
state. To place the DS90C185 in its lowest power state, the
device can be powered down by driving the PDB pin to LOW.
Sleep Mode (PDB)
The DS90C185 provides a power down feature. When the
device has been powered down, current draw through the
supply pins is minimized and the PLL is shut down. The LVDS
drivers are also powered down with their outputs pulled to
GND through 100Ω resistors.
TABLE 2. Power Down Select
PDB Result
0 SLEEP Mode (default)
1 ACTIVE (enabled)
LVDS Outputs
The DS90C185's LVDS drivers are compatible with ANSI/
TIA/EIA-64 LVDS receivers. The LVDS drivers an output a
power saving low VOD or a high VOD to enable longer trace
and cable lengths by configuring the VODSEL pin.
TABLE 3. VOD Select
VODSEL Result
0 ±180 mV (360mVpp)
1 ±300 mV (600mVpp)
For more information regarding the electrical characteristics
of the LVDS outputs, refer to the LVDS DC Characteristics
and LVDS Switching Specifications.
18 bit / 24 bit Color Mode (18B)
The 18B pin can be used to further save power by powering
down the 4th LVDS driver in each used bank when the appli-
cation requires only 18 bit color or 3D+C LVDS. Set the 18B
pin to logic HIGH to TRI-STATE® TxOUT3 +/-. For 24 bit color
applications this pin should be set to logic LOW. Note that the
power down function takes priority of the TRI-STATE® func-
tion.
TABLE 4. Color DepthConfigurations
18B Result
0 24bpp, LVDS 4D+C
1 18bpp, LVDS 3D+C
LVCMOS Inputs
The DS90C185 has 28 data inputs. These inputs are typically
used for 24 or 18 bits of RGB video with 1, 2 or 3 video control
signal (HS, VS and DE) inputs. All LVCMOS input pins are
designed for 1.8V LVCMOS logic.
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DS90C185
Applications Information
Power Up Sequence
The VDD power supply pins do not require a specific power on
sequence and can be powered on in any order. Active clock
and data inputs should not be applied to the DS90C185 until
all of the input power pins have been powered on and the
power rails have settled to the recommended operating volt-
age.
The user experience can be impacted by the way a system
powers up and powers down an LCD screen. The following
sequence is recommended:
Power up sequence (DS90C185 PDB input initially LOW):
1. Ramp up LCD power (maybe 0.5ms to 10ms) but keep
backlight turned off.
2. Wait for additional 0-200ms to ensure display noise won’t
occur.
3. Toggle DS90C185 power down pin to PDB = VIH.
4. Enable video source output; start sending black video
data.
5. Send >1ms of black video data; this allows the
DS90C185 to be phase locked, and the display to show
black data first.
6. Start sending true image data.
7. Enable backlight.
Power Down sequence (DS90C185 PDB input initially HIGH):
1. Disable LCD backlight; wait for the minimum time
specified in the LCD data sheet for the backlight to go
low.
2. Video source output data switch from active video data
to black image data (all visible pixel turn black); drive this
for >2 frame times.
3. Set DS90C185 power down pin to PDB = GND.
4. Disable the video output of the video source.
5. Remove power from the LCD panel for lowest system
power.
Power Supply Filtering
The DS90C185 has several power supply pins at 1.8V it is
important that these pins all be connected and properly by-
passed. Bypassing should consist of at least one 0.1µF ca-
pacitor placed on each pin, with an additional 4.7µF – 10µF
capacitor placed on the PLL supply pin (VDDP).
Layout Guidlines
It is important to follow good layout practices for high speed
devices. Noisy components should not be placed next to the
LVDS traces. The LVDS traces must have a controlled differ-
ential impedance of 100Ω. If vias are required for the LVDS
traces, they should be placed symmetrically on each side of
the differential pair with return vias placed nearby to ensure
a consistant return path for the signal. For more tips and detail
suggestions regarding high speed board layout principles,
please consult the LVDS Owner's Manual at:
http://www.national.com/lvds
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DS90C185
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead LLP Quad Package
Dimensions in millimeters only
TI Package Number SQF48A
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DS90C185
Notes
DS90C185 Low Power 1.8V FPD-Link (LVDS) Serializer
www.ti.com
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