ASM5P2304AF-1-08-ST - ON Semiconductor L.L.C.

August, 2011 − Rev. 3

1Publication Order Number:

ASM5P2304A/D

ASM5P2304A

3.3 V Zero Delay Buffer

Description

ASM5P2304A is a versatile, 3.3 V zero−delay buffer designed to

distribute high−speed clocks in PC, workstation, datacom, telecom

and other high−performance applications. It is available in 8−pin

package. The part has an on−chip PLL which locks to an input clock

presented on the REF. The PLL feedback is required to be driven to

FBK pin, and can be obtained from one of the outputs. The

input−to−output propagation delay is guaranteed to be less than

±250 pS, and the output−to−output skew is guaranteed to be less than

200 pS.

ASM5P2304A has two banks of two outputs each. Multiple

ASM5P2304A devices can accept the same input clock and distribute

it. In this case the skew between the outputs of the two devices is

guaranteed to be less than 500 pS.

ASM5P2304A is available in two different configurations. Refer to

ASM5P2304A Configurations Table. The ASM5P2304A−1 is the base

part, where the output frequencies equal the reference if there is no

counter in the feedback path. The ASM5P2304A−1H is the high−drive

version of the −1 and the rise and fall times on this device are faster.

ASM5P2304A−2 allows the user to obtain REF and 1/2x or 2x

frequencies on each output bank. The exact configuration and output

frequencies depend on which output drives the feedback pin.

Features

•Zero Input−Output Propagation Delay, Adjustable by Capacitive

Load on FBK Input

•Multiple Configurations −

Refer to ASM5P2304A Configurations Table

•Input Frequency Range: 10 MHz to 133 MHz

− Multiple Low−skew Outputs

− Output−Output Skew less than 200 pS

− Device−Device Skew less than 500 pS

− Two Banks of Two Outputs Each

•Less than 200 pS Cycle−to−Cycle Jitter

(−1, −1H, −2, −2H)

•8−pin SOIC Package

•3.3 V Operation

•Commercial and Industrial Temperature Range

•Advanced 0.35 m CMOS Technology

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

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SOIC−8

S SUFFIX

CASE 751BD

PIN CONFIGURATION

(Top View)

See detailed ordering and shipping information in the package

dimensions section on page 8 of this data sheet.

ORDERING INFORMATION

FBK

VDD

CLKB2

CLKB1

CLKA1

CLKA2

REF

GND

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Figure 1. Block Diagram

PLL

/2 Extra Divider (−2)

CLKA2

CLKA1

FBK

CLKB1

CLKB2

REF

Table 1. ASM5P2304A CONFIGURATIONS

Device Feedback From Bank A Frequency Bank B Frequency

ASM5P2304A (−1, 1H) Bank A or Bank B Reference Reference

ASM5P2304A (−2, −2H) Bank A Reference Reference /2

ASM5P2304A (−2, −2H) Bank B 2 x Reference Reference

Zero Delay and Skew Control

For applications requiring zero input−output delay, all outputs must be equally loaded.

REF−Input to CLKA / CLKB Delay (pS)

1500

1000

500

−500

−1000

−1500

3025201510

−5−10−15−20−25

−30

Output Load Difference: FBK Load − CLKA/CLKB Load (pF)

Figure 2. REF Input to CLKA/CLKB Delay vs. Difference in Loading

between FBK Pin and CLKA/CLKB Pins

To close the feedback loop of the ASM5P2304A, the FBK

pin can be driven from any of the four available clock

outputs. The output driving the FBK pin will be driving a

total load of 7 pF plus any additional load that it drives. The

relative loading of this output (with respect to the remaining

outputs) can adjust the input−output delay. This is shown in

the above graph.

For applications requiring zero input−output delay, all

outputs including the one providing feedback should be

equally loaded. If input−output delay adjustments are

required, use the above graph to calculate loading

differences between the feedback output and remaining

outputs. For zero output−output skew, be sure to load outputs

equally.

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Table 2. PIN DESCRIPTION

Pin # Pin Name Description

1REF (Note 1) Input reference clock frequency, 5 V tolerant input

2CLKA1 (Note 2) Buffered clock output, bank A

3CLKA2 (Note 2) Buffered clock output, bank A

4 GND Ground

5CLKB1 (Note 2) Buffered clock output, bank B

6CLKB2 (Note 2) Buffered clock output, bank B

7 VDD 3.3 V supply

8 FBK PLL feedback input

1. Weak pull−down.

2. Weak pull−down on all outputs.

Table 3. ABSOLUTE MAXIMUM RATINGS

Parameter Min Max Unit

Supply Voltage to Ground Potential −0.5 +4.6 V

DC Input Voltage (Except REF) −0.5 VDD + 0.5 V

DC Input Voltage (REF) −0.5 7 V

Storage Temperature −65 +150 °C

Max. Soldering Temperature (10 sec) 260 °C

Junction Temperature 150 °C

Static Discharge Voltage (As per JEDEC STD22− A114−B) 2000 V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

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Table 4. OPERATING CONDITIONS

Parameter Description Min Max Unit

VDD Supply Voltage 3.0 3.6 V

TA Operating Temperature

(Ambient Temperature)

Commercial temperature 0 70 °C

Industrial temperature −40 85

CL Load Capacitance, below 100 MHz 30 pF

CL Load Capacitance, from 100 MHz to 133 MHz 15 pF

CIN Input Capacitance (Note 3) 7 pF

3. Applies to both Ref Clock and FBK.

Table 5. ELECTRICAL CHARACTERISTICS

Parameter Description Test Conditions Min Max Unit

VIL Input LOW Voltage 0.8 V

VIH Input HIGH Voltage 2.2 V

IIL Input LOW Current VIN = 0 V 50 mA

IIH Input HIGH Current VIN = VDD 100 mA

VOL Output LOW Voltage (Note 4) IOL = 8 mA (−1, −2)

IOL = 12 mA (−1H, −2H)

0.4 V

VOH Output HIGH Voltage (Note 4) IOH = −8 mA (−1, −2)

IOH = −12 mA (−1H, −2H)

2.4 V

IDD Supply Current Unloaded outputs @ 100 MHz Commercial temp. 35 mA

Industrial temp. 40

Unloaded outputs @ 66 MHz,

(−1, −1H, −2, −2H)

Commercial temp. 25

Industrial temp. 30

Unloaded outputs @ 33 MHz,

(−1, −1H, −2, −2H)

Commercial temp. 16

Industrial temp. 20

4. Parameter is guaranteed by design and characterization. Not 100% tested in production.

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Table 6. SWITCHING CHARACTERISTICS (Notes 5, 6)

Parameter Test Conditions Min Typ Max Unit

Output Frequency 30 pF load (−1, −1H) devices 10 100 MHz

(−2, −2H) devices 12 100

15 pF load (−1, −1H) devices 10 133

(−2, −2H) devices 12 133

Duty Cycle (Note 7)

(−1, −2, −1H, −2H)

Measured at 1.4 V,

FOUT < 66.66 MHz, 30 pF load

40 50 60 %

Duty Cycle (Note 7)

(−1, −2,−1H, −2H)

Measured at 1.4 V,

FOUT ≤ 50 MHz, 15 pF load

45 50 55 %

Output Rise Time (Note 7)

(−1, −2)

Measured between 0.8 V

and 2.0 V, 30 pF load

Commercial temp. 2.2 nS

Industrial temp. 2.5

Output Rise Time (Note 7)

(−1H, −2H)

Measured between 0.8 V

and 2.0 V, 30 pF load

Commercial temp.,

Industrial temp.

1.5 2 nS

Output Rise Time (Note 7)

(−1, −2)

Measured between 0.8 V

and 2.0 V, 15 pF load

1.5 nS

Output Fall Time (Note 7)

(−1, −2)

Measured between 2.0 V

and 0.8 V, 30 pF load

Commercial temp. 2.2 nS

Industrial temp. 2.5

Output Fall Time (Note 7)

(−1H, −2H)

Measured between 2.0 V

and 0.8 V, 30 pF load

Commercial temp.,

Industrial temp.

1.25 1.5 nS

Output Fall Time (Note 7)

(−1, −2)

Measured between 2.0 V

and 0.8 V, 15 pF load

1.5 nS

Output−to−output skew on same bank

(−1, −1H, −2, −2H) (Note 7)

All outputs equally loaded 200 pS

Output bank A −to− output bank B

skew (−1, −1H)

All outputs equally loaded 200

Output bank A to output Bank B

skew (−2, −2H) (Note 7)

All outputs equally loaded 400

Delay, REF Rising Edge to FBK

Rising Edge (Note 7)

Measured at VDD /2 0±250 pS

Device−to−Device Skew (Note 7) Measured at VDD/2 on the FBK pins of the device 0 500 pS

Cycle−to−Cycle Jitter

(Note 7)

(−1, −1H) Measured at 66.67 MHz, loaded outputs, 15 pF load 180 pS

Measured at 66.67 MHz, loaded outputs, 30 pF load 200

Measured at 133 MHz, loaded outputs, 15 pF load 125

(−2, −2H) Measured at 66.67 MHz, loaded outputs, 15 pF load 380

Measured at 66.67 MHz, loaded outputs, 30 pF load 400

PLL Lock Time (Note 7) Stable power supply, valid clock presented on

REF and FBK pins

1.0 mS

5. For all measurements use Test Circuit #1.

6. All parameters are specified at Commercial and Industrial temperature unless stated otherwise.

7. Parameter is guaranteed by design and characterization. Not 100% tested in production.

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Switching Waveforms

Figure 3. Duty Cycle Timing

Figure 4. All Outputs Rise/Fall Time

Figure 5. Output−Output Skew

Figure 6. Input−Output Propagation Delay

Figure 7. Device−Device Skew

OUTPUT

1.4 V 1.4 V 1.4 V

OUTPUT 0 V

VDD

0.8 V

2 V

0.8 V

2 V

OUTPUT

1.4 V

FBK

INPUT

FBK, Device1

FBK, Device2

t3t4

VDD/2

Figure 8. Test Circuit

22 W

CLOAD

CLK A / CLK B

GND

FBK

VDD

ASM5P2304A

+3.3 V

0.1 mF

TEST CIRCUIT #1

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PACKAGE DIMENSIONS

SOIC 8, 150 mils

CASE 751BD−01

ISSUE O

E1 E

PIN # 1

IDENTIFICATION

TOP VIEW

SIDE VIEW END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-012.

SYMBOL MIN NOM MAX

0º 8º

0.10

0.33

0.19

0.25

4.80

5.80

3.80

1.27 BSC

1.75

0.25

0.51

0.25

0.50

5.00

6.20

4.00

L0.40 1.27

1.35

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Table 7. ORDERING INFORMATION

Part Number Marking Package Type Temperature

P5P2304AF−1−08SR 5P2304AF−1 8−pin 150−mil SOIC−TAPE & REEL, Pb free Commercial

ASM5P2304AF−1−08−ST 5P2304AF−1 8−pin 150−mil SOIC−TUBE, Pb free Commercial

ASM5I2304AF−1−08−SR 5I2304AF−1 8−pin 150−mil SOIC−TAPE & REEL, Pb free Industrial

ASM5I2304AF−1−08−ST 5I2304AF−1 8−pin 150−mil SOIC−TUBE, Pb free Industrial

P5P2304AF−1H08SR 5P2304AF−1H 8−pin 150−mil SOIC−TAPE & REEL, Pb free Commercial

ASM5P2304AF−1H−08−ST 5P2304AF−1H 8−pin 150−mil SOIC−TUBE, Pb free Commercial

P5I2304AF−1H08SR 5I2304AF−1H 8−pin 150−mil SOIC−TAPE & REEL, Pb free Industrial

ASM5I2304AF−1H−08−ST 5I2304AF−1H 8−pin 150−mil SOIC−TUBE, Pb free Industrial

P5P2304AF−2−08SR 5P2304AF−2 8−pin 150−mil SOIC−TAPE & REEL, Pb free Commercial

P5P2304AF−2−08ST 5P2304AF−2 8−pin 150−mil SOIC−TUBE, Pb free, Pb free Commercial

ASM5I2304AF−2−08−SR 5I2304AF−2 8−pin 150−mil SOIC−TAPE & REEL, Pb free Industrial

P5I2304AF−2−08ST 5I2304AF−2 8−pin 150−mil SOIC−TUBE, Pb free Industrial

ASM5P2304AF−2H−08−SR 5P2304AF−2H 8−pin 150−mil SOIC−TAPE & REEL, Pb free Commercial

ASM5P2304AF−2H−08−ST 5P2304AF−2H 8−pin 150−mil SOIC−TUBE, Pb free Commercial

ASM5I2304AF−2H−08−SR 5I2304AF−2H 8−pin 150−mil SOIC−TAPE & REEL, Pb free Industrial

ASM5I2304AF−2H−08−ST 5I2304AF−2H 8−pin 150−mil SOIC−TUBE, Pb free Industrial

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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

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ASM5P2304A/D

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