1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2009-2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Single, Dual, Quad General Purpose Micropower, RRIO
Operational Amplifiers
ISL28114, ISL28214, ISL28414
The ISL28114, ISL28214, and ISL28414 are single, dual, and
quad channel general purpose micropower, rail-to-rail input
and output operational amplifiers with supply voltage range of
1.8V to 5.5V. Key features are a low supply current of 390µA
maximum per channel at room temperature, a low bias
current and a wide input voltage range, which enables the
ISL28x14 devices to be excellent general purpose op-amps for
a wide range of applications.
The ISL28114 is available in the SC70-5 and SOT23-5
packages, the ISL28214 is in the MSOP8, SO8 packages, and
the ISL28414 is in the TSSOP14, SOIC14 packages. All devices
operate over the extended temperature range of -40°C to
+125°C.
Related Literature
•See AN1519 for “ISL28213/14SOICEVAL2Z Evaluation
Board User’s Guide”
•See AN1520 for “ISL28113/14SOT23EVAL1Z Evaluation
Board User’s Guide”
•See AN1542 for “ISL28213/14MSOPEVAL2Z Evaluation
Board User’s Guide”
•See AN1547 for “ISL28414TSSOPEVAL1Z Evaluation Board
User’s Guide”
Features
• Low Current Consumption . . . . . . . . . . . . . . . . . . . . . . . 390µA
• Wide Supply Range . . . . . . . . . . . . . . . . . . . . . . . . 1.8V to 5.5V
• Gain Bandwidth Product . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz
• Input Bias Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20pA, Max.
• Operating Temperature Range. . . . . . . . . . .-40°C to +125°C
•Packages
- ISL28114 (Single) . . . . . . . . . . . . . . . . . . . SC70-5, SOT23-5
- ISL28214 (Dual). . . . . . . . . . . . . . . . . . . . . . . . .MSOP8, SO8
- ISL28414 (Quad) . . . . . . . . . . . . . . . . . . . SOIC14, TSSOP14
Applications
• Power Supply Control/Regulation
• Process Control
• Signal Ban/Buffers
• Active Filters
• Current Shunt Sensing
•Trans-impedance Amp
IN-
IN+
RF
RREF+
ISL28x14
+5V
V-
V+
RIN-
10kΩ
RIN+
10kΩ
-
+
100kΩ
VREF
100kΩ
VOUT
LOAD
RSENSE
SINGLE-SUPPLY, LOW-SIDE CURRENT SENSE AMPLIFIER
GAIN = 10
FIGURE 1. TYPICAL APPLICATION
May 10, 2012
FN6800.7
ISL28114, ISL28214, ISL28414
2FN6800.7
May 10, 2012
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL28114FEZ-T7 (Note 1) BKA (Note 4) 5 Ld SC-70 P5.049
ISL28114FEZ-T7A (Note 1) BKA (Note 4) 5 Ld SC-70 P5.049
ISL28114FHZ-T7 (Note 1) BDBA (Note 4) 5 Ld SOT-23 P5.064A
ISL28114FHZ-T7A (Note 1) BDBA (Note 4) 5 Ld SOT-23 P5.064A
ISL28214FUZ 8214Z 8 Ld MSOP M8.118A
ISL28214FUZ-T7 (Note 1) 8214Z 8 Ld MSOP M8.118A
ISL28214FBZ 28214 FBZ 8 Ld SOIC M8.15E
ISL28214FBZ-T7 (Note 1) 28214 FBZ 8 Ld SOIC M8.15E
ISL28214FBZ-T13 (Note 1) 28214 FBZ 8 Ld SOIC M8.15E
ISL28414FVZ 28414 FVZ 14 Ld TSSOP MDP0044
ISL28414FVZ-T7 (Note 1) 28414 FVZ 14 Ld TSSOP MDP0044
ISL28414FVZ-T13 (Note 1) 28414 FVZ 14 Ld TSSOP MDP0044
ISL28414FBZ 28414 FBZ 14 Ld SOIC MDP0027
ISL28414FBZ-T7 (Note 1) 28414 FBZ 14 Ld SOIC MDP0027
ISL28414FBZ-T13 (Note 1) 28414 FBZ 14 Ld SOIC MDP0027
ISL28114SOT23EVAL1Z Evaluation Board
ISL28214MSOPEVAL2Z Evaluation Board
ISL28214SOICEVAL2Z Evaluation Board
ISL28414TSSOPEVAL1Z Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28114, ISL28214, ISL28414. For more information on MSL please
see Tech Brief TB363.
4. The part marking is located on the bottom of the part.
Pin Configurations
ISL28114FEZ
(5 LD SC-70)
TOP VIEW
ISL28114
(5 LD SOT-23)
TOP VIEW
ISL28214
(8 LD MSOP, 8 LD SOIC)
TOP VIEW
IN+
VS-
IN-
VS+
OUT
1
2
3
5
4
OUT
VS-
IN+
VS+
IN-
1
2
3
5
4
OUT_A
IN-_A
IN+_A
VS-
VS+
OUT_B
IN-_B
IN+_B
1
2
3
45
6
7
8
ISL28114, ISL28214, ISL28414
3FN6800.7
May 10, 2012
ISL28414
(14 LD TSSOP, 14 LD SOIC)
TOP VIEW
Pin Configurations (Continued)
OUT_A
IN-_A
IN+_A
VS+
IN+_B
IN-_B
OUT_B
OUT_D
IN-_D
IN+_D
VS-
IN+_C
IN-_C
OUT_C
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Pin Descriptions
PIN NAME
PIN NO.
DESCRIPTION5 Ld SC-70 5 Ld SOT-23
8 Ld MSOP,
8 Ld SOIC
14 Ld TSSOP,
14 LD SOIC
OUT
OUT_A
OUT_B
OUT_C
OUT_D
41
1
7
1
7
8
14
Output
CIRCUIT 1
VS- 2 2 4 11 Negative supply
voltage
CIRCUIT 2
IN+
IN+_A
IN+_B
IN+_C
IN+_D
13
3
5
3
5
10
12
Positive Input
CIRCUIT 3
IN-
IN-_A
IN-_B
IN-_C
IN-_D
34
2
6
2
6
9
13
Negative Input
VS+ 5 5 8 4 Positive supply voltage See “CIRCUIT 2”
V+
V-
OUT
V+
V-
CAPACITIVELY
TRIGGERED
ESD CLAMP
IN+IN-
V+
V-
ISL28114, ISL28214, ISL28414
4FN6800.7
May 10, 2012
Absolute Maximum Ratings (TA = +25°C) Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.5V
Supply Turn-on Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . .V- - 0.5V to V+ + 0.5V
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V- - 0.5V to V+ + 0.5V
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4000V
Machine Model (ISL28114, ISL28214) . . . . . . . . . . . . . . . . . . . . . . . 350V
Machine Model (ISL28414). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400V
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000V
Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)
5 Ld SC-70 (Notes 5, 6) . . . . . . . . . . . . . . . . 250 N/A
5 Ld SOT-23 (Notes 5, 6) . . . . . . . . . . . . . . . 225 N/A
8 Ld MSOP (Notes 5, 6) . . . . . . . . . . . . . . . . 180 100
8 Ld SOIC Package (Notes 5, 6) . . . . . . . . . 126 90
14 Ld TSSOP Package (Notes 5, 6) . . . . . . 120 40
14 Ld SOIC Package (Notes 5, 6) . . . . . . . . 90 50
Ambient Operating Temperature Range . . . . . . . . . . . . . .-40°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications VS+ = 5V, VS- = 0V, RL = Open, VCM = VS/2, TA = +25°C, unless otherwise specified. Boldface limits apply over
the operating temperature range, -40°C to +125°C, unless otherwise specified.
PARAMETER DESCRIPTION CONDITIONS
MIN
(Note 7) TYP
MAX
(Note 7) UNIT
DC SPECIFICATIONS
VOS Input Offset Voltage -4 0.5 4 mV
-40°C to +125°C -5 5 mV
TCVOS Input Offset Voltage Temperature
Coefficient
-40°C to +125°C 5µV/°C
IOS Input Offset Current 130 pA
IBInput Bias Current ISL28114 -20 3 20 pA
-100 100 pA
ISL28214, ISL28414 -20 3 20 pA
-50 50 pA
Common Mode Input
Voltage Range
- 0.1 5.1 V
CMRR Common Mode Rejection Ratio VCM = -0.1V to 5.1V 72 dB
-40°C to +125°C 70 dB
PSRR Power Supply Rejection Ratio VS = 1.8V to 5.5V 71 dB
-40°C to +125°C 70 dB
VOH Output Voltage Swing, High RL = 10kΩ4.985 4.993 V
4.98 V
VOL Output Voltage Swing, Low RL = 10kΩ13 15 mV
20 mV
V+Supply Voltage 1.8 5.5 V
ISSupply Current per Amplifier RL = OPEN 300 390 µA
475 µA
ISC+ Output Source Short Circuit Current RL = 10Ω to V- -31 mA
ISC- Output Sink Short Circuit Current RL = 10Ω to V+ 26 mA
ISL28114, ISL28214, ISL28414
5FN6800.7
May 10, 2012
AC SPECIFICATIONS
GBWP Gain Bandwidth Product VS = ±2.5V
AV = 100, RF = 100kΩ,
RG=1kΩ, RL = 10kΩ to VCM
5MHz
eN VP-P Peak-to-Peak Input Noise Voltage VS = ±2.5V
f = 0.1Hz to 10Hz
12 µVP-P
eNInput Noise Voltage Density VS = ±2.5V
f = 1kHz
40 nV/√(Hz)
iNInput Noise Current Density VS = ±2.5V
f = 1kHz
8fA/√(Hz)
ZIN Input Impedance 1012 Ω
Cin Differential Input Capacitance VS = ±2.5V
f = 1MHz
1.0 pF
Common Mode Input Capacitance 1.3 pF
TRANSIENT RESPONSE
SR Slew Rate VOUT = 0.5V to 4.5V 2.5 V/µs
tr, tf, Small Signal Rise Time, tr 10% to 90% VS = ±2.5V
AV = +1, VOUT = 0.05VP-P,
RF=0Ω, RL = 10kΩ, CL= 15pF
37 ns
Fall Time, tf 10% to 90% 42 ns
tsSettling Time to 0.1%, 4VP-P Step VS = ±2.5V
AV = +1, RF = 0Ω, RL=10kΩ,
CL= 1.2pF
5.6 µs
NOTE:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Electrical Specifications VS+ = 5V, VS- = 0V, RL = Open, VCM = VS/2, TA = +25°C, unless otherwise specified. Boldface limits apply over
the operating temperature range, -40°C to +125°C, unless otherwise specified. (Continued)
PARAMETER DESCRIPTION CONDITIONS
MIN
(Note 7) TYP
MAX
(Note 7) UNIT
ISL28114, ISL28214, ISL28414
6FN6800.7
May 10, 2012
Typical Performance Curves VS = ±2.5V, VCM = 0V, RL = Open, unless otherwise specified.
FIGURE 2. INPUT BIAS CURRENT vs TEMPERATURE FIGURE 3. INPUT NOISE VOLTAGE SPECTRAL DENSITY
FIGURE 4. OPEN-LOOP GAIN, PHASE vs FREQUENCY,
RL= 100kΩ, CL = 10pF, VS = ±0.9V
FIGURE 5. OPEN-LOOP GAIN, PHASE vs FREQUENCY,
RL=100kΩ, CL = 10pF, VS = ±2.5V
FIGURE 6. CMRR vs FREQUENCY (SIMULATED DATA) FIGURE 7. PSRR vs FREQUENCY, VS = ±0.9V, ±2.5V
-50
-40
-30
-20
-10
0
10
20
30
40
50
-40 -20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
IBIAS (pA)
SIMULATION
FREQUENCY (Hz)
10
100
1000
INPUT NOISE VOLTAGE (nV/√Hz)
1 10 100 1k 10k 100k
10,000
V+ = ±2.5V
AV = 1
-80
-60
-40
-20
0
20
40
60
80
100
120
0.1 1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
OPEN LOOP GAIN (dB)
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
20
PHASE (°)
RL = 100k
SIMULATION
CL = 10pF
PHASE
GAIN
V+ = ±0.9V
-80
-60
-40
-20
0
20
40
60
80
100
120
0.1 1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
OPEN LOOP GAIN (dB)
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
20
PHASE (°)
RL = 100k
SIMULATION
CL = 10pF
PHASE
GAIN
V+ = ±0.9V
0
10
20
30
40
50
60
70
80
0.01 0.1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
CMRR (dB)
SIMULATION
1
PSRR (dB)
FREQUENCY (Hz)
100 1k 10k 100k 1M 10M
0
10
20
30
40
50
60
70
80
90
RL = INF
AV = +1
VCM = 100mVP-P
CL = 4pF
PSRR- VS = ±0.9V
PSRR- VS = ±2.5V
PSRR+ VS = ±2.5V
PSRR+ VS = ±0.9V
ISL28114, ISL28214, ISL28414
7FN6800.7
May 10, 2012
FIGURE 8. FREQUENCY RESPONSE vs CLOSED LOOP GAIN FIGURE 9. FREQUENCY RESPONSE vs VOUT
FIGURE 10. GAIN vs FREQUENCY vs RLFIGURE 11. GAIN vs FREQUENCY vs CL
FIGURE 12. GAIN vs FREQUENCY vs SUPPLY VOLTAGE FIGURE 13. CROSSTALK, VS= ±2.5V
Typical Performance Curves VS = ±2.5V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
FREQUENCY (Hz)
GAIN (dB)
100k 1M 10M
10 10k
1k
100 100M
V+ = ±2.5V
VOUT = 50mVP-P
CL = 4pF
RL = 10k
AV = 1
AV = 100
AV = 1000 Rg = 100, Rf = 100k
AV = 10
Rg = OPEN, Rf = 0
Rg = 1k, Rf = 100k
Rg = 10k, Rf = 100k
-10
0
10
20
30
40
50
60
70
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
100 1k 10k 100k 1M 10M 100M
VS = ±2.5V
AV = +1
RL = 10k
CL = 4pF
VOUT = 1VP-P
VOUT = 100mVP-P
VOUT = 50mVP-P
VOUT = 10mVP-P
VOUT = 500mVP-P
VOUT = 200mVP-P
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
V+ = ±2.5V
AV = +1
VOUT = 50mVP-P
CL = 4pF
100 1k 10k 100k 1M 10M 100M
RL = 1k
RL = 100
RL = 4.99k
RL = 499
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
-4
-2
0
2
4
6
8
10
12
14
1k 10k 100k 1M 10M
VS = ±2.5V
RL = 10k
AV = +1
VOUT = 50mVP-P
CL = 474pF
CL = 224pF
CL = 104pF
CL = 26pF
CL = 4pF
CL = 1004pF
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
100k 1M 10M
10k
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
100M
CL = 4pF
RL = 10k
AV = +1
VOUT = 50mVP-P
VS = ±2.5V
VS = ±0.9V
VS = ±1.25V
VS = ±1.75V
0
20
40
60
80
100
120
140
10 100 1k 10k 100k 1M 10M
CROSSTALK (dB)
FREQUENCY (Hz)
RL-RECEIVER = 10k
AV = +1
VSOURCE = 1VP-P
CL = 4pF
RL-DRIVER = INF
VS = ±2.5V
ISL28114, ISL28214, ISL28414
8FN6800.7
May 10, 2012
FIGURE 14. SMALL SIGNAL TRANSIENT RESPONSE, VS= ±2.5V FIGURE 15. LARGE SIGNAL TRANSIENT RESPONSE vs
RLVS= ±0.9V, ±2.5V
FIGURE 16. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,
VS= ±0.9V, ±2.5V
FIGURE 17. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,
VS= ±0.9V, ±2.5V
FIGURE 18. % OVERSHOOT vs LOAD CAPACITANCE, VS= ±2.5V
Typical Performance Curves VS = ±2.5V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
TIME (ns)
SMALL SIGNAL (mV)
-40
-30
-20
-10
0
10
20
30
0 80 160 240 320 400 480 560 640 720 800
RL = 10k
AV = +1
CL = 15pF
VOUT = 50mVP-P
VS = ±2.5V
-3
-2
-1
0
1
2
3
012345678910
TIME (µs)
LARGE SIGNAL (V)
RL = 10k
AV = +1
CL = 15pF
VOUT = RAIL
VS = ±0.9V
VS = ±2.5V
TIME (ms)
INPUT (V)
OUTPUT (V)
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0
0.5
0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.3 3.6 4.0
INPUT
RL = INF
AV =10
CL = 15pF
Rf = 9.09k, Rg = 1k
OUTPUT @ VS = ±0.9V
OUTPUT @ VS = ±2.5V
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
TIME (ms)
INPUT (V)
-0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT (V)
INPUT
RL = INF
AV =10
CL = 15pF
Rf = 9.09k, Rg = 1k
OUTPUT @ VS=±0.9V
OUTPUT @ VS = ±2.5V
0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.3 3.6 4.0
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1k 10k
CAPACITANCE (pF)
OVERSHOOT (%)
OVERSHOOT +
VS = ±2.5V
RL = 10k
AV = 1
VOUT = 50mVP-P
OVERSHOOT -
ISL28114, ISL28214, ISL28414
9FN6800.7
May 10, 2012
Applications Information
Functional Description
The ISL28114, ISL28214 and ISL28414 are single dual and
quad, CMOS rail-to-rail input, output (RRIO) micropower
operational amplifiers. They are designed to operate from single
supply (1.8V to 5.5V) or dual supply (±0.9V to ±2.75V). The parts
have an input common mode range that extends 100mV above
and below the power supply voltage rails. The output stage can
swing to within 15mV of the supply rails with a 10kΩ load.
Input ESD Diode Protection
All input terminals have internal ESD protection diodes to both
positive and negative supply rails, limiting the input voltage to
within one diode beyond the supply rails. For applications where
the input differential voltage is expected to exceed 0.5V, an
external series resistor must be used to ensure the input currents
never exceed 20mA (see Figure 19).
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. The ISL28114, ISL28214 and ISL28414 are immune to
output phase reversal, even when the input voltage is 1V beyond
the supplies.
Unused Channels
If the application requires less than all amplifiers one channel,
the user must configure the unused channel(s) to prevent it from
oscillating. The unused channel(s) will oscillate if the input and
output pins are floating. This will result in higher than expected
supply currents and possible noise injection into the channel
being used. The proper way to prevent this oscillation is to short
the output to the inverting input and ground the positive input (as
shown in Figure 20).
Power Dissipation
It is possible to exceed the +125°C maximum junction
temperatures under certain load, power supply conditions and
ambient temperature conditions. It is therefore important to
calculate the maximum junction temperature (TJMAX) for all
applications to determine if power supply voltages, load
conditions, or package type need to be modified to remain in the
safe operating area. These parameters are related using
Equation 1:
where:
•P
DMAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
•PD
MAX for each amplifier can be calculated using Equation 2:
where:
•T
MAX = Maximum ambient temperature
•θJA = Thermal resistance of the package
•PD
MAX = Maximum power dissipation of 1 amplifier
•V
S = Total supply voltage
•I
qMAX = Maximum quiescent supply current of 1 amplifier
•V
OUTMAX = Maximum output voltage swing of the application
•R
L = Load resistance
ISL28114, ISL28214 and ISL28414 SPICE
Model
Figure 21 shows the SPICE model schematic and Figure 22 shows
the net list for the SPICE model. The model is a simplified version
of the actual device and simulates important AC and DC
parameters. AC parameters incorporated into the model are: 1/f
and flatband noise, Slew Rate, CMRR, Gain and Phase. The DC
parameters are IOS, total supply current and output voltage swing.
The model uses typical parameters given in the “Electrical
Specifications” Table beginning on page 4. The AVOL is adjusted
for 90dB with the dominate pole at 125Hz. The CMRR is set 72dB,
f = 80kHz). The input stage models the actual device to present an
accurate AC representation. The model is configured for ambient
temperature of +25°C.
Figures 23 through 30 show the characterization vs simulation
results for the Noise Voltage, Closed Loop Gain vs Frequency,
Large Signal 5V Step Response and CMRR and Open Loop Gain
Phase.
FIGURE 19. INPUT ESD DIODE CURRENT LIMITING
-
+
RIN-
RL
VIN-
V+
V-
RIN+
RF
RG
FIGURE 20. PREVENTING OSCILLATIONS IN UNUSED CHANNELS
-
+
TJMAX TMAX θJAxPDMAXTOTAL
+= (EQ. 1)
PDMAX VSIqMAX VS
( - VOUTMAX )VOUTMAX
RL
------------------------
×+×=(EQ. 2)
ISL28114, ISL28214, ISL28414
10 FN6800.7
May 10, 2012
LICENSE STATEMENT
The information in this SPICE model is protected under the
United States copyright laws. Intersil Corporation hereby grants
users of this macro-model hereto referred to as “Licensee”, a
nonexclusive, nontransferable licence to use this model as long
as the Licensee abides by the terms of this agreement. Before
using this macro-model, the Licensee should read this license. If
the Licensee does not accept these terms, permission to use the
model is not granted.
The Licensee may not sell, loan, rent, or license the macro-
model, in whole, in part, or in modified form, to anyone outside
the Licensee’s company. The Licensee may modify the macro-
model to suit his/her specific applications, and the Licensee may
make copies of this macro-model for use within their company
only.
This macro-model is provided “AS IS, WHERE IS, AND WITH NO
WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED,
INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.”
In no event will Intersil be liable for special, collateral, incidental,
or consequential damages in connection with or arising out of
the use of this macro-model. Intersil reserves the right to make
changes to the product and the macro-model without prior
notice.
ISL28114, ISL28214, ISL28414
11 FN6800.7
May 10, 2012
.
IN-
IN+
Common Mode
Gain Stage
with Zero
Correction Current
Sources Output Stage
Pole Stage
Input Stage 1st Gain Stage
Mid Supply ref V
Voltage Noise Stage
2nd Gain Stage
28
7
20
13
2
Vin+
2222
Vin-
116
21
21
17
26
Vmid
V-
5
18
V--
V+
3
VOUT
27
En
Vc
8
V++
23
29
15
141414
14
4
12
10
19
916
Vg
Vcm
24
25
0
0
0
0
V11e-6
V11e-6
RA1 1
RA1 1
+
-
G8
GAIN = 6.283e-4
+
-
G8
GAIN =
R6
10
R6
10
M15
NCHANNELMOSFET
M15
NCHANNELMOSFET
V8
.08
V8
.08
R10
1e9
R10
1e9
+
-
G2A
GAIN =
+
-
G2A
GAIN = 351
R2
4.0004
R2
R14
636.6588k
R14
636.6588k
DY
D12
DY
D12
+
-
G5
GAIN = 2.5118E-08
+
-
G5
GAIN = 2.5118E-08
+
-
G4
GAIN = 24.89e-3
+
-
G4
GAIN = 24.89e-3
Cin1
1.26e-12
Cin1
1.26e-12
C5
10e-12
C5
10e-12
Cin2
1.26e-12
Cin2
1.26e-12
DX
D1
DX
D1
M17
PMOSISIL
M17
PMOSISIL
C4
10e-12
C4
10e-12
DX
D3
DX
D3
DY
D11
DY
D11
R20
50
R20
50
V7
.08
V7
.08
-
+
+
-
E2
GAIN = 1
-
+
+
-
E2
GAIN = 1
DX
D10
DX
D10
+
-
G9
GAIN = 0.02
+
-
G9
GAIN = 0.02
R17
1591.596
R17
I1
5e-3
I1
5e-3
+
-
G6
GAIN = 2.5118E-08
+
-
G6
GAIN = 2.5118E-08
CinDif
1.02E-12
CinDif
1.02E-12
R7
4
R7
R5
10
R5
10
V4
.61 V4.61
+
-
G11
GAIN = 0.02
+
-
G11
GAIN = 0.02
-
+
+
-
E3
GAIN = 1
-
+
+
-
E3
GAIN = 1
R12 1
R12 1
DX
D2
DX
D2
R15
10e3
R15
10e3
R13
636.6588k
R13
636.6588k
DX
D4
DX
D4
R21
30
R21
30
V21e-6
V21e-6
V9
0.425
V9
0.425
L2
15.9159E-3
L2
15.9159E-3
R9
100
R9
100
RA2 1
RA2 1
V3
.61 V3.61
DX
D7
DX
D7
DX
D9
DX
D9
+
-
G2
GAIN = 334.753e-3
+
-
G2
GAIN = 334.753e-3
R25
10
R25
10
R23
5e11
R23
5e11
R11 1
R11 1
M16
PMOSISIL
M16
PMOSISIL
-
+
+
-
En
GAIN = 1
-
+
+
-
En
GAIN = 1
+
-
G3
GAIN = 24.89e-3
+
-
G3
GAIN = 24.89e-3
+
-
G12
GAIN = 0.02
+
-
G12
GAIN = 0.02
IOS1
25e-12
IOS1
25e-12
M14
NCHANNELMOSFET
M14
NCHANNELMOSFET
R8
4
R8
R16
10e3
R16
10e3
+
-
G10
GAIN = 0.02
+
-
G10
GAIN = 0.02
+
-
G7
GAIN = 6.283e-4
+
-
G7
GAIN =
DX
D6
DX
D6
R19
50
R19
50
L1
15.9159E-3
L1
15.9159E-3
DX
D5
DX
D5
-
+
+
-
E4
-
+
+
-
E4
DX
D8
DX
D8
-
+
+
-
EOS
GAIN = 1e-3
-
+
+
-
EOS
GAIN =
R22
5e11
R22
5e11
ISY
300e-6 ISY
300e-6
R1
4.0004
R1
+
-
G1
GAIN = 334.753e-3
+
-
G1
GAIN = 334.753e-3
I2
5e-3
I2
5e-3
R18
1591.596
R18
+
-
G1A
GAIN = 351
+
-
G1A
GAIN =
V6
.604 V6
.604
R24
10
R24
10
V5
.604 V5
.604
C2
2E-9
C2
2E-9
C3
2E-9
C3
2E-9
DN
D13
DN
D13
FIGURE 21. SPICE SCHEMATIC
ISL28114, ISL28214, ISL28414
12 FN6800.7
May 10, 2012
FIGURE 22. SPICE NET LIST
*ISL28114 Macromodel - covers following
*products
*ISL28114
*ISL28214
*ISL28414
**
*Revis ion Histor y:
*Revision C, LaFontaine October 20th 2011
*Model for Noise to match measured part,
* quiescent supply currents,
*CMRR 72dB
*fcm=100kHz, AVOL 90dB f=125Hz, SR =
*2.5V/us, GBWP 5MHz, 2nd pole 10Mhz
output voltage clamp and short ckt current
*limit.
**
*Copyright 2011 by Intersil Corporation
*Refer to data sheet "LICENSE
*STATEMENT" Use of this model indicates
*your acceptance with the terms and
*provisions in the License Statement.
*
*Intended use:
*This Pspice Macromodel is intended to give
*typical DC and AC performance
*characteristics under a wide range of
*external circuit configurations using
*compatible simulation platforms - such as
*iSim PE.
*
*Device performance features supported by
*this model:
*Typical, room temp., nominal power supply
*voltages used to produce the following
*characteristics:
*Open and closed loop I/O impedances
*Open loop gain and phase
*Closed loop bandwidth and frequency
*response
*Loading effects on closed loop frequency
*response
*Input noise terms including 1/f effects
*Slew rate
*Input and Output Headroom limits to I/O
*voltage swing
*Supply current at nominal specified supply
*voltages
**
*Devic e performance features NOT
*supported by this model
*Harmonic dist ortion effects
*Disable operation (if any)
*Thermal effects and/or over temperature
*parameter variation
*Limited performance variation vs. supply
*voltage is modeled
*Part to part performance variation due to
*normal process parameter spread
*Any performance difference arising from
*different packaging
* source
* Connections: +input
* | -input
* | | +Vsupply
* | | | -Vsupply
* | | | | output
* | | | | |
.subckt ISL28114 Vin+ Vin- V+ V- VOUT
* source ISL28114_DS rev2
*
*Voltage Noise
E_En VIN+ EN 28 0 1
D_D13 29 28 DN
V_V9 29 0 0.425
R_R21 28 0 30
*
*Input Stage
M_M14 3 1 5 5 NCHANNELMOSFET
M_M15 4 VIN- 6 6 NCHANNELMOSFET
M_M16 11 VIN- 9 9 PMOSISIL
M_M17 12 1 10 10 PMOSISIL
I_I1 7 V-- DC 5e-3
I_I2 V++ 8 DC 5e-3
I_IOS VIN- 1 DC 25e-12
G_G1A V++ 14 4 3 351
G_G2A V-- 14 11 12 351
V_V1 V++ 2 1e-6
V_V2 13 V-- 1e-6
R_R1 3 2 4.0004
R_R2 4 2 4.0004
R_R3 5 7 10
R_R4 7 6 10
R_R5 9 8 10
R_R6 8 10 10
R_R7 13 11 4
R_R8 13 12 4
R_RA1 14 V++ 1
R_RA2 V-- 14 1
C_CinDif VIN- EN 1.02E-12
C_Cin1 V-- EN 1.26e-12
C_Cin2 V-- VIN- 1.26e-12
*
*1st Gain Stage
G_G1 V++ 16 15 VMID 334.753e-3
G_G2 V-- 16 15 VMID 334.753e-3
V_V3 17 16 .61
V_V4 16 18 .61
D_D1 15 VMID DX
D_D2 VMID 15 DX
D_D3 17 V++ DX
D_D4 V-- 18 DX
R_R9 15 14 100
R_R10 15 VMID 1e9
R_R11 16 V++ 1
R_R12 V-- 16 1
*
*2nd Gain Stage
G_G3 V++ VG 16 VMID 24.893e-3
G_G4 V-- VG 16 VMID 24.893e-3
V_V5 19 VG .604
V_V6 VG 20 .604
D_D5 19 V++ DX
D_D6 V-- 20 DX
R_R13 VG V++ 636.658e3
R_R14 V-- VG 636.658e3
C_C2 VG V++ 2E-09
C_C3 V-- VG 2E-09
*
*Mid supply Ref
E_E4 VMID V-- V++ V-- 0.5
E_E2 V++ 0 V+ 0 1
E_E3 V-- 0 V- 0 1
I_ISY V+ V- DC 300e-6
*
*Common Mode Gain Stage with Zero
G_G5 V++ VC VCM VMID 2.5118E-8
G_G6 V-- VC VCM VMID 2.5118E-8
E_EOS 1 EN VC VMID 1e-3
R_R15 VC 21 10e3
R_R16 22 VC 10e3
R_R22 EN VCM 5e11
R_R23 VCM VIN- 5e11
L_L1 21 V++ 15.9159e-3
L_L2 22 V-- 15.9159e-3
*
*Pole Stage
G_G7 V++ 23 VG VMID 6.283e-4
G_G8 V-- 23 VG VMID 6.283e-4
R_R17 23 V++ 1591.596
R_R18 V-- 23 1591.596
C_C4 23 V++ 10e-12
C_C5 V-- 23 10e-12
*
*Output Stage with Correction Current
Sources
G_G9 26 V-- VOUT 23 0.02
G_G10 27 V-- 23 VOUT 0.02
G_G11 VOUT V++ V++ 23 0.02
G_G12 V-- VOUT 23 V-- 0.02
V_V7 24 VOUT .08
V_V8 VOUT 25 .08
D_D7 23 24 DX
D_D8 25 23 DX
D_D9 V++ 26 DX
D_D10 V++ 27 DX
D_D11 V-- 26 DY
D_D12 V-- 27 DY
R_R19 VOUT V++ 50
R_R20 V-- VOUT 50
.model pmosisil pmos (kp=16e-3 vto=-0.6)
.model NCHANNELMOSFET nmos (kp=3e-3
vto=0.6)
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28114
ISL28114, ISL28214, ISL28414
13 FN6800.7
May 10, 2012
Characterization vs Simulation Results
FIGURE 23. CHARACTERIZED INPUT NOISE VOLTAGE FIGURE 24. SIMULATED INPUT NOISE VOLTAGE
FIGURE 25. CHARACTERIZED CLOSED LOOP GAIN vs FREQUENCY FIGURE 26. SIMULATED CLOSED LOOP GAIN vs FREQUENCY
FIGURE 27. CHARACTERIZED LARGE SIGNAL TRANSIENT
RESPONSE vs RL, VS = ±0.9V, ±2.5V
FIGURE 28. SIMULATED LARGE SIGNAL TRANSIENT RESPONSE vs
RL, VS = ±0.9V, ±2.5V
FREQUENCY (Hz)
10
100
1000
INPUT NOISE VOLTAGE (nV/√Hz)
1 10 100 1k 10k 100k
10,000
V+ = ±2.5V
AV = 1
FREQUENCY (Hz)
10
100
1000
INPUT NOISE VOLTAGE (nV/√Hz)
1 10 100 1k 10k 100k
10,000
V+ = ±2.5V
AV = 1
FREQUENCY (Hz)
GAIN (dB)
100k 1M 10M10 10k1k100
70
-10
0
10
20
30
40
50
60
100M
V+ = ±2.5V
VOUT = 50mVP-P
CL = 4pF
RL = 10k
AV = 1
AV = 100
AV = 1000 Rg = 100, Rf = 100k
Rg = 10k, Rf = 100k
Rg = 1k, Rf = 100k
AV = 10
Rg = OPEN, Rf = 0
(A) AC sims.dat (active)
FREQUENCY (Hz)
10 100 1.0k 10k 100k 1.0M 10M 100M
0
20
40
60
-10
70
AV = 100
AV = 1000 Rg = 100, Rf = 100k
Rg = 10k, Rf = 100k
AV = 10
Rg = 1k, Rf = 100k
Rg = 100k, Rf = 100k
GAIN (dB)
-3
-2
-1
0
1
2
3
012345678910
TIME (µs)
RL = 10k
AV = +1
CL = 15pF
VOUT = RAIL
VS = ±0.9V
VS = ±2.5V
LARGE SIGNAL (V)
(A) AC sims.dat (active)
TIME (µs)
510 15 20 25 30
-3
-2
-1
-0
1
2
3
0
RL = 10k
AV = +10
CL = 15pF
VOUT = RAIL
VS = ±2.5V
VOUT
VIN
LARGE SIGNAL (V)
V(VIN+)/VOUT)
ISL28114, ISL28214, ISL28414
14 FN6800.7
May 10, 2012
FIGURE 29. SIMULATED (DESIGN) OPEN-LOOP GAIN, PHASE vs
FREQUENCY
FIGURE 30. SIMULATED (SPICE) OPEN-LOOP GAIN, PHASE vs
FREQUENCY
FIGURE 31. SIMULATED (DESIGN) CMRR FIGURE 32. SIMULATED (SPICE) CMRR
Characterization vs Simulation Results (Continued)
-80
-60
-40
-20
0
20
40
60
80
100
120
0.1 1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
OPEN LOOP GAIN (dB)
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
20
PHASE (°)
RL = 100k
SIMULATION
CL = 10pF
PHASE
GAIN
V+ = ±0.9V
(A) AC2.dat (active)
FREQUENCY (Hz)
0.01 0.1 1.0 10 100 1.0k 10k 100k 1M 10M 100M
0
40
80
120
160
200
GAIN
RL = 10k
MODEL VOS SET TO ZERO
CL = 10pF
FOR THIS TEST
PHASE
OPEN LOOP GAIN (dB)/PHASE (°)
0
10
20
30
40
50
60
70
80
0.01 0.1 1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
CMRR (dB)
SIMULATION
(A) AC sims.dat (active)
0
10
20
30
40
50
60
70
80
0.01 0.1 1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
CMRR (dB)
ISL28114, ISL28214, ISL28414
15 FN6800.7
May 10, 2012
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to Web to make sure you
have the latest Rev.
DATE REVISION CHANGE
April 13, 2012 FN6800.7 Changed the low supply current in “Features” and description on page 1 from 360µA to 390µA.
Removed ISL28114FEV1Z-T7 Coming Soon parts from “Ordering Information” on page 2.
Removed applicable pinout from page 2.
On page 4, changed MIN/MAX limits for “VOS” at 25°C from -5/5mV to -4/4mV.
On page 4, changed MIN/MAX limits for “VOS” at -40°C to 125°C from -6/6mV to -5/5mV.
On page 4, changed “TCVOS” TYP from 2µV/°C to 5µV/°C.
On page 4, changed MAX limit for “IS” MAX at 25°C from 360µA to 390µA.
On page 4, changed MAX limit for “IS” MAX at -40°C to 125°C from 400µA to 475µA.
Revised Figure 8, “FREQUENCY RESPONSE vs CLOSED LOOP GAIN,” on page 7.
Revised Figure 11, “GAIN vs FREQUENCY vs CL,” on page 7.
Revised Figure 18, “% OVERSHOOT vs LOAD CAPACITANCE, VS = ±2.5V,” on page 8.
January 3, 2012 FN6800.6 Revised “SPICE SCHEMATIC” on page 11 and “SPICE NET LIST” on page 12.
May 18, 2011 FN6800.5 - On page 3, Pin Descriptions: Circuit 3 diagram, removed anti-parallel diodes from the IN+ to IN-
terminals.
- On page 4, Absolute Maximum Ratings: changed Differential Input Voltage from "0.5V" to "V- -
0.5V to V+ + 0.5V"
- On page 4, updated CMRR and PSRR parameters in Electrical Specifications table with test
condition specifying -40°C to 125°C typical parameter.
- On page 5, updated Note 7, referenced in MIN and MAX column headings of Electrical
Specifications table, from "Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not
production tested." to new standard "Compliance to datasheet limits is assured by one or more
methods: production test, characterization and/or design."
- On page 9, under “Input ESD Diode Protection,” removed “They also contain back to-back
diodes across the input terminals.” Removed “Although the amplifier is fully protected, high
input slew rates that exceed the amplifier slew rate (±2.5V/µs) may cause output distortion.”
- On page 9, Figure 19: updated circuit schematic by removing back-to-back input protection
diodes.
- On page 11 replaced SPICE schematic (Figure 21)
- On page 12 replaced SPICE Netlist (Figure 22)
- On page 13 replaced Figure 24
- On page 14 replaced Figure 32
September 23, 2010 FN6800.4 Added new SC70 pinout package extension as follows:
Added to Related Literature on page 1 “See AN1547 for “ISL28414TSSOPEVAL1Z Evaluation
Board User’s Guide”.
Added to ordering information ISL28114FEV1Z-T7 and ISL28114FEV1Z-T7A and Evaluation
boards.
Added to Pin Configurations new pinout for ISL28114FEV1Z.
Added in Pin Descriptions ISL28114FEV1Z SC70 pin description column.
July 28, 2010 Changed Note 6 on page page 4 from “For θJC, the “case temp” location is the center of the
exposed metal pad on the package underside.” to
“For θJC, the “case temp” location is taken at the package top center.”
May 13, 2010 Added “Related Literature” on page 1.
Changed package outline drawing from MDP0038 to P5.064A on page 2 and page 18.
MDP0038 package contained 2 packages for both the 5 and 6 Ld SOT-23. MDP0038 was
obsoleted and the packages were separated and made into 2 separate package outline
drawings; P5.064A and P6.064A. Changes to the 5 Ld SOT-23 were to move dimensions from
table onto drawing, add land pattern and add JEDEC reference number.
Added Note 4 to “Ordering Information” on page 2.
December 16, 2009 FN6800.3 Removed “Coming Soon” from MSOP package options in the “Ordering Information” on page 2.
Updated the Theta JA for the MSOP package option from 170°C/W to 180°C/W on page 4.
November 17, 2009 FN6800.2 Removed “Coming Soon” from SC70 and SOT-23 package options in the “Ordering Information”
on page 2.
November 12, 2009 FN6800.1 Changed theta Ja to 250 from 300. Added license statement (page 10) and reference in spice
model (page 12).
ISL28114, ISL28214, ISL28414
16
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6800.7
May 10, 2012
For additional products, see www.intersil.com/product_tree
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL28114, ISL28214, ISL28414
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/search.php
October 23, 2009 FN6800.0 Initial Release
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to Web to make sure you
have the latest Rev. (Continued)
DATE REVISION CHANGE
ISL28114, ISL28214, ISL28414
17 FN6800.7
May 10, 2012
Small Outline Transistor Plastic Packages (SC70-5)
D
e1
E
E1
C
L
C
C
L
eb
C
L
A2
AA1
C
L
0.20 (0.008) M
0.10 (0.004) C
C
-C-
SEATING
PLANE
45
123
VIEW C
VIEW C
L
R1
R
4X θ1
4X θ1
GAUGE PLANE
L1
SEATING
αL2
C
PLANE
c
BASE METAL
WITH
c1
b1
PLATING
b
0.4mm
0.75mm
0.65mm
2.1mm
TYPICAL RECOMMENDED LAND PATTERN
P5.049
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.031 0.043 0.80 1.10 -
A1 0.000 0.004 0.00 0.10 -
A2 0.031 0.039 0.80 1.00 -
b 0.006 0.012 0.15 0.30 -
b1 0.006 0.010 0.15 0.25
c 0.003 0.009 0.08 0.22 6
c1 0.003 0.009 0.08 0.20 6
D 0.073 0.085 1.85 2.15 3
E 0.071 0.094 1.80 2.40 -
E1 0.045 0.053 1.15 1.35 3
e 0.0256 Ref 0.65 Ref -
e1 0.0512 Ref 1.30 Ref -
L 0.010 0.018 0.26 0.46 4
L1 0.01 7 R ef. 0.420 Ref. -
L2 0.006 BSC 0.15 BSC
α0o8o0o8o-
N5 55
R 0.004 - 0.10 -
R1 0.004 0.010 0.15 0.25
Rev. 3 7/07
NOTES:
1. Dimensioning and tolerances per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC70 and JEDEC MO-203AA.
3. Dimensions D and E1 are exclusive of mold flash, protrusions , or gate
burrs.
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
6. These Dimensions apply to the flat section of the lead between 0.08mm
and 0.15mm from the lead tip.
7. Controlling dimension: MILLIMETER. Convert ed inch dimensions
are for reference only.
ISL28114, ISL28214, ISL28414
18 FN6800.7
May 10, 2012
Package Outline Drawing
P5.064A
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
Rev 0, 2/10
Dimension is exclusive of mold flash, protrusions or gate burrs.
This dimension is measured at Datum “H”.
Package conforms to JEDEC MO-178AA.
Foot length is measured at reference to guage plane.
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to ASME Y14.5M-1994.
6.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
DETAIL "X"
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
INDEX AREA
PIN 1
SEATING PLANE
GAUGE
0.45±0.1
(2 PLCS)
10° TYP
4
1.90
0.40 ±0.05
2.90
0.95
1.60
2.80
0.05-0.15
1.14 ±0.15
0.20 CA-B DM
(1.20)
(0.60)
(0.95)
(2.40)
0.10 C
0.08-0.20
SEE DETAIL X
1.45 MAX
(0.60)
0-3°
C
B
A
D
3
3
3
0.20 C
(1.90)
2x
0.15 C
2x
D
0.15 C
2x
A-B
(0.25)
H
5
2
4
5
5
END VIEW
PLANE
ISL28114, ISL28214, ISL28414
19 FN6800.7
May 10, 2012
Package Outline Drawing
M8.118A
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP)
Rev 0, 9/09
Plastic or metal protrusions of 0.15mm max per side are not
Dimensions “D” and “E1” are measured at Datum Plane “H”.
This replaces existing drawing # MDP0043 MSOP 8L.
Plastic interlead protrusions of 0.25mm max per side are not
Dimensioning and tolerancing conform to JEDEC MO-187-AA
6.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
DETAIL "X"
SIDE VIEW 1
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
SIDE VIEW 2
included.
included.
GAUGE
PLANE
3°±3°
0.25 C A B
B
0.10 C
0.08 C A B
A
0.25
0.55 ± 0.15
0.95 BSC
0.18 ± 0.05
1.10 Max
C
H
4.40
3.00
5.80
0.65
3.0±0.1 4.9±0.15
1.40
0.40
0.65 BSC
PIN# 1 ID
DETAIL "X"
0.33 +0.07/ -0.08 0.10 ± 0.05
3.0±0.1
12
8
0.86±0.09
SEATING PLANE
and AMSE Y14.5m-1994.
ISL28114, ISL28214, ISL28414
20 FN6800.7
May 10, 2012
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
Unless otherwise specified, tolerance : Decimal ± 0.05
The pin #1 identifier may be either a mold or mark feature.
Interlead flash or protrusions shall not exceed 0.25mm per side.
Dimension does not include interlead flash or protrusions.
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
DETAIL "A"
SIDE VIEW “A
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
A
B
4
4
0.25 AMC B
C
0.10 C
5
ID MARK
PIN NO.1
(0.35) x 45°
SEATING PLANE
GAUGE PLANE
0.25
(5.40)
(1.50)
4.90 ± 0.10
3.90 ± 0.10
1.27 0.43 ± 0.076
0.63 ±0.23
4° ± 4°
DETAIL "A" 0.22 ± 0.03
0.175 ± 0.075
1.45 ± 0.1
1.75 MAX
(1.27) (0.60)
6.0 ± 0.20
Reference to JEDEC MS-012.
6.
SIDE VIEW “B”
ISL28114, ISL28214, ISL28414
21 FN6800.7
May 10, 2012
Small Outline Package Family (SO)
GAUGE
PLANE
A2
A1 L
L1
DETAIL X
4° ±4°
SEATING
PLANE
eH
b
C
0.010 BMCA
0.004 C
0.010 BMCA
B
D
(N/2)
1
E1
E
NN (N/2)+1
A
PIN #1
I.D. MARK
h X 45°
A
SEE DETAIL “X”
c
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SYMBOL
INCHES
TOLERANCE NOTESSO-8 SO-14 SO16
(0.150”) SO16 (0.300”)
(SOL-16) SO20
(SOL-20) SO24 (SOL-
24) SO28 (SOL-
28)
A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX -
A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 -
A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 -
b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 -
c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 -
D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3
E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 -
E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3
e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic -
L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 -
L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic -
h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference -
N 8 14 16 16 20 24 28 Reference -
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not inclu ded.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
ISL28114, ISL28214, ISL28414
22 FN6800.7
May 10, 2012
Thin Shrink Small Outline Package Family (TSSOP)
N(N/2)+1
(N/2)
TOP VIEW
AD
0.20 C
2X
B A
N/2 LEAD TIPS
B
E1
E
0.25 CAB
M
1
H
PIN #1 I.D.
0.05
e
C
0.10 C
N LEADS SIDE VIEW
0.10 CABM
b
c
SEE DETAIL “X”
END VIEW
DETAIL X
A2
0° - 8°
GAUGE
PLANE
0.25
L
A1
A
L1
SEATING
PLANE
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
SYMBOL
MILLIMETERS TOLER-
ANCE14 LD 16 LD 20 LD 24 LD 28 LD
A 1.20 1.20 1.20 1.20 1.20 Max
A1 0.10 0.10 0.10 0.10 0.10 ±0.05
A2 0.90 0.90 0.90 0.90 0.90 ±0.05
b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06
c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06
D 5.00 5.00 6.50 7.80 9.70 ±0.10
E 6.40 6.40 6.40 6.40 6.40 Basic
E1 4.40 4.40 4.40 4.40 4.40 ±0.10
e 0.65 0.65 0.65 0.65 0.65 Basic
L 0.60 0.60 0.60 0.60 0.60 ±0.15
L1 1.00 1.00 1.00 1.00 1.00 Reference
Rev. F 2/07
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15mm per
side.
2. Dimension “E1” does not include interlead flash or pr otrusions. In ter-
lead flash and protrusions shall not exceed 0.25mm per side.
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
