FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus 3.3 Volt Synchronous x10/x20 First-In/First-Out Queue Memory Organization Device Memory Organization Device 262,144 x 20 / 524,286 x 10 131,072 x 20 / 262,144 x 10 65,536 x 20 / 131,072 x 10 32,768 x 20 / 65,536 x 10 FQV202113 FQV202103 FQV20293 FQV20283 16,384 x 20 / 32,768 x 10 8,192 x 20 / 16,384 x 10 4,096 x 20 / 8,192 x 10 2,048 x 20 / 4,096 x 10 FQV20273 FQV20263 FQV20253 FQV20243 Key Features * * * * * * * * * * * * * * * * * * * * * Industry leading First-In/First-Out Queues (up to 166MHz) Write cycle time of 6.0ns independent of Read cycle time (Data Setup time = 2.0ns) Read cycle time of 6.0ns independent of Write cycle time (Data Access time = 4.0ns) User selectable input and output port bus-sizing Big Endian/Little Endian user selectable byte representation 3.3V power supply 5V input tolerant on all control and data input pins 5V output tolerant on all flags and data output pins Master Reset clears all previously programmed configurations including Write and Read pointers Partial Reset clears Write and Read pointers but maintains all previously programmed configurations First Word Fall Through (FWFT) and Standard Timing modes Presets for eight different Almost Full and Almost Empty offset values Parallel/Serial programming of PRAF and PRAE offset values Programmable 8-bit or 10-bit parallel programming modes for offset values Full, Empty, Almost Full, Almost Empty, and Half Full indicators PRAF and PRAE operates in either synchronous or asynchronous modes Asynchronous output enable tri-state data output drivers Data retransmission with programmable zero or normal latency modes Available package: 144 - pin Plastic Thin Quad Flat Pack (TQFP) (0C to 70C) Commercial operating temperature available for cycle time of 6.0ns and above (-40C to 85C) Industrial operating temperature available for cycle time of 7.5ns and above Product Description HBA's FlexQTM III Plus offers industry leading FIFO queuing bandwidth (up to 3.0 Gbps), with a wide range of memory configurations (from 2,048 x 20 to 262,144 x 20 or 4,096 x 10 to 524,286 x 10). System designer has full flexibility of implementing deeper and wider queues using FWFT mode and width expansion features. Full, Empty, and Half-Full indicators allow easy handshaking between transmitters and receivers. User programmable Almost Full and Almost Empty (Parallel/Serial) indicators allow implementation of virtual queue depths. 5V tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. Asynchronous Output Enable pin configures the tri-state data output drivers. Independent Write and Read controls provide rate-matching capability. Master Reset clears all previously programmed configurations by providing a low pulse on MRST pin. In addition, Write and Read pointers to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will initialize Write and Read pointers to zero. In FWFT mode, the first data written into the queue appears on output data bus after the specified latency period at the low to high transition of RCLK. Subsequent reads from the queue will require asserting REN . This feature is useful when implementing depth expansion functions. In this mode, DRDY and QRDY are used instead of FULL and EMPTY respectively. 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 1 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus Product Description (Continued) In Standard mode, always assert REN whenever a read operation. FULL and EMPTY are used instead of DRDY and QRDY respectively. Bus matching feature is available with the following configurations: Input Bus Width x10 x10 x20 x20 Output Bus Width x10 x20 x10 x20 In addition, Endian Select is available for implementing byte re-ordering on data outputs. Eight different default offset values are available for Almost Full ( PRAF ) and Almost Empty ( PRAE ) flags. Parallel and Serial programming of these offset values provide total flexibility other than the pre-defined default values. Both 8-bit and 10-bit parallel programming modes for offset values can be selected for convenience. PRAF , PRAE , and HALF are available in either FWFT or Standard mode. PRAF and PRAE can operate in either synchronous or asynchronous modes. At any time, data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the physical 0th (Read pointer = zero), location of the queue. Both zero and normal latency timing modes are available for retransmit operation. These FlexQTM III Plus devices have low power consumption, hence minimizing system power requirements. In addition, industry standard 144 - pin Plastic TQFP is offered to save system board space. These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test equipment, network switching, etc. . 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 2 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus Block Diagram of Single Synchronous Queue 262,144 x 20 / 131,072 x 20 / 65,536 x 20 / 32,768 x 20 / 16,384 x 20 / 8,192 x 20 / 4,096 x 20 / 2,048 x 20 / 524,286 x 10 / 262,144 x 10 / 131,072 x 10 / 65,536 x 10 / 32,768 x 10 / 16,384 x 10 / 8,192 x 10 / 4,096 x 10 PARTIAL RESET ( PRST ) MASTER RESET ( MRST) READ CLOCK (RCLK) WRTIE CLOCK (WCLK) READ ENABLE ( REN ) WRITE ENABLE ( WEN) OUTPUT ENABLE ( OE ) LOAD ( LOAD) x20 or x10 DATA IN (D 19 - 0) SERIAL DATA ENABLE ( SDEN ) FIRST WORD FALL THROUGH/ SERIAL DATA INPUT (FWFT/SDI) FULL FLAG / INPUT READY ( FULL / DRDY ) PROGRAMMABLE ALMOST-FULL (PRAF) FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20253 FQV20243 x20 or x10 DATA OUT (Q 19 - 0) RETRANSMIT ( RET ) EMPTY FLAG / OUTPUT READY (EMPTY / QRDY ) PROGRAMMABLE ALMOSTEMPTY ( PRAE ) HALF-FULL FLAG ( HALF ) BIG-ENDIAN / LITTLE-ENDIAN ( ES ) INTERSPERSED / NON-INTERSPERSED PARITY (IPAR) BUS MATCHING 1 (BM1) BUS MATCHING 0 (BM0) Figure 1. Single Device Configuration Signal Flow Diagram 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 3 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus WCLK IPAR WEN LOAD SDEN FWFT/SDI FULL / DRDY Write Control Logic PRAF EMPTY/ QRDY Offset Register PRAE HALF FWFT/SDI SFM Flag Logic Write Pointer PFS1 PFS0 D 19-0 x20, x10 Input Register SRAM Output Register Output Buffer Q 19-0 x20, x10 OE Read Pointer Read Control Logic RETZL RET RCLK REN Reset MRST PRST Bus Configuration ES BM1 BM0 Figure 2. Device Architecture 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 4 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 GND GND RCLK REN RET OE 112 111 110 109 115 113 RETZL 116 114 SFM EMPTY/QRDY 117 PRAE DNC1 118 120 119 Vcc DNC1 121 Vcc DNC1 124 122 IPAR 125 123 GND ES 126 129 GND PFS0 HALF 130 PFS1 BM0 131 127 GND GND 134 132 PRAF 135 133 Vcc Vcc 136 GND FULL/DRDY 139 137 GND 140 138 LOAD FWFT/SDI 141 PRST MRST 142 WCLK 143 144 FlexQTMIII Plus 128 Index WEN 1 108 Q19 SDEN 2 107 Q18 GND 3 106 Vcc Vcc 4 105 Q17 BM1 5 104 DNC1 D19 6 103 DNC1 DNC1 7 102 GND DNC1 8 101 DNC1 DNC1 9 100 DNC1 D18 10 99 Vcc Q16 Vcc 11 98 DNC1 12 97 DNC1 DNC1 13 96 Q15 D17 14 95 DNC1 DNC 15 94 DNC1 D16 16 93 Vcc DNC1 17 92 Q14 D15 18 91 Q13 DNC1 19 90 GND DNC1 1 D14 20 89 DNC1 21 88 DNC1 GND 22 87 Q12 D13 23 86 Vcc Vcc 24 85 DNC1 DNC1 25 84 DNC1 D12 26 83 DNC1 DNC1 27 82 GND 66 68 69 70 71 72 DNC1 DNC1 DNC1 DNC1 Q6 65 DNC1 67 64 GND Vcc 63 Q5 Vcc 62 Q4 61 58 Q2 60 57 GND Vcc 56 Q1 Vcc 55 Q0 59 54 Q3 53 D0 GND D2 Vcc Vcc D6 DNC1 D7 52 Q7 D1 73 51 36 50 DNC1 49 Q8 48 74 47 35 D3 DNC1 Vcc D4 Q9 75 46 76 34 45 33 D8 D5 DNC1 GND Q10 44 77 GND 32 43 Vcc D9 42 78 DNC1 31 DNC1 DNC1 DNC1 41 79 40 30 39 DNC1 D10 38 Q11 80 37 81 29 DNC1 28 DNC1 D11 DNC1 TQFP - 144 (Drw No: PF-03A: Order code: PF) Top View NOTES: 1. DNC = Do Not Connect. Figure 3. Device Pin Out 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 5 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus Pin # 142 Pin Name Master Reset Pin Symbol MRST Input/Output Description Input Master Reset is required to initialize Write and Read pointers to the first position of the queue by setting MRST low. In Standard mode, FULL and PRAF will go high; EMPTY and PRAE will go low. In FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state as Standard mode. In both modes, all data outputs will go low. Previous programmed configurations will not be maintained. 143 Partial Reset PRST Input Partial Reset is required to initialize Write and Read pointers to the first position of the queue by setting PRST low. In Standard mode, FULL and PRAF will go high; EMPTY and PRAE will go low. In FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state as Standard mode. In both modes, all data outputs will go low. Previous programmed configurations will be maintained. 144 Write Clock WCLK Input Writes data into queue during low to high transitions of WCLK if WEN is set to low. 1 Write Enable WEN Input Controls write operation into queue or offset registers during low to high transition of WCLK. 141 Load Enable LOAD Input During Master Reset, set LOAD low to select parallel programming or one of eight default-offset values. Set LOAD high to select serial programming or one of eight default offset values. After Master Reset, LOAD controls write/read, to/from offset registers during low to high transition of WCLK/RCLK respectively. Use in conjunction with WEN / REN . 127 Default Programming 1 PFS1 Input During Master Reset, select one of eight default-offset values. Use in conjunction with LOAD and PFS1. 130 Default Programming 0 PFS0 Input During Master Reset, select one of eight default-offset values. Use in conjunction with LOAD and PFS0. 06,10,14,16, 18,20,23,26, 28,30,32,34, 39,41,46,47, 48,51,52,53. Data Inputs D19-0 Input 20 - bit wide input data bus. 112 Read Clock RCLK Input Reads data from queue during low to high transitions of RCLK if REN is set to low. 111 Read Enable REN Input Controls read operation from queue or offset registers during low to high transition of RCLK. 109 Output Enable OE Input Setting OE low activates the data output drivers. Setting OE high deactivates the data output drivers (High-Z). Table 1. Pin Descriptions 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 6 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus Pin # Pin Name Pin Symbol Input/Output 108,107,105,98, 96,92,91,87, 81,77,76,74, 73,72,63,62, 59,58,56,55 Data Outputs Q19-0 Output Description 20 - bit wide output data bus. Input Selects FWFT timing or Standard timing mode during Master Reset. After Master Reset, if serial programming is selected ( LOAD = high), FWFT/SDI is used as the serial data input for the offset registers. Serial data is written during the low to high transition of WCLK. Use in conjunction with SDEN . SDEN Input If serial programming is selected, setting SDEN low and LOAD low enables serial data input to be written into offset registers during the low to high transition of WCLK. Bus Matching 1 BM1 Input During Master Reset, set BM1 low to select x20 input bus width or BM1 high to select x10 input bus width. 131 Bus Matching 0 BM0 Input During Master Reset, set BM0 low to select x20 output bus width or BM0 high to select x10 output bus width. 125 Endian Select ES Input During Master Reset, set ES high to select byte reordering on data outputs or ES low to select no byte re-ordering on data outputs. 140 First Word Fall Through/Serial Data Input 2 Serial Data Input Enable 5 FWFT/SDI 110 Retransmit RET Input Data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the physical 0th (Read pointer = zero) location of the queue. 115 Zero Latency Retransmit RETZL Input During Master Reset, set RETZL low to select zero latency retransmit or RETZL high to select normal latency retransmit. 137 Full/Data Input Ready Flag FULL / DRDY Output Queue is full when FULL goes low during the low to high transition of WCLK. This prohibits further writes into the queue. In FWFT mode, queue is full when DRDY goes high during low to high transition of WCLK. This prohibits further writes into the queue. 116 Empty/Data Output Ready Flag EMPTY / QRDY Output Queue is empty when EMPTY goes low during the low to high transition of RCLK. This prohibits further reads from the queue. In FWFT mode, queue is empty when QRDY goes high during the low to high transition of RCLK. This prohibits further reads from the queue. 124 Interspersed Parity IPAR Input During Master Reset, set IPAR low to select 10-bit parallel programming mode or IPAR high to select 8bit parallel programming mode. Table 1. Pin Descriptions (Continued) 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 7 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus Description Pin # Pin Name Pin Symbol Input/Output 117 Synchronous Partial Flag Mode SFM Input During Master Reset, set SFM high to select Synchronous Partial Flag mode or SFM low to select Asynchronous Partial Flag mode. Output Queue is almost full when PRAF goes low during the low to high transition of WCLK. Default (Full-offset) or programmed offset values determine the status of PRAF . 134 Almost Full PRAF 119 Almost Empty PRAE Output Queue is almost empty when PRAE goes low during the low to high transition of RCLK. Default (Empty +offset) or programmed offset values determine the status of PRAE . 129 Half Full HALF Output Queue is more than half full when HALF goes low. Triggered by both WCLK and RCLK. 07,08,09,12, 13,15,17,19, 21,25,27,29, 31,33,36,37, 38,40,42,43, 65,68,69,70, 71,75,79,80, 83,84,85,88, 89,94,95,97, 100,101,103, 104,118,120, 122. Do Not Connect DNC N/A Do not connect. 04,11,24,35, 49,50,60,61, 66,67,78,86, 93,99,106,121, 123,135,136. Power VCC N/A 3.3V power supply. 03,22,44,45, 54,5764,82, 90,102,113, 114,118,120, 126,128,132, 133,138,139 Ground GND N/A 0V Ground. Table 1. Pin Descriptions (Continued) 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 8 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus Symbol Com'l & Ind'l Unit Terminal Voltage with respect to GND -0.5 to + 4.5 V TSTG Storage Temperature -55 to +125 IOUT DC Output Current -50 to +50 VTERM Rating NOTES: Absolute Max Ratings are for reference only. Permanent damage to the device may occur if extended period of operation is outside this range. Standard operation should fall within the Recommended Operating Conditions. C mA Table 2. Absolute Maximum Ratings FQV202113, FQV202103FQV20293, FQV20283 FQV20273, FQV20263, FQV20253, FQV20243 Commercial Clock = 6ns, 7.5ns, 10ns Industrial Clock = 7.5ns, 10ns, 15ns Symbol Parameter Recommended Operating Conditions Min. Typ. Max. Min. Typ. Max. Unit Vcc Supply Voltage Com'l / Ind'l 3.15 3.3 3.45 3.15 3.3 3.45 V GND Supply Voltage 0 0 0 0 0 0 V VIH Input High Voltage Com'l / Ind'l 2.0 - 5.5 2.0 - 5.5 V VIL Input Low Voltage Com'l / Ind'l - - 0.8 - - 0.8 V TA Operating Temperature Commercial 0 - 70 0 - 70 TA Operating Temperature Industrial -40 - 85 -40 - 85 C C DC Electrical Characteristics ILI(1) Input Leakage Current (any input) -10 - 10 -10 - 10 A ILO Output Leakage Current -10 - 10 -10 - 10 A VOH Output Logic "1" Voltage, IOH=-2mA 2.4 - - 2.4 - - V VOL Output Logic "0" Voltage, IOL = 8mA - - 0.4 - - 0.4 V ICC1(2,3) Active Power Supply Current (x10 Input to x10 Output) - - 30 - - 30 mA ICC1(2,3) Active Power Supply Current (x20 Input to x20 Output) - - 35 - - 35 mA ICC2(4) Standby Current - - 15 - - 15 mA Power Consumption Table 3. DC Specifications 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 9 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus Capacitance at 100MHz Ambient Temperature (25C) Symbol Parameter CIN(2) Input Capacitance COUT(2,4) Output Capacitance Conditions Max. Unit VIN= 0V 10 pF VOUT= 0V 10 pF NOTES: 1. 2. 3. 4. Measurement with 0.4<=VIN<=Vcc. With output tri-stated ( OE = High). Icc(1,2) is measured with WCLK and RCLK at 20 MHz. Design simulated, not tested. Table 3. DC Specifications (Continued) 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 10 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus Commercial FQV202113-6 FQV202103-6 FQV20293-6 FQV20283-6 FQV20273-6 FQV20263-6 FQV20253-6 FQV20243-6 Symbol Parameter Commercial & Industrial FQV202113-7.5 FQV202103-7.5 FQV20293-7.5 FQV20283-7.5 FQV20273-7.5 FQV20263-7.5 FQV20253-7.5 FQV20243-7.5 FQV202113-10 FQV202103-10 FQV20293-10 FQV20283-10 FQV20273-10 FQV20263-10 FQV20253-10 FQV20243-10 Min. Max. Min. Max. Min. Max. Unit fS Clock Cycle Frequency - 166 - 133 - 100 MHz tA Data Access Time 1 4 2 5 2 6.5 ns tWCLK Write Clock Cycle Time 6 - 7.5 - 10 - ns tWCLKH Write Clock High Time 2.5 - 3.5 - 4.5 - ns tWCLKL Write Clock Low Time 2.5 - 3.5 - 4.5 - ns tRCLK Read Clock Cycle Time 6 - 7.5 - 10 - ns tRCLKH Read Clock High Time 2.5 - 3.5 - 4.5 - ns tRCLKL Read Clock Low Time 2.5 - 3.5 - 4.5 - ns tDS Data Set-up Time 2.0 - 2.5 - 3.5 - ns tDH Data Hold Time 0.5 - 0.5 - 0.5 - ns tENS Enable Set-up Time 2.0 - 2.5 - 3.5 - ns tENH Enable Hold Time 0.5 - 0.5 - 0.5 - ns 8 - 10 - 10 - ns 15 - ns (1) tRST Reset Pulse Width tRSTS Reset Set-up Time 10 - 15 tRSTR Reset Recovery Time 10 - 10 - 10 - ns tRSTF Reset to Flag and Output Time - 10 - 15 - 15 ns 0 - 0 - 0 - ns (1) tOLZ Output Enable to Output in Low-Z tOE Output Enable to Output Valid 2 4 2 6 2 6 ns tOHZ Output Enable to Output in High-Z(1) 2 4 2 6 2 6 ns tFULL Write Clock to Full Flag - 4 - 5 - 6.5 ns tEMPTY Read Clock to Empty Flag - 4 - 5 - 6.5 ns tPRAFS Write Clock to Synchronous Almost-Full Flag - 4 - 5 - 6.5 ns tPRAES Read Clock to Synchronous Almost-Empty Flag - 4 - 5 - 6.5 ns tSKEW1 Skew time between Read Clock & Write Clock for Full Flag / Empty Flag 4 - 5 - 7 - ns tSKEW2 Skew time between Read Clock & Write Clock for PRAE & PRAF 6 - 7 - 10 - ns tLOADS Load Setup Time 2 - 2.5 - 3.5 - ns tLOADH Load Hold Time 0.5 - 0.5 - 0.5 - ns Table 4. AC Electrical Characteristics 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 11 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus Commercial Symbol Parameter Commercial & Industrial FQV202113-6 FQV202103-6 FQV20293-6 FQV20283-6 FQV20273-6 FQV20263-6 FQV20253-6 FQV20243-6 FQV202113-7.5 FQV202103-7.5 FQV20293-7.5 FQV20283-7.5 FQV20273-7.5 FQV20263-7.5 FQV20253-7.5 FQV20243-7.5 FQV202113-10 FQV202103-10 FQV20293-10 FQV20283-10 FQV20273-10 FQV20263-10 FQV20253-10 FQV20243-10 Min. Max. Min. Max. Min. Max. Unit tRETS Retransmit Setup Time 3 - 3.5 - 3.5 - ns tHALF Clock to HALF - 12 - 12.5 - 16 ns tPRAFA Write Clock to Asynchronous Programmable Almost-Full Flag - 12 - 12.5 - 16 ns tPRAEA Read Clock to Asynchronous Programmable Almost-Empty Flag - 12 - 12.5 - 16 ns NOTES: 1. Design simulated, not tested. Table 4. AC Electrical Characteristics (Continued) 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 12 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load, clock = 6ns, 7.5ns, 10ns Refer to Figure 4 Table 5. AC Test Condition Vcc/2 50 I/O Z0 = 50 Figure 4. AC Test Load for clock = 6ns, 7.5ns, 10ns 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 13 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus Pin Functions MRST Master Reset is required to initialize Write and Read pointers to the first position of the queue by setting MRST low. In Standard mode, FULL and PRAF will go high; EMPTY and PRAE will go low. In FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state as Standard mode. In both modes, all data outputs will go low. Previous programmed configurations will not be maintained. PRST Partial Reset is required to initialize Write and Read pointers to the first position of the queue by setting PRST low. In Standard mode, FULL and PRAF will go high; EMPTY and PRAE will go low. In FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state as Standard mode. In both modes, all data outputs will go low. Previous programmed configurations will be maintained. WCLK Writes data into queue during low to high transitions of WCLK if WEN is activated. Synchronizes FULL / DRDY and PRAF flags. WCLK and RCLK are independent of each other. WEN Controls write operation into queue or offset registers during low to high transition of WCLK. LOAD During Master Reset, set LOAD low to select parallel programming or one of eight default offset values. Set LOAD high to select serial programming or one of eight default offset values. After Master Reset, LOAD controls write/read, to/from offset registers during low to high transition of WCLK/RCLK respectively for parallel programming. Use in conjunction with WEN / REN . During programming of offset registers, PRAF and PRAE flag status is invalid. For Serial programming, LOAD is used to enable serial loading of offset registers together with SDEN . Refer to Figure 5 & Table 11 for details. PFS1 During Master Reset, select one of eight default-offset values. Use in conjunction with LOAD and PFS1. Refer to Table 11 for details. PFS0 During Master Reset, select one of eight default-offset values. Use in conjunction with LOAD and PFS0. Refer to Table 11 for details. D19-0 20 - bit wide input data bus. RCLK Reads data from queue during low to high transitions of RCLK if REN is set low. Synchronizes the EMPTY / QRDY and PRAE flags. RCLK and WCLK are independent of each other. REN Reads data from queue during low to high transitions of RCLK if REN is set low. This also advances the Read pointer of the queue. OE Setting OE low activates the data output drivers. Setting OE high deactivates the data output drivers (High-Z). OE does not control advancement of Read pointer. Q19-0 20 - bit wide output data bus. FWFT/SDI Selects FWFT timing or Standard timing mode during Master Reset. After Master Reset, if serial programming is selected ( LOAD = high), FWFT/SDI is used as the serial data input for the offset registers. Serial data is written during the low to high transition of WCLK. Use in conjunction with SDEN . In FWFT mode, DRDY and QRDY is used instead of FULL and EMPTY . Refer to Table 9 for all flags status. In Standard mode, FULL and EMPTY are used instead of DRDY and QRDY . Refer to Table 9 for all flags status. SDEN If serial programming is selected, setting SDEN low and LOAD low enables serial data to be written into offset registers during the low to high transition of WCLK. During serial programming, PRAF and PRAE flags status is invalid. Refer to Figure 5 for details. 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 14 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus Pin Functions (Continued) BM1 During Master Reset, setting BM1 low selects x20 input bus width. Set BM1 high selects x10 input bus width. Refer to Table 10 for details. BM0 During Master Reset, set BM0 low to select x20 output bus width. Set BM0 high to select x10 output bus width. Refer to Table 10 for details. ES During Master Reset, Set ES high to select byte re-ordering on data outputs or set ES low to select no byte re-ordering on data outputs. ES must be static throughout device operation. Refer to Table 10 for details. RET Data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the physical 0th (Read pointer = zero), location of the queue. Refer to Diagram 7 & 8 for details. RETZL During Master Reset, set RETZL low to select zero latency retransmit or set RETZL high to select normal latency retransmit. FULL / DRDY In Standard mode, queue is full when FULL goes low during the low to high transition of WCLK. This prohibits further writes into the queue and prevents advancement of Write pointer. In FWFT mode, queue is full when DRDY goes high during the low to high transition of WCLK. This prohibits further writes into the queue and prevents advancement of Write pointer. Refer to Table 8 & 9 for behavior of FULL / DRDY . EMPTY / QRDY In Standard mode, queue is empty when EMPTY goes low during the low to high transition of RCLK. This prohibits further reads from the queue and prevents advancement of Read pointer. In FWFT mode, queue is empty when QRDY goes low during the low to high transition of RCLK. This prohibits further reads from the queue and prevents advancement of Read pointer. Refer to Table 8 & 9 for behavior of EMPTY / QRDY . IPAR During Master Reset, set IPAR low to select 10-bit parallel programming mode or set IPAR high to select 8-bit parallel programming mode. In 10-bit mode, 10-bit wide data input/output bus width is used for storing/fetching offset values. In 8-bit mode, 8-bit wide data input/output bus is used for storing/fetching offset values. SFM During Master Reset, set SFM high to select Synchronous Partial Flag mode or set SFM low to select Asynchronous Partial Flag mode. In Synchronous mode, PRAF and PRAE are synchronous to WCLK and RCLK respectively. In Asynchronous mode, WCLK synchronizes the assertion of PRAF and deassertion of PRAE . RCLK synchronizes the assertion of PRAE and de-assertion of PRAE . PRAF In Synchronous mode, queue is almost full when PRAF goes low during the low to high transition of WCLK. Default (Full-offset) or programmed offset values determine the status of PRAF . In Asynchronous mode, PRAF is triggered by both WCLK and RCLK. Refer to Table 8 & 9 for behavior of PRAF . PRAE In Synchronous mode, queue is almost empty when PRAE goes low during the low to high transition of RCLK. Default (Empty+offset) or programmed offset values determine the status of PRAE . In Asynchronous timing mode, PRAF is triggered by both WCLK and RCLK. Refer to Table 8 & 9 for behavior of PRAE . HALF Queue is more than half full when HALF goes low during the low to high transition of WCLK. HALF goes high during low to high transition of RCLK when queue is less than half full. Refer to Table 8 & 9 for details. 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 15 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus LOAD 0 WEN 0 0 1 REN 1 0 SDEN WCLK 1 RCLK X 1 X 0 1 1 0 X 1 1 1 1 0 X X 1 X 0 X X 1 1 1 X X X FQV20283 FQV20273 FQV20263 FQV20253 FQV20243 Selection / Sequence Parallel write to offset registers: Empty Offset (Low Byte) Empty Offset (High Byte) Full Offset (Low Byte) Full Offset (High Byte) Parallel write to registers: 1. PRAE Low Byte 2. PRAE High Byte 3. PRAF Low Byte 4. PRAF High Byte Parallel read from offset registers: Empty Offset (Low Byte) Empty Offset (High Byte) Full Offset (Low Byte) Full Offset (High Byte) Parallel read from registers: 1. PRAE Low Byte 2. PRAE High Byte 3. PRAF Low Byte 4. PRAF High Byte X x10 to x10 Mode Serial shift into registers: 32 bits for the FQV20283 30 bits for the FQV20273 28 bits for the FQV20263 26 bits for the FQV20253 24 bits for the FQV20243 1 bit for each rising WCLK edge Starting with Empty Offset (Low Byte) Ending with Full Offset (High Byte) X No Operation X Write Memory All Other Modes Serial shift into registers: 30 bits for the FQV20283 28 bits for the FQV20273 26 bits for the FQV20263 24 bits for the FQV20253 22 bits for the FQV20243 1 bit for each rising WCLK edge Starting with Empty Offset (Low Byte) Ending with Full Offset (High Byte) Read Memory X No Operation Figure 5. Programmable Flag Offset Programming Sequence (FQV20283, FQV20273, FQV20263, FQV20253 and FQV20243) 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 16 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus LOAD 0 0 WEN 0 1 REN 1 0 SDEN WCLK 1 RCLK X 1 X 0 1 1 0 X 1 1 1 1 0 X X 1 X 0 X X 1 1 1 X X X FQV202113 FQV202103 FQV20293 Selection / Sequence Parallel write to offset registers: Empty Offset (Low Byte) Empty Offset (Mid Byte) Empty Offset (High Byte) Full Offset (Low Byte) Full Offset (Mid Byte) Full Offset (High Byte) Parallel write to registers: 1. PRAE Low Byte 2. PRAE Mid Byte 3. PRAE High Byte 4. PRAF Low Byte 5. PRAF Mid Byte 6. PRAF High Byte Parallel read from offset registers: Empty Offset (Low Byte) Empty Offset (Mid Byte) Empty Offset (High Byte) Full Offset (Low Byte) Full Offset (Mid Byte) Full Offset (High Byte) Parallel read from registers: 1. PRAE Low Byte 2. PRAE Mid Byte 3. PRAE High Byte 4. PRAF Low Byte 5. PRAF Mid Byte 6. PRAF High Byte X x10 to x10 Mode Serial shift into registers: 38 bits for the FQV202113 36 bits for the FQV202103 34 bits for the FQV20293 1 bit for each rising WCLK edge Starting with Empty Offset (Low Byte) Ending with Full Offset (High Byte) X No Operation X Write Memory All Other Modes Serial shift into registers: 36 bits for the FQV202113 34 bits for the FQV202103 32 bits for the FQV20293 1 bit for each rising WCLK edge Starting with Empty Offset (Low Byte) Ending with Full Offset (High Byte) Read Memory X No Operation Figure 6. Programmable Flag Offset Programming Sequence (FQV202113, FQV202103, FQV20293) 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 17 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus Device PRAF Programming (bits) FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20253 FQV20243 PRAE Programming (bits) D/Q15 - 0 Non-IPAR D/Q15 - 0 Non-IPAR D/Q17 - 10 & D/Q7 - 0 IPAR D/Q17 - 10 & D/Q7 - 0 IPAR D/Q15 - 0 Non-IPAR D/Q15 - 0 Non-IPAR D/Q17 - 10 & D/Q7 - 0 IPAR D/Q17 - 10 & D/Q7 - 0 IPAR D/Q15 - 0 Non-IPAR D/Q15 - 0 Non-IPAR D/Q17 - 10 & D/Q7 - 0 IPAR D/Q17 - 10 & D/Q7 - 0 IPAR D/Q14 - 0 Non-IPAR D/Q14 - 0 Non-IPAR D/Q16 - 10 & D/Q7 - 0 IPAR D/Q16 - 10 & D/Q7 - 0 IPAR D/Q13 - 0 Non-IPAR D/Q13 - 0 Non-IPAR D/Q15 - 10 & D/Q7 - 0 IPAR D/Q15 - 10 & D/Q7 - 0 IPAR D/Q12 - 0 Non-IPAR D/Q12 - 0 Non-IPAR D/Q14 - 10 & D/Q7 - 0 IPAR D/Q14 - 10 & D/Q7 - 0 IPAR D/Q11 - 0 Non-IPAR D/Q11 - 0 Non-IPAR D/Q13 - 10 & D/Q7 - 0 IPAR D/Q13 - 10 & D/Q7 - 0 IPAR D/Q10 - 0 Non-IPAR D/Q10 - 0 Non-IPAR IPAR D/Q12 - 10 & D/Q7 - 0 IPAR D/Q12 - 10 & D/Q7 - 0 Condition Applies to: Write Cycle with x20 input Bus Width and/or Read Cycle with x20 output Bus Width Device FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20253 FQV20243 PRAF Programming (bits) PRAE Programming (bits) D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q7 - 0 Mid Byte D/Q7 - 0 Mid Byte D/Q1 - 0 High Byte D/Q1 - 0 High Byte D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q7 - 0 Mid Byte D/Q7 - 0 Mid Byte D/Q0 High Byte D/Q 0 High Byte D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q7 - 0 High Byte D/Q7 - 0 High Byte D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q6 - 0 High Byte D/Q6 - 0 High Byte D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q5 - 0 High Byte D/Q5 - 0 High Byte D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q4 - 0 High Byte D/Q4 - 0 High Byte D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q3 - 0 High Byte D/Q3 - 0 High Byte D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q2 - 0 High Byte D/Q2 - 0 High Byte Condition Applies to: Write Cycle with x10 input Bus Width or Read Cycle with x10 output Bus Width (except x10 to x10 mode) 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 18 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus Device PRAF Programming (bits) FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20253 FQV20243 PRAE Programming (bits) D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q7 - 0 Mid Byte D/Q7 - 0 Mid Byte D/Q2 - 0 High Byte D/Q2 - 0 High Byte D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q7 - 0 Mid Byte D/Q7 - 0 Mid Byte D/Q1 - 0 High Byte D/Q1 - 0 High Byte D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q7 - 0 Mid Byte D/Q7 - 0 Mid Byte D/Q0 High Byte D/Q0 High Byte D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q7 - 0 High Byte D/Q7 - 0 High Byte D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q6 - 0 High Byte D/Q6 - 0 High Byte D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q5 - 0 High Byte D/Q5 - 0 High Byte D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q4 - 0 High Byte D/Q4 - 0 High Byte D/Q7 - 0 Low Byte D/Q7 - 0 Low Byte D/Q3 - 0 High Byte D/Q3 - 0 High Byte Condition Applies to: Write Cycle with x10 input Bus Width and Read Cycle with x10 output Bus Width (only x10 to x10 mode) Table 6. Parallel Offset Write/Read Cycle Register Location Device Standard Mode FWFT Mode FQV202113 262,144 x 20 / 524,288 x10 262,145 x 20 / 524,289 x10 FQV202103 131,072 x 20 / 262,144 x10 131,073 x 20 / 262,145 x 10 FQV20293 65,536 x 20 / 131,072 x 10 65,537,x 20 / 131,073 x 10 FQV20283 32,768 x 20 / 65,536 x 10 32,769 x 20 / 65,537 x 10 FQV20273 16,384 x 20 / 32,768 x 10 16,385 x 20 / 32,769 x 10 FQV20263 8,192 x 20 / 16,384 x 10 8,193 x 20 / 16,385 x 10 FQV20253 4,096 x 20 / 8,192 x 10 4,097 x 20 / 8,193 x 10 FQV20243 2,048 x 20 / 4,096 x 10 2,049 x 20 / 4,097 x 10 Table 7. Maximum Depth of Queue for Standard and FWFT Mode 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 19 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus Data Width D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 1st Cycle PRAE Low Byte 7 66 55 4 37 2 17 0 2nd Cycle PRAE High Byte 15 14 13 12 11 10 9 8 3rd Cycle PRAF Low Byte 77 66 55 4 37 2 17 0 4th Cycle PRAF High Byte 15 14 13 12 11 10 9 8 FQV20293, FQV20283, FQV20273, FQV20263, FQV20253, FQV20243 Parallel Offset Write/Read Cycles for x10 Bus Width Condtion Applies to: Write Cycle with x10 input Bus Width and/or Read Cycle output with x10 Bus Width (except FQV20293 x10 to x10 mode) Data Width D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 1st Cycle PRAE Low Byte 7 66 55 4 37 2 17 0 2nd Cycle PRAE Mid Byte 15 14 13 12 11 10 9 8 18 17 16 3rd Cycle PRAE High Byte 4th Cycle PRAF Low Byte 77 66 55 4 37 2 17 0 5th Cycle PRAF Mid Byte 15 14 13 12 11 10 9 8 18 17 16 6th Cycle PRAF High Byte FQV202113, FQV202103, FQV20293 Parallel Offset Write/Read Cycles for x10 Bus Width Condtion Applies to: FQV20293 x10 to x10 mode or FQV202113, FQV202103 for all modes 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 20 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus x10 to x10 Mode All Other Modes # of Bits for Offset Registers # of Bits for Offset Registers 19 bits for FQV202113 18 bits for FQV202103 17 bits for FQV20293 16 bits for FQV20283 15 bits for FQV20273 14 bits for FQV20263 13 bits for FQV20253 12 bits for FQV20243 18 bits for FQV202113 17 bits for FQV202103 16 bits for FQV20293 15 bits for FQV20283 14 bits for FQV20273 13 bits for FQV20263 12 bits for FQV20253 11 bits for FQV20243 Note: Don't Care applies to all unused bits Note: Don't Care applies to all unused bits Figure 7. Parallel Offset Write/Read Cycle Diagram 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 21 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus Data Width D/Q19 D/Q18 D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 1st Cycle PRAE Non-Interspersed Parity Interspersed Parity Data Width 15 14 15 14 13 12 11 10 13 12 11 10 9 8 D/Q19 D/Q18 D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 2nd Cycle PRAF Non-Interspersed Parity Interspersed Parity 15 14 15 14 13 12 11 10 13 12 11 10 9 8 FQV20293, FQV20283, FQV20273, FQV20263, FQV20253, FQV20243 Parallel Offset Write/Read Cycles for x20 Bus Width Condtion Applies to: Write Cycle with x20 input Bus Width and/or Read Cycle for x20 output Bus Width Data Width D/Q19 D/Q18 D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Non-Interspersed Parity 17 16 Interspersed Parity 17 16 1st Cycle PRAE Non-Interspersed Parity Interspersed Parity 15 14 15 14 13 12 11 10 13 12 11 10 9 8 2nd Cycle PRAE 3rd Cycle PRAF Non-Interspersed Parity 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Non-Interspersed Parity 17 16 Interspersed Parity 17 16 Interspersed Parity 15 14 15 14 13 12 11 10 13 12 11 10 9 8 9 8 4th Cycle PRAF FQV202113, FQV202103 Parallel Offset Write/Read Cycles for x20 Bus Width Condtion Applies to: Write Cycle with x20 input Bus Width and/or Read Cycle for x20 output Bus Width Figure 7. Parallel Offset Write/Read Cycles Diagram (Continued) 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 22 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus FQV202113 BM1 = BM0 = x10 0 1 to y(1) (y+1) to 262,144 262,145 to [524,288-(x+1)] (524,288 -x) to 524,287 524,288 FQV202103 FQV202113 BM1 = BM0 = x10 BM1 BM0 or BM1 = BM0 = x20 0 1 to y(1) (y+1) to 131,072 131,073 to [262,144-(x+1)] (262,144 -x) to 262,143 262,144 FQV20293 FQV202103 BM1 = BM0 = x10 BM1 BM0 or BM1 = BM0 = x20 0 1 to y(1) (y+1) to 65,536 65,537 to [131,072-(x+1)] (131,072 -x) to 131,071 131,072 FQV20283 FQV20293 BM1 = BM0 = x10 BM1 BM0 or BM1 = BM0 = x20 0 1 to y(1) (y+1) to 32,768 32,769 to [65,536-(x+1)] (65,536 -x) to 65,535 65,536 FQV20273 FQV20283 BM1 = BM0 = x10 BM1 BM0 or BM1 = BM0 = x20 0 1 to y(1) (y+1) to 16,384 16,385 to [32,768-(x+1)] (32,768 -x) to 32,767 32,768 FULL PRAF HALF PRAE H H H H H L H H H H L L H H H L L L L L H H H H EMPTY L H H H H H FULL PRAF HALF PRAE EMPTY H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H FULL PRAF HALF PRAE EMPTY H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H FULL PRAF HALF PRAE EMPTY H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H FULL PRAF HALF PRAE EMPTY H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H NOTES: 1. See Table 11 for values x, y. Table 8. Status Flags (Standard Mode) 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 23 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus FQV20263 FQV20273 BM1 = BM0 = x10 BM1 BM0 or BM1 = BM0 = x20 0 1 to y(1) (y+1) to 8,192 8,193 to [16,384-(x+1)] (16,384 -x) to 16,383 16,384 FQV20253 FQV20263 BM1 = BM0 = x10 BM1 BM0 or BM1 = BM0 = x20 0 1 to y(1) (y+1) to 4,096 4,097 to [8,192-(x+1)] (8,192 -x) to 8,191 8,192 FQV20243 FQV20253 BM1 = BM0 = x10 BM1 BM0 or BM1 = BM0 = x20 0 1 to y(1) (y+1) to 2,048 2,049 to [4,096-(x+1)] (4,096 -x) to 4,095 4,096 FULL PRAF HALF PRAE EMPTY H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H FULL PRAF HALF PRAE EMPTY H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H FULL PRAF HALF PRAE EMPTY H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H FULL PRAF HALF PRAE H H H H H L H H H H L L H H H L L L L L H H H H EMPTY L H H H H H FQV20243 BM1 BM0 or BM1 = BM0 = x20 0 1 to y(1) (y+1) to 1,024 1,025 to [2,048-(x+1)] (2,048-x) to 2,047 2,048 NOTES: 1. See Table 11 for values x, y. Table 8. Status Flags (Standard Mode) (Continued) 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 24 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus FQV202113 BM1 = BM0 = x10 0 1 to y+1(1) (y+2) to 262,145 262,146 to [524,289-(x+1)] (524,289-x) to 524,288 524,289 FQV202103 FQV202113 BM1 = BM0 = x10 BM1 BM0 or BM1 = BM0 = x20 0 1 to y+1(1) (y+2) to 131,073 131,074 to [262,145-(x+1)] (262,145-x) to 262,144 262,145 FQV20293 FQV202103 BM1 = BM0 = x10 BM1 BM0 or BM1 = BM0 = x20 0 1 to y+1(1) (y+2) to 65,637 65,638 to [131,073-(x+1)] (131,073-x) to 131,072 131,073 FQV20283 FQV20293 BM1 = BM0 = x10 BM1 BM0 or BM1 = BM0 = x20 0 1 to y+1(1) (y+2) to 32,769 32,770 to [65,537-(x+1)] (65,537 -x) to 65,536 65,537 FQV20273 FQV20283 BM1 = BM0 = x10 BM1 BM0 or BM1 = BM0 = x20 0 1 to y+1(1) (y+2) to 16,385 16,386 to [32,769-(x+1)] (32,769-x) to 32,768 32,769 DRDY PRAF HALF PRAE QRDY L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L FULL PRAF HALF PRAE EMPTY L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L FULL PRAF HALF PRAE EMPTY L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L DRDY PRAF HALF PRAE QRDY L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L DRDY PRAF HALF PRAE QRDY L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L NOTES: 1. See Table 11 for values x, y. Table 9. Status Flags (FWFT Mode) 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 25 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus FQV20263 FQV20273 BM1 = BM0 = x10 BM1 BM0 or BM1 = BM0 = x20 0 1 to y+1(1) (y+2) to 8,193 8,194 to [16,385-(x+1)] (16,385 -x) to 16,384 16,385 FQV20253 FQV20263 BM1 = BM0 = x10 BM1 BM0 or BM1 = BM0 = x20 0 1 to y+1(1) (y+2) to 4,097 4,098 to [8,193-(x+1)] (8,193 -x) to 8,192 8,193 FQV20243 FQV20253 BM1 = BM0 = x10 BM1 BM0 or BM1 = BM0 = x20 0 1 to y+1(1) (y+2) to 2,049 2,050 to [4,097-(x+1)] (4,097-x) to 4,096 4,097 DRDY PRAF HALF PRAE QRDY L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L FULL PRAF HALF PRAE EMPTY L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L FULL PRAF HALF PRAE EMPTY L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L DRDY PRAF HALF PRAE QRDY L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L FQV20243 BM1 BM0 or BM1 = BM0 = x20 0 1 to y+1(1) (y+2) to 1,025 1,026 to [2,049 -(x+1)] (2,049 -x) to 2,048 2,049 NOTES: 1. See Table 11 for values x, y. Table 9. Status Flags (FWFT Mode) (Continued) 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 26 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus ES BM1 BM0 I/O Width D/Q19 - 10 D/Q9 - 0 Sequence 0 0 0 I 20 Byte 2 Byte 1 1st Write O 20 Byte 2 Byte 1 1st Read I 20 Byte 2 Byte 1 1st Write O 10 X Byte 2 1st Read X Byte 1 2nd Read X Byte 2 1st Write X Byte 1 2nd Write 0 0 X 0 1 1 1 0 1 I O 20 Byte 2 Byte 1 1st Read I 10 X Byte 2 1st Write X Byte 1 2nd Write X Byte 2 1st Read X Byte 1 2nd Read O 1 1 1 0 0 1 0 1 0 10 10 I 20 Byte 2 Byte 1 1st Write O 20 Byte 1 Byte 2 1st Read I 20 Byte 2 Byte 1 1st Write O 10 X Byte 1 1st Read X Byte 2 2nd Read X Byte 2 1st Write X Byte 1 2nd Write Byte 1 Byte 2 1st Read I O 10 20 Table 10. Bus-Matching Table 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 27 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus PFS0 LOAD FQV20273 FQV20263 FQV20253 FQV20243 PFS1 Offsets x, y LOAD 0 0 0 127 0 0 1 511 0 1 0 255 0 1 1 63 1 0 0 1,023 1 0 1 31 1 1 0 15 1 1 1 7 PFS0 FQV202113 FQV202103 FQV20293 FQV20283 Offsets x, y PFS1 All Other Modes x10 to x10 Mode Offsets x, y 0 0 0 127 127 127 0 0 1 511 16,383 16,383 0 1 0 255 8,191 8,191 0 1 1 63 4,095 4,095 1 0 0 1,023 1,023 1,023 1 0 1 31 2,047 2,047 1 1 0 15 511 511 1 1 1 7 255 255 NOTES: 1. x = PRAF offset, y = PRAE offset. Table 11. Default Programmable Flag Offsets 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 28 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus Timing Diagrams t R ST M RST t R ST S t RSTR t R ST S t RSTR t R ST S t RSTR t R ST S t RSTR REN W EN FW FT/SDI LO AD t R ST S PFS1/PFS0 t RSTS BM 1/BM 0 t R ST S ES t R ST S RETZL t R ST S SFM t R ST S IPAR t R ST S R ET t R ST S SDEN t R ST F If FW FT = 1,Q RD Y = 1 EM PTY / Q RD Y If FW FT = 0, EM PTY = 0 t R ST F If FW FT = 0, FULL = 1 FULL / DRDY If FW FT = 1, DR DY = 0 t R ST F PRAE t R ST F PRAF / H ALF t R ST F OE = 1 Q 19 - 0 OE = 0 Diagram 1. Master Reset Timing 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 29 of 30 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus tRST PRST tRSTS tRSTR tRSTS tRSTR REN WEN tRSTS RET tRSTS SDEN tRSTF If FWFT = 1,QRDY = 1 EMPTY / QRDY If FWFT = 0, EMPTY = 0 tRSTF If FWFT = 0, FULL = 1 FULL / DRDY If FWFT = 1, DRDY = 0 tRSTF PRAE tRSTF PRAF / HALF tRSTF OE = 1 Q19 - 0 OE = 0 Diagram 2. Partial Reset Timing 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 30 of 30 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. 2. 1. tENS tA tENH Output Register Data tSKEW1 1 No Write tFULL 2 tDS tWCLKH DWi tENS tFULL tDH ___________ Data Read tWCLK tSKEW1 tWCLKL tA tENH 1 No Write tFULL 2 DWi + 1 __________ Next Data Read tDS tFULL tDH ______ LOAD = High, OE = Low. ___________ Diagram 3. Write Cycle and Full Flag Timing (Standard Mode) If the time between a rising edge of RCLK to the rising edge of WCLK is greater or equal than tSKEW1, FULL will go high (after one WCLK cycle plus tFULL). If tSKEW1 is not met, then FULL will assert 1 or more WCLK cycles. NOTES: Q 19 - 0 REN RCLK WEN FULL D 19 - 0 WCLK No Write FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus JULY 2002 Page 31 of 31 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. 2. 3. 1. tENS tOLZ tA tEMPTY tENS tENH tDS tSKEW1 DW1 tOEN tDH tENH tOHZ Last Word 1 tDS tENS DW2 tEMPTY ______________ tDH tENH tOLZ 2 tRCLK Last Word tENS tA tRCLKL tENH ______________ DW1 tEMPTY tENS tA tENH DW2 Diagram 4. Read Cycle, Empty Flag and First Data Word Latency Timing (Standard Mode) LOAD = High. First word latency: tSKEW1 + tEMPTY + 1 * tRCLK. ___________ If the time between a rising edge of WCLK to the rising edge of RCLK is greater or equal than tSKEW11, EMPTY will go high (after RCLK cycle plus tEMPTY). If tSKEW1 is not met, then EMPTY will assert 1 or more RCLK cycles. NOTES: D19 - 0 WEN WCLK OE Q19 - 0 EMPTY REN RCLK tRCLKH FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus JULY 2002 Page 32 of 32 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. tDS tENS 4. 5. 6. 3. 2. 1. 1 tSKEW1 DW2 Output Register Data DW1 tDH 2 DW3 3 DW4 tEMPTY tA tDS DW1 DW[y+2] 1 tSKEW2 DW[y+3] 2 DW[y+4] tPRAES DW[(D-1)/2+1] tDS DW[(D-1)/2+2] ____________ tHALF DW[(D-1)/2+3] DW[D-x-3] tDS DW[D-x] DW[D-x+1] 1 DW[D-x+2] 2 tPRAFS DW[D-x+2] DW[D-1] DWD ____________ tFULL tENH ___________ ______ ___________ y = PRAE offset, x = PRAF offset. D = maximum queue depth. Please refer to Table 7 for Depth. First word latency: tSKEW1 + tEMPTY + 2 * tRCLK ___________ LOAD = High, OE = Low. ___________ Diagram 5. Write Timing (FWFT Mode) If the time between a rising edge of WCLK to the rising edge of RCLK is greater or equal than tSKEW2, PRAE will go high (after one RCLK cycle plus tPRAES). If tSKEW2 is not met, then PRAE will assert 1 or more RCLK cycles. ___________ If the time between a rising edge of WCLK to the rising edge of RCLK is greater or equal than tSKEW1, QRDY will go low (after two RCLK cycle plus tEMPTY). If tSKEW1 is not met, then QRDY will assert 1 or more RCLK cycles. NOTES: DRDY PRAF HALF PRAE QRDY Q 19 - 0 REN RCLK D 19 - 0 WEN WCLK FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus JULY 2002 Page 33 of 33 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus RCLK 2 1 tENS tENH tRETS tENS tENH REN tA Q 19 - 0 tA DWi DWi+1 tA DW1 DW2 tSKEW2 WCLK 1 2 tRETS WEN tENS tENH RET tEMPTY tEMPTY EMPTY tPRAES PRAE tHALF HALF tPRAFS PRAF NOTES: 1. 2. 3. 4. Upon completion of retransmit setup, a read operation can begin only after EMPTY returns high. OE = Low. DWi = Words written to the queue after MRST . Where i = 1,2,3... depth. Upon reset completion, there must be more than two words written to the queue for a retransmit setup to be valid. Diagram 7. Retransmit Timing (Standard Mode) 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 34 of 34 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus RCLK 1 tENS tENH 2 tRETS 3 4 tENS tENH REN tA Q 19 - 0 DWi DWi+1 tA DW1 tA DW2 tA DW3 DW4 tSKEW2 WCLK 1 2 tRETS WEN tENS tENH RET tEMPTY tEMPTY QRDY tPRAES PRAE tHALF HALF tPRAFS PRAF NOTES: 1. 2. 3. 4. 5. Upon completion of retransmit setup, a read operation can begin only after QRDY returns low. OE = Low. DWi = Words written to the queue after MRST . Where i = 1,2,3... depth. Upon reset completion, there must be more than two words written to the queue for a retransmit setup to be valid. Please refer to Table 7 for Depth. Diagram 8. Retransmit Timing (FWFT Mode) 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 35 of 35 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus RCLK 1 2 3 tENS tENH REN tA Q 19 - 0 tA tA DWi+1 DWi tA DW1 DW2 tA DW3 DW4 tSKEW2 WCLK 1 2 tRETS WEN tENS tENH RET EMPTY tPRAES PRAE tHALF HALF tPRAFS PRAF NOTES: 1. 2. 3. 4. 5. 6. If the part is empty at the point of retransmit, the Empty Flag ( EMPTY ) will be updated based on RCLK (Retransmit Clock cycle). Valid data will appear on the output. OE = Low; enables data to be read on outputs Q19 - 0. DW1= first word written to the queue after Master Reset; DW2= second word written to the queue after Master Reset. No more than D-2 may be written to the queue between reset (Master or Partial) and retransmit setup. Therefore, FULL will be high throughout the retransmit setup procedure. Please refer to Table 7 for Depth. There must be at least two words written to zero latency retransmit from the queue before a retransmit operation can be invoked. RETZL is set Low during MRST . Diagram 9. Zero Latency Retransmit Timing (Standard Mode) 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 36 of 36 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus RCLK 1 2 3 4 5 tENH tENS REN tA tA DW i+1 DWi Q 19 - 0 tA DW1 tA DW2 tA tA DW3 DW4 DW5 tSKEW2 WCLK 1 2 tRETS WEN tENS tENH RET QRDY tPRAES PRAE tHALF HALF tPRAFS PRAF NOTES: 1. 2. 3. 4. 5. 6. If the part is empty at the point of retransmit, the output ready flag ( QRDY ) will be updated based on RCLK (Retransmit Clock cycle). Valid data will appear on the output. No more than D-2 words may be written to the queue between reset (Master or Partial) and retransmit setup. Therefore, DRDY will be low throughout the retransmit setup procedure. Please refer to Table 7 for Depth. OE = Low. DW1, DW2, DW3 = first, second and third words written to the queue after Master Reset. There must be at least two words written to the queue before a retransmit operation can be invoked. RETZL is set low during MRST . Diagram 10. Zero Latency Retransmit Timing (FWFT Mode) 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 37 of 37 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus WCLK tENS tENH tENH tLOADH tLOADH SDEN tLOADS LOAD tDS tDH SDI BIT 0 BIT MSB BIT 0 BIT MSB PRAE Offset PRAF Offset *Refer to Table 12 Diagram 11. Serial Loading of Programmable Flag Registers (Standard and FWFT Mode) MSB for x10 to x10 MSB for All Other Modes FQV202113 FQV202103 FQV20293 FQV20283 FQV20273 FQV20263 FQV20253 FQV20243 18 17 16 15 14 13 12 11 17 16 15 14 13 12 11 10 Table 12. Reference Table for Diagram 11 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 38 of 38 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus tWCLK tWCLKH tWCLKL WCLK tLOADS tLOADH tLOADH LOAD tENS tENH tENH WEN tDS tDH tDS tDH tDS tDH tDS tDH D 19 - 0 PRAE offset (Low Byte) PRAE offset (High Byte) PRAF offset (Low Byte) PRAF offset (High Byte) Diagram 12. Parallel Loading of Programmable Flag Registers (Standard and FWFT Mode) tRCLK tRCLKH tRCLKL RCLK tLOADS tLOADH tLOADH tENH tENH LOAD tENS REN tA Q 19 - 0 tA tA tA Data Output Register PRAE offset (Low Byte) PRAE offset (High Byte) PRAF offset (Low Byte) PRAF offset (High Byte) Diagram 13. Parallel Read of Programmable Flag Registers (Standard and FWFT Mode) 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 39 of 39 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus tWCLKH tWCLKL WCLK 1 tENS 2 1 2 tENH WEN tPRAFS PRAF tPRAFS D - ( x + 1 ) words in Queue D - x words in Queue D - ( x + 1 ) words in Queue tSKEW2 RCLK tENS tENH REN NOTES:___________ 1. 2. 3. x = PRAF offset. D = maximum queue depth. Please refer to Table 7 for Depth. ___________ If the time between a rising edge of___________ RCLK to the rising edge of WCLK is greater or equal than tSKEW2, PRAF will go high (after on WCLK cycle plus t___________ PRAFS). If tSKEW2 is not met, then PRAF will assert 1 or more WCLK cycles. PRAF synchronizes to the rising edge of WCLK only. 4. Diagram 14. Synchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode) tWCLKH tWCLKL WCLK tWCLKH tWCLKL WEN PRAE y words in Queue(2) ; y+1 words in Queue(3) tSKEW2 RCLK tPRAES 1 y words in Queue(2) ; y+1 words in Queue(3) y+1 words in Queue(2) ; y+2 words in Queue(3) tPRAES 2 1 tENS 2 tENH REN NOTES:___________ 1. 2. 3. 4. 5. y = PRAE offset. For Standard Mode. For FWFT Mode. ___________ If the time between a rising edge of WCLK to the rising edge of RCLK is greater or equal than tSKEW2, PRAE will go high (after one RCLK cycle plus ___________ t___________ PRAES). If tSKEW2 is not met, then PRAE will assert 1 or more RCLK cycles. PRAE synchronizes to the rising edge of RCLK only. Diagram 15. Synchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode) 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 40 of 40 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus tWCLKH tWCLKL WCLK tENS tENH WEN tPRAFA D - x words in Queue D - ( x + 1) words in Queue PRAF D - ( x + 1) words in Queue tPRAFA RCLK tENH tENS REN NOTES:___________ 1. 2. 3. 4. x = PRAF offset. D = maximum queue depth. Please refer to Table 7 for Depth. PRAF is asserted to low on WCLK transition and reset to high on RCLK transition. Select this mode by setting SFM low during Master Reset. ___________ Diagram 16. Asynchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode) tWCLKH tWCLKL WCLK tENS tENH WEN tPRAEA y+1 words in Queue(2); y+2 words in Queue (3) y words in Queue(2); y+1 words in Queue(3) PRAE y words in Queue(2); y+1 words in Queue(3) tPRAEA RCLK tENS tENH REN NOTES:___________ 1. 2. 3. 4. 5. y = PRAE offset. For Standard Mode. For FWFT Mode. ___________ PRAE is asserted to low on RCLK transition and reset to high on WCLK transition. Select this mode by setting SFM low during Master Reset. Diagram 17. Asynchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode) 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 41 of 41 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus tWCLKH tWCLKL WCLK tENS tENH WEN D/2 + 1 words in Queue(1); [(D+1)/2 + 1] words in Queue(2) tHALF HALF D/2 words in Queue(1); [(D+1)/2] words in Queue(2) tHALF D/2 words in Queue(1); [(D+1)/2] words in Queue(2) RCLK tENS tENH REN NOTES: 1. 2. 3. For Standard Mode. For FWFT Mode. Please refer to Table 7 for Depth. Diagram 18. Half-Full Flag Timing (Standard and FWFT Mode) 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. JULY 2002 Page 42 of 42 FQV202113 * FQV202103 * FQV20293 * FQV20283 * FQV20273 * FQV20263 * FQV20253* FQV20243 FlexQTMIII Plus Order Information: HBA Device Family Device Type Power Speed (ns) * Package** Temperature Range XX FQ XXXXX V202113 (524,288 x 10) X Low XX 6 - 166 MHz XX PF X Blank - Commercial (0C to 70C) (262,144 x 20) 7-5 - 133 MHz V202103 (262,144 x 10) 10 - 100 MHz I - Industrial (-40 to 85C) (131,072 x 20) V20293 (131,072 x 10) (65,536 x 20) V20283 (65,536 x 10) (32,768 x 20) V20273 (32,768 x 10) (16,384 x 20) V20263 (16,384 x 10) V20253 (8,192 x 10) V20243 (4,096 x 10) (8,192 x 20) (4,096 x 20) (2,048 x 20) *Speed - 6ns available only in Commercial temp (0C to 70C) **Package - 144 - pin Plastic Thin Quad Flat Pack (TQFP) Example: FQV20283L6PF FQV20273L10PFI USA 2107 North First Street, Suite 415 San Jose, CA 95131, USA www.hba.com (64k x 10, 6ns, Commercial temp) (32k x 10, 10ns, Industrial temp) Tel: 408.453.8885 Fax: 408.453.8886 3F3P1020B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Taiwan No. 81, Suite 8F-9, Shui-Lee Rd. Hsinchu, Taiwan, R.O.C. www.hba.com Tel: 886.3.516.9118 Fax: 886.3.516.9181 JULY 2002 Page 43 of 43