Sense & Control
Data Sheet
Rev. 2.0, 2014-02
TLE5012B
Angle Sensor
GMR-Based Angle Sensor
TLE5012B
Data Sheet 2 Rev. 2.0, 2014-02
TLE5012B
Data Sheet 3 Rev. 2.0, 2014-02
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™,
CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, EasyPIM™, EconoBRIDGE™, EconoDUAL™,
EconoPIM™, EconoPACK™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™,
ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™,
POWERCODE™; PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™,
ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, TEMPFET™,
thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR
development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,
FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.
FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of
Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data
Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of
MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics
Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™ of MURATA
MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of
OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF
Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™
of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co.
TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™
of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas
Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes
Zetex Limited.
Last Trademarks Update 2011-11-11
Revision History
Page or Item Subjects (major changes since previous revision)
Rev. 2.0, 2014-02
All chapters revised
TLE5012B
Table of Contents
Data Sheet 4 Rev. 2.0, 2014-02
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1 Internal Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.2 Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.3 SD-ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.4 Digital Signal Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.5 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.6 Safety Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Sensing Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3 Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3.1 Input/Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3.2 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3.3 GMR Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3.4 Angle Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3.5 Autocalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3.6 Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3.7 Clock Supply (CLK Timing Definition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.4 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.4.1 Synchronous Serial Communication (SSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.4.1.1 SSC Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.4.1.2 SSC Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.4.2 Pulse Width Modulation (PWM) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.4.3 Short PWM Code (SPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.4.3.1 Unit Time Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.4.3.2 Master Trigger Pulse Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.4.3.3 Checksum Nibble Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.4.4 Hall Switch Mode (HSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.4.5 Incremental Interface (IIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.5 Test Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.5.1 ADC Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.6 Supply Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.6.1 Internal Supply Voltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table of Contents
TLE5012B
Table of Contents
Data Sheet 5 Rev. 2.0, 2014-02
4.6.2 VDD Overvoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.6.3 GND - Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.6.4 VDD - Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5 Pre-Configured Derivates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.1 IIF-type: E1000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.2 HSM-type: E3005 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.3 PWM-type: E5000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.4 PWM-type: E5020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.5 SPC-type: E9000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.2 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.3 Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.4 Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
TLE5012B
List of Figures
Data Sheet 6 Rev. 2.0, 2014-02
Figure 1-1 PG-DSO-8 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2-1 TLE5012B block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 2-2 Sensitive bridges of the GMR sensor (not to scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2-3 Ideal output of the GMR sensor bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 2-4 Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3-1 Application circuit for TLE5012B with IIF interface and SSC (using internal CLK). . . . . . . . . . . . . 15
Figure 3-2 Application circuit for TLE5012B with HS Mode and SSC (using internal CLK). . . . . . . . . . . . . . . 15
Figure 3-3 Application circuit for TLE5012B with only PWM interface (using internal CLK) . . . . . . . . . . . . . . 16
Figure 3-4 Application circuit for TLE5012B with only PWM interface (using internal CLK) . . . . . . . . . . . . . . 16
Figure 3-5 Application circuit for TLE5012B with only SPC interface (using internal CLK) . . . . . . . . . . . . . . . 17
Figure 3-6 SSC configuration in sensor-slave mode with push-pull outputs (high-speed application) . . . . . . 17
Figure 3-7 SSC configuration in sensor-slave mode and open-drain (bus systems). . . . . . . . . . . . . . . . . . . . 18
Figure 4-1 Allowed magnetic field range as function of junction temperature.. . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 4-2 Offset and amplitude definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 4-3 Additional angle error for temperature changes above 5 Kelvin within 1.5 revolutions . . . . . . . . . 25
Figure 4-4 Signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 4-5 Delay of sensor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 4-6 External CLK timing definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 4-7 SSC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 4-8 SSC data transfer (data-read example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 4-9 SSC data transfer (data-write example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 4-10 SSC bit ordering (read example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 4-11 Update of update registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 4-12 Fast CRC polynomial division circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 4-13 Typical example of a PWM signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 4-14 SPC frame example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 4-15 SPC pause timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 4-16 SPC Master pulse timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 4-17 Hall Switch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 4-18 HS hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 4-19 Incremental interface with A/B mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 4-20 Incremental interface with Step/Direction mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 4-21 ADC test vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 4-22 Overvoltage comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 4-23 GND - off comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 4-24 VDD - off comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 6-1 PG-DSO-8 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 6-2 Position of sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 6-3 Footprint of PG-DSO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 6-4 Tape and Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
List of Figures
TLE5012B
List of Tables
Data Sheet 7 Rev. 2.0, 2014-02
Table 1-1 Derivate Ordering codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2-1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4-1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4-2 Operating range and parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 4-3 Input voltage and output currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 4-4 Driver strength characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 4-5 Electrical parameters for 4.5 V < VDD < 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 4-6 Electrical parameters for 3.0 V < VDD < 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 4-7 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 4-8 Basic GMR parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 4-9 Angle performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4-10 Signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 4-11 Internal clock timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 4-12 External Clock Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 4-13 SSC push-pull timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 4-14 SSC open-drain timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 4-15 Structure of the Command Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 4-16 Structure of the Safety Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 4-17 Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 4-18 PWM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 4-19 Frame configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 4-20 Structure of status nibble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 4-21 Predivider setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 4-22 Master pulse parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 4-23 Hall Switch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 4-24 Incremental Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 4-25 ADC test vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 4-26 Test comparator threshold voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 6-1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 6-2 Sensor IC placement tolerances in package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
List of Tables
TLE5012B
Product Description
Data Sheet 8 Rev. 2.0, 2014-02
1 Product Description
Figure 1-1 PG-DSO-8 package
1.1 Overview
The TLE5012B is a 360° angle sensor that detects the orientation of a magnetic field. This is achieved by
measuring sine and cosine angle components with monolithic integrated Giant Magneto Resistance (iGMR)
elements. These raw signals (sine and cosine) are digitally processed internally to calculate the angle orientation
of the magnetic field (magnet).
The TLE5012B is a pre-calibrated sensor. The calibration parameters are stored in laser fuses. At start-up the
values of the fuses are written into flip-flops, where these values can be changed by the application-specific
parameters. Further precision of the angle measurement over a wide temperature range and a long lifetime can
be improved by enabling an optional internal autocalibration algorithm.
Data communications are accomplished with a bi-directional Synchronous Serial Communication (SSC) that is
SPI-compatible. The sensor configuration is stored in registers, which are accessible by the SSC interface.
Additionally four other interfaces are available with the TLE5012B: Pulse-Width-Modulation (PWM) Protocol,
Short-PWM-Code (SPC) Protocol, Hall Switch Mode (HSM) and Incremental Interface (IIF). These interfaces can
be used in parallel with SSC or alone. Pre-configured sensor derivates with different interface settings are
available (see Table 1-1 and Chapter 5)
Online diagnostic functions are provided to ensure reliable operation.
Note: See Chapter 5 for description of derivates.
Table 1-1 Derivate Ordering codes
Product Type Marking Ordering Code Package
TLE5012B E1000 012B1000 SP001166960 PG-DSO-8
TLE5012B E3005 012B3005 SP001166964 PG-DSO-8
TLE5012B E5000 012B5000 SP001166968 PG-DSO-8
TLE5012B E5020 012B5020 SP001166972 PG-DSO-8
TLE5012B E9000 012B9000 SP001166998 PG-DSO-8
TLE5012B
Product Description
Data Sheet 9 Rev. 2.0, 2014-02
1.2 Features
•Giant Magneto Resistance (GMR)-based principle
• Integrated magnetic field sensing for angle measurement
• 360° angle measurement with revolution counter and angle speed measurement
• Two separate highly accurate single bit SD-ADC
• 15 bit representation of absolute angle value on the output (resolution of 0.01°)
• 16 bit representation of sine / cosine values on the interface
• Max. 1.0° angle error over lifetime and temperature-range with activated auto-calibration
• Bi-directional SSC Interface up to 8Mbit/s
• Supports Safety Integrity Level (SIL) with diagnostic functions and status information
• Interfaces: SSC, PWM, Incremental Interface (IIF), Hall Switch Mode (HSM), Short PWM Code (SPC, based
on SENT protocol defined in SAE J2716)
• Output pins can be configured (programmed or pre-configured) as push-pull or open-drain
• Bus mode operation of multiple sensors on one line is possible with SSC or SPC interface in open-drain
configuration
•0.25 μm CMOS technology
• Automotive qualified: -40°C to 150°C (junction temperature)
• ESD > 4kV (HBM)
• RoHS compliant (Pb-free package)
• Halogen-free
1.3 Application Example
The TLE5012B GMR-based angle sensor is designed for angular position sensing in automotive applications such
as:
• Electrical commutated motor (e.g. used in Electric Power Steering (EPS))
• Rotary switches
• Steering angle measurements
• General angular sensing
TLE5012B
Functional Description
Data Sheet 10 Rev. 2.0, 2014-02
2 Functional Description
2.1 Block Diagram
Figure 2-1 TLE5012B block diagram
2.2 Functional Block Description
2.2.1 Internal Power Supply
The internal stages of the TLE5012B are supplied with several voltage regulators:
• GMR Voltage Regulator, VRG
• Analog Voltage Regulator, VRA
• Digital Voltage Regulator, VRD (derived from VRA)
These regulators are directly connected to the supply voltage VDD.
2.2.2 Oscillator and PLL
The digital clock of the TLE5012B is given by the Phase-Locked Loop (PLL), which is by default fed by an internal
oscillator. In order to synchronize the TLE5012B with other ICs in a system, the TLE5012B can be configured via
VRG VRA VRD
TLE5012B V
DD
X
GMR
Y
GMR
Temp
SD-
ADC
SD-
ADC
SD-
ADC
Digital
Signal
Processing
Unit
CORDIC
CCU
RAM
SSC Interface
Incremental IF
PWM
HSM
SPC
CSQ
SCK
DATA
IFA
IFB
GND
IFC
Osc PLL
ISM
Fuses
TLE5012B
Functional Description
Data Sheet 11 Rev. 2.0, 2014-02
SSC interface to use an external clock signal supplied on the IFC pin as source for the PLL, instead of the internal
clock. External clock mode is only available in PWM or SPC interface configuration.
2.2.3 SD-ADC
The Sigma-Delta Analog-Digital-Converters (SD-ADC) transform the analog GMR voltages and temperature
voltage into the digital domain.
2.2.4 Digital Signal Processing Unit
The Digital Signal Processing Unit (DSPU) contains the:
•Intelligent State Machine (ISM), which does error compensation of offset, offset temperature drift, amplitude
synchronicity and orthogonality of the raw signals from the GMR bridges, and performs additional features
such as auto-calibration, prediction and angle speed calculation
•COordinate Rotation DIgital Computer (CORDIC), which contains the trigonometric function for angle
calculation
•Capture Compare Unit (CCU), which is used to generate the PWM and SPC signals
•Random Access Memory (RAM), which contains the configuration registers
• Laser Fuses, which contain the calibration parameters for the error-compensation and the IC default
configuration, which is loaded into the RAM at startup
2.2.5 Interfaces
Bi-directional communication with the TLE5012B is enabled by a three-wire SSC interface. In parallel to the SSC
interface, one secondary interface can be selected, which is available on the IFA, IFB, IFC pins:
•PWM
• Incremental Interface
• Hall Switch Mode
• Short PWM Code
By using pre-configured derivates (see Chapter 5), the TLE5012B can also be operated with the secondary
interface only, without SSC communication.
2.2.6 Safety Features
The TLE5012B offers a multiplicity of safety features to support the Safety Integrity Level (SIL) and it is a PRO-
SILTM product.
Safety features are:
• Test vectors switchable to ADC input (activated via SSC interface)
• Inversion or combination of filter input streams (activated via SSC interface)
• Data transmission check via 8-bit Cyclic Redundancy Check (CRC) for SSC communcation and 4-bit CRC
nibble for SPC interface
• Built-in Self-test (BIST) routines for ISM, CORDIC, CCU, ADCs run at startup
• Two independent active interfaces possible
• Overvoltage and undervoltage detection
Disclaimer
PRO-SIL™ is a Registered Trademark of Infineon Technologies AG.
The PRO-SIL™ Trademark designates Infineon products which contain SIL Supporting Features.
SIL Supporting Features are intended to support the overall System Design to reach the desired SIL (according
to IEC61508) or A-SIL (according to ISO26262) level for the Safety System with high efficiency.
TLE5012B
Functional Description
Data Sheet 12 Rev. 2.0, 2014-02
SIL respectively A-SIL certification for such a System has to be reached on system level by the System
Responsible at an accredited Certification Authority.
SIL stands for Safety Integrity Level (according to IEC 61508)
A-SIL stands for Automotive-Safety Integrity Level (according to ISO 26262)
2.3 Sensing Principle
The Giant Magneto Resistance (GMR) sensor is implemented using vertical integration. This means that the
GMR-sensitive areas are integrated above the logic part of the TLE5012B device. These GMR elements change
their resistance depending on the direction of the magnetic field.
Four individual GMR elements are connected to one Wheatstone sensor bridge. These GMR elements sense one
of two components of the applied magnetic field:
• X component, Vx (cosine) or the
• Y component, Vy (sine)
With this full-bridge structure the maximum GMR signal is available and temperature effects cancel out each other.
Figure 2-2 Sensitive bridges of the GMR sensor (not to scale)
Attention: Due to the rotational placement inaccuracy of the sensor IC in the package, the sensors 0°
position may deviate by up to 3° from the package edge direction indicated in Figure 2-2.
In Figure 2-2, the arrows in the resistors represent the magnetic direction which is fixed in the reference layer. If
the external magnetic field is parallel to the direction of the Reference Layer, the resistance is minimal. If they are
anti-parallel, resistance is maximal.
The output signal of each bridge is only unambiguous over 180° between two maxima. Therefore two bridges are
oriented orthogonally to each other to measure 360°.
With the trigonometric function ARCTAN2, the true 360° angle value is calculated out of the raw X and Y signals
from the sensor bridges.
V
DD
GNDADC
X
+
GMR Resistors
ADC
X
-ADC
Y
+ADC
Y
-
VXVY
0°
N
S
90°
TLE5012B
Functional Description
Data Sheet 13 Rev. 2.0, 2014-02
Figure 2-3 Ideal output of the GMR sensor bridges
V
Angle α
90° 180° 270° 360°0°
V
X
(COS)
Y Component (SIN)
V
Y
(SIN)
V
Y
V
X
X Component (COS)
TLE5012B
Functional Description
Data Sheet 14 Rev. 2.0, 2014-02
2.4 Pin Configuration
Figure 2-4 Pin configuration (top view)
2.5 Pin Description
Table 2-1 Pin Description
Pin No. Symbol In/Out Function
1IFC
(CLK / IIF_IDX / HS3)
I/O Interface C:
External Clock1) / IIF Index / Hall Switch
Signal 3
1) External clock feature is not available in IIF or HSM interface mode
2 SCK I SSC Clock
3 CSQ I SSC Chip Select
4 DATA I/O SSC Data
5IFA
(IIF_A / HS1 / PWM / SPC)
I/O Interface A:
IIF Phase A / Hall Switch Signal 1 /
PWM / SPC output (input for SPC trigger
only)
6V
DD - Supply Voltage
7GND-Ground
8IFB
(IIF_B / HS2)
O Interface B:
IIF Phase B / Hall Switch Signal 2
1234
5678 Center of Sensitive
Area
TLE5012B
Application Circuits
Data Sheet 15 Rev. 2.0, 2014-02
3 Application Circuits
The application circuits in this chapter show the various communication possibilities of the TLE5012B. The pin
output mode configuration is device-specific and it can be either push-pull or open-drain. The bit IFAB_OD
(register IFAB, 0DH) indicates the output mode for the IFA, IFB and IFC pins. The SSC pins are by default push-
pull (bit SSC_OD, register MOD_3, 09H).
Figure 3-1 shows a basic block diagram of a TLE5012B with Incremental Interface and SSC configuration. The
derivate TLE5012B - E1000 is by default configured with push-pull IFA (IIF_A), IFB (IIF_ B) and IFC (IIF_IDX) pins.
Figure 3-1 Application circuit for TLE5012B with IIF interface and SSC (using internal CLK)
In case that the IFA, IFB and IFC pins are configurated via the SSC interface as open-drain pins, three resistors
(one for each line) between output line and VDD would be recommended (e.g. 2.2kΩ).
Figure 3-2 shows a basic block diagram of the TLE5012B with HS Mode and SSC configuration. The derivate
TLE5012B - E3005 is by default configurated with push-pull IFA (HS1), IFB (HS2) and IFC (HS3) pins.
Figure 3-2 Application circuit for TLE5012B with HS Mode and SSC (using internal CLK)
VRG VRA VRD
TLE5012B
X
GMR
Y
GMR
Temp
SD-
ADC
SD-
ADC
SD-
ADC
SSC Interface
Incremental IF
PWM
HSM
Osc
*) recommended , e.g . 100Ω
100 nF
IFC (IIF_IDX)
VDD (3.0 – 5.5V)
**)
GND
PLL
CSQ
SCK
DATA
IFA (IIF_A)
IFB (IIF_B)
SSC
IIF
**) recommended , e .g. 470 Ω
*)
*)
Digital
Signal
Processing
Unit
CORDIC
CCU
RAM
ISM
Fuses
VRG VRA VRD
TLE5012B
X
GMR
Y
GMR
Temp
SD-
ADC
SD-
ADC
SD-
ADC
SSC Interface
Incremental IF
PWM
HSM
Osc
*) recommended , e.g . 100Ω
100nF
IFC (HS3)
V
DD
(3.0 – 5.5V)
**)
GND
PLL
CSQ
SCK
DATA
IFA (HS1)
IFB (HS2)
SSC
HSM
**) recom mended , e .g. 470 Ω
*)
*)
Digital
Signal
Processing
Unit
CORDIC
CCU
RAM
ISM
Fuses
TLE5012B
Application Circuits
Data Sheet 16 Rev. 2.0, 2014-02
In case that the IFA, IFB and IFC pins are configurated via the SSC interface as open drain pins, three resistors
(one for each line) between the output line and VDD would be recommended (e.g. 2.2kΩ).
The TLE5012B can be configured with PWM only (Figure 3-3). The derivate TLE5012B - E5000 is by default
configurated with push-pull IFA (PWM) pin. Therefore the following configuration is recommended:
Figure 3-3 Application circuit for TLE5012B with only PWM interface (using internal CLK)
The TLE5012B - E5020 is also a PWM derivate but with open drain IFA (PWM) pin. A pull-up resistor (e.g. 2.2kΩ)
should then be added between the IFA line and VDD, as shown in Figure 3-4.
Figure 3-4 Application circuit for TLE5012B with only PWM interface (using internal CLK)
For safety reasons it is better that the non-used pins are connected to ground, rather than floating. A resistor
between he DATA line pin and ground is recommended to avoid shortcuts if DATA generates any unexpected
output. The CSQ line has to be connected to VDD to avoid unintentional activation of the SSC interface.
VRG VRA VRD
TLE5012B
X
GMR
Y
GMR
Temp
SD-
ADC
SD-
ADC
SD-
ADC
SSC Interface
Incremental IF
PWM
HSM
Osc
*) r ecom m ended , e .g. 10 .0k Ω
100 nF
IFC
V
DD
(3.0 – 5.5V)
*)
GND
PLL
CSQ
SCK
DATA
IFA (PWM)
IFB
Digital
Signal
Processing
Unit
CORDIC
CCU
RAM
ISM
Fuses
VRG VRA VRD
TLE5012B
X
GMR
Y
GMR
Temp
SD-
ADC
SD-
ADC
SD-
ADC
SSC Interface
Incremental IF
PWM
HSM
Osc
*) r ecom m ended , e.g . 2.2kΩ
100nF
IFC
V
DD
(3.0 – 5.5V)
**)
GND
PLL
CSQ
SCK
DATA
IFA (PWM)
IFB
**) recommended , e.g. 10.0kΩ
*)
Digital
Signal
Processing
Unit
CORDIC
CCU
RAM
ISM
Fuses
TLE5012B
Application Circuits
Data Sheet 17 Rev. 2.0, 2014-02
The TLE5012B can be configured with SPC only (Figure 3-5). This is only possible with the TLE5012B - E9000
derivate, which is by default configurated with an open-drain IFA (SPC) pin.
Figure 3-5 Application circuit for TLE5012B with only SPC interface (using internal CLK)
In Figure 3-5 the IFC (S_NR[1]) and SCK (S_NR[0]) pins are set to ground to generate the slave number (S_NR)
0D (or 00B). For safety reasons it is better that the non-used pins are connected to ground, rather than floating. A
resistor between the DATA line pin and ground is recommended to avoid shortcuts if DATA generates any
unexpected output. The CSQ line has to be connected to VDD to avoid unintentional activation of the SSC interface.
Synchronous Serial Communication (SSC) configuration
In Figure 3-1 and Figure 3-2 the SSC interface has the default push-pull configuration (see details in Figure 3-6).
Series resistors on the DATA, SCK (serial clock signal) and CSQ (chip select) lines are recommended to limit the
current in the erroneous case that either the sensor pushes high and the microcontroller pulls low at the same time
or vice versa. The resistors in the SCK and CSQ lines are only necessary in case of disturbances or noise.
Figure 3-6 SSC configuration in sensor-slave mode with push-pull outputs (high-speed application)
VRG VRA VRD
TLE5012B
X
GMR
Y
GMR
Temp
SD-
ADC
SD-
ADC
SD-
ADC
SSC Interface
Incremental IF
PWM
HSM
Osc
*) recommended , e.g . 2 .2kΩ
100nF
IFC (S_NR[1])
V
DD
(3.0 – 5.5V)
**)
GND
PLL
CSQ
SCK (S_NR[0])
DATA
IFA (SPC )
IFB
**) recommended , e .g. 10.0kΩ
*)
Digital
Signal
Processing
Unit
CORDIC
CCU
RAM
ISM
Fuses
Shift Reg. Shift Reg.
Clock Gen.
DATA MTSR
MRST
SCK SCK
(SSC Slave) TLE 5012B µC (SSC Master)
CSQ CSQ
**)
*)
*)
EN EN
*) optional , e.g. 100 Ω
**) optional , e.g. 470 Ω
TLE5012B
Application Circuits
Data Sheet 18 Rev. 2.0, 2014-02
It is also possible to use an open-drain setup for the DATA, SCK and CSQ lines. This setup is designed to
communicate with a microcontroller in a bus system, together with other SSC slaves (e.g. two TLE5012B devices
for redundancy reasons). This mode can be activated using the bit SSC_OD.
The open-drain configuration can be seen in Figure 3-7. Series resistors on the DATA, SCK, and CSQ lines are
recommended to limit the current in case either the microcontroller or the sensor are accidentally switched to push-
pull. A pull-up resistor of typ. 1 kΩ is required on the DATA line.
Figure 3-7 SSC configuration in sensor-slave mode and open-drain (bus systems)
Shift Reg. Shift Reg.
Clock Gen.
DATA MRST
MTSR
SCK SCK
(SSC Slave) TLE 5012B µC (SSC Master)
CSQ CSQ
*)
*)
*)
*)
typ. 1kΩ
*) optional , e.g. 100 Ω
TLE5012B
Specification
Data Sheet 19 Rev. 2.0, 2014-02
4 Specification
4.1 Absolute Maximum Ratings
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the device.
4.2 Operating Range
The following operating conditions must not be exceeded in order to ensure correct operation of the TLE5012B.
All parameters specified in the following sections refer to these operating conditions, unless otherwise noted.
Table 4-2 is valid for -40°C < TJ < 150°C unless otherwise noted.
Table 4-1 Absolute maximum ratings
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Voltage on VDD pin with respect to
ground (VSS)
VDD -0.5 6.5 V Max 40 h/Lifetime
Voltage on any pin with respect to
ground (VSS)
VIN -0.5 6.5 V
VDD +
0.5
V
Junction temperature TJ-40 150 °C
150 °C For 1000 h, not additive
Magnetic field induction B 200 mT Max. 5 min @ TA = 25°C
150 mT Max. 5 h @ TA = 25°C
Storage temperature TST -40 150 °C Without magnetic field
Table 4-2 Operating range and parameters
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Supply voltage VDD 3.0 5.0 5.5 V 1)
Supply current IDD 14 16 mA
Magnetic induction at TJ =
25°C2)3)
BXY 30 50 mT -40°C < TJ < 150°C
30 60 mT -40°C < TJ < 100°C
30 70 mT -40°C < TJ < 85°C
Extended magnetic induction
range at TJ = 25°C2)3)
BXY 25 30 mT Additional angle error of 0.1°
Angle range Ang 0 360 °
POR level VPOR 2.0 2.9 V Power-on reset
POR hysteresis VPORhy 30 mV
TLE5012B
Specification
Data Sheet 20 Rev. 2.0, 2014-02
The field strength of a magnet can be selected within the colored area of Figure 4-1. By limitation of the junction
temperature, a higher magnetic field can be applied. In case of a maximum temperature TJ=100°C, a magnet with
up to 60mT at TJ = 25°C is allowed.
It is also possible to widen the magnetic field range for higher temperatures. In that case, additional angle errors
have to be considered.
Figure 4-1 Allowed magnetic field range as function of junction temperature.
Power-on time4) tPon 57msV
DD > VDDmin;
Fast Reset time5) tRfast 0.5 ms Fast reset is triggered by
disabling startup BIST
(S_BIST = 0), then enabling
chip reset (AS_RST = 1)
1) Directly blocked with 100-nF ceramic capacitor
2) Values refer to a homogeneous magnetic field (BXY) without vertical magnetic induction (BZ = 0mT).
3) See Figure 4-1
4) During “Power-on time,” write access is not permitted (except for the switch to External Clock which requires a readout as
a confirmation that external clock is selected)
5) Not subject to production test - verified by design/characterization
Table 4-2 Operating range (cont’d)and parameters
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
TLE5012B
Specification
Data Sheet 21 Rev. 2.0, 2014-02
4.3 Characteristics
4.3.1 Input/Output characteristics
The indicated parameters apply to the full operating range, unless otherwise specified. The typical values
correspond to a supply voltage VDD = 5.0 V and 25 °C, unless individually specified. All other values correspond
to -40 °C < TJ < 150°C.
Within the register MOD_3, the driver strength and the slope for push-pull communication can be varied depending
on the sensor output. The driver strength is specified in Table 4-3 and the slope fall and rise time in Table 4-4.
Table 4-3 Input voltage and output currents
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Input voltage VIN -0.3 5.5 V
VDD+ 0.3 V
Output current (DATA-Pad) IQ-25 mA PAD_DRV =’0x’, sink current1)2)
1) Max. current to GND over open-drain output
2) At VDD = 5 V
-5 mA PAD_DRV =’10’, sink current1)2)
-0.4 mA PAD_DRV =’11’, sink current1)2)
Output current (IFA / IFB / IFC -
Pad)
IQ-15 mA PAD_DRV =’0x’, sink current1)2)
-5 mA PAD_DRV =’1x’, sink current1)2)
Table 4-4 Driver strength characteristic
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Output rise/fall time tfall, trise 8 ns DATA, 50 pF,
PAD_DRV=’00’1)2)
1) Valid for push-pull output
2) Not subject to production test - verified by design/characterization
28 ns DATA, 50 pF,
PAD_DRV=’01’1)2)
45 ns DATA, 50 pF,
PAD_DRV=’10’1)2)
130 ns DATA, 50 pF,
PAD_DRV=’11’1)2)
15 ns IFA/IFB, 20 pF,
PAD_DRV=’0x’1)2)
30 ns IFA/IFB, 20 pF,
PAD_DRV=’1x’1)2)
TLE5012B
Specification
Data Sheet 22 Rev. 2.0, 2014-02
Table 4-5 Electrical parameters for 4.5 V < VDD < 5.5 V
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Input signal low-level VL5 0.3 VDD V
Input signal high level VH5 0.7 VDD V
Output signal low-level VOL5 1V DATA; I
Q = -25 mA (PAD_DRV=’0x’),
IQ = -5 mA (PAD_DRV=’10’), IQ = -0.4
mA (PAD_DRV=’11’)
1V IFA,B,C; I
Q = -15 mA (PAD_DRV=’0x’),
IQ = -5 mA (PAD_DRV=’1x’)
Pull-up current1)
1) Internal pull-ups on CSQ and DATA pin are always enabled.
IPU -10 -225 μACSQ
-10 -150 μADATA
Pull-down current2)
2) Internal pull-downs on IFA, IFB and IFC are enabled during startup and in open-drain mode, internal pull-down on SCK is
always enabled.
IPD 10 225 μASCK
10 150 μA IFA, IFB, IFC
Table 4-6 Electrical parameters for 3.0 V < VDD < 3.6 V
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Input signal low-level VL3 0.3 VDD V
Input signal high level VH3 0.7 VDD V
Output signal low-level VOL3 0.9 V DATA; IQ = -15 mA
(PAD_DRV=’0x’), IQ = -3 mA
(PAD_DRV=’10’), IQ = -0.24 mA
(PAD_DRV=’11’)
0.9 V IFA,IFB; IQ = - 10 mA
(PAD_DRV=’0x’), IQ = -3 mA
(PAD_DRV=’1x’)
Pull-up current1)
1) Internal pull-ups on CSQ and DATA pin are always enabled.
IPU -3 -225 μACSQ
-3 -150 μADATA
Pull-down current2)
2) Internal pull-downs on IFA, IFB and IFC are enabled during startup and in open-drain mode, internal pull-down on SCK is
always enabled.
IPD 3225μASCK
3150μA IFA, IFB, IFC
TLE5012B
Specification
Data Sheet 23 Rev. 2.0, 2014-02
4.3.2 ESD Protection
4.3.3 GMR Parameters
All parameters apply over BXY = 30mT and TA = 25°C, unless otherwise specified.
Figure 4-2 Offset and amplitude definition
Table 4-7 ESD protection
Parameter Symbol Values Unit Notes
Min. Max.
ESD voltage VHBM ±4.0 kV Human Body Model1)
1) Human Body Model (HBM) according to: AEC-Q100-002
VSDM ±0.5 kV Socketed Device Model2)
2) Socketed Device Model (SDM) according to: ESDA/ANSI/ESD SP5.3.2-2008
Table 4-8 Basic GMR parameters
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
X, Y output range RGADC ±23230 digits Operating range1)
1) Not subject to production test - verified by design/characterization
X, Y amplitude2)
2) See Figure 4-2
AX, AY6000 9500 15781 digits At ambient temperature
3922 20620 digits Operating range
X, Y synchronicity3)
3) k = 100*(AX/AY)
k 87.5 100 112.49 %
X, Y offset4)
4) OY=(YMAX + YMIN) / 2; OX = (XMAX + XMIN) / 2
OX, OY-2048 0 +2047 digits
X, Y orthogonality error ϕ-11.25 0 +11.24 °
X, Y amplitude without magnet X0, Y0+4096 digits Operating range1)
Angle
90° 180° 270° 360°0°
+A
Offset
V
Y
0
-A
TLE5012B
Specification
Data Sheet 24 Rev. 2.0, 2014-02
4.3.4 Angle Performance
After internal calculation, the sensor has a remaining error, as shown in Table 4-9. The error value refers to BZ=
0mT and the operating conditions given in Table 4-2 “Operating range and parameters” on Page 19.
The overall angle error represents the relative angle error. This error describes the deviation from the reference
line after zero-angle definition. It is valid for a static magnetic field.
If the magnetic field is rotating during the measurement, an additional propagation error is caused by the angle
delay time (see Table 4-10 “Signal processing” on Page 27), which the sensor needs to calculate the angle
from the raw sine and cosine values from the MR bridges. In fast-turning applications, prediction can be enabled
to reduce this propagation error.
If autocalibration (see Chapter 4.3.5) is enabled and the temperature changes by more than 5 Kelvin during 1.5
revolutions an additional error has to be added to the specified angle error in Table 4-9. This error depends on the
temperature change (Delta Temperature) as well as from the initial temperature (Tstart) as shown in Figure 4-3.
Once the temperature stabilizes and the application completes 1.5 revolutions, then the angle error is as specified
in Table 4-9.
For negative Delta Temperature changes (from higher to lower temperatures) the additional angle error will be
smaller than the corresponding positive Delta Temperature changes (from lower to higher temperatures) shown
in Figure 4-3. The Figure 4-3 applies to the worst case.
Table 4-9 Angle performance
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Overall angle error (with auto-
calibration)
αErr 0.61)
1) At 25°C, B = 30mT
1.0 ° Including lifetime and
temperature drift2)3)4). Note:
in case of temperature
changes above 5 Kelvin
within 1.5 revolutions refer
to Figure 4-3 for additional
angle error.
2) Including hysteresis error, caused by revolution direction change
3) Relative error after zero angle definition
4) Not subject to production test - verified by design/characterization
Overall angle error (without auto-
calibration)
αErr 0.61) 1.3 ° Including temperature
drift2)3)5)
5) 0h
1.9 ° Including lifetime and
temperature drift2)3)4)
TLE5012B
Specification
Data Sheet 25 Rev. 2.0, 2014-02
Figure 4-3 Additional angle error for temperature changes above 5 Kelvin within 1.5 revolutions
4.3.5 Autocalibration
The autocalibration enables online parameter calculation and therefore reduces the angle error due to
temperature and lifetime drifts.
The TLE5012B is a pre-calibrated sensor, so autocalibration is only enabled in some devices by default. The
update mode can be chosen with the AUTOCAL setting in the MOD_2 register. The TLE5012B needs 1.5
revolutions to generate new autocalibration parameters. These parameters are continuously updated. The
parameters are updated in a smooth way (one Least-Significant Bit within the chosen range or time) to avoid an
angle jump on the output.
AUTOCAL Modes:
• 00: No autocalibration
• 01: Autocalibration Mode 1. One LSB to final values within the update time tupd (depending on FIR_MD setting).
• 10: Autocalibration Mode 2. Only one LSB update over one full parameter generation (1.5 revolutions). After
update of one LSB, the autocalibration will calculate the parameters again.
• 11: Autocalibration Mode 3. One LSB to final values within an angle range of 11.25°
0
0.5
1
1.5
2
2.5
3
3.5
0 102030405060708090100110120130140150160170180190
Additional angle error (°)
Delta Temperature (Kelvin) within 1.5 revolutions
Tstart -40°C
Tstart 25°C
Tstart 85°C
Tstart 105°C
Tstart 125°C
Tstart 135°C
Tstart >135°C
TLE5012B
Specification
Data Sheet 26 Rev. 2.0, 2014-02
4.3.6 Signal Processing
Figure 4-4 Signal path
The signal path of the TLE5012B is depicted in Figure 4-4. It consists of the GMR-bridge, ADC, filter and angle
calculation. The delay time between a physical change in the GMR elements and a signal on the output depends
on the filter and interface configurations. In fast turning applications, this delay causes an additional rotation speed
dependent angle error.
The TLE5012B has an optional prediction feature, which serves to reduce the speed dependent angle error in
applications where the rotation speed does not change abruptly. Prediction uses the difference between current
and last two angle values to approximate the angle value which will be present after the delay time (see
Figure 4-5). The output value is calculated by adding this difference to the measured value, according to
Equation (4.1).
(4.1)
Figure 4-5 Delay of sensor output
X
GMR
Y
GMR
SD-
ADC
SD-
ADC
Angle
Calculation
Filter
Filter
TLE5012B Microcontroller
IF
adelIIF
t
delIF
t
adelSSC
t
)2()1()()1(
−−−+=+
tttt
α
α
α
α
time
Angle With
Prediction
Without
Prediction
tadel tupd
Magnetic field
direction
Sensor output
TLE5012B
Specification
Data Sheet 27 Rev. 2.0, 2014-02
All delay times specified in Table 4-10 are valid for an ideal internal oscillator frequency of 24 MHz. For the exact
timing, the variation of the internal oscillator frequency has to be taken into account (see Chapter 4.3.7)
Table 4-10 Signal processing
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Filter update period tupd 42.7 μs FIR_MD = 1 (default)1)
1) Not subject to production test - verified by design/characterization
85.3 μsFIR_MD = 2
1)
170.6 μsFIR_MD = 3
1)
Angle delay time without
prediction2)
2) Valid at constant rotation speed
tadelSSC 85 95 μsFIR_MD = 1
1)
150 165 μsFIR_MD = 2
1)
275 300 μsFIR_MD = 3
1)
tadelIIF 120 135 μsFIR_MD = 1
1)
180 200 μsFIR_MD = 2
1)
305 330 μsFIR_MD = 3
1)
Angle delay time with prediction2) tadelSSC 45 50 μs FIR_MD = 1; PREDICT =
11)
65 70 μs FIR_MD = 2; PREDICT =
11)
105 115 μs FIR_MD = 3; PREDICT = 1
1)
tadelIIF 75 90 µs FIR_MD = 1; PREDICT =
11)
95 110 µs FIR_MD = 2; PREDICT =
11)
135 150 µs FIR_MD = 3; PREDICT = 1
1)
Angle noise (RMS) NAngle 0.08 ° FIR_MD = 11)
0.05 ° FIR_MD = 21)(default)
0.04 ° FIR_MD = 31)
TLE5012B
Specification
Data Sheet 28 Rev. 2.0, 2014-02
4.3.7 Clock Supply (CLK Timing Definition)
The internal clock supply of the TLE5012B is subject to production-specific variations, which have to be considered
for all timing specifications.
In order to fix the IC timing and synchronize the TLE5012B with other ICs in a system, it can be switched to operate
with an external clock signal supplied to the IFC pin. The clock input signal must fulfill certain requirements:
• The high or low pulse width must not exceed the specified values, because the PLL needs a minimum pulse
width and must be spike-filtered.
• The duty cycle factor should typically be 50%, but it can vary between 30% and 70%.
• The PLL is triggered at the positive edge of the clock. If more than 2 edges are missing, a chip reset is
generated automatically and the sensor restarts with the internal clock. This is indicated by the S_RST, and
CLK_SEL bits, and additionally by the Safety Word (see Chapter 4.4.1.2).
Figure 4-6 External CLK timing definition
Table 4-11 Internal clock timing specification
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Digital clock fDIG 22.8 24 25.8 MHz
Internal oscillator frequency fCLK 3.8 4.0 4.3 MHz
Table 4-12 External Clock Specification
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Input frequency fCLK 3.8 4.0 4.3 MHz
CLK duty cycle1)2)
1) Minimum duty cycle factor: tCLKh(min) / tCLK with tCLK= 1 / fCLK
2) Maximum duty cycle factor: tCLKh(max) / tCLK with tCLK= 1 / fCLK
CLKDUTY 30 50 70 %
CLK rise time tCLKr 30 ns From VL to VH
CLK fall time tCLKf 30 ns From VH to VL
t
CLKh
t
CLKl
t
CLK
t
V
L
V
H
TLE5012B
Specification
Data Sheet 29 Rev. 2.0, 2014-02
4.4 Interfaces
4.4.1 Synchronous Serial Communication (SSC)
The 3-pin SSC interface consists of a bi-directional push-pull (tri-state on receive) or open-drain data pin
(configurable with SSC_OD bit) and the serial clock and chip-select input pins. The SSC Interface is designed to
communicate with a microcontroller peer-to-peer for fast applications.
4.4.1.1 SSC Timing Definition
Figure 4-7 SSC timing
SSC Inactive Time (CSoff)
The SSC inactive time defines the delay time after a transfer before the TLE5012B can be selected again.
Table 4-13 SSC push-pull timing specification
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
SSC baud rate fSSC 8.0 Mbit/s 1)
1) Not subject to production test - verified by design/characterization
CSQ setup time tCSs 105 ns 1)
CSQ hold time tCSh 105 ns 1)
CSQ off tCSoff 600 ns SSC inactive time1)
SCK period tSCKp 120 125 ns 1)
SCK high tSCKh 40 ns 1)
SCK low tSCKl 30 ns 1)
DATA setup time tDATAs 25 ns 1)
DATA hold time tDATAh 40 ns 1)
Write read delay twr_delay 130 ns 1)
Update time tCSupdate 1μsSee Figure 4-111)
SCK off tSCKoff 170 ns 1)
SCK
t
CSs
t
SCKp
t
SCKh
t
CSh
CSQ
t
SCKl
t
CSoff
t
DATAs
DATA
t
DATAh
TLE5012B
Specification
Data Sheet 30 Rev. 2.0, 2014-02
Table 4-14 SSC open-drain timing specification
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
SSC baud rate fSSC 2.0 Mbit/s Pull-up Resistor = 1kΩ1)
1) Not subject to production test - verified by design/characterization
CSQ setup time tCSs 300 ns 1)
CSQ hold time tCSh 400 ns 1)
CSQ off tCSoff 600 ns SSC inactive time1)
SCK period tSCKp 500 ns 1)
SCK high tSCKh 190 ns 1)
SCK low tSCKl 190 ns 1)
DATA setup time tDATAs 25 ns 1)
DATA hold time tDATAh 40 ns 1)
Write read delay twr_delay 130 ns 1)
Update time tCSupdate 1μsSee Figure 4-111)
SCK off tSCKoff 170 ns 1)
TLE5012B
Specification
Data Sheet 31 Rev. 2.0, 2014-02
4.4.1.2 SSC Data Transfer
The SSC data transfer is word-aligned. The following transfer words are possible:
• Command Word (to access and change operating modes of the TLE5012B)
• Data words (any data transferred in any direction)
• Safety Word (confirms the data transfer and provides status information)
Figure 4-8 SSC data transfer (data-read example)
Figure 4-9 SSC data transfer (data-write example)
Command Word
SSC Communication between the TLE5012B and a microcontroller is generally initiated by a command word. The
structure of the command word is shown in Table 4-15. If an update is triggered by shortly pulling low CSQ without
a clock on SCK a snapshot of all system values is stored in the update registers simultaneously. A read command
with the UPD bit set then allows to readout this consistent set of values instead of the current values. Bits with an
update buffer are marked by an “u” in the Type column in register descriptions. The initialization of such an update
is described on page 33.
Table 4-15 Structure of the Command Word
Name Bits Description
RW [15] Read - Write
0: Write
1: Read
Lock [14..11] 4-bit Lock Value
0000B: Default operating access for addresses 0x00:0x04
1010B: Configuration access for addresses 0x05:0x11
COMMAND READ Data 1 READ Data 2
SAFETY-WORD
SSC-Master is driving DATA
SSC-Slave is driving DATA
t
wr_delay
COMMAND WRITE Data 1
SAFETY-WORD
SSC-Master is driving DATA
SSC-Slave is driving DATA
t
wr_delay
TLE5012B
Specification
Data Sheet 32 Rev. 2.0, 2014-02
Safety Word
The safety word consists of the following bits:
Bit Types
The types of bits used in the registers are listed here:
UPD [10] Update-Register Access
0: Access to current values
1: Access to values in update buffer
ADDR [9..4] 6-bit Address
ND [3..0] 4-bit Number of Data Words
Table 4-16 Structure of the Safety Word
Name Bits Description
STAT1)
1) When an error occurs, the corresponding status bit in the safety word remains “low” until the STAT register (address 00H)
is read via SSC interface.
Chip and Interface Status
[15] Indication of chip reset or watchdog overflow (resets after readout) via SSC
0: Reset occurred
1: No reset
[14] System error (e.g. overvoltage; undervoltage; VDD-, GND- off; ROM;...)
0: Error occurred (S_VR; S_DSPU; S_OV; S_XYOL: S_MAGOL; S_FUSE;
S_ROM; S_ADCT)
1: No error
[13] Interface access error (access to wrong address; wrong lock)
0: Error occurred
1: No error
[12] Valid angle value (NO_GMR_A = 0; NO_GMR_XY = 0)
0: Angle value invalid
1: Angle value valid
RESP [11..8] Sensor number response indicator
The sensor number bit is pulled low and the other bits are high
CRC [7..0] Cyclic Redundancy Check (CRC)
Table 4-17 Bit Types
Abbreviation Function Description
r Read Read-only registers
w Write Read and write registers
u Update Update buffer for this bit is present. If an update is issued and the Update-
Register Access bit (UPD in Command Word) is set, the immediate values
are stored in this update buffer simultaneously. This allows a snapshot of all
necessary system parameters at the same time.
Table 4-15 Structure of the Command Word (cont’d)
Name Bits Description
TLE5012B
Specification
Data Sheet 33 Rev. 2.0, 2014-02
Data communication via SSC
Figure 4-10 SSC bit ordering (read example)
Figure 4-11 Update of update registers
The data communication via SSC interface has the following characteristics:
• The data transmission order is Most-Significant Bit (MSB) first, Last-Significant Bit (LSB) last.
• Data is put on the data line with the rising edge on SCK and read with the falling edge on SCK.
• The SSC Interface is word-aligned. All functions are activated after each transmitted word.
• After every data transfer with ND ≥ 1, the 16-bit Safety Word is appended by the TLE5012B.
• A “high” condition on the Chip Select pin (CSQ) of the selected TLE5012B interrupts the transfer immediately.
The CRC calculator is automatically reset.
• After changing the data direction, a delay twr_delay (see Table 4-14) has to be implemented before continuing
the data transfer. This is necessary for internal register access.
• If in the Command Word the number of data is greater than 1 (ND > 1), then a corresponding number of
consecutive registers is read, starting at the address given by ADDR.
• In case an overflow occurs at address 3FH, the transfer continues at address 00H.
• If in the Command Word the number of data is zero (ND = 0), the register at the address given by ADDR is
read, but no Safety Word is sent by the TLE5012B. This allows a fast readout of one register.
• At a rising edge of CSQ without a preceding data transfer (no SCK pulse, see Figure 4-11), the content of all
registers which have an update buffer is saved into the buffer. This procedure serves to take a snapshot of all
relevant sensor parameters at a given time. The content of the update buffer can then be read by sending a
read command for the desired register and setting the UPD bit of the Command Word to “1”.
• After sending the Safety Word, the transfer ends. To start another data transfer, the CSQ has to be deselected
once for at least tCSoff.
• By default, the SSC interface is set to push-pull. The push-pull driver is active only if the TLE5012B has to send
data, otherwise the DATA pin is set to high-impedance.
SCK
DATA 811 10 9MSB 14 13 12
CSQ
SSC Transfer
LSB3217 6 5 4
Command Word Data Word (s)
SSC -Master is driving DAT A
SSC -Slave is driving DAT A
LSB1
RW ADDR LENGTHLOCK
MSB
t
wr_delay
UPD
SCK
DATA
CSQ
LSB LSBMSB
Command Word Data Word (s)Update -Signal
Update -Event
SSC -Master is driving DAT A
SSC -Slave is driving DAT A
t
CSupdate
TLE5012B
Specification
Data Sheet 34 Rev. 2.0, 2014-02
Cyclic Redundancy Check (CRC)
• This CRC is according to the J1850 Bus Specification.
• Every new transfer restarts the CRC generation.
• Every Byte of a transfer will be taken into account to generate the CRC (also the sent command(s)).
• Generator polynomial: X8+X4+X3+X2+1, but for the CRC generation the fast-CRC generation circuit is used
(see Figure 4-12)
• The seed value of the fast CRC circuit is ’11111111B’.
• The remainder is inverted before transmission.
Figure 4-12 Fast CRC polynomial division circuit
4.4.2 Pulse Width Modulation (PWM) Interface
The Pulse Width Modulation (PWM) interface can be selected via SSC (IF_MD = ‘01’).
The PWM update rate can be programmed within the register 0EH (IFAB_RES) in the following steps:
• ~0.25 kHz with 12-bit resolution
• ~0.5 kHz with 12-bit resolution
• ~1.0 kHz with 12-bit resolution
• ~2.0 kHz with 12-bit resolution
PWM uses a square wave with constant frequency whose duty cycle is modulated according to the last measured
angle value (AVAL register).
Figure 4-13 shows the principal behavior of a PWM with various duty cycles and the definition of timing values.
The duty cycle of a PWM is defined by the following general formulas:
(4.2)
The duty cycle range between 0 - 6.25% and 93.75 - 100% is used only for diagnostic purposes. In case the sensor
detects an error, the corresponding error bit in the Status register is set and the PWM duty cycle goes to the lower
(0 - 6.25%) or upper (93.75 - 100%) diagnostic range, depending on the kind of error (see “Output duty cycle
range” in Table 4-18). Except for an S_ADCT error, an error is only indicated by the corresponding diagnostic
duty-cycle as long as it persists, but at least once. However the value in the status register will remain until a read-
out via the SSC interface or a chip reset is performed. An S_ADCT error on the other side will be transmitted until
the next chip reset. This fail-safe diagnostic function can be disabled via the MOD_4 register.
Sensors with preset PWM are available as TLE5012B E50x0.
xor
X7 X6 X5 X4 X3 X2
xor
X0
xor xor Input
Serial
CRC
output
&
TX_CRC
1111 1 1 11
X1
parallel
Remainder
PWM
PWM
offonPWM
PWM
on
t
f
ttt
t
t
CycleDuty
1
=
+=
=
TLE5012B
Specification
Data Sheet 35 Rev. 2.0, 2014-02
Figure 4-13 Typical example of a PWM signal
The PWM frequency is derived from the digital clock via
(4.3)
The min/max values given in Table 4-18 take into account the internal digital clock variation specified in
Chapter 4.3.7. If external clock is used, the variation of the PWM frequency can be derived from the variation of
the external clock using Equation (4.3).
Table 4-18 PWM interface
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
PWM output frequencies
(Selectable by IFAB_RES)
fPWM1 232 244 262 Hz 1)
1) Not subject to production test - verified by design/characterization
fPWM2 464 488 525 Hz 1)
fPWM3 929 977 1050 Hz 1)
fPWM4 1855 1953 2099 Hz 1)
Output duty cycle range DYPWM 6.25 93.75 % Absolute angle1)
2 % Electrical Error (S_RST;
S_VR)1)
98 % System error (S_FUSE;
S_OV; S_XYOL;
S_MAGOL; S_ADCT)1)
0 1 % Short to GND1)
99 100 % Short to VDD, power loss1)
t
ON
‚0'
t
ON = High level
OFF = Low level Duty cycle = 6.25%
Duty cycle = 50%
Duty cycle = 93.75%
t
PWM
t
OFF
Vdd
U
IFA
Vdd
U
IFA
t
‚0'
t
Vdd
U
IFA
‚0'
4096*24
2*
IFAB_RES
DIG
PWM
f
f=
TLE5012B
Specification
Data Sheet 36 Rev. 2.0, 2014-02
4.4.3 Short PWM Code (SPC)
The Short PWM Code (SPC) is a synchronized data transmission based on the SENT protocol (Single Edge
Nibble Transmission) defined by SAE J2716. As opposed to SENT, which implies a continuous transmission of
data, the SPC protocol transmits data only after receiving a specific trigger pulse from the microcontroller. The
required length of the trigger pulse depends on the sensor number, which is configurable. Thereby, SPC allows
the operation of up to four sensors on one bus line.
SPC enables the use of enhanced protocol functionality due to the ability to select between various sensor slaves
(ID selection). The slave number (S_NR) can be given by the external circuit of SCK and IFC pin. In case of VDD
on SCK, the S_NR[0] can be set to 1 and in the case of GND on SCK the S_NR[0] is equal to 0. S_NR[1] can be
adjusted in the same way by the IFC pin.
As in SENT, the time between two consecutive falling edges defines the value of a 4-bit nibble, thus representing
numbers between 0 and 15. The transmission time therefore depends on the transmitted data values. The single
edge is defined by a 3 Unit Time (UT, see Chapter 4.4.3.1) low pulse on the output, followed by the high time
defined in the protocol (nominal values, may vary depending on the tolerance of the internal oscillator and the
influence of external circuitry). All values are multiples of a unit time frame concept. A transfer consists of the
following parts (Figure 4-14):
• A trigger pulse by the master, which initiates the data transmission
• A synchronization period of 56 UT (in parallel, a new sample is calculated)
• A status nibble of 12-27 UT
• Between 3 and 6 data nibbles of 12-27 UT
• A CRC nibble of 12-27 UT
• An end pulse to terminate the SPC transmission
Figure 4-14 SPC frame example
The CRC checksum includes the status nibble and the data nibbles, and can be used to check the validity of the
decoded data. The sensor is available for the next trigger pulse 90μs after the falling edge of the end pulse (see
Figure 4-15).
Figure 4-15 SPC pause timing diagram
In SPC mode, the sensor does not continuously calculate an angle from the raw data. Instead, the angle
calculation is started by the trigger nibble from the master. In this mode, the AVAL register, which stores the angle
value and can be read via SSC, contains the angle which was calculated after the last SPC trigger nibble.
Synchronisation Frame Status -Nibble Data -Nibble 1
Bit 11-8
Data -Nibble 2
Bit 7-4
Data -Nibble 3
Bit 3-0 CRC
56 tck 12..27 tck 12.. 27 tck 12.. 27 tck 12..27 tck 12..27 tck
Nibble-Encoding : ( 12+x)*tck
Time-Base : 1 tck ( 3µs+ /-dtck )
Trigger Nibble End -Pulse
24,34,51,78 tck 12 tck
µC Activity
Sensor Activity
Synchronisation Frame
...
Trigger Nibble End- Pulse
µC Activity
Sensor Activity
Synchronisation Frame
...
Trigger Nibble
> 90 µs
End-Pulse
TLE5012B
Specification
Data Sheet 37 Rev. 2.0, 2014-02
In parallel to SPC, the SSC interface can be used for individual configuration. The number of transmitted SPC
nibbles can be changed to customize the amount of information sent by the sensor. The frame contains a 16-bit
angle value and an 8-bit temperature value in the full configuration (Table 4-19).
Sensors with preset SPC are available as TLE5012B E9000
The status nibble, which is sent with each SPC data frame, provides an error indication similar to the Safety Word
of the SSC protocol. In case the sensor detects an error, the corresponding error bit in the Status register is set
and either the bit SYS_ERR or the bit ELEC_ERR of the status nibble will be “high”, depending on the kind of error
(see Table 4-20). Except for an S_ADCT error, an error is only indicated by the corresponding error bit in the
status nibble as long as it persists, but at least once. However the value in the status register will remain until a
read-out via the SSC interface or a chip reset is performed. An S_ADCT error on the other side will be transmitted
until the next chip reset. The fail-safe diagnostic function can be disabled via the MOD_4 register.
4.4.3.1 Unit Time Setup
The basic SPC protocol unit time granularity is defined as 3 μs. Every timing is a multiple of this basic time unit.To
achieve more flexibility, trimming of the unit time can be done within IFAB_HYST. This enables a setup of different
unit times.
Table 4-19 Frame configuration
Frame type IFAB_RES Data nibbles
12-bit angle 00 3 nibbles
16-bit angle 01 4 nibbles
12-bit angle, 8-bit temperature 10 5 nibbles
16-bit angle, 8-bit temperature 11 6 nibbles
Table 4-20 Structure of status nibble
Name Bits Description
SYS_ERR [3] Indication of system error (S_FUSE, S_OV, S_XYOL, S_MAGOL, S_ADCT)
0: No system error
1: System error occurred
ELEC_ERR [2] Indication of electrical error (S_RST, S_VR)
0: No electrical error
1: Electrical error occurred
S_NR [1] Slave number bit 1 (level on IFC)
[0] Slave number bit 0 (level on SCK)
Table 4-21 Predivider setting
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Unit time tUnit 3.0 μs IFAB_HYST = 001)
1) Not subject to production test - verified by design/characterization
2.5 IFAB_HYST = 011)
2.0 IFAB_HYST = 101)
1.5 IFAB_HYST = 111)
TLE5012B
Specification
Data Sheet 38 Rev. 2.0, 2014-02
4.4.3.2 Master Trigger Pulse Requirements
An SPC transmission is initiated by a master trigger pulse on the IFA pin. To detect a low-level on the IFA pin, the
voltage must be below a threshold Vth. The sensor detects that the IFA line has been released as soon as Vth is
crossed. Figure 4-16 shows the timing definitions for the master pulse. The master low time tmlow as well as the
total trigger time tmtr are given in Table 4-22.
If the master low time exceeds the maximum low time, the sensor does not respond and is available for a next
triggering 30 μs after the master pulse crosses Vthr. tmd,tot is the delay between internal triggering of the falling edge
in the sensor and the triggering of the ECU.
Figure 4-16 SPC Master pulse timing
4.4.3.3 Checksum Nibble Details
The checksum nibble is a 4-bit CRC of the data nibbles including the status nibble. The CRC is calculated using
a polynomial x4+x3+x2+1 with a seed value of 0101B. The remainder after the last data nibble is transmitted as
CRC.
Table 4-22 Master pulse parameters
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Threshold Vth 50 % of
VDD
1)
1) Not subject to production test - verified by design/characterization
Threshold hysteresis Vthhyst 8% ofV
DD = 5 V1)
3V
DD VDD = 3 V1)
Total trigger time tmtr 90 UT SPC_Trigger = 0;1)2)
2) Trigger time in the sensor is fixed to the number of units specified in the “typ.” column, but the effective trigger time varies
due to the sensor’s clock variation
tmlow
+12
UT SP_Trigger = 11)
Master low time tmlow 8 12 14 UT S_NR =001)
16 22 27 S_NR =011)
29 39 48 S_NR =101)
50 66 81 S_NR =111)
Master delay time tmd,tot 5.8 μs1)
SPC
ECU trigger
level
V
th
t
mlow
t
md,tot
t
mtr
TLE5012B
Specification
Data Sheet 39 Rev. 2.0, 2014-02
4.4.4 Hall Switch Mode (HSM)
The Hall Switch Mode (HSM) within the TLE5012B makes it possible to emulate the output of 3 Hall switches. Hall
switches are often used in electrical commutated motors to determine the rotor position. With these 3 output
signals, the motor will be commutated in the right way. Depending on which pole pairs of the rotor are used, various
electrical periods have to be controlled. This is selectable within 0EH (HSM_PLP). Figure 4-17 depicts the three
output signals with the relationship between electrical angle and mechanical angle. The mechanical 0° point is
always used as reference.
The HSM is generally used with push-pull output, but it can be changed to open-drain within the register IFAB_OD.
Sensors with preset HSM are available as TLE5012B E3005.
Figure 4-17 Hall Switch Mode
The HSM Interface can be selected via SSC (IF_MD = 010).
Table 4-23 Hall Switch Mode
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Rotation speed n 10000 rpm Mechanical2)
HS1
HS2
HS3
0°Electrical Angle 60° 120° 180° 240° 300° 360°
Hall-Switch-Mode: 3phase Generation
Angle
Mech. Angle with
5 Pole Pairs 0° 12° 24° 36° 48° 60° 72°
0° 20° 40° 60° 80° 100° 120°
Mech. Angle with
3 Pole Pairs
TLE5012B
Specification
Data Sheet 40 Rev. 2.0, 2014-02
Electrical angle accuracy αelect 0.6 1 ° 1 pole pair with
autocalibration1)2)
1.2 2 ° 2 pole pairs with autocal.1)2)
1.8 3 ° 3 pole pairs with autocal.1)2)
2.4 4 ° 4 pole pairs with autocal.1)2)
3.0 5 ° 5 pole pairs with autocal.1)2)
3.6 6 ° 6 pole pairs with autocal.1)2)
4.2 7 ° 7 pole pairs with autocal.1)2)
4.8 8 ° 8 pole pairs with autocal.1)2)
5.4 9 ° 9 pole pairs with autocal.1)2)
6.0 10 ° 10 pole pairs with
autocal.1)2)
6.6 11 ° 11 pole pairs with
autocal.1)2)
7.2 12 ° 12 pole pairs with
autocal.1)2)
7.8 13 ° 13 pole pairs with
autocal.1)2)
8.4 14 ° 14 pole pairs with
autocal.1)2)
9.0 15 ° 15 pole pairs with
autocal.1)2)
9.6 16 ° 16 pole pairs with
autocal.1)2)
Mechanical angle switching
hysteresis
αHShystm 0 0.703 ° Selectable by
IFAB_HYST2)3)4)
Table 4-23 Hall Switch Mode (cont’d)
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
TLE5012B
Specification
Data Sheet 41 Rev. 2.0, 2014-02
To avoid switching due to mechanical vibrations of the rotor, an artificial hysteresis is recommended (Figure 4-18).
Electrical angle switching
hysteresis5)
αHShystel 0.70 ° 1 pole pair;
IFAB_HYST=111)2)
1.41 ° 2 pole pairs;
IFAB_HYST=111)2)
2.11 ° 3 pole pairs;
IFAB_HYST=111)2)
2.81 ° 4 pole pairs;
IFAB_HYST=111)2)
3.52 ° 5 pole pairs;
IFAB_HYST=111)2)
4.22 ° 6 pole pairs;
IFAB_HYST=111)2)
4.92 ° 7 pole pairs;
IFAB_HYST=111)2)
5.62 ° 8 pole pairs;
IFAB_HYST=111)2)
6.33 ° 9 pole pairs;
IFAB_HYST=111)2)
7.03 ° 10 pole pairs;
IFAB_HYST=111)2)
7.73 ° 11 pole pairs;
IFAB_HYST=111)2)
8.44 ° 12 pole pairs;
IFAB_HYST=111)2)
9.14 ° 13 pole pairs;
IFAB_HYST=111)2)
9.84 ° 14 pole pairs;
IFAB_HYST=111)2)
10.55 ° 15 pole pairs;
IFAB_HYST=111)2)
11.25 ° 16 pole pairs;
IFAB_HYST=111)2)
Fall time tHSfall 0.02 1 μsR
L = 2.2kΩ; CL < 50pF2)
Rise time tHSrise 0.4 1 μsR
L = 2.2kΩ; CL < 50pF2)
1) Depends on internal oscillator frequency variation (Section 4.3.7)
2) Not subject to production test - verified by design/characterization
3) GMR hysteresis not considered
4) Minimum hysteresis without switching
5) The hysteresis has to be considered only at change of rotation direction
Table 4-23 Hall Switch Mode (cont’d)
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
TLE5012B
Specification
Data Sheet 42 Rev. 2.0, 2014-02
Figure 4-18 HS hysteresis
4.4.5 Incremental Interface (IIF)
The Incremental Interface (IIF) emulates the operation of an optical quadrature encoder with a 50% duty cycle. It
transmits a square pulse per angle step, where the width of the steps can be configured from 9bit (512 steps per
full rotation) to 12bit (4096 steps per full rotation) within the register MOD_4 (IFAB_RES). The rotation direction is
given either by the phase shift between the two channels IFA and IFB (A/B mode) or by the level of the IFB channel
(Step/Direction mode), as shown in Figure 4-19 and Figure 4-20. The incremental interface can be configured for
A/B mode or Step/Direction mode in register MOD_1 (IIF_MOD).
Using the Incremental Interface requires an up/down counter on the microcontroller, which counts the pulses and
thus keeps track of the absolute position. The counter can be synchronized periodically by using the SSC interface
in parallel. The angle value (AVAL register) read out by the SSC interface can be compared to the stored counter
value. In case of a non-synchronization, the microcontroller adds the difference to the actual counter value to
synchronize the TLE5012B with the microcontroller.
After startup, the IIF transmits a number of pulses which correspond to the actual absolute angle value. Thus, the
microcontroller gets the information about the absolute position. The Index Signal that indicates the zero crossing
is available on the IFC pin.
Sensors with preset IIF are available as TLE5012B E1000.
A/B Mode
The phase shift between phases A and B indicates either a clockwise (A follows B) or a counterclockwise (B
follows A) rotation of the magnet.
Figure 4-19 Incremental interface with A/B mode
Ideal Switching Point
α
elect
α
HShystel
α
HShystel
α
elect
0°
90° el . Phase shift
0 1 2 3 4 5 6 7 6 5 4 3 2 1
Phase A
Counter
Phase B
Incremental Interface
(A/B Mode)
V
H
V
L
V
H
V
L
TLE5012B
Specification
Data Sheet 43 Rev. 2.0, 2014-02
Step/Direction Mode
Phase A pulses out the increments and phase B indicates the direction.
Figure 4-20 Incremental interface with Step/Direction mode
4.5 Test Mechanisms
4.5.1 ADC Test Vectors
In order to test the correct functionality of the ADCs, the ADC inputs can be switched from the GMR bridge outputs
to a chain of fixed resitors which act as a voltage divider. The ADCs are then fed with test vectors of fixed voltages
to simulate a set of magnet positions. The functionality of the ADCs is verified by checking the angle value (AVAL
register) for each test vector. This test is activated via SSC command within the SIL register (ADCTV_EN).
Registers ADCTV_Y and ADCTV_X are used to select the test vector, as shown in Figure 4-21.
The following X/Y ADC values can be programmed:
• 4 points, circle amplitude = 70% (0°,90°, 180°, 270°)
• 8 points, circle amplitude = 100% (0°, 45°, 90°, 135°, 180°, 225°, 270°, 315°)
• 8 points, circle amplitude = 122.1% (35.3°, 54.7°, 125.3°, 144.7°, 215.3°, 234.7°, 305.3°, 324.7°)
• 4 points, circle amplitude = 141.4% (45°, 135°, 225°, 315°)
Note: The 100% values typically correspond to 21700 digits and the 70% values to 15500 digits.
Table 4-24 Incremental Interface
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Incremental output frequency fInc 1.0 MHz Frequency of phase A and
phase B1)
1) Not subject to production test - verified by design/characterization
Index pulse width t0° 5μs0°
1)
Table 4-25 ADC test vectors
Register bits X/Y values (decimal)
Min. Typ. Max.
000 0
001 15500
010 21700
011 32767
1001) 0
101 -15500
Step
Counter
Direction
Incremental Interface
(Step/Direction Mode)
V
H
V
L
V
H
V
L
0 1 2 3 4 5 6 7 6 5 4 3 2 1
TLE5012B
Specification
Data Sheet 44 Rev. 2.0, 2014-02
Figure 4-21 ADC test vectors
4.6 Supply Monitoring
The internal voltage nodes of the TLE5012B are monitored by a set of comparators in order to ensure error-free
operation. An over- or undervoltage condition must be active at least 256 periods of the digital clock to set the
corresponding error bits in the Status register. This works as digital spike suppression.
Over- or undervoltage errors trigger the S_VR bit of Status register. This error condition is signaled via the in the
Safety Word of the SSC protocol, the status nibble of the SPC interface or the lower diagnostic range of the PWM
interface.
110 -21700
111 -32768
1) Not allowed to use
Table 4-26 Test comparator threshold voltages
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Overvoltage detection VOVG 2.80 V 1)
1) Not subject to production test - verified by design/characterization
VOVA 2.80 V 1)
VOVD 2.80 V 1)
VDD overvoltage VDDOV 6.05 V 1)
VDD undervoltage VDDUV 2.70 V 1)
GND - off voltage VGNDoff -0.55 V 1)
VDD - off voltage VVDDoff 0.55 V 1)
Spike filter delay tDEL 10 μs1)
Table 4-25 ADC test vectors (cont’d)
Register bits X/Y values (decimal)
Min. Typ. Max.
ADCTV_X
ADCTV_Y
0%
122.1%
100.0%
70%
141.4%
TLE5012B
Specification
Data Sheet 45 Rev. 2.0, 2014-02
4.6.1 Internal Supply Voltage Comparators
Every voltage regulator has an overvoltage (OV) comparator to detect malfunctions. If the nominal output voltage
of 2.5 V is larger than VOVG, VOVA and VOVD, then this overvoltage comparator is activated.
4.6.2 VDD Overvoltage Detection
The overvoltage detection comparator monitors the external supply voltage at the VDD pin.
Figure 4-22 Overvoltage comparator
4.6.3 GND - Off Comparator
The GND - Off comparator is used to detect a voltage difference between the GND pin and SCK. This circuit can
detect a disconnection of the supply GND Pin.
Figure 4-23 GND - off comparator
4.6.4 VDD - Off Comparator
The VDD - Off comparator detects a disconnection of the VDD pin supply voltage. In this case, the TLE5012B is
supplied by the SCK and CSQ input pins via the ESD structures.
Figure 4-24 VDD - off comparator
REF
-
+
10µs
Spike
Filter
xxx_OV
V
DDA
GNDGND
V
DD
V
RG
V
RA
V
RD
-
+
10µs
Spike
Filter
GND_OFF
V
DDA
GND
SCK
GND
V
DD
+dV
Diode-
reference
1µs
Mono
Flop
10µs
Spike
Filter
VDD_OFF
V
DDA
GND
V
DD
CSQ
SCK -dV
GND
1µs
Mono
Flop
-
+
V
VDDoff
TLE5012B
Pre-Configured Derivates
Data Sheet 46 Rev. 2.0, 2014-02
5 Pre-Configured Derivates
Derivates of the 5012B are available with different pre-configured register settings for specific applications. The
configuration of all derivates can be changed via SSC interface.
5.1 IIF-type: E1000
The TLE5012B-E1000 is preconfigured for Incremental Interface and fast angle update period (42.7 μs). It is most
suitable for BLDC motor commutation.
• Autocalibration mode 1 enabled.
• Prediction enabled.
• Hysteresis is set to 0.703°.
• 12bit mode, one count per 0.088° angle step.
• Incremental Interface A/B mode.
5.2 HSM-type: E3005
The TLE5012B-E3005 is preconfigured for Hall-Switch-Mode and fast angle update period (42.7 μs). It is most
suitable as a replacement for three Hall switches for BLDC motor commutation.
• Number of pole pairs is set to 5.
• Autocalibration mode 1 enabled.
• Prediction enabled.
• Hysteresis is set to 0.703°.
5.3 PWM-type: E5000
The TLE5012B-E5000 is preconfigured for Pulse-Width-Modulation interface. It is most suitable for steering angle
and actuator position sensing.
• Filter update period is 85.4 μs.
• PWM frequency is 244 Hz.
• Autocalibration, Prediction, and Hysteresis are disabled.
5.4 PWM-type: E5020
The TLE5012B-E5020 is preconfigured for Pulse-Width-Modulation interface with high frequency. It is most
suitable for steering angle and actuator position sensing.
• Filter update period is 42.7 μs.
• PWM frequency is 1953 Hz.
• Autocalibration mode 2 enabled.
• Prediction and Hysteresis are disabled.
• PWM interface is set to open-drain output.
5.5 SPC-type: E9000
The TLE5012B-E9000 is preconfigured for Short-PWM-Code interface. It is most suitable for steering angle and
actuator position sensing.
• Filter update period is 85.4 μs.
• Autocalibration, Prediction, and Hysteresis are disabled.
• SPC unit time is 3 μs.
• SPC interface is set to open-drain output.
TLE5012B
Package Information
Data Sheet 47 Rev. 2.0, 2014-02
6 Package Information
6.1 Package Parameters
6.2 Package Outline
Figure 6-1 PG-DSO-8 package dimension
Table 6-1 Package Parameters
Parameter Symbol Limit Values Unit Notes
Min. Typ. Max.
Thermal resistance RthJA 150 200 K/W Junction to air1)
1) according to Jedec JESD51-7
RthJC 75 K/W Junction to case
RthJL 85 K/W Junction to lead
Soldering moisture level MSL 3 260°C
Lead Frame Cu
Plating Sn 100% > 7 μm
TLE5012B
Package Information
Data Sheet 48 Rev. 2.0, 2014-02
Figure 6-2 Position of sensing element
6.3 Footprint
Figure 6-3 Footprint of PG-DSO-8
Table 6-2 Sensor IC placement tolerances in package
Parameter Values Unit Notes
Min. Max.
position eccentricity -200 200 µm in X- and Y-direction
rotation -3 3 ° affects zero position offset of sensor
tilt -3 3 °
0.65
1.31
5.69
1.27
TLE5012B
Package Information
Data Sheet 49 Rev. 2.0, 2014-02
6.4 Packing
Figure 6-4 Tape and Reel
6.5 Marking
Processing
Note: For processing recommendations, please refer to Infineon’s Notes on processing
Position Marking Description
1st Line 012Bxxxx See ordering table on Page 8
2nd Line xxx Lot code
3rd Line Gxxxx G..green, 4-digit..date code
8
6.4
5.2
0.3
±0.3
12
2.1
1.75
