W49L401(T) 256K x 16 CMOS FLASH MEMORY 1. GENERAL DESCRIPTION The W49L401(T) is a 4-megabit, 3.3-volt only CMOS flash memory organized as 256K x 16 bits. The device can be programmed and erased in-system with a standard 3.3-volt power supply. A 12-volt VPP is not required. The unique cell architecture of the W49L401(T) results in fast program/erase operations with extremely low current consumption (compared to other comparable 3.3-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers. 2. FEATURES * Single Voltage operations: - 3.0 - 3.6V Read/Erase/Program * Fast Program operation: - Word-by-Word programming: 30 S (typ.) * Fast Erase operation: - Page/Block Erase time: 50 mS (typ.) - Chip Erase time: 200 mS (typ.) * Optional Uniform Page configuration * Low power consumption - Active current: 10 mA (typ.) - Standby current: 5 A (typ.) * Automatic program and erase timing with internal VPP generation * End of program or erase detection * Fast Read access time: 70 nS - Toggle bit * Endurance: 10K cycles (typ.) - Data polling * Twenty-year data retention * Hardware data protection * * RY/#BY open-drain output provides hardware end-of-write detection Block configuration * Hardware #RESET pin - One 8K-word boot block with lockout protection * Latched address and data * TTL compatible I/O * JEDEC standard word-wide pinouts * Available packages: 44-pin SOP, 48-pin TSOP - Two 4K-word parameter blocks - One 16K-word main memory array block - Seven 32K-word main memory array blocks - 128 uniform 2K-word pages -1- Publication Release Date: August 16, 2002 Revision A4 W49L401(T) 3. PIN CONFIGURATIONS 4. BLOCK DIAGRAM NC RY/#BY A17 A7 A6 A5 A4 A3 A2 A1 A0 #CE VSS #OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 1 22 24 23 A15 A14 A13 A12 A11 A10 A9 A8 NC NC #WE #RESET NC NC RY/#BY NC A17 A7 A6 A5 A4 A3 A2 A1 1 48 2 3 47 4 45 5 6 44 43 7 42 44 2 43 3 4 42 41 5 40 6 39 7 8 38 37 9 10 11 44-pin SOP 36 35 34 12 33 13 14 32 15 31 30 16 29 17 18 28 27 19 26 25 20 21 8 9 10 11 46 48-pin TSOP 41 40 39 38 12 13 37 36 14 35 15 16 34 33 17 32 18 19 31 30 20 29 21 28 22 23 27 26 24 25 #RESET #WE A8 A9 A10 A11 A12 A13 A14 A15 A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 #OE VSS #CE A0 RY/#BY #CE #OE #WE #RESET A0 DQ0 CONTROL D E C O D E R . . A17 OUTPUT BUFFER . . DQ15 W49L401 W49L401T 3FFFF MAIN MEMORY 240K WORDS (1x16K WORDS BOOT BLOCK 8K WORDS 04000 7x32K WORDS) 03FFF PARAMETER PARAMETER BLOCK2 BLOCK1 4K WORDS 4K WORDS 03000 02FFF PARAMETER PARAMETER BLOCK2 BLOCK1 4K WORDS 4K WORDS 02000 01FFF BOOT BLOCK MAIN MEMORY 8K WORDS 240K WORDS 00000 (1x16K WORDS 7x32K WORDS) 5. PIN DESCRIPTION SYMBOL #RESET Reset RY/#BY Ready/#Busy Output A0 - A17 Address Inputs DQ0 - DQ15 -2- PIN NAME Data Inputs/Outputs #CE Chip Enable #OE Output Enable #WE Write Enable VDD Power Supply VSS Ground NC No Connection 3FFFF 3E000 3DFFF 3D000 3CFFF 3C000 3BFFF 00000 W49L401(T) 6. FUNCTIONAL DESCRIPTION Read Mode The read operation of the W49L401(T) is controlled by #CE and #OE, both of which have to be low for the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is de-selected and only standby power will be consumed. #OE is the output control and is used to gate data to the output pins. The data bus is in high impedance state when either #CE or #OE is high. Refer to the timing waveforms for further details. Reset Operation The #RESET input pin can be used in some application. When #RESET pin is at high state, the device is in normal operation mode. When #RESET pin is driven low for at least a period of TRP, it will halt the device and all outputs are at high impedance state. The device also resets the internal state machine to read array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence to assure data integrity. As the high state re-asserted to the #RESET pin, the device will return to read or standby mode, it depends on the control signals. The system can read data TRH after the #RESET pin returns to VIH. The other function for #RESET pin is temporary reset the boot block. By applying the 12V to #RESET pin, the boot block can be reprogrammed even though the boot block lockout function is enabled. Boot Block Operation There is one 8K-word boot block in this device, which can be used to store boot code. It is located in the first 8K words (for W49L401T, located in the last 8K words) of the memory with the address range from 0000(hex) to 1FFF(hex). (for W49L401T, address range from 3E000h to 3FFFFh) See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set, the data for the designated block cannot be erased or programmed (programming lockout); the regular programming method can change the data in other memory locations. There is one condition that the lockout feature can be over-ridden. Just apply 12V to #RESET pin, the lockout feature will temporarily be inactivated and the boot block can be erased/programmed. Once the #RESET pin returns to CMOS/TTL level, the lockout feature will be activated again. In order to detect whether the boot block feature is set on the 8K-words block, users can perform software command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address "0002 hex". If the output data in DQ0 is "1", the boot block programming lockout feature is activated; if the output data in DQ0 is "0", the lockout feature is inactivated and the block can be erased/programmed. To return to normal operation, perform a three-byte command sequence (or an alternate single-word command) to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection. Chip Erase Operation The chip-erase mode can be initiated by a six-word command sequence. After the command loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed in a fast 200 mS (typical). The host system is not required to provide any control or timing during this operation. The entire memory array will be erased to FFFF(hex) by the chip erase operation if the boot block programming lockout feature is not activated. Once the boot block lockout feature is activated, the chip erase function will erase all the blocks/pages except the boot block. -3- Publication Release Date: August 16, 2002 Revision A4 W49L401(T) Block/Page Erase Operation The W49L401(T) provides both uniform small page (2K-word) and non-symmetrical block (4K/8K/16K/32K-word) erase capabilities for versatile Flash applications. Each block or page can be erased individually by initiating a six-word command sequence. The block address (BA) or page address (PA) is latched on the falling #WE edge of the sixth cycle while the XX30/XX50(hex) data input command is latched at the rising edge of #WE. After the command loading cycle, the device enters the internal block/page erase mode, which is automatically timed and will be completed in a fast 50 mS (typical). The host system is not required to provide any control or timing during this operation. The device will automatically return to normal read mode after the erase operation completed. Data-polling, Toggle-Bit and/or RY/#BY pin can be used to detect end of erase cycle. The bootblock (8K-words) consists of 4 corresponding uniform pages of 2K-words each. When the boot block lockout feature is activated, any page/block erase command with the associated PA/BA within the bootblock address range (0000-01FFF for W49L401, and 3E000-3FFFF for W49L401T) will be ignored and the device will return to read mode without any data changes. Program Operation The W49L401(T) is programmed on a word-by-word basis. Program operation can only change logical data "1" to logical data "0" The erase operation (changed entire data in individual page/block or whole chip from "0" to "1") is needed before programming. The program operation is initiated by a 4-word command cycle (see Command Codes for Word Programming). The device will internally enter the program operation immediately after the wordprogram command is entered. The internal program timer will automatically time-out (50 S max. TBP) once completed and return to normal read mode. Data_polling, Toggle_Bit and/or RY/#BY pin can be used to detect end of program cycle. Hardware Data Protection The integrity of the data stored in the W49L401(T) is also hardware protected in the following ways: (1) Noise/Glitch Protection: A #WE pulse of less than 10 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming operation and read are inhibited when VDD is less than 1.8V typical. (3) Write Inhibit Mode: Forcing #OE low, #CE high, or #WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out 10 mS before any write (erase/program) operation. Data Polling (DQ7)- Write Status Detection The W49L401(T) includes a data polling feature to indicate the end of a program or erase cycle. When the W49L401(T) is in the internal program or erase cycle, any attempt to read DQ7 of the last word loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ7 will show the true data. Note that, DQ7 will show logical "0" during the erase cycle. And it will become logical "1" or true data when the erase cycle is completed. Toggle Bit (DQ6)- Write Status Detection In addition to data polling, the W49L401(T) provides another method for determining the end of a program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will -4- W49L401(T) produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation. Ready/#Busy The W49L401(T) also provides the hardware method to detect the completion of program/erase cycle . The RY/#BY output pin will be asserted low (busy) during programming/erasing operations, and will be released to high state by an external pull-up (ready) when internal program/erase cycle is completed. This is an open-drain output pin for easy external connection. Product Identification The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms. The manufacturer and device codes can be accessed by software or hardware operation. In the software access mode, a six-word (or JEDEC 3-word) command sequence can be used to access the product ID. A read from address 0000H outputs the manufacturer code, 00DA(hex). A read from address 0001(hex) outputs the device code, 003D(hex) for bottom boot (and TBD for top boot). The product ID operation can be terminated by a three-word command sequence or an alternative oneword command sequence (see Command Definition table). In the hardware access mode, access to the product ID is activated by forcing #CE and #OE low, #WE + high, and raising A9 to VHH (12V /- 0.5V). Table of Operating Modes Operating Mode Selection (VHH = 12V 0.5V) MODE PINS #CE #OE #WE #RESET VIL VIL VIH VIH AIN Erase/Program VIL VIH VIL VIH AIN Din Standby VIH X X VIH X High Z VIH X X VIH X High Z X VIL X VIH X High Z/DOUT X X VIH VIH X High Z/DOUT X VIH X VIH X High Z A0 = VIL; A1-A15 = VIL; A9 = VHH Manufacturer Code 00DA (Hex) Read Erase/Program Inhibit Output Disable Product ID Reset VIL VIL VIH VIH X X X VIL -5- ADDRESS DQ. Dout Device Code A0 = VIH; A1 - A15 = VIL; 003D (Hex) for bottom A9 = VHH TBD for Top X High Z Publication Release Date: August 16, 2002 Revision A4 W49L401(T) Table of Software Command Definition COMMAND DESCRIPTION Chip Erase Block Erase Page Erase Word Program Boot Block Lockout Product ID Entry (1) Product ID Exit (1) Product ID Exit NO. OF Cycles 6 6 6 4 6 3 3 1 1ST CYCLE Addr. Data 2ND CYCLE Addr. Data 3RD CYCLE Addr. Data 4TH CYCLE Addr. Data 5TH CYCLE Addr. Data 6TH CYCLE Addr. Data 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 BA(5) 30 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 PA(4) 50 5555 AA 2AAA 55 5555 A0 AIN DIN 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40 5555 AA 2AAA 55 5555 90 5555 AA 2AAA 55 5555 F0 XXXX F0 Notes: 1. Address Format: A14 - A0 (Hex); Data Format: DQ15 - DQ8 (Don't Care); DQ7 - DQ0 (Hex) 2. If any invalid command or read cycle (both #CE & #OE are active low) is inserted during any of the above software command sequence, it will abort the operation and the device return to read mode. 3. Either one of the two Product ID Exit commands can be used, and Read mode is resumed after this command executed. 4. PA: Page Address W49L401 PA = 00000h to 007FFh for Page0 PA = 00800h to 00FFFh for Page1 PA = 01000h to 017FFh for Page2 PA = 01800h to 01FFFh for Page3 PA = 02000h to 027FFh for Page4 PA = 02800h to 02FFFh for Page5 ... ... ... PA = 3D000h to 3D7FFh for Page122 PA = 3D800h to 3DFFFh for Page123 PA = 3E000h to 3E7FFh for Page124 PA = 3E800h to 3EFFFh for Page125 PA = 3F000h to 3F7FFh for Page126 PA = 3F800h to 3FFFFh for Page127 W49L401T PA = 3F800h to 3FFFFh for Page0 PA = 3F000h to 3F7FFh for Page1 PA = 3E800h to 3EFFFh for Page2 PA = 3E000h to 3E7FFh for Page3 PA = 3D800h to 3DFFFh for Page4 PA = 3D000h to 3D7FFh for Page5 ... ... ... PA = 02800h to 02FFFh for Page122 PA = 02000h to 027FFh for Page123 PA = 01800h to 01FFFh for Page123 PA = 01000h to 017FFh for Page125 PA = 00800h to 00FFFh for Page126 PA = 00000h to 007FFh for Page127 5. BA: Block Address W49L401 BA = 00000h to 01FFFh for Boot Block (8KW) BA = 02XXXh for Parameter Block1 (4KW) BA = 03XXXh for Parameter Block2 (4KW) BA = 04000h to 07FFFh for Main Memory Block1 (16KW) BA = 08000h to 0FFFFh for Main Memory Block2 (32KW) BA = 10000h to 17FFFh for Main Memory Block3 (32KW) BA = 18000h to 1FFFFh for Main Memory Block4 (32KW) BA = 20000h to 27FFFh for Main Memory Block5 (32KW) BA = 28000h to 2FFFFh for Main Memory Block6 (32KW) BA = 30000h to 37FFFh for Main Memory Block7 (32KW) BA = 38000h to 3FFFFh for Main Memory Block8 (32KW) -6- W49L401T BA = 3E000h to 3FFFFh for Boot Block (8KW) BA = 3DXXXh for Parameter Block1 (4KW) BA = 3CXXXh for Parameter Block2 (4KW) BA = 38000h to 3BFFFh for Main Memory Block1 (16KW) BA = 30000h to 37FFFh for Main Memory Block2 (32KW) BA = 28000h to 2FFFFh for Main Memory Block2 (32KW) BA = 20000h to 27FFFh for Main Memory Block3 (32KW) BA = 18000h to 1FFFFh for Main Memory Block4 (32KW) BA = 10000h to 17FFFh for Main Memory Block5 (32KW) BA = 08000h to 07FFFh for Main Memory Block7 (32KW) BA = 00000h to 07FFFh for Main Memory Block8 (32KW) W49L401(T) Embedded Programming Algorithm Start Write Program Command Sequence (see below) #Data Polling/ Toggle bit Pause T EC /TSEC No Increment Address Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program Data -7- Publication Release Date: August 16, 2002 Revision A4 W49L401(T) Embedded Erase Algorithm Start Write Erase Command Sequence (see below) #Data Polling or Toggle Bit Successfully Completed Pause T EC /T SEC Erasure Completed Chip Erase Command Sequence Individual PageErase Command Sequence (Address/Command): (Address/Command): Individual BlockErase Command Sequence (Address/Command): 5555H/AAH 5555H/AAH 5555H/AAH 2AAAH/55H 2AAAH/55H 2AAAH/55H 5555H/80H 5555H/80H 5555H/80H 5555H/AAH 5555H/AAH 5555H/AAH 2AAAH/55H 2AAAH/55H 2AAAH/55H 5555H/10H Block Address/30H -8- PageAddress/50H W49L401(T) Embedded #Data Polling Algorithm Start VA = Byte address for programming = Any of the sector addresses within the sector being erased during sector erase operation = Valid address equals any sector group address during chip erase Read Byte (DQ0 - DQ7) Address = VA No DQ7 = Data ? Yes Pass Embedded Toggle Bit Algorithm Start Read Byte (DQ0 - DQ7) Address = Don't Care Yes DQ6 = Toggle ? No Pass -9- Publication Release Date: August 16, 2002 Revision A4 W49L401(T) Software Product Identification and Boot Block Lockout Detection Acquisition Flow Product Identification Entry (1) Load data AA to address 5555 Load data 55 to address 2AAA Load data 90 to address 5555 Pause 10 S Product Identification and Boot Block Lockout Detection Mode (3) Product Identification Exit(6) Load data AA to address 5555 (2) Read address = 0000 data = 00DA Read address = 0001 data = 003D for bottom TBD for top Read address = 0002 data in DQ0 =1/0 Load data 55 to address 2AAA (2) Load data F0 to address 5555 (4) Pause 10 S (5) Normal Mode - 10 - W49L401(T) Boot Block Lockout Enable Acquisition Flow Boot Block Lockout Feature Set Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 40 to address 5555 Pause 200 mS Exit - 11 - Publication Release Date: August 16, 2002 Revision A4 W49L401(T) 7. DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT -0.5 to +4.6 V 0 to +70 C -65 to +150 C D.C. Voltage on Any Pin to Ground Potential except A9 or #RESET -0.5 to VDD +1.0 V Transient Voltage (<20 nS) on Any Pin to Ground Potential -1.0 to VDD +1.0 V -0.5 to 12.5 V Power Supply Voltage to Vss Potential Operating Temperature Storage Temperature Voltage on A9 or #RESET Pin to Ground Potential Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. DC Operating Characteristics (VDD = 3.0 ~ 3.6V, VSS = 0V, TA = 0 to 70 C) PARAMETER VDD Current - Read SYM. ICC LIMITS TEST CONDITIONS #CE = #OE = VIL, #WE = VIH, all DQs open UNIT MIN. TYP. MAX. - 10 20 - 15 25 mA - - 1 mA - 5 50 mA Address inputs = VIL/VIH, at f = 5 MHz VDD Current - Write ICCW #CE = #WE = VIL, #OE = VIH Standby VDD ISB1 #CE = VIH, all DQs open Current (TTL input) Standby VDD Current (CMOS input) Other inputs = VIL/VIH ISB2 #CE = VDD -0.3V, all DQs open Other inputs = VDD -0.3V / VSS A Input Leakage Current ILI VIN = VSS to VDD - - 10 A Output Leakage Current ILO VOUT = VSS to VDD - - 10 A Input Low Voltage VIL - -0.2 - 0.8 V Input High Voltage VIH - 2.0 - VDD +0.3 V Output Low Voltage VOL IOL = 2.1 mA - - 0.45 V Output High Voltage VOH IOH = -0.4 mA 2.4 - - V - 12 - W49L401(T) Power-up Timing TYPICAL UNIT Power-up to Read Operation PARAMETER TPU. READ SYMBOL 200 Power-up to Write Operation TPU. WRITE 10 S mS MAX. UNIT 12 6 pf pf Capacitance (VDD = 3.3V, TA = 25 C, f = 1 MHz) PARAMETER SYMBOL I/O Pin Capacitance Input Capacitance CI/O CIN CONDITIONS VI/O = 0V VIN = 0V 8. AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 0V to 0.9 VDD < 5 nS 1.5V/1.5V 1 TTL Gate and CL = 30 pF AC Test Load and Waveform +3.3V 1.8K D OUT 30 pF (Including Jig and Scope) 1.3K Input 0.9V Output DD 1.5V 1.5V 0V Test Point Test Point - 13 - Publication Release Date: August 16, 2002 Revision A4 W49L401(T) AC Characteristics, continued Read Cycle Timing Parameters (VDD = 3.0 ~ 3.6V, VSS = 0V, TA = 0 to 70 C) PARAMETER 70 nS SYMBOL UNIT MIN. MAX. Read Cycle Time TRC 70 - nS Chip Enable Access Time TCE - 70 nS Address Access Time TAA - 70 nS Output Enable Access Time TOE - 35 nS #CE Low to Active Output TCLZ 0 - nS #OE Low to Active Output TOLZ 0 - nS #CE High to High-Z Output TCHZ - 25 nS #OE High to High-Z Output TOHZ - 25 nS Output Hold from Address Change TOH 0 - nS Note: The parameter of TCLZ, TOLZ, TCHZ, TOHZ are characterized only and is not 100% tested. Write Cycle Timing Parameters PARAMETER SYMBOL MIN. TYP. MAX. UNIT Address Setup Time TAS 10 - - nS Address Hold Time TAH 100 - - nS #WE and #CE Setup Time TCS 10 - - nS #WE and #CE Hold Time TCH 10 - - nS #OE High Setup Time TOES 10 - - nS #OE High Hold Time TOEH 0 - - nS #CE Pulse Width TCP 100 - - nS #WE Pulse Width TWP 100 - - nS #WE High Width TWPH 50 - - nS Data Setup Time TDS 100 - - nS Data Hold Time TDH 10 - - nS Word programming Time TBP - 30 50 S Page Erase Cycle Time TPEC - 25 50 mS Block Erase Cycle Time TBEC - 25 50 mS Chip Erase Cycle Time TEC - 100 200 mS Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL. - 14 - W49L401(T) AC Characteristics, continued Data Polling and Toggle Bit Timing Parameters PARAMETER 70 nS SYM. UNIT MIN. MAX. #OE to Data Polling Output Delay TOEP - 35 nS #CE to Data Polling Output Delay TCEP - 70 nS #WE High to #OE Low for Data Polling TOEHP 100 - nS #OE to Toggle Bit Output Delay TOET - 35 nS #CE to Toggle Bit Output Delay TCET - 70 nS #WE High to #OE Low for Toggle Bit TOEHT 100 - nS SYM. MIN. MAX. UNIT #RESET Pulse Width TRP 500 - nS #RESET High Time Before Read (1) TRH 50 - S Hardware Reset Timing Parameters PARAMETER Note: 1. The parameters are characterized only and is not 100% tested. - 15 - Publication Release Date: August 16, 2002 Revision A4 W49L401(T) 9. TIMING WAVEFORMS Read Cycle Timing Diagram TRC Address A17-0 TCE #CE TOE #OE TOHZ TOLZ VIH #WE TCLZ TOH TCHZ High-Z High-Z DQ15-0 Data Valid Data Valid TAA #WE Controlled Command Write Cycle Timing Diagram TAS TAH Address A17-0 #CE TCS TCH TOES TOEH #OE TWP #WE TWPH TDS DQ15-0 Data Valid TDH - 16 - W49L401(T) Timing Waveforms, continued #CE Controlled Command Write Cycle Timing Diagram TAS TAH Address A17-0 TCPH TCP #CE TOES TOEH #OE #WE TDS DQ15-0 High Z Data Valid TDH Program Cycle Timing Diagram Word Program Cycle Address A17-0 2AAA 5555 XXAA DQ15-0 5555 XX55 Address XXA0 Data-In #CE * #OE * T WPH TBP TWP #WE Word 0 Word 1 Word 2 Word 3 Internal Write Start *Note: It is not allowed to assert read operation(#CE & #OE are both active) during the command sequence. If read command is asserted during the command sequence, then the device will return to read mode (abort write). - 17 - Publication Release Date: August 16, 2002 Revision A4 W49L401(T) Timing Waveforms, continued #DATA Polling Timing Diagram Address A17-0 An An An An #WE TCEP #CE TOEHP #OE TOEP DQ7 X X TBP, TEC, TBEC or TPEC Toggle Bit Timing Diagram Address A17-0 #WE TCET #CE TOET #OE TOEHT DQ6 TBP, TEC,TBEC orTPEC - 18 - X X W49L401(T) Timing Waveforms, continued Boot Block Lockout Enable Timing Diagram Six-word code for Boot Block Lockout Feature Enable Address A17-0 DQ15-0 5555 2AAA XX55 XXAA 5555 5555 XX80 XXAA 2AAA XX55 5555 XX40 #CE #OE TWP 200uS #WE TWPH SW0 SW1 SW23 SW3 SW4 SW5 *Note: It is not allowed to assert read operation(#CE & #OE are both active) during the command sequence. If read command is asserted during the command sequence, then the device will return to read mode(abort write). Chip Erase Timing Diagram Six-word code for 3.3V-only software chip erase Address A17-0 DQ15-0 5555 2AAA XXAA XX55 5555 5555 XX80 XXAA 2AAA XX55 5555 XX10 #CE #OE TWP #WE TEC TWPH SW0 SW1 SW2 SW3 - 19 - SW4 SW5 Internal Erase starts Publication Release Date: August 16, 2002 Revision A4 W49L401(T) Timing Waveforms, continued Block/Page Erase Timing Diagram Six-word code for 3.3V-only software Block/Page Erase Address A17-0 XX555 XX2AA XX555 XX555 XX2AA BA PA DQ15-0 XX55 XXAA XX80 XXAA XX55 XX30 XX50 #CE #OE TWP TBEC or TPEC #WE TWPH SW0 SW1 SW2 SW3 SW5 SW4 Internal Erase starts *Note: It is not allowed to assert read operation(#CE & #OE are both active) during the command sequence. If read command is asserted during the command sequence, then the device will return to read mode(abort write). BA = Block Address; PA = Page Address Ready/#Busy Timing Diagram Address A17-0 An An An An #WE TCEP #CE TOEHP TOES #OE TOEP DQ15-DQ0 PD invalid X X Program/Erase in Progress tRB tBUSY RY/#BY - 20 - W49L401(T) Timing Waveforms, continued Reset Timing Diagram #CE #OE TRH #RESET TRP - 21 - Publication Release Date: August 16, 2002 Revision A4 W49L401(T) 10. ORDERING INFORMATION ACCESS TIME (nS) OPERATING VOLTAGE (V) BOOT BLOCK LOCATION W49L401S-70B 70 3.0 ~ 3.6 BOTTOM 44-pin SOP W49L401T-70B 70 3.0 ~ 3.6 BOTTOM 48-pin TSOP (12 mm x 20 mm) W49L401TS70B 70 3.0 ~ 3.6 TOP 44-pin SOP W49L401TT70B 70 3.0 ~ 3.6 TOP 48-pin TSOP (12 mm x 20 mm) PART NO. PACKAGE Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. 11. HOW TO READ THE TOP MARKING Example: The top marking of 48-pin TSOP W49L401T-70B W49L401T70B 2138977A-A12 149OBAA st 1 line: winbond logo nd 2 line: the part number: W49L401T-70B rd 3 line: the lot number th 4 line: the tracking code: 149 O B AA 149: Packages made in 0' 1, week 49 O: Assembly house ID: A means ASE, O means OSE, ... etc. B: IC revision; A means version A, B means version B, ... etc. AA: Process code - 22 - W49L401(T) 12. PACKAGE DIMENSIONS 48-pin TSOP (12 mm x 20 mm) 1 48 Dimension in mm Symbol MIN. e NOM. b c A1 0.05 A2 0.95 D 18.3 HD 19.8 E 11.9 b c 0.10 0.002 0.037 0.039 0.720 0.724 0.041 0.728 20.0 20.2 0.780 0.787 0.795 12.0 12.1 0.468 0.472 0.476 0.17 0.50 A1 L1 0.004 0.009 0.011 0.008 0.020 0.020 0.024 0.031 0.70 0 0.028 0.004 0.10 Y 0.007 0.60 0.80 L1 Y A L 0.27 0.21 0.22 0.50 L A2 MAX. 0.047 1.05 18.5 1.00 18.4 e D HD NOM. 1.20 A E Dimension in Inches MIN. MAX. 0 5 5 44-pin SOP 44 23 L L1 Symbol Dimension in mm MIN. NOM. 1 c 22 D e b A1 0.10 A2 b 2.26 MAX. 0.118 0.004 2.82 0.089 0.50 0.014 0.111 0.016 0.020 c 0.10 0.15 0.21 0.004 0.006 0.008 D 28.07 28.19 28.32 1.105 1.110 1.115 E 13.10 13.30 13.50 0.516 0.524 0.531 HE 15.80 16.00 16.20 0.622 0.630 0.638 e 1.12 1.27 1.42 0.044 0.050 0.056 L 0.60 0.80 1.35 1.00 0.024 0.032 0.040 - 23 - NOM. 0.41 Y A1 MIN. 0.36 L1 A2 A Y SEATING PLANE Dimension in Inches 3.00 A E HE MAX. 0.053 0.10 0 7 0.004 0 7 Publication Release Date: August 16, 2002 Revision A4 W49L401(T) 13. VERSION HISTORY VERSION DATE PAGE A1 Apr. 2001 - A2 July 2001 18 A3 January 2, 2002 1, 3, 6, 15 18 17 1, 18, 19, 26 26 DESCRIPTION Initial Issued Change TRH from 50 nS to 10 S Delete the description of Auto-Power Saving Change TRH from 10 S to 30 S (min.) Change TEC from 200/1000 to 100/200 mS (typ./max.) Change TPEC, TPBC from 50/200 to 25/50 mS (typ./max.) Delete read access time of 55 nS Add HOW TO READ THE TOP MARKING 9, 10, 11, 12, 13 Delete old flow chart and add embedded algorithm A4 August 16, 2002 4 Modify VDD Power Up/Down Detection in Hardware Data Protection 21 Modify Program Cycle Timing Diagram 9 - 13 23 Modify Flow charts Modify Reset Timing Diagram Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No.480, Rueiguang Rd., Neihu Chiu, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 24 -