Features
•Floating channel designed for bootstrap operation
Fully operational to +500V
T olerant to negative transient voltage
dV/dt immune
•Gate drive supply range from 12 to 18V
•Undervoltage lockout
•Current detection and limiting loop to limit driven
power transistor current
•Error lead indicates fault conditions and programs
shutdown time
•Output in phase with input
•2.5V, 5V and 15V input logic compatible
Description
The IR2125(S) is a high voltage, high speed power
MOSFET and IGBT driver with over-current limiting
protection circuitry. Proprietar y HVIC and latch im-
mune CMOS technologies enable ruggedized mono-
lithic construction. Logic inputs are compatible with
standard CMOS or LSTTL outputs, down to 2.5V
logic. The output driver features a high pulse current
buffer stage designed for minimum driver cross-
CURRENT LIMITING SINGLE CHANNEL DRIVER
Product Summary
VOFFSET 500V max.
IO+ /- 1A / 2A
VOUT 12 - 18V
VCSth 230 mV
ton/off (typ.) 150 & 150 ns
Packages
Typical Connection
conduction. The protection circuitry detects over-current in the driven power transistor and limits the gate drive volt-
age. Cycle by cycle shutdown is programmed by an external capacitor which directly controls the time interval
between detection of the over-current limiting conditions and latched shutdown. The floating channel can be used to
drive an N-channel power MOSFET or IGBT in the high or low side configuration which operates up to 500 volts.
VCC VB
CS
OUT
VS
COM
IN
ERR
VCC
IN
TO
LOAD
up to 500V
IR2125(S)
Data Sheet No. PD60017-M
www.irf.com 1
(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical
connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
8-Lead PDIP 16-Lead SOIC
(Wide Body)
IR2125(S)
2www.irf.com
Symbol Definition Min. Max. Units
VBHigh Side Floating Supply Voltage -0.3 525
VSHigh Side Floating Offset Voltage VB - 25 VB + 0.3
VHO High Side Floating Output Voltage VS - 0.3 VB + 0.3
VCC Logic Supply Voltage -0.3 25 V
VIN Logic Input Voltage -0.3 VCC + 0.3
VERR Error Signal Voltage -0.3 VCC + 0.3
VCS Current Sense Voltage VS - 0.3 VB + 0.3
dVs/dt Allowable Offset Supply Voltage Transient — 50 V/ns
PDPackage Power Dissipation @ TA ≤ +25°C (8 lead PDIP) — 1.0
(16 lead SOIC) — 1.25
RthJA Thermal Resistance, Junction to Ambient (8 lead PDIP) — 125
(16lLead SOIC) — 100
TJJunction Temperature — 150
TSStorage Temperature -55 150
TLLead Temperature (Soldering, 10 seconds) — 300
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured
under board mounted and still air conditions.
Symbol Definition Min. Max. Units
VBHigh Side Floating Supply Voltage VS + 12 VS + 18
VSHigh Side Floating Offset Voltage Note 1 500
VHO High Side Floating Output Voltage VSVB
VCC Logic Supply V oltage 0 18
VIN Logic Input Voltage 0 VCC
VERR Error Signal Voltage 0 VCC
VCS Current Sense Signal Voltage VSVB
TAAmbient Temperature -40 125 °C
Note 1: Logic operational for VS of -5 to +500V. Logic state held f or VS of -5V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the
recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential.
W
°C/W
°C
V
www.irf.com 3
IR2125(S)
Symbol Definition Figure Min . Typ. Max. Units Test Conditions
VIH Logic “1” Input Voltage 14 2.2 — —
VIL Logic “0” Input Voltage 15 — — 0.8
VCSTH+ CS Input Positiv e Going Threshold 1 6 15 0 2 30 3 20
VCSTH- CS Input Negative Going Threshold 1 7 1 30 2 00 2 60
VOH High Lev el Output Voltage, VBIAS - VO18 — — 100 IO = 0A
VOL Low Lev el Output V oltage, VO19 — — 100 IO = 0A
ILK Offset Supply Leakage Current 2 0 — — 5 0 VB = VS = 500V
IQBS Quiescent VBS Supply Current 2 1 — 4 00 1000 VIN = VCS = 0V or 5V
IQCC Quiescent VCC Supply Current 2 2 — 7 0 0 1200 VIN = VCS = 0V or 5V
IIN+ Logic “1” Input Bias Current 2 3 — 4.5 1 0 µA VIN = 5V
IIN- Logic “0” Input Bias Current 2 4 — — 1.0 VIN = 0V
ICS+ “High” CS Bias Current 2 5 — 4.5 1 0 VCS = 3V
ICS- “Low” CS Bias Current 26 — — 1.0 VCS = 0V
VBSUV+ VBS Supply Undervoltage P ositiv e Going 2 7 8.5 9.2 10.0
Threshold
VBSUV- VBS Supply Undervoltage Negative Going 28 7.7 8.3 9.0
Threshold
VCCUV+ VCC Supply Undervoltage P ositive Going 2 9 8.3 8 .9 9.6
Threshold
VCCUV- VCC Supply Undervoltage Negative Going 3 0 7.3 8.0 8.7
Threshold
IERR ERR Timing Charge Current 31 65 1 00 13 0 VIN = 5V, VCS = 3V
ERR < VERR+
IERR+ ERR Pull-Up Current 32 8.0 15 — VIN = 5V, VCS = 3V
ERR > VERR+
IERR- ERR Pull-Down Current 33 16 30 — VIN = 0V
IO+ Output High Short Circuit Pulsed Current 3 4 1.0 1 .6 — VO = 0V, VIN = 5V
PW ≤ 10 µs
IO- Output Low Short Circuit Pulsed Current 3 5 2.0 3 .3 — VO = 15V, VIN = 0V
PW ≤ 10 µs
V
mV
mA
V
µA
A
Static Electrical Characteristics
VBIAS (VCC, VBS) = 15V and TA = 25°C unless otherwise specified. The V IN, VTH and IIN parameters are ref erenced to
COM. The VO and IO parameters are referenced to VS.
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15V, CL = 3300 pF and T A = 25°C unless otherwise specified. The dynamic electrical characteristics
are measured using the test circuit shown in Figures 3 through 6.
Symbol Definition Figure Min. Typ. Max. Units Test Conditions
ton Turn-On Propagation Delay 7 — 15 0 200 VIN = 0 & 5V
VS = 0 to 600V
toff Turn-Off Propagation Delay 8 — 1 50 190
tsd ERR Shutdown Propagation Delay 9 — 1.7 2.2 µs
trTurn-On Rise Time 1 0 — 43 60
tfTurn-Off Fall Time 1 1 — 2 6 3 5
tcs CS Shutdown Propagation Delay 1 2 — 0.7 1.2
terr CS to ERR Pull-Up Propagation Delay 1 3 — 9.0 12 CERR = 270 pF
ns
µs
ns
IR2125(S)
4www.irf.com
Lead Definitions
Symbol Description
VCC Logic and gate driv e supply
I N Logic input for gate dr iver output (HO), in phase with HO
ERR Serves multiple functions; status reporting, linear mode timing and cycle by cycle logic
shutdown
COM Logic ground
VBHigh side floating supply
HO High side gate drive output
VSHigh side floating supply return
CS Current sense input to current sense comparator
Functional Block Diagram
Lead Assignments
8 Lead PDIP
IR2125 16 Lead SOIC (Wide Body)
IR2125S
DOWN
SHIFTERS
QR
UV
DETECT
ERROR
TIMING
PULSE
GEN
UV
DETECT
PULSE
FILTER
PRE
DRIVER
PULSE
GEN
500 ns
BLANK
COMPARATOR
BUFFER
0.23V
HV
LEVEL
VB
HO
VS
CS
R
S
RQ
VCC
IN
UP
SHIFTERS
COM
ERR
LATCHED
SHUTDOWN
1.8V
1.8V
AMPLIFER
-
+
PULSE
FILTER
VB
S
SHIFT
HV
LEVEL
SHIFT
Part Number
1
2
7
6
5
4
3
8
16
15
14
13
12
11
10
9
Vcc
IN
ERR
COM VS
CS
HO
VB
VCC
IN
ERR
COM
VB
HO
CS
VS
1
2
3
4
8
7
6
5
www.irf.com 5
IR2125(S)
tsd
HV=10 to 600V
IR2125(S)
6www.irf.com
0.00
1.00
2.00
3.00
4.00
5.00
-50 -25 0 25 50 75 100 125
Temperature (°C)
ERR to Output Shutdown Delay Time (µs)
Max.
T
y
p.
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
Temperature (°C)
Turn-Off Delay Time (ns)
Max.
T
y
p.
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
Temperature (°C)
Turn-On Delay Time (ns)
Max.
T
y
p.
Figure 8A. Turn-Off Time vs. Temperature Figure 8B. Turn-Off Time vs. Voltage
Figure 7A. Turn-On Time vs. Temperature Figure 7B. Turn-On Time vs. Voltage
Figure 9B. ERR to Output Shutdown vs. Voltage
Figure 9A. ERR to Output Shutdown vs. Temperature
0
100
200
300
400
500
10 12 14 16 18 20
VBIAS Supply Volt a
g
e (V)
Turn-On Time (ns)
Max.
T
y
p.
0
100
200
300
400
500
10 12 14 16 18 20
VBIAS Supply Volta
g
e (V)
Turn-Off Time (ns)
Max.
T
y
p.
0.00
1.00
2.00
3.00
4.00
5.00
10 12 14 16 18 20
VBIAS Supply Volta
g
e (V)
ERR to Output Shutdown Delay Time (µs)
Max.
T
y
p.
www.irf.com 7
IR2125(S)
0.00
0.40
0.80
1.20
1.60
2.00
-50 -25 0 25 50 75 100 125
Temperature (°C)
CS to Output Shutdown Delay Time (µs)
Max.
T
y
p.
0
20
40
60
80
100
-50 -25 0 25 50 75 100 125
Temperature (°C)
Turn-On Rise Time (ns)
Max.
T
y
p.
Figure 11A. Turn-Off Fall Time vs. Temperature Figure 11B. Turn-Off Fall Time vs. Voltag e
Figure 10A. Turn-On Rise Time vs. Temperature Figure 10B. Turn-On Rise Time vs. Voltage
Figure 12A. CS to Output Shutdown vs. Temperature Figure 12B. CS to Output Shutdown vs. Voltage
0
20
40
60
80
100
10 12 14 16 18 20
VBIAS Supply Volt a
g
e (V)
Turn-On Rise Time (ns)
Max.
T
y
p.
0
20
40
60
80
100
-50 -25 0 25 50 75 100 125
Temperature (°C)
Turn-Off Fall Time (ns)
Max.
T
y
p.
0
20
40
60
80
100
10 12 14 16 18 20
VBIAS Supply Volta
g
e (V)
Turn-Off Fall Time (ns)
Max.
T
y
p.
0.00
0.40
0.80
1.20
1.60
2.00
10 12 14 16 18 20
VBIAS Supply Volta
g
e (V)
CS to Output Shutdown Delay Time (µs)
Max.
T
y
p.
IR2125(S)
8www.irf.com
0.00
1.00
2.00
3.00
4.00
5.00
-50 -25 0 25 50 75 100 125
Temperature (°C)
Logic "1" Input Threshold (V)
Min.
Figure 14A. Logic “1” Input Threshold vs.
Temperature Figure 14B. Logic “1” Input Threshold vs. Voltage
Figure 13B. CS to ERR Pull-Up vs. VoltageFigure 13A. CS to ERR Pull-Up vs. Temperature
Figure 15A. Logic “0” Input Threshold vs.
Temperature Figure 15B. Logic “0” Input Threshold vs. Voltage
0.0
4.0
8.0
12.0
16.0
20.0
10 12 14 16 18 20
VBIAS Supply Volta
g
e (V)
CS to ERR Pull-Up Delay Time (µs)
Max.
Typ.
0.0
4.0
8.0
12.0
16.0
20.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
CS to ERR Pull-Up Delay Time (µs)
Max.
T
y
p.
0.00
1.00
2.00
3.00
4.00
5.00
10 12 14 16 18 20
VCC Lo
g
ic Supply Volta
g
e (V)
Logic "1" Input Threshold (V)
Min.
0.00
1.00
2.00
3.00
4.00
5.00
10 12 14 16 18 20
VCC Lo
g
ic Supply Volta
g
e (V)
Logic "0" Input Threshold (V)
Max.
0.00
1.00
2.00
3.00
4.00
5.00
-50 -25 0 25 50 75 100 125
Temperature (°C)
Logic "0" Input Threshold (V)
Max.
www.irf.com 9
IR2125(S)
0.00
0.20
0.40
0.60
0.80
1.00
-50 -25 0 25 50 75 100 125
Temperature (°C)
High Level Output Voltage (V)
Max.
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
Temperature (°C)
CS Input Positive Going Threshold (mV)
Min.
T
y
p.
Max.
Figure 17A. CS Input Threshold (-) vs. Temperature Figure 17B. CS Input Threshold (-) vs. Voltage
Figure 16A. CS Input Threshold (+) vs.
Temperature Figure 16B. CS Input Threshold (+) vs. Voltage
Figure 18A. High Level Output vs. Temperature Figure 18B. High Level Output vs. Voltage
0
100
200
300
400
500
10 12 14 16 18 20
VBS Floatin
g
Supply Volta
g
e (V)
CS Input Positive Going Threshold (mV)
Min.
T
y
p.
Max.
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
Temperature (°C)
CS Input Negative Going Threshold (mV)
Max.
T
y
p.
Min.
0
100
200
300
400
500
10 12 14 16 18 20
VBS Floatin
g
Supply Volta
g
e (V)
CS Input Negative Going Threshold (mV)
Min.
T
y
p.
Max.
0.00
0.20
0.40
0.60
0.80
1.00
10 12 14 16 18 20
VBS Floatin
g
Supply Volta
g
e (V)
High Level Output Voltage (V)
Max.
IR2125(S)
10 www.irf.com
0.00
0.40
0.80
1.20
1.60
2.00
-50 -25 0 25 50 75 100 125
Temperature (°C)
VBS Supply Current (mA)
Max.
T
y
p.
0
100
200
300
400
500
-50 -25 0 25 50 75 100 125
Temperature (°C)
Offset Supply Leakage Current (µA)
Max.
0.00
0.20
0.40
0.60
0.80
1.00
-50 -25 0 25 50 75 100 125
Temperature (°C)
Low Level Output Voltage (V)
Max.
Figure 20A. Offset Supply Current vs. Temperature Figure 20B. Offset Supply Current vs. Voltage
Figure 19A. Low Level Output vs. Temperature Figure 19B. Low Level Output vs. Voltage
Figure 21A. VBS Supply Current vs. Temperature Figure 21B. VBS Supply Current vs. Voltage
0.00
0.20
0.40
0.60
0.80
1.00
10 12 14 16 18 20
VBS Floatin
g
Supply Volta
g
e (V)
Low Level Output Voltage (V)
Max.
0
100
200
300
400
500
0 100 200 300 400 500
VB Boost Volta
g
e (V)
Offset Supply Leakage Current (µA)
Max.
0.00
0.40
0.80
1.20
1.60
2.00
10 12 14 16 18 20
VBS Floatin
g
Supply Volta
g
e (V)
VBS Supply Current (mA)
Max.
T
y
p.
www.irf.com 11
IR2125(S)
0.00
1.00
2.00
3.00
4.00
5.00
-50 -25 0 25 50 75 100 125
Temperature (°C)
Logic "0" Input Bias Current (µA)
Max.
0
5
10
15
20
25
-50 -25 0 25 50 75 100 125
Temperature (°C)
Logic "1" Input Bias Current (µA)
Max.
T
y
p.
0.00
0.40
0.80
1.20
1.60
2.00
-50 -25 0 25 50 75 100 125
Temperature (°C)
VCC Supply Current (mA)
Max.
T
y
p.
Figure 23A. Logic “1” Input Current vs.
Temperature Figure 23B. Logic “1” Input Current vs. Voltage
Figure 22A. VCC Supply Current vs. Temperature Figure 22B. VCC Supply Current vs. Voltage
Figure 24A. Logic “0” Input Current vs.
Temperature Figure 24B. Logic “0” Input Current vs. Voltage
0.00
0.40
0.80
1.20
1.60
2.00
10 12 14 16 18 20
VCC Lo
g
ic Supply Volta
g
e (V)
VCC Supply Current (mA)
Max.
T
y
p.
0
5
10
15
20
25
10 12 14 16 18 20
VCC Lo
g
ic Supply Volta
g
e (V)
Logic "1" Input Bias Current (µA)
Max.
T
y
p.
0.00
1.00
2.00
3.00
4.00
5.00
10 12 14 16 18 20
VCC Lo
g
ic Supply Volta
g
e (V)
Logic "0" Input Bias Current (µA)
Max.
IR2125(S)
12 www.irf.com
6.0
7.0
8.0
9.0
10.0
11.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
VBS Undervoltage Lockout + (V)
Max.
T
y
p.
Min.
0.00
1.00
2.00
3.00
4.00
5.00
-50 -25 0 25 50 75 100 125
Temperature (°C)
"Low" CS Bias Current (µA)
Max.
0.0
5.0
10.0
15.0
20.0
25.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
"High" CS Bias Current (µA)
Max.
T
y
p.
Figure 26A. “Low” CS Bias Current vs. Temperature Figure 26B. “Low” CS Bias Current vs. Voltage
Figure 25A. “High” CS Bias Current vs.
Temperature Figure 25B. “High” CS Bias Current vs. Voltage
Figure 27. VBS Undervoltage (+) vs. Temperature Figure 28. VBS Undervoltage (-) vs. Temperature
0.0
5.0
10.0
15.0
20.0
25.0
10 12 14 16 18 20
VBS Floatin
g
Supply Volta
g
e (V)
"High" CS Bias Current (µA)
Max.
T
y
p.
0.00
1.00
2.00
3.00
4.00
5.00
10 12 14 16 18 20
VBS Floatin
g
Supply Volta
g
e (V)
"Low" CS Bias Current (µA)
Max.
6.0
7.0
8.0
9.0
10.0
11.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
VBS Undervoltage Lockout - (V)
Max.
T
y
p.
Min.
www.irf.com 13
IR2125(S)
0
50
100
150
200
250
-50 -25 0 25 50 75 100 125
Temperature (°C)
ERR Timing Charge Current (µA)
Max.
T
y
p.
Min.
6.0
7.0
8.0
9.0
10.0
11.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
VCC Undervoltage Lockout + (V)
Max.
T
y
p.
Min.
Figure 31A. ERR Timing Charge Current vs.
Temperature Figure 31B. ERR Timing Charge Current vs.
Voltage
Figure 29. VCC Undervoltage (+) vs. Temperature Figure 30. VCC Undervoltage (-) vs. Temperature
Figure 32A. ERR Pull-Up Current vs. Temperature Figure 32B. ERR Pull-Up Current vs. Voltage
6.0
7.0
8.0
9.0
10.0
11.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
VCC Undervoltage Lockout - (V)
Max.
T
y
p.
Min.
0
50
100
150
200
250
10 12 14 16 18 20
VCC Lo
g
ic Supply Volta
g
e (V)
ERR Timing Charge Current (µA)
Min.
T
y
p.
Max.
0.0
5.0
10.0
15.0
20.0
25.0
-50 -25 0 25 50 75 100 125
Temperature (°C)
ERR Pull-Up Current (mA)
T
p.
Min.
0.0
5.0
10.0
15.0
20.0
25.0
10 12 14 16 18 20
VCC Lo
g
ic Su pply Volt a
g
e (V)
ERR Pull-Up Current (mA)
Min.
T
p.
IR2125(S)
14 www.irf.com
0.00
1.00
2.00
3.00
4.00
5.00
-50 -25 0 25 50 75 100 125
Temperature (°C)
Output Sink Current (A)
T
y
p.
Min.
0.00
0.50
1.00
1.50
2.00
2.50
-50 -25 0 25 50 75 100 125
Temperature (°C)
Output Source Current (A)
T
y
p.
Min.
0
10
20
30
40
50
-50-250 255075100125
Te m per ature (°C)
ERR Pull-Down Current (mA)
T
p.
Min.
Figure 34A. Output Source Current vs.
Temperature Figure 34B. Output Source Current vs. Voltage
Figure 33A. ERR Pull-Down Current vs.Temperature Figure 33B. ERR Pull-Down Current vs. Voltage
Figure 35A. Output Sink Current vs.Temperature Figure 35B. Output Sink Current vs. Voltage
0
10
20
30
40
50
10 12 14 16 18 20
VCC Logic Supply Voltage (V)
ERR Pull-Down Current (mA)
Max.
Typ.
0.00
0.50
1.00
1.50
2.00
2.50
10 12 14 16 18 20
VBS Floatin
g
Supply Volta
g
e (V)
Output Source Current (A)
Min.
T
y
p.
0.00
1.00
2.00
3.00
4.00
5.00
10 12 14 16 18 20
VBS Floatin
g
Supply Volta
g
e (V)
Output Sink Current (A)
Min.
T
y
p.
www.irf.com 15
IR2125(S)
Figure 37. Maximum VS Negative Offset vs. Supply
Voltage
-15.00
-12.00
-9.00
-6.00
-3.00
0.00
10 12 14 16 18 20
VBS Floatin
g
Supply Volta
g
e (V)
VS Offset Supply Voltage (V)
T
y
p.
Figure 36A. T urn-On Time vs. Input Voltage Figure 36B. T urn-Off Time vs. Input Voltage
0
50
100
150
200
250
300
02468101214161820
Input Voltage (V)
Turn-On Delay Time (ns)
0
50
100
150
200
250
300
0 2 4 6 8 10121416182
0
Max.
T
y
p.
Input Voltage (V)
Turn-Off Delay Time (ns)
IR2125(S)
16 www.irf.com
WORLD HEADQUARTERS: 233 Kansas Street, El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 5/15/2001
01-6014
01-3003 01 (MS-001AB)
8-Lead PDIP
Case outlines
01-6027
01-0021 11 (MS-012AA)
8-Lead SOIC
87
5
65
D B
E
A
e
6X
H
0.25 [.010] A
6
4312
4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.
NOTES:
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994.
2. CONTROLLING DIMENSION: MILLIMETER
3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].
7
K x 4 5°
8X L 8X c
y
FOOTPRINT
8X 0. 72 [.028]
6.46 [.255]
3X 1. 27 [.050] 8X 1. 78 [.070]
5 DIMENS ION DOES NOT INCLUDE MOLD PROTRUSIONS.
6 DIMENS ION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].
7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO
A SUBSTRATE.
MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].
0.25 [.010] C A B
e1 A
A1
8X b
C
0.10 [.004]
e1
D
E
y
b
A
A1
H
K
L
.189
.1497
0°
.013
.050 BASIC
.0532
.0040
.2284
.0099
.016
.1968
.1574
8°
.020
.0688
.0098
.2440
.0196
.050
4.80
3.80
0.33
1.35
0.10
5.80
0.25
0.40
0°
1.27 BASIC
5.00
4.00
0.51
1.75
0.25
6.20
0.50
1.27
MIN MAX MILLIMETERSINCHES MIN MAX
DIM
8°
e
c .0075 .0098 0.19 0.25
.025 BASIC 0.635 BASIC