General Description
The MAX4850/MAX4850H/MAX4852/MAX4852H family
of dual SPDT (single-pole/double-throw) switches oper-
ate from a single +2V to +5.5V supply and can handle
signals greater than the supply rail. These switches fea-
ture low 3.5Ωor 3.5Ω/7Ωon-resistance with low on-
capacitance, making them ideal for switching audio
and data signals.
The MAX4850/MAX4850H are configured with two
SPDT switches and feature two comparators for head-
phone detection or mute/send key functions. The
MAX4852 has two SPDT switches with no comparators
for low 1µA supply current.
For over-rail applications, these devices offer either the
pass-through or high-impedance option. For the
MAX4850/MAX4852, the signal (up to 5.5V) passes
through the switch without distortion even when the posi-
tive supply rail is exceeded. For the MAX4850H/
MAX4852H, the switch input becomes high impedance
when the input signal exceeds the supply rail.
The MAX4850/MAX4850H/MAX4852/MAX4852H are
available in the space-saving (3mm x 3mm), 16-pin
TQFN package and operate over the extended temper-
ature range of -40°C to +85°C.
Applications
USB Switching
Audio-Signal Routing
Cellular Phones
Notebook Computers
PDAs and Other Handheld Devices
Features
USB 2.0 Full Speed (12MB) and USB 1.1 Signal
Switching Compliant
Switch Signals Greater than VCC
0.1ns Differential Skew
3.5Ω/7ΩOn-Resistance
135MHz -3dB Bandwidth
+2V to +5.5V Supply Range
1.8V Logic Compatible
Low Supply Current
1µA (MAX4852)
5µA (MAX4850)
10µA (MAX4850H/MAX4852H)
Available in a Space-Saving (3mm x 3mm),
16-Pin TQFN Package
MAX4850/MAX4850H/MAX4852/MAX4852H
Dual SPDT Analog Switches with
Over-Rail Signal Handling
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
VCC
3
MAX4850
MAX4850H
NC1
NO1
NC2
NO2
COUT2
COM1
IN1
IN2
COM2
CIN2
VCC
3
COUT1
CIN1
MAX4852
MAX4852H
NC1
NO1
NC2
NO2
COM1
IN1
IN2
COM2
MAX4850_
MAX4852_
IN_ NO_ NC_
0 OFF ON
1 ON OFF
SWITCHES SHOWN FOR
LOGIC 0 INPUT
3.5Ω
3.5Ω
7Ω
3.5Ω
3.5Ω
7Ω
Block Diagrams/Truth Table
19-3375; Rev 0; 7/04
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
*EP = Exposed paddle.
PART TEMP RANGE PIN-PACKAGE TOP
MARK
MAX4850ETE -40°C to +85°C 16 TQFN-EP* ABU
MAX4850HETE -40°C to +85°C 16 TQFN-EP* ABV
MAX4852ETE -40°C to +85°C 16 TQFN-EP* ABZ
MAX4852HETE -40°C to +85°C 16 TQFN-EP* ACA
Pin Configurations and Selector Guide appear at end of
data sheet.
ABRIDGED DATA SHEET
Detailed Description
The MAX4850/MAX4850H/MAX4852/MAX4852H are low
on-resistance, low-voltage, analog switches that operate
from a +2V to +5.5V single supply and are fully specified
for nominal 3.0V applications. These devices feature
over-rail signal capability that allows signals up to 5.5V
with supply voltages down to 2.0V. These devices are
configured as dual SPDT switches.
These switches have low 50pF on-channel capacitance,
which allows for 12Mbps switching of the data signals for
USB 2.0 full speed/1.1 applications. The MAX485_ _ are
designed to switch D+ and D- USB signals with a guaran-
teed skew of less than 1ns (see Figure 1), as measured
from 50% of the input signal to 50% of the output signal.
The MAX4850_ feature a comparator that can be used
for headphone or mute detection. The comparator
threshold is internally generated to be approximately 1/3
of VCC.
Applications Information
Digital Control Inputs
The logic inputs (IN_) accept up to +5.5V even if the
supply voltages are below this level. For example, with a
+3.3V VCC supply, IN_ can be driven low to GND and
high to +5.5V, allowing for mixing of logic levels in a
system. Driving IN_ rail-to-rail minimizes power con-
sumption. For a +2V supply voltage, the logic thresholds
are 0.5V (low) and 1.4V (high); for a +5V supply voltage,
the logic thresholds are 0.8V (low) and 1.8V (high).
Analog Signal Levels
The on-resistance of these switches changes very little
for analog input signals across the entire supply volt-
age range (see Typical Operating Characteristics). The
switches are bidirectional, so NO_, NC_, and COM_
can be either inputs or outputs.
Comparator
The positive terminal of the comparator is internally set to
VCC/3. When the negative terminal (CIN_) is below the
threshold (VCC/3), the comparator output (COUT_) goes
high. When CIN_ rises above VCC/3, COUT_ goes low.
The comparator threshold allows for detection of head-
phones since headphone audio signals are typically
biased to VCC/2.
Power-Supply Sequencing
Caution: Do not exceed the absolute maximum ratings
because stresses beyond the listed ratings may cause
permanent damage to the device.
Proper power-supply sequencing is recommended for
all CMOS devices. Always apply VCC before applying
analog signals, especially if the analog signal is not
current-limited.
MAX4850/MAX4850H/MAX4852/MAX4852H
Dual SPDT Analog Switches with
Over-Rail Signal Handling
______________________________________________________________________________________ 11
ABRIDGED DATA SHEET
MAX4850/MAX4850H/MAX4852/MAX4852H
Dual SPDT Analog Switches with
Over-Rail Signal Handling
12 ______________________________________________________________________________________
Test Circuits/Timing Diagrams
tR < 20ns
tF < 20ns
50%
LOGIC
INPUT
RL
COM_
GND
IN_
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
VOUT = VNO ( RL )
RL + RON
VNO tOFF
0V
NO_
0.9 x V0UT 0.9 x VOUT
tON
VOUT
SWITCH
OUTPUT
LOGIC
INPUT
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
VCC
CL
VCC
VOUT
MAX4850_
MAX4852_
VCC
0V
SWITCH
INPUT
NORMAL MODE NORMAL MODE
HIGH-Z MODE
VCC + 0.5V
tHIZ
tHIZB
Figure 1. Switching Time
tskew_i
90%
50%
10%
90%
50%
10%
tfi
INPUT A
INPUT A-
tri
tskew_o
90%
50%
10%
90%
50%
10%
tfo
OUTPUT B
OUTPUT B-
tro
B-
CL
A-
Rs
AB
CL
TxD+
TxD-
Rs
Rs = 39Ω
CL = 50pF
DELAY DUE TO SWITCH FOR RISING INPUT AND RISING OUTPUT SIGNALS.
DELAY DUE TO SWITCH FOR FALLING INPUT AND FALLING OUTPUT SIGNALS.
CHANGE IN SKEW THROUGH THE SWITCH FOR OUTPUT SIGNALS.
CHANGE IN SKEW THROUGH THE SWITCH FOR INPUT SIGNALS.
|tskew_i|
|tskew_o|
|tfo - tfi|
|tro - tri|
Figure 2. Input/Output Skew Timing Diagram
ABRIDGED DATA SHEET
MAX4850/MAX4850H/MAX4852/MAX4852H
Dual SPDT Analog Switches with
Over-Rail Signal Handling
______________________________________________________________________________________ 13
50%
VCC
0V
LOGIC
INPUT
VOUT 0.9 x VOUT
tBBM
LOGIC
INPUT
RL
GND
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO_
IN_
NC_ VOUT
VCC
VCC
CL
VN_ COM_
MAX4850_
MAX4852_
Figure 3. Break-Before-Make Interval
VGEN GND
COM_
CL
VOUT
VCC VOUT
IN
OFF ON OFF
ΔVOUT
Q = (ΔVOUT)(CL)
NC_
LOGIC-INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
OFF ON OFF
IN
VIL TO VIH
VCC
RGEN
IN_
MAX4850_
MAX4852_
OR NO_
Figure 4. Charge Injection
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
OFF-ISOLATION IS MEASURED BETWEEN COM_ AND "OFF", NO_ OR NC_ TERMINAL ON EACH SWITCH.
ON-LOSS IS MEASURED BETWEEN COM_ AND "ON", NO_ OR NC_ TERMINAL ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
+5V
VOUT
VCC
IN_
NC1
COM1
NO1*
VIN
MAX4850_
MAX4852_
OFF-ISOLATION = 20log VOUT
VIN
ON-LOSS = 20log VOUT
VIN
CROSSTALK = 20log VOUT
VIN
NETWORK
ANALYZER
50Ω
50Ω50Ω
50Ω
MEAS REF
10nF
0V OR VCC
50ΩGND
*FOR CROSSTALK THIS PIN IS NO2.
NC2 AND COM2 ARE OPEN.
Figure 5. On-Loss, Off-Isolation, and Crosstalk
ABRIDGED DATA SHEET
MAX4850/MAX4850H/MAX4852/MAX4852H
Dual SPDT Analog Switches with
Over-Rail Signal Handling
14 ______________________________________________________________________________________
CAPACITANCE
METER NC_ OR
NO_
COM_
GND
IN VIL OR VIH
10nF VCC
f = 1MHz
VCC
MAX4850_
MAX4852_
Figure 6. Channel Off-/On-Capacitance
MAX4850_
VCC
3
VTH + 100mV
VTH - 100mV
VOUT
0V
tCOMP tCOMP
50%
50%
50%
50%
tR < 20ns
tF < 20ns
VCC
VCC
GND
VCOUT_
CIN_
COUT_
VCIN_
NO_
VTH = VCC/3
COMPARATOR
INPUT (VCIN_)
COMPARATOR
OUTPUT (VCOUT_)
Figure 7. Comparator Switching Time
ABRIDGED DATA SHEET
MAX4850/MAX4850H/MAX4852/MAX4852H
Dual SPDT Analog Switches with
Over-Rail Signal Handling
______________________________________________________________________________________ 15
TOP VIEW
16
1
2
3
4
12
11
10
9
15 14 13
5678
NC1
IN1
VCC
COUT2
NO2
COUT1
COM2
IN2
CIN1
CIN2
COM1
NO1
GND
NC2
N.C.
N.C.
MAX4850
MAX4850H
16
1
2
3
4
12
11
10
9
15 14 13
5678
NC1
IN1
VCC
N.C.
NO2
N.C.
COM2
IN2
N.C.
N.C.
COM1
NO1
GND
NC2
N.C.
N.C.
MAX4852
MAX4852H
THIN QFN THIN QFN
CONNECT EXPOSED PADDLE TO GROUND.
Pin Configurations
PART
RON
NC_/NO_
(Ω)
COMPARATORS OVER-RAIL
HANDLING
MAX4850 3.5/3.5 2
Input signal
passes through
the switch
MAX4850H 3.5/3.5 2 High-impedance
switch input
MAX4852 3.5/7
Input signal
passes through
the switch
MAX4852H 3.5/7 High-impedance
switch input
Selector Guide
Chip Information
TRANSISTOR COUNT: 735
PROCESS: CMOS
DATA
SOURCE
AUDIO
SOURCE VCC
3
MUTE
BUTTON
VCC
MAX4850_
OUT+
OUT-
OUT+
OUT-
NC1
NO1
NC2
NO2
COUT
COM1
IN1
IN2
COM2
CIN
INPUT
SELECT
MUTE
Typical Operating Circuit
ABRIDGED DATA SHEET
MAX4850/MAX4850H/MAX4852/MAX4852H
Dual SPDT Analog Switches with
Over-Rail Signal Handling
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products is a registered trademark of Maxim Integrated Products.
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
12x16L QFN THIN.EPS
0.10 C0.08 C
0.10 M C A B
D
D/2
E/2
E
A1
A2
A
E2
E2/2
L
k
e
(ND - 1) X e
(NE - 1) X e
D2
D2/2
b
L
e
L
C
L
e
C
L
L
C
L
C
PACKAGE OUTLINE
21-0136
2
1
I
8, 12, 16L THIN QFN, 3x3x0.8mm
MARKING
AAAA
EXPOSED PAD VARIATIONS
CODES
PKG.
T1233-1
MIN.
0.95
NOM.
1.10
D2
NOM.
1.10
MAX.
1.25
MIN.
0.95
MAX.
1.25
E2
12N
k
A2
0.25
NE
A1
ND
0
0.20 REF
--
3
0.02
3
0.05
L
e
E
0.45
2.90
b
D
A
0.20
2.90
0.70
0.50 BSC.
0.55
3.00
0.65
3.10
0.25
3.00
0.75
0.30
3.10
0.80
16
0.20 REF
0.25 -
0
4
0.02
4
-
0.05
0.50 BSC.
0.30
2.90
0.40
3.00
0.20
2.90
0.70
0.25
3.00
0.75
3.10
0.50
0.80
3.10
0.30
PKG
REF. MIN.
12L 3x3
NOM. MAX. NOM.
16L 3x3
MIN. MAX.
0.35 x 45°
PIN ID JEDEC
WEED-1
T1233-3 1.10 1.25 0.95 1.10 0.35 x 45°1.25 WEED-10.95
T1633F-3 0.65
T1633-4 0.95
0.80 0.95 0.65 0.80
1.10 1.25 0.95 1.10
0.225 x 45°
0.95 WEED-2
0.35 x 45°
1.25 WEED-2
T1633-2 0.95 1.10 1.25 0.95 1.10 0.35 x 45°
1.25 WEED-2
PACKAGE OUTLINE
21-0136
2
2
I
8, 12, 16L THIN QFN, 3x3x0.8mm
WEED-11.25
1.100.95 0.35 x 45°
1.251.10
0.95
T1233-4
T1633FH-3 0.65 0.80 0.95 0.225 x 45°
0.65 0.80 0.95 WEED-2
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994 .
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO
JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED
WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS .
9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
10. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
11. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
12. WARPAGE NOT TO EXCEED 0.10mm.
0.25 0.30 0.35
2
0.25
0
0.20 REF
--
0.02 0.05
0.35
8
2
0.55 0.75
2.90
2.90 3.00 3.10
0.65 BSC.
3.00 3.10
8L 3x3
MIN.
0.70 0.75 0.80
NOM. MAX.
TQ833-1 1.250.25 0.70 0.35 x 45°WEEC1.250.700.25
T1633-5 0.95 1.10 1.25 0.35 x 45°WEED-2
0.95 1.10 1.25
ABRIDGED DATA SHEET