Integrated Optical Module with Ambient Light Rejection and Two LEDs ADPD188GG Data Sheet FEATURES GENERAL DESCRIPTION 3.8 mm x 5.0 mm x 0.9 mm module with integrated optical components 2 green LEDs, 2 PDs with IR cut filter 2 external sensor inputs 3, 370 mA LED drivers 20-bit burst accumulator enabling 20 bits per sample period On-board sample to sample accumulator enabling up to 27 bits per data read Custom optical package made to work under a glass window Optimized SNR for signal limited cases I2C or SPI communications The ADPD188GG is a complete photometric system designed to measure optical signals from ambient light and from synchronous reflected light emitting diode (LED) pulses. Synchronous measurement offers best-in-class rejection of ambient light interference, both dc and ac. The module integrates a highly efficient photometric front end, two LEDs, and two photodiode (PD). All of these items are housed in a custom package that prevents light from going directly from the LED to the photodiode without first entering the subject. The front end of the application specific integrated circuit (ASIC) consists of a control block, a 14-bit analog-to-digital converter (ADC) with a 20-bit burst accumulator, and three flexible, independently configurable LED drivers. The control circuitry includes flexible LED signaling and synchronous detection. The analog front end (AFE) features best-in-class rejection of signal offset and corruption due to modulated interference commonly caused by ambient light. The data output and functional configuration occur over a 1.8 V I2C interface or a serial peripheral interface (SPI) port. APPLICATIONS Optical heart rate monitoring Reflective PPG measurement CNIBP measurement FUNCTIONAL BLOCK DIAGRAM VDD1 VDD2 PDC ADPD188GG PD1 EXT_IN1 CH1 BPF 1 INTEGRATOR TIA_VREF VREF PD2 EXT_IN2 1F CH2 PDC BPF 1 INTEGRATOR TIA_VREF PDET1 PD3 CH3 BPF CS 1 INTEGRATOR TIME SLOT A DATA TIA_VREF CH4 BPF VLED1 GREEN SDA SCL TIA_VREF LED1/DNC LED1 DRIVER DIGITAL INTERFACE AND CONTROL GPIO0 GPIO1 LED3 DRIVER LED3 LED2 TIME SLOT B DATA 1 INTEGRATOR MOSI MISO 14-BIT ADC PD4 LED2 DRIVER LGND NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN WHEN USING INTERNAL LEDs. AGND DGND 16111-001 PDET2 SCLK Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com ADPD188GG Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Connection Diagram ................................................... 22 Applications ...................................................................................... 1 Land Pattern ............................................................................... 22 General Description ......................................................................... 1 Recommended Start-Up Sequence .......................................... 23 Functional Block Diagram .............................................................. 1 Reading Data............................................................................... 23 Revision History ............................................................................... 2 Clocks and Timing Calibration ................................................ 24 Specifications .................................................................................... 3 Optional Timing Signals Available on GPIO0 and GPIO1 . 25 Analog Specifications................................................................... 5 LED Driver Pins and LED Supply Voltage............................. 26 Digital Specifications ................................................................... 6 LED Driver Operation ............................................................... 26 Timing Specifications .................................................................. 7 Determining the Average Current........................................... 27 Absolute Maximum Ratings ........................................................... 9 Determining CVLED ..................................................................... 27 Thermal Resistance ...................................................................... 9 Using External LEDs ................................................................. 28 Recommended Soldering Profile ............................................... 9 Calculating Current Consumption.......................................... 28 ESD Caution.................................................................................. 9 Mechanical Considerations for Covering the ADPD188GG ... 31 Pin Configuration and Function Descriptions .......................... 10 TIA ADC Mode .......................................................................... 31 Typical Performance Characteristics ........................................... 11 Pulse Connect Mode .................................................................. 33 Theory of Operation ...................................................................... 13 Introduction ................................................................................ 13 Synchronous ECG and PPG Measurement Using TIA ADC Mode ............................................................................................ 34 Optical Components .................................................................. 13 Float Mode .................................................................................. 35 Dual Time Slot Operation ......................................................... 14 Register Listing ............................................................................... 42 Time Slot Switch ......................................................................... 15 LED Control Registers ............................................................... 46 Adjustable Sampling Frequency............................................... 16 AFE Configuration Registers.................................................... 48 External Synchronization for Sampling .................................. 16 Float Mode Registers ................................................................. 52 State Machine Operation .......................................................... 16 System Registers ......................................................................... 55 Normal Mode Operation and Data Flow................................ 17 ADC Registers ............................................................................ 59 Communications Interface ........................................................... 19 Data Registers ............................................................................. 60 I2C Interface ................................................................................ 19 Outline Dimensions ....................................................................... 61 SPI Port ........................................................................................ 20 Ordering Guide .......................................................................... 61 Applications Information.............................................................. 22 REVISION HISTORY 4/2020--Rev. A to Rev. B Change to Applications Section ..................................................... 1 Changes to Table 4 and Figure 2 .................................................... 7 Change to Reset Column, Table 26.............................................. 42 Added Endnote 1, Table 27 ........................................................... 46 Changes to Table 32 ....................................................................... 55 10/2018--Rev. 0 to Rev. A Changes to Figure 24 and Figure 25 ............................................ 22 Changes to Calibrating the 32 kHz Clock Section..................... 25 Added Improving SNR Using Integrator Chopping Section and Figure 32; Renumbered Sequentially ........................................... 29 Added Table 18; Renumbered Sequentially ............................... 30 Changes to Table 26 ....................................................................... 42 Changes to Table 29 ....................................................................... 50 Changes to Table 30 ....................................................................... 51 Changes to Address 0x58 Description Column, Table 31........ 53 2/2018--Revision 0: Initial Version Rev. B | Page 2 of 61 Data Sheet ADPD188GG SPECIFICATIONS The voltage applied at the VDD1 and VDD2 pins (VDD) = 1.8 V, and TA = full operating temperature range, unless otherwise noted. Table 1. Parameter CURRENT CONSUMPTION Peak VDD Supply Current VDD Standby Current Average VDD Supply Current 1 Pulse 10 Pulses Average VLED Supply Current 1 Pulse 10 Pulses SATURATION ILLUMINANCE1 Direct Illumination DATA ACQUISITION ADC Resolution Per Sample Per Data Read LED PERIOD Sampling Frequency 4 Test Conditions/Comments See the Calculating Current Consumption section for the relevant equations Single-channel (Register 0x3C, Bits[8:3] = 0x38) Min Rev. B | Page 3 of 61 Max Unit 4.5 0.3 mA A 53 41 76 107 95 184 A A A A A A 3.75 7.5 15 38 75 150 A A A A A A 58.8 29.4 14.7 7.4 kLux kLux kLux kLux 14 20 27 19 17 2000 Bits Bits Bits s s Hz 0.122 1600 Hz 0.122 1600 Hz 0.122 1000 Hz 100 Hz data rate; LED offset = 25 s; LED pulse period (tLED_PERIOD) = 13 s; LED peak current = 25 mA Time Slot A only Time Slot B only Both Time Slot A and Time Slot B Time Slot A only Time Slot B only Both Time Slot A and Time Slot B LED peak current = 25 mA 50 Hz data rate 100 Hz data rate 200 Hz data rate 50 Hz data rate 100 Hz data rate 200 Hz data rate Blackbody color temperature (T = 5500 K) 2, PDET1 and PDET2 multiplexed into a single channel (1.2 mm2active area) Transimpedance amplifier (TIA) gain = 25 k TIA gain = 50 k TIA gain = 100 k TIA gain = 200 k Single pulse 64 pulses to 255 pulses 64 pulses to 255 pulses; 128 samples averaged AFE width = 4 s 3 AFE width = 3 s Time Slot A or Time Slot B; normal mode; 1 pulse; SLOTA_LED_OFFSET = 23 s; SLOTA_PERIOD = 19 s Both time slots; normal mode; 1 pulse; SLOTA_LED_OFFSET = 23 s; SLOTA_PERIOD = 19 s Time Slot A or Time Slot B; normal mode; 8 pulses; SLOTA_LED_OFFSET = 23 s; SLOTA_PERIOD = 19 s Both time slots; normal mode; 8 pulses; SLOTA_LED_OFFSET = 23 s; SLOTA_PERIOD = 19 s Typ 13 11 0.122 ADPD188GG Parameter CATHODE PIN (PDC) VOLTAGE During All Sampling Periods During Time Slot A Sampling During Time Slot B Sampling During Sleep Periods Data Sheet Test Conditions/Comments Min Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 1 5 Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 0 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x05 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x1 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x2 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[9:8] = 0x3 6 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x05 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x1 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x2 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[11:10] = 0x36 Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 1 Register 0x54, Bit 7 = 0x0; Register 0x3C, Bit 9 = 0 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x0 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x1 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x2 Dominant Wavelength 7 LED1; Green LED Luminous Intensity Photodiode Responsivity Active Area Photodiode 1 Photodiode 2 POWER SUPPLY VOLTAGES VDD VLED1 8, 9 DC Power Supply Rejection Ratio (PSRR) TEMPERATURE RANGE Operating Adjustable via the Register 0x22 through Register 0x25 settings IF = 40 mA = 525 nm, IF = 40 mA at 25C 12 1.7 4 At 75% full scale input signal -40 Unit V V V V V V V V V V V V V V V V 370 mA 3200 nm mcd 525 2800 Wavelength, = 525 nm The ADPD188GG does not require a specific power-up sequence Applied at the VDD1 and VDD2 pins Max 1.8 1.3 1.8 1.3 TIA_VREF + 0.25 0 1.8 1.3 TIA_VREF + 0.25 0 1.8 1.3 1.8 1.3 TIA_VREF + 0.25 0 Register 0x54, Bit 7 = 0x1; Register 0x54, Bits[13:12] = 0x3 LEDs LED Peak Current Setting Typ 0.25 A/W 0.4 0.8 mm2 mm2 1.8 4.5 24 1.9 5.0 V V dB +85 C Saturation illuminance refers to the amount of ambient light that saturates the ADPD188GG signal. Actual results may vary by factors of up to 2x from typical specifications. As a point of reference, Air Mass 1.5 (AM1.5) sunlight (brightest sunlight) produces 100 kLux. 2 Blackbody color temperature (T = 5800 K) closely matches the light produced by solar radiation (sunlight). 3 Minimum LED period = (2 x AFE width) + 5 s. 4 The maximum values in this specification are the internal ADC sampling rates in normal mode. The I2C read rates in some configurations may limit the output data rate. 5 This mode may induce additional noise and is not recommended unless necessary. The 1.8 V setting uses VDD, which contains greater amounts of differential voltage noise with respect to the anode voltage. A differential voltage between the anode and cathode injects a differential current across the capacitance of the photodiode of the magnitude of C x dV/dt. 6 This setting is not recommended for photodiodes because it causes a 1.3 V forward bias of the photodiode. 7 IF is the forward current of the diode. 8 Set VLEDx such that the maximum desired LED current is achievable with the turn on voltage of the LEDs that are wired to the LEDx/DNC pins. The LEDx/DNC pins are connected to the LEDx driver, which can be modeled as current sinks (see Figure 1). When an appropriate VLEDx is used, the voltage at the LEDx/DNC pins adjusts automatically to accommodate the LED turn on voltage and the LED current. 9 See Figure 9 for the current limitation at the minimum VLED supply voltage, VLED. 1 Rev. B | Page 4 of 61 Data Sheet ADPD188GG ANALOG SPECIFICATIONS VDD1 = VDD2 = 1.8 V, and TA = full operating temperature range, unless otherwise noted. Table 2. Parameter EXT_INx SERIES RESISTANCE (R_IN) 1 PULSED SIGNAL CONVERSIONS, 3 s WIDE LED PULSE 2 ADC Resolution 3 ADC Saturation Level Ambient Signal Headroom on Pulsed Signal PULSED SIGNAL CONVERSIONS, 2 s WIDE LED PULSE2 ADC Resolution3 ADC Saturation Level Ambient Signal Headroom on Pulsed Signal FULL SIGNAL CONVERSIONS 4 TIA Saturation Level Pulsed Signal and Ambient Level TIA Linear Range Test Conditions/Comments Measured from -3 A to +3 A 4 s wide AFE integration; normal operation, Register 0x43 and Register 0x45 = 0xADA5 TIA feedback resistor 25 k 50 k 100 k 200 k TIA feedback resistor 25 k 50 k 100 k 200 k TIA feedback resistor Min Typ 6.5 Max Unit k 3.27 1.64 0.82 0.41 nA/LSB nA/LSB nA/LSB nA/LSB 26.8 13.4 6.7 3.35 A A A A 25 k 50 k 100 k 200 k 3 s wide AFE integration; normal operation, Register 0x43 and Register 0x45 = 0xADA5 TIA feedback resistor 25 k 50 k 100 k 200 k TIA feedback resistor 25 k 50 k 100 k 200 k TIA feedback resistor 23.6 11.8 5.9 2.95 A A A A 4.62 2.31 1.15 0.58 nA/LSB nA/LSB nA/LSB nA/LSB 37.84 18.92 9.46 4.73 A A A A 25 k 50 k 100 k 200 k 12.56 6.28 3.14 1.57 A A A A 50.4 25.2 12.6 6.3 A A A A 42.8 21.4 10.7 5.4 A A A A TIA feedback resistor 25 k 50 k 100 k 200 k TIA feedback resistor 25 k 50 k 100 k 200 k Rev. B | Page 5 of 61 ADPD188GG Data Sheet Parameter SYSTEM PERFORMANCE Total Output Noise Floor Test Conditions/Comments Min Normal mode; per pulse; per channel; no LED; photodiode capacitance (CPD) = 25 pF 25 k; referred to ADC input 25 k; referred to peak input signal for 2 s LED pulse 25 k; referred to peak input signal for 3 s LED pulse 25 k; saturation signal-to-noise ratio (SNR) per pulse per channel 5 50 k; referred to ADC input 50 k; referred to peak input signal for 2 s LED pulse 50 k; referred to peak input signal for 3 s LED pulse 50 k; saturation SNR per pulse per channel5 100 k; referred to ADC input 100 k; referred to peak input signal for 2 s LED pulse 100 k; referred to peak input signal for 3 s LED pulse 100 k; saturation SNR per pulse per channel5 200 k; referred to ADC input 200 k; referred to peak input signal for 2 s LED pulse 200 k; referred to peak input signal for 3 s LED pulse 200 k; saturation SNR per pulse per channel5 Typ Max Unit 1.0 4.6 3.3 78.3 LSB rms nA rms nA rms dB 1.1 2.5 1.8 77.4 1.2 1.4 0.98 76.7 1.4 0.81 0.57 75.3 LSB rms nA rms nA rms dB LSB rms nA rms nA rms dB LSB rms nA rms nA rms dB The R_IN value can be ignored for current source inputs or for PD inputs. This value is important for calculating correct voltages for voltage inputs through a resistor. This saturation level applies to the ADC only and, therefore, includes only the pulsed signal. Any nonpulsatile signal is removed prior to the ADC stage. 3 ADC resolution is listed per pulse. If using multiple pulses, divide by the number of pulses. 4 This saturation level applies to the full signal path and, therefore, includes both the ambient signal and the pulsed signal. 5 The noise term of the saturation SNR value refers to the receive noise only and does not include photon shot noise or any noise on the LED signal itself. 1 2 DIGITAL SPECIFICATIONS VDD1 = VDD2 = 1.7 V to 1.9 V, unless otherwise noted. Table 3. Parameter LOGIC INPUTS Input Voltage Level High High Low Input Current Level High Low Input Capacitance LOGIC OUTPUTS Output Voltage Level High Low Output Voltage Level Low Output Current Level Low Symbol Test Conditions/Comments Min VIH VIH VIL GPIOx, SCLK, MOSI, CS SCL, SDA 0.7 x VDDx 0.7 x VDDx IIH IIL CIN VOH VOL VOL1 IOL Typ -10 -10 Max Unit VDDx 3.6 0.3 x VDDx V +10 +10 A A pF 10 GPIOx, MISO 2 mA high level output current 2 mA low level output current SDA 2 mA low level output current SDA VOL1 = 0.6 V Rev. B | Page 6 of 61 VDDx - 0.5 6 V 0.5 V V 0.2 x VDDx V mA Data Sheet ADPD188GG TIMING SPECIFICATIONS I2C Timing Specifications Table 4. Parameter SCL Frequency Minimum Pulse Width High Low START CONDITION Hold Time Setup Time SDA SETUP TIME SDA HOLD TIME SCL AND SDA Rise Time Fall Time STOP CONDITION Setup Time Symbol Min Typ Max Unit 1 0.4 Mb/sec t1 t2 370 530 ns ns t3 t4 t5 t9 260 260 50 0 ns ns ns ns t6 t7 1000 300 t8 t3 260 t5 t9 ns ns ns t3 SDA t6 t1 t2 t7 t4 Figure 2. I2C Timing Diagram Rev. B | Page 7 of 61 t8 16111-002 SCL ADPD188GG Data Sheet SPI Timing Specifications Table 5. Parameter SCLK Frequency Minimum Pulse Width High Low CS Setup Time Symbol Test Conditions/Comments Min Typ fSCLK tSCLKPWH tSCLKPWL Max Unit 10 MHz 20 20 ns ns tCSS CS setup to SCLK rising edge 10 ns Hold Time tCSH CS hold from SCLK rising edge 10 ns Pulse Width High tCSPWH CS pulse width high 10 ns MOSI Setup Time Hold Time MISO OUTPUT DELAY tMOSIS tMOSIH tMISOD MOSI setup to SCLK rising edge MOSI hold from SCLK rising edge MISO valid output delay from SCLK falling edge ns ns 10 10 21 ns tCSH tCSS tCSPWH tSCLKPWL tSCLKPWH CS SCLK MOSI tMOSIH MISO tMISOD Figure 3. SPI Timing Diagram Rev. B | Page 8 of 61 16111-003 tMOSIS Data Sheet ADPD188GG ABSOLUTE MAXIMUM RATINGS RECOMMENDED SOLDERING PROFILE Table 6. 1 Figure 4 and Table 8 provide details about the recommended soldering profile. TL L TSMIN tS 3000 V 1250 V 100 V RAMP-DOWN t25C TO PEAK TIME Figure 4. Recommended Soldering Profile 260 (+0/-5)C <30 sec Table 8. Recommended Soldering Profile -40C to +85C -40C to +105C 105C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Profile Feature Average Ramp Rate (TL to TP) Preheat Minimum Temperature (TSMIN) Maximum Temperature (TSMAX) Time, TSMIN to TSMAX (tS) TSMAX to TL Ramp-Up Rate Time Maintained Above Liquidous Temperature Liquidous Temperature (TL) Time (tL) Peak Temperature (TP) Time Within 5C of Actual Peak Temperature (tP) Ramp-Down Rate Time 25C to Peak Temperature ESD CAUTION Table 7. Thermal Resistance 1 TSMAX PREHEAT The absolute maximum voltage allowable between VLEDx and LGND is the voltage that causes the LEDx/DNC pins to reach or exceed their absolute maximum voltage. Package Type1 CE-24-1 ASIC LED1 CRITICAL ZONE TL TO TP P TP 16111-004 Rating -0.3 V to +2.2 V -0.3 V to +2.2 V -0.3 V to +2.2V -0.3 V to +2.2 V -0.3 V to +2.2 V -0.3 V to +3.6 V -0.3 V to +3.6 V -0.3 V to +5.0 V TEMPERATURE Parameter VDD1, VDD2 to AGND VDD1, VDD2 to DGND EXT_IN1/EXT_IN2 GPIO0/GPIO1 to DGND MISO/MOSI/SCLK/CS to DGND LEDx/DNC to LGND SCL/SDA to DGND VLEDx to LGND1 Electrostatic Discharge (ESD) Human Body Model (HBM) Charged Device Model (CDM) Machine Model (MM) Solder Reflow (Pb-Free) Peak Temperature Time at Peak Temperature Temperature Range Powered Storage Junction Temperature Supply Pins JA Unit VDD1, VDD2 VLED1 67 156 C/W C/W Thermal impedance simulated values are based on JEDEC 2S2P and two thermal vias. See JEDEC JESD51. Rev. B | Page 9 of 61 Condition (Pb-Free) 2C/sec max 150C 200C 60 sec to 120 sec 2C/sec max 217C 60 sec to 150 sec 260 (+0/-5)C <30 sec 3C/sec max 8 minutes max ADPD188GG Data Sheet EXT_IN1 VDD1 VREF AGND DGND 24 23 22 21 20 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PDC 1 19 CS EXT_IN2 2 18 SCLK 17 MOSI 16 MISO NIC 3 TOP VIEW (Not to Scale) GPIO0 NIC 7 13 SDA LED1/ DNC 12 14 SCL 6 11 NIC LGND GPIO1 10 15 LED2 5 9 VLED1 LED3 4 8 VDD2 NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN WHEN USING INTERNAL LEDs. 2. NIC = NO INTERNAL CONNECTION. 16111-005 ADPD188GG Figure 5. Pin Configuration Table 9. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 Mnemonic PDC EXT_IN2 NIC VDD2 VLED1 NIC NIC LED1/DNC LED3 LED2 LGND SCL SDA GPIO0 GPIO1 MISO MOSI SCLK CS DGND AGND VREF VDD1 EXT_IN1 Type 1 AO AI NIC S S NIC NIC AO/DNC AO AO S DI DO DIO DIO DO DI DI DI S S REF S AI Description Photodiode Common Cathode Bias. EXT_IN2 Current Input. No Internal Connection. This pin is not internally connected. 1.8 V Supply. Green LED Anode Supply Voltage. No Internal Connection. This pin is not internally connected. No Internal Connection. This pin is not internally connected. LED1 Driver Current Sink (LED1)/Do Not Connect (DNC). Do not connect to this pin when using internal LEDs. LED3 Driver Current Sink. If not in use, leave this pin floating. LED2 Driver Current Sink. If not in use, leave this pin floating. LED Driver Ground. I2C Clock Input. I2C Data Output. General-Purpose Input/Output 0. General-Purpose Input/Output 1. SPI Master Input, Slave Output. SPI Master Output, Slave Input. SPI Clock Input. SPI Chip Select (Active Low). Digital Ground. Analog Ground. Internally Generated ADC Voltage Reference. Connect a 1 F ceramic capacitor from VREF to ground. 1.8 V Supply. EXT_IN1 Current Input. AO is analog output, AI is analog input, NIC is not internally connected, S is supply, DNC is do not connect, DI is digital input, DO is digital output, DIO is digital input/output, and REF is analog reference. Rev. B | Page 10 of 61 Data Sheet ADPD188GG TYPICAL PERFORMANCE CHARACTERISTICS 0.35 FILTERED ADPD188 PERCENT OF POPULATION (%) 0.25 0.20 0.15 0.10 20 15 10 5 0.05 300 400 500 600 700 800 900 1000 1100 0 WAVELENGTH (nm) 16111-008 200 16111-006 0 27.5 28.0 28.5 29.0 29.5 30.0 30.5 31.0 31.5 32.0 FREQUENCY (MHz) Figure 8. 32 MHz Clock Frequency Distribution; Default Settings; Before User Calibration, Register 0x4D = 0x425E Figure 6. Typical Photodiode Responsivity 400 30 LED COARSE SETTING = 0xF 350 DRIVER CURRENT (mA) 25 20 15 10 300 250 200 150 100 5 50 LED COARSE SETTING = 0x0 Figure 7. 32 kHz Clock Frequency Distribution; Default Settings; Before User Calibration, Register 0x4B = 0x2612 2.6 2.4 2.2 16111-009 LED DRIVER VOLTAGE (V) 2.0 SAMPLE FREQUENCY DEVIATION FROM NOMINAL (%) 0 1.8 15 1.6 10 1.4 5 1.2 0 1.0 -5 0.8 -10 0.6 -15 0.4 -20 0 -25 0.2 0 16111-007 PERCENT OF POPULATION (%) RESPONSIVITY (A/W) 0.30 Figure 9. LED Driver Current vs. LED Driver Voltage at Various Coarse Settings Rev. B | Page 11 of 61 ADPD188GG Data Sheet 0.6 0.4 0.2 0.2 0.4 0.6 0.6 40 0.8 60 80 0.6 0.4 0.2 0.2 0.4 0.6 ANGULAR DISPLACEMENT (Degrees) 20 HORIZONTAL VERTICAL 60 0.4 0.2 0.2 0.4 0.6 Figure 12. LED Relative Intensity vs. Angular Displacement 16111-111 RELATIVE SENSITIVITY (A.U.) 1.0 0.8 80 Figure 10. PD1 Relative Sensitivity vs. Angular Displacement 0 40 16111-112 80 1.0 ANGULAR DISPLACEMENT (Degrees) 60 RELATIVE SENSITIVITY (A.U.) 0.8 ANGULAR DISPLACEMENT (Degrees) 40 20 HORIZONTAL VERTICAL 16111-110 RELATIVE SENSITIVITY (A.U.) HORIZONTAL VERTICAL 1.0 0 20 0 Figure 11. PD2 Relative Sensitivity vs. Angular Displacement Rev. B | Page 12 of 61 Data Sheet ADPD188GG THEORY OF OPERATION INTRODUCTION This highly integrated system works well in environments where ambient light is poorly controlled and the signal modulation ratio is low. As a result, the device produces high SNR for relatively low LED power. The ADPD188GG is a complete, integrated, optical module designed for photoplethysmography (PPG) measurements. The module contains two optical detectors. Photodiode 1 (PDET1) has 0.4 mm2 of active area and is connected to Channel 3 of the ASIC. Photodiode 2 (PDET2) has 0.8 mm2 of active area and is connected to Channel 4 of the ASIC. The two photodiodes can be combined into a single detector with 1.2 mm2 of active area. Both photo-diodes are coated with an infrared (IR) cut filter that maximizes ambient light rejection without the need for other light cancellation techniques. OPTICAL COMPONENTS Photodiode The ADPD188GG integrates a 1.2 mm2 deep junction photodiode. The optical sensing area is a dual detector that is connected to Channel PD3 and Channel PD4 in the ASIC. The photodiodes are accessible from Time Slot A or Time Slot B. The responsivity of the ADPD188GG photodiode is shown in Figure 6. The module combines the dual photodetector with two green LEDs, and a mixed-signal, photometric, front-end ASIC into a single compact device for optical measurements. The on-board ASIC includes an analog signal processing block, an ADC, a digital signal processing block, an I2C and SPI communication interface, and three, independently programmable, pulsed LED current sources. LEDs The ADPD188GG module integrates two green LEDs. Table 10. LED Dominant Wavelength LED Color Green (2x) Driver LED1 Typical Wavelength (nm) 525 In addition to the integrated LEDs, the ADPD188GG has the ability to drive external LEDs. The core circuitry stimulates the LEDs and measures the corresponding optical return signals in discrete data locations. Data can be read from output registers directly or through a first in, first out (FIFO) buffer. 1.67 Figure 13. Optical Component Locations Rev. B | Page 13 of 61 16111-012 PD2 5.0 3.8 PD2 0.9 PD1 PD1 1.42 ADPD188GG Data Sheet The timing parameters in Figure 14 are defined as follows: DUAL TIME SLOT OPERATION tA (s) = 25 + nA x 19 The ADPD188GG operates in two independent time slots, Time Slot A and Time Slot B, which are carried out sequentially. The entire signal path from LED stimulation to data capture and processing is executed during each time slot. Each time slot has a separate datapath that uses independent settings for the LED driver, AFE setup, and the resulting data. Time Slot A and Time Slot B operate in sequence for every sampling period, as shown in Figure 14. where nA is the number of pulses for Time Slot A (Register 0x31, Bits[15:8]). tB (s) = 25 + nB x 19 where nB is the number of pulses for Time Slot B (Register 0x36, Bits[15:8]). t1 = 68 s, the processing time for Time Slot A t2 = 20 s, the processing time for Time Slot B fSAMPLE is the sampling frequency (Register 0x12, Bits[15:0]). ACTIVE tA nA PULSES t1 tB t2 nB PULSES TIME SLOT A 16111-013 SLEEP TIME SLOT B 1/fSAMPLE Figure 14. Time Slot Timing Diagram Table 11. Recommended AFE and LED Timing Configuration Register Name SLOTx_LEDMODE SLOTx_AFEMODE Time Slot A 0x30 0x39 Address Time Slot B 0x35 0x3B Rev. B | Page 14 of 61 Recommended Setting 0x0319 0x2209 Data Sheet ADPD188GG TIME SLOT SWITCH PDC Multiple configurations of the four input channels are supported, depending on the settings of Register 0x14. The integrated photodiodes can either be routed to Channel 3 and Channel 4, or summed together into Channel 1. The external EXT_IN1 and EXT_IN2 inputs can be routed to Channel 1 and Channel 2, respectively, or summed into Channel 2. See Figure 15 and Figure 16 for the supported configurations. In Figure 15 and Figure 16, PDET1 is Photodiode 1, and PDET2 is Photodiode 2. PDET1 CH1 EXT_IN1 CH2 EXT_IN2 INPUT CONFIGURATION FOR REGISTER 0x14[11:8] = 1 REGISTER 0x14[7:4] = 1 EXT_IN1 16111-015 See Table 12 for the time slot switch registers. It is important to leave any unused inputs floating for proper operation of the devices. The photodiode inputs are current inputs and, as such, these pins are also considered to be voltage outputs. Tying these inputs to a voltage may saturate the analog block. PDET2 Figure 16. Current Summation CH1 EXT_IN2 CH2 PDC PDET1 CH3 PDC PDET2 INPUT CONFIGURATION FOR REGISTER 0x14[11:8] = 5 REGISTER 0x14[7:4] = 5 16111-014 CH4 Figure 15. PD1 to PD4 Connection Table 12. Time Slot Switch (Register 0x14) Address 0x14 Bits [11:8] Name SLOTB_PD_SEL [7:4] SLOTA_PD_SEL Description These bits select the connection of input channels for Time Slot B as shown in Figure 15 and Figure 16. 0x0: inputs are floating in Time Slot B. 0x1: PDET1 and PDET2 are connected to Channel 1; EXT_IN1 and EXT_IN2 are connected to Channel 2 during Time Slot B. 0x5: EXT_IN1 is connected to Channel 1, EXT_IN2 is connected to Channel 2, PDET1 is connected to Channel 3, and PDET2 is connected to Channel 4 during Time Slot B. Other: reserved. These bits select the connection of input channels for Time Slot A as shown in Figure 15 and Figure 16. 0x0: inputs are floating in Time Slot A. 0x1: PDET1 and PDET2 are connected to Channel 1; EXT_IN1 and EXT_IN2 are connected to Channel 2 during Time Slot A. 0x5: EXT_IN1 is connected to Channel 1, EXT_IN2 is connected to Channel 2, PDET1 is connected to Channel 3, and PDET2 is connected to Channel 4 during Time Slot A. Other: reserved. Rev. B | Page 15 of 61 ADPD188GG Data Sheet Providing an External 32 kHz Clock Register 0x12 controls the sampling frequency setting of the ADPD188GG and Register 0x4B, Bits[5:0] further tunes this clock for greater accuracy. The sampling frequency is governed by an internal 32 kHz sample rate clock that also drives the transition of the internal state machine. The maximum sampling frequencies for some sample conditions are listed in Table 1. The maximum sample frequency for all conditions, fSAMPLE,_MAX, is determined by the following equation: fSAMPLE_MAX = 1/(tA + t1 + tB + t2 + tSLEEP_MIN) where tSLEEP_MIN is the minimum sleep time required between samples. See the Dual Time Slot Operation section for the definitions of tA, t1, tB, and t2. If a given time slot is not in use, elements from that time slot do not factor into the calculation. For example, if Time Slot A is not in use, tA and t1 do not add to the sampling period and the new maximum sampling frequency is calculated as follows: fSAMPLE_MAX = 1/(tB + t2 + tSLEEP_MIN) EXTERNAL SYNCHRONIZATION FOR SAMPLING The ADPD188GG provides an option to use an external synchronization signal to trigger the sampling periods. This external sample synchronization signal can be provided either on the GPIO0 pin or the GPIO1 pin. This functionality is controlled by Register 0x4F, Bits[3:2]. When enabled, a rising edge on the selected input specifies when the next sample cycle occurs. When triggered, there is a delay of one to two internal sampling clock (32 kHz) cycles, and then the normal start-up sequence occurs. This sequence is the same as when the normal sample timer provides the trigger. To enable the external synchronization signal feature, use the following procedure: 1. 2. 3. 4. 5. The ADPD188GG has an option for the user to provide an external 32 kHz clock to the device for system synchronization or for situations where a clock with better accuracy than the internal 32 kHz clock is required. The external 32 kHz clock is provided on the GPIO1 pin only. To enable the 32 kHz external clock, use the following procedure at startup: 1. 2. 3. 4. 5. 6. Drive the GPIO1 pin to a valid logic level or with the desired 32 kHz clock prior to enabling the GPIO1 pin as an input. Do not leave the pin floating prior to enabling it. Write 0x1 to Register 0x4F, Bits[6:5] to enable the GPIO1 pin as an input. Write 0x2 to Register 0x4B, Bits[8:7] to configure the devices to use an external 32 kHz clock. This setting disables the internal 32 kHz clock and enables the external 32 kHz clock. Write 0x1 to Register 0x10 to enter program mode. Write additional control registers in any order while the device is in program mode to configure the device as required. Write 0x2 to Register 0x10 to start the normal sampling operation STATE MACHINE OPERATION During each time slot, the ADPD188GG operates according to a state machine. The state machine operates in the sequence shown in Figure 17. Write 0x1 to Register 0x10 to enter program mode. Write the appropriate value to Register 0x4F, Bits[3:2] to select whether the GPIO0 pin or the GPIO1 pin specifies when the next sample cycle occurs. Also, enable the appropriate input buffer using Register 0x4F, Bit 1, for the GPIO0 pin, or Register 0x4F, Bit 5, for the GPIO1 pin. Write 0x4000 to Register 0x38. Write 0x2 to Register 0x10 to start the sampling operations. Apply the external synchronization signal on the selected pin at the desired rate; sampling occurs at that rate. As with normal sampling operations, read the data using the FIFO or the data registers. The maximum frequency constraints also apply in this case. Rev. B | Page 16 of 61 STANDBY REGISTER 0x10 = 0x0000 ULTRALOW POWER MODE NO DATA COLLECTION ALL REGISTER VALUES ARE RETAINED. PROGRAM REGISTER 0x10 = 0x0001 SAFE MODE FOR PROGRAMMING REGISTERS NO DATA COLLECTION DEVICE IS FULLY POWERED IN THIS MODE. NORMAL OPERATION REGISTER 0x10 = 0x0002 LEDs ARE PULSED AND PHOTODIODES ARE SAMPLED STANDARD DATA COLLECTION DEVICE POWER IS CYCLED BY INTERNAL STATE MACHINE. Figure 17. State Machine Operation Flowchart 16111-016 ADJUSTABLE SAMPLING FREQUENCY Data Sheet ADPD188GG NORMAL MODE OPERATION AND DATA FLOW The ADPD188GG operates in one of three modes: standby, program, or normal sampling mode. Standby mode is a power saving mode in which data collection does not occur. All register values are retained in this mode. To place the device in standby mode, write 0x0 to Register 0x10, Bits[1:0]. The device powers up in standby mode. Program mode is used for programming registers. Always cycle the ADPD188GG through program mode when writing registers or changing modes. Because power cycling does not occur in this mode, the device may consume higher current in program mode than in normal operation. To place the device in program mode, write 0x1 to Register 0x10, Bits[1:0]. In normal operation, the ADPD188GG pulses light and collects data. Power consumption in this mode depends on the pulse count and data rate. To place the device in normal sampling mode, write 0x2 to Register 0x10, Bits[1:0]. In normal mode, the ADPD188GG follows a specific pattern set up by the state machine. This pattern is shown in the corresponding data flow diagram in Figure 18. The pattern, in order, is as follows: 1. LED pulse and sample. The ADPD188GG pulses external LEDs. The response of the photodiode to the reflected light is measured by the ADPD188GG. Each data sample is constructed from the sum of n individual pulses, where n is user configurable between 1 and 255. Intersample averaging. If desired, the logic can average n samples, from 2 to 128 in powers of 2, to produce output data. New output data is saved to the output registers every N samples. Data read. The host processor reads the converted results from the data register or the FIFO. Repeat. The sequence has a few different loops that enable different types of averaging while keeping both time slots close in time relative to each other. 2. 3. 4. [14 + LOG2(nA x NA)] BITS UP TO 27 BITS [14 + LOG2(nA)] BITS UP TO 20 BITS NA NA 14 BITS 1 14 BITS nA nA nA 14-BIT ADC 1 ADC OFFSET 20-BIT CLIP IF VAL (220 - 1) VAL = VAL ELSE VAL = 2 20 - 1 0 16-BIT CLIP 16 BITS IF VAL (216 - 1) VAL = VAL ELSE VAL = 216 - 1 1 REGISTER 0x11[13] [14 + LOG2(nA)] BITS UP TO 22 BITS 32-BIT DATA REGISTERS FIFO 16-BIT DATA REGISTERS SAMPLE 1: TIME SLOT A SAMPLE 1: TIME SLOT B 0 1 SAMPLE NA: TIME SLOT A SAMPLE N B: TIME SLOT B NB NOTES 1. nA AND nB = NUMBER OF LED PULSES FOR TIME SLOT A AND TIME SLOT B. 2. NA AND NB = NUMBER OF AVERAGES FOR TIME SLOT A AND TIME SLOT B. NB 1 [14 + LOG2(nB)] BITS UP TO 20 BITS [14 + LOG2 (nB x NB)] BITS UP TO 27 BITS Figure 18. State Machine Operating Sequence (Datapath) Rev. B | Page 17 of 61 16-BIT CLIP IF VAL (216 - 1) VAL = VAL ELSE VAL = 216 - 1 16 BITS 16111-017 TIME SLOT A TIME SLOT B ADPD188GG Data Sheet LED Pulse and Sample data is still acquired by the AFE at the sampling frequency, fSAMPLE (see Register 0x12), but new data is written to the registers at the rate of fSAMPLE/N every Nth sample. This new data consists of the sum of the previous N samples. The full 32-bit sum is stored in the 32-bit registers. However, before sending this data to the FIFO, a divide by N operation occurs. This divide operation maintains bit depth to prevent clipping on the FIFO. At each sampling period, the selected LED driver drives a series of LED pulses, as shown in Figure 19. The magnitude, duration, and number of pulses are programmable over the communications interface. Each LED pulse coincides with a sensing period so that the sensed value represents the total charge acquired on the photodiode in response to only the corresponding LED pulse. Charge, such as ambient light that does not correspond to the LED pulse, is rejected. Use this between sample averaging to lower the noise while maintaining 16-bit resolution. If the pulse count registers are kept to 8 or less, the 16-bit width is never exceeded. Therefore, when using Register 0x15 to average subsequent pulses, many pulses can be accumulated without exceeding the 16-bit word width. This setting can reduce the number of FIFO reads required by the host processor. After each LED pulse, the photodiode output relating to the pulsed LED signal is sampled and converted to a digital value by the 14-bit ADC. Each subsequent conversion within a sampling period is summed with the previous result. Up to 255 pulse values from the ADC can be summed in an individual sampling period. There is a 20-bit maximum range for each sampling period. Data Read Averaging The host processor reads output data from the ADPD188GG via the communications interface, from the data registers, or from the FIFO. New output data is made available every N samples, where N is the user configured averaging factor. The averaging factors for Time Slot A and Time Slot B are configurable independently of each other. If the factors are the same, both time slots can be configured to save data to the FIFO. If the two averaging factors are different, only one time slot can save data to the FIFO; data from the other time slot can be read from the output registers. The ADPD188GG offers sample accumulation and averaging functionality to increase signal resolution. Within a sampling period, the AFE can sum up to 256 sequential pulses. As shown in Figure 18, samples acquired by the AFE are clipped to 20 bits at the output of the AFE. Additional resolution, up to 27 bits, can be achieved by averaging between sampling periods. This accumulated data of N samples is stored as 27-bit values and can be read out directly by using the 32-bit output registers or the 32-bit FIFO configuration. The data read operations are described in more detail in the Reading Data section. When using the averaging feature set up by the register, subsequent pulses can be averaged by powers of 2. The user can select from 2, 4, 8, ..., up to 128 samples to be averaged. Pulse SHOWN WITH fSAMPLE = 10Hz OPTICAL SAMPLING LOCATIONS 0 0.5 1.0 1.5 2.0 2.5 3.0 TIME (Seconds) NUMBER OF LED PULSES (nA OR nB) 16111-018 LED CURRENT (ILED) Figure 19. Example of a PPG Signal Sampled at a Data Rate of 10 Hz Using Five Pulses per Sample Rev. B | Page 18 of 61 Data Sheet ADPD188GG COMMUNICATIONS INTERFACE For multiword operations, each pair of data bytes is followed by an acknowledge (ACK) from the host until the last byte of the last word is read. The host indicates the last read word by sending a no acknowledge. When reading from the FIFO (Register 0x60), the data is automatically advanced to the next word in the FIFO, and the space is freed. When reading from other registers, the register address is automatically advanced to the next register, allowing the user to read without readdressing each register, thereby reducing the amount of overhead required to read multiple registers. This auto-increment does not apply to the register that precedes the FIFO, Register 0x5F, or the last data register, Register 0x7E. The ADPD188GG supports both an SPI and I2C serial interface, although only one can be used at any given time in the actual application. All internal registers are accessed through the selected communications interface. I2C INTERFACE The ADPD188GG I2C conforms to the UM10204 I2C-Bus Specification and User Manual, Rev. 05--9 October 2012, available from NXP Semiconductors. The device supports fast mode (400 kbps) data transfer. Register read and write operations are supported, as shown in Figure 20. The 7-bit I2C slave address for the device is 0x64. If the I2C interface is being used, the CS pin must be pulled high to disable the SPI port. Single-word and multiword read operations are supported. For a single register read, the host sends a no acknowledge (NACK) after the second data byte is read and a new register address is needed for each access. All register writes are single-word only and require 16 bits (one word) of data. The software reset (Register 0x0F, Bit 0) returns an acknowledge. The device then returns to standby mode with all registers in the default state. Table 13. Definitions of I2C Terminology Term SCL SDA Master Slave Start (S) Start (Sr) Stop (P) ACK NACK Slave Address Read (R) Write (W) Description Serial clock. Serial address and data. The device that initiates a transfer, generates clock signals, and terminates a transfer. The device addressed by a master. The ADPD188GG operates as a slave device. A high to low transition on the SDA line while SCL is high; all transactions begin with a start condition. Repeated start condition. A low to high transition on the SDA line while SCL is high. A stop condition terminates all transactions. During the acknowledge (ACK) or no acknowledge (NACK) clock pulse, the SDA line is pulled low, and it remains low. During the ACK or NACK clock pulse, the SDA line remains high. After a start (S), a 7-bit slave address is sent, which is followed by a data direction bit (read or write). A 1 indicates a request for data. A 0 indicates a transmission. I2C WRITE REGISTER WRITE MASTER START SLAVE ADDRESS + WRITE SLAVE REGISTER ADDRESS ACK DATA[15:8] DATA[7:0] ACK ACK STOP ACK I2C SINGLE-WORD READ MODE REGISTER READ MASTER START SLAVE ADDRESS + WRITE SLAVE REGISTER ADDRESS ACK Sr ACK SLAVE ADDRESS + READ ACK ACK DATA[15:8] ACK DATA[15:8] NACK STOP DATA[7:0] I2C MULTIWORD READ MODE REGISTER READ SLAVE SLAVE ADDRESS + WRITE REGISTER ADDRESS ACK Sr SLAVE ADDRESS + READ ACK ACK/NACK ACK DATA TRANSFERRED NOTES 1. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING. Figure 20. I2C Write and Read Operations Rev. B | Page 19 of 61 STOP DATA[7:0] 16111-019 MASTER START ADPD188GG Data Sheet SPI PORT Table 15. SPI Address and Write/R Byte Format The SPI port uses a 4-wire interface, consisting of the CS, MOSI, MISO, and SCLK signals, and it is always a slave port. The CS signal goes low at the beginning of a transaction and high at the end of a transaction. The SCLK signal latches MOSI on a low to high transition. The MISO data is shifted out of the device on the falling edge of SCLK and must be clocked into a receiving device, such as a microcontroller, on the SCLK rising edge. The MOSI signal carries the serial input data, and the MISO signal carries the serial output data. The MISO signal remains three-state until a read operation is requested, which allows other SPI-compatible peripherals to share the same MISO line. All SPI transactions have the same basic format shown in Table 14. A timing diagram is shown in Figure 3. Write all data MSB first. Bit 0 A6 Table 14. Generic Control Word Sequence Byte 0 Address[6:0], W/R Byte 1 Data[15:8] Byte 2 Data[7:0] Subsequent Bytes Data[15:8], Data[7:0] The first byte written in a SPI transaction is a 7-bit address, which is the location of the address being accessed, followed by the W/R bit. This bit determines whether the communication is a write (Logic Level 1) or a read (Logic Level 0). This format is shown in Table 15. Bit 1 A5 Bit 2 A4 Bit 3 A3 Bit 4 A2 Bit 5 A1 Bit 6 A0 Bit 7 W/R Data on the MOSI pin is captured on the rising edge of the clock, and data is propagated on the MISO pin on the falling edge of the clock. The maximum read and write speed for the SPI slave port is 10 MHz. A sample timing diagram for a multiple word SPI write operation to a register is shown in Figure 21. A sample timing diagram of a single-word SPI read operation is shown in Figure 22. The MISO pin transitions from being three-state to being driven following the reception of a valid R bit. In this example, Byte 0 contains the address and the W/R bit, and subsequent bytes carry the data. A sample timing diagram of a multiple word SPI read operation is shown in Figure 23. In Figure 21 to Figure 23, rising edges on SCLK are indicated with an arrow, signifying that the data lines are sampled on the rising edge. When performing multiple word reads or writes, the data address is automatically incremented to the next consecutive address for subsequent transactions except for Address 0x5F, Address 0x60 (FIFO), and Address 0x7F. Rev. B | Page 20 of 61 Data Sheet ADPD188GG 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CS ADDRESS[6:0] MOSI DATA BYTE 1 DATA BYTE 2 16111-021 SCLK DATA BYTE N Figure 21. SPI Slave Write Clocking (Burst Write Mode, N Bytes) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CS SCLK ADDRESS[6:0] MOSI DATA BYTE 1 MISO DATA BYTE 2 16111-022 W/R Figure 22. SPI Slave Read Clocking (Single-Word Mode, Two Bytes) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CS SCLK MOSI ADDRESS[6:0] MISO DATA BYTE 1 DATA BYTE 2 Figure 23. SPI Slave Read Clocking (Burst Read Mode, N Bytes) Rev. B | Page 21 of 61 DATA BYTE N 16111-023 W/R ADPD188GG Data Sheet APPLICATIONS INFORMATION TYPICAL CONNECTION DIAGRAM 0.1F 1.8V For best noise performance, connect AGND, DGND, and LGND together at a large conductive surface such as a ground plane, ground pour, or large ground trace. DGND 20 17 ADPD188GG 6 14 GPIO0 7 13 12 9 11 GPIO1 1.8V LAND PATTERN Figure 26 shows the recommended PCB footprint (land pattern). Table 8 and Figure 4 provide the recommended soldering profile. 2.0mm 0.28mm 0.56mm VDD2 DGND 18 SCLK 17 MOSI 3 ADPD188GG 4 16 MISO 5 15 GPIO1 6 14 7 GPIO0 SDA 1.8V 12 SCL 11 LGND LED2 10 13 9 NIC LED3 NIC 8 CVLED LED1/DNC VLED1 0.18mm Figure 26. Land Pattern Figure 24. SPI Mode Connection Diagram Rev. B | Page 22 of 61 16111-026 20 AGND 21 VREF 22 2 0.1F VLED1 0.2mm 16111-024 1.8V 23 VDD1 EXT_IN1 24 NIC 3.0mm CS 1.8V SCL 10k 0.3mm 19 10k SDA 1.0F 1 MISO 15 0.1F PDC MOSI Figure 25. I2C Mode Connection Diagram 1.8V EXT_IN2 1.8V SCLK 5 8 NIC 16 SCL NIC 10 VLED1 CS 16111-025 VREF AGND 21 23 3 4 0.1F CVLED 18 LED2 VDD2 2 LGND NIC VLED1 22 VDD1 EXT_IN1 24 EXT_IN2 1.8V 19 1 LED3 Provide a regulated 1.8 V supply, tied to VDD1 and VDD2. The VLEDx level uses a standard regulator circuit according to the peak current requirements specified in Table 1 and calculated in the Calculating Current Consumption section. Place 0.1 F ceramic decoupling capacitors as close as possible to VDD1 and VDD2; a 1.0 F ceramic capacitor must be placed as close as possible to the VREF pin. PDC LED1/DNC Figure 24 shows the recommended connection diagram for the ADPD188GG using the SPI communications port. Figure 25 shows a circuit using the I2C port. The desired communications port, together with the GPIO0 and GPIO1 lines, connects to a system microprocessor or sensor hub. When using the SPI port, the I2C interface must be disabled by connecting the SDA and SCL pins high to 1.8 V. When using the I2C interface, the SPI is disabled by connecting CS to 1.8 V. Tie the unused inputs, SCLK and MOSI, to ground. The EXT_IN1 and EXT_IN 2 pins are current inputs and can be connected to external sensors. A voltage source can be connected to the EXT_IN1 and EXT_IN2 pins through a series resistance, effectively converting the voltage into a current (see the Using the EXT_IN 1 and EXT_IN 2 Inputs with a Voltage Source section). 1.0F Data Sheet ADPD188GG RECOMMENDED START-UP SEQUENCE Reading Data Using the FIFO At power-up, the device is in standby mode (Register 0x10 = 0x0), as shown in Figure 17. The ADPD188GG does not require a particular power-up sequence. The ADPD188GG includes a 128-byte FIFO memory buffer that can be configured to store data from either or both time slots. Register 0x11 selects the type of data from each time slot to be written to the FIFO. Note that both time slots can be enabled to use the FIFO, but only if their output data rate is the same. From standby mode, to begin measurement, initiate the ADPD188GG as follows: 1. 2. 3. 4. Set the CLK32K_EN bit (Register 0x4B, Bit 7) to start the sample clock (32 kHz clock). This clock controls the state machine. If this clock is off, the state machine is not able to transition as defined by Register 0x10. Write 0x1 to Register 0x10 to force the device into program mode. Step 1 and Step 2 can be swapped, but the actual state transition does not occur until both steps occur. Write additional control registers in any order while the device is in program mode to configure the devices as required. Write 0x2 to Register 0x10 to start normal sampling operation. To terminate normal operation, follow this sequence to place the ADPD188GG in standby mode: 1. 2. 3. 4. 5. Write 0x1 to Register 0x10 to force the devices into program mode. Write to the registers in any order while the devices are in program mode. Write 0x00FF to Register 0x00 to clear all interrupts. If desired, clear the FIFO as well by writing 0x80FF to Register 0x00. Write 0x0 to Register 0x10 to force the devices into standby mode. Optionally, stop the 32 kHz clock by resetting the CLK32K_ EN bit (Register 0x4B, Bit 7). Register 0x4B, Bit 7 = 0 is the only write that must be written when the device is in standby mode (Register 0x10 = 0x0). If 0 is written to this bit while in program mode or normal mode, the devices become unable to transition into any other mode, including standby mode, even if they are subsequently written to do so. As a result, the power consumption in what appears to be standby mode is greatly elevated. For this reason, and due to the very low current draw of the 32 kHz clock while in operation, it is recommended from an ease of use perspective to keep the 32 kHz clock running after it is turned on. Output Data Rate = fSAMPLE/Nx where: fSAMPLE is the sampling frequency. Nx is the averaging factor for each time slot (NA for Time Slot A and NB for Time Slot B). In other words, NA = NB must be true to store data from both time slots in the FIFO. Data packets are written to the FIFO at the output data rate. A data packet for the FIFO consists of a complete sample for each enabled time slot. Data for each photodiode channel can be stored as either 16 or 32 bits. Each time slot can store 2, 4, 8, or 16 bytes of data per sample, depending on the mode and data format. To ensure that data packets are intact, new data is only written to the FIFO if there is sufficient space for a complete packet. Any new data that arrives when there is not enough space is lost. The FIFO continues to store data when sufficient space exists. Always read FIFO data in complete packets to ensure that data packets remain intact. The number of bytes currently stored in the FIFO is available in Register 0x00, Bits[15:8]. A dedicated FIFO interrupt is also available and automatically generates when a specified amount of data is written to the FIFO. Interrupt-Based Method To read data from the FIFO using an interrupt-based method, use the following procedure: 1. 2. 3. 4. READING DATA The ADPD188GG provides multiple methods for accessing the sample data. Each time slot can be independently configured to provide data access using the FIFO or the data registers. Interrupt signaling is also available to simplify timely data access. The FIFO is available to loosen the system timing requirements for data accesses. 5. 6. Rev. B | Page 23 of 61 In program mode, set the configuration of the time slots as desired for operation. Write Register 0x11 with the desired data format for each time slot. Set FIFO_THRESH in Register 0x06, Bits[13:8] to the interrupt threshold. A recommended value for this is the number of 16-bit words in a data packet, minus 1. This causes an interrupt to generate when there is at least one complete packet in the FIFO. Enable the FIFO interrupt by writing a 0 to the FIFO_ INT_MASK in Register 0x01, Bit 8. Also, configure the interrupt pin (GPIO0) by writing the appropriate value to the bits in Register 0x02. Enter normal operation mode by setting Register 0x10 to 0x2. When an interrupt occurs, a. There is no requirement to read the FIFO_SAMPLES bits, because the interrupt is generated only if there is one or more full packets. Optionally, the interrupt routine can check for the presence of more than one available packet by reading these bits. ADPD188GG Data Sheet b. Read a complete packet using one or more multiword accesses using Register 0x60. Reading the FIFO automatically frees the space for new samples. 3. 4. The FIFO interrupt automatically clears immediately upon reading any data from the FIFO and is set again only when the FIFO is written and the number of words is above the threshold. Polling Method To read data from the FIFO in a polling method, use the following procedure: 1. 2. 3. In program mode, set the configuration of the time slots as desired for operation. Write Register 0x11 with the desired data format for each time slot. Enter normal operation mode by setting Register 0x10 to 2. Next, begin the polling operations. 1. 2. 3. Wait for the polling interval to expire. Read the FIFO_SAMPLES bits (Register 0x00, Bits[15:8]). If FIFO_SAMPLES the packet size, read a packet using the following steps: a. Read a complete packet using one or more multiword accesses via Register 0x60. Reading the FIFO automatically frees the space for new samples. b. Repeat Step 1. When a mode change is required, or any other disruption to normal sampling is necessary, the FIFO must be cleared. Use the following procedure to clear the state and empty the FIFO: 1. 2. Enter program mode by setting Register 0x10 to 0x1. Write 1 to Register 0x00, Bit 15. If both time slots are in use, it is possible to use only the Time Slot B interrupt to signal when all registers can be read. It is recommended to use the multiword read to transfer the data from the data registers. Reading Data from Registers Without Interrupts If the system interrupt response is not fast or predictable enough to use the interrupt method, or if the interrupt pin (GPIOx) is not used, it is possible to obtain reliable data access by using the data hold mechanism. To guarantee that the data read from the registers is from the same sample time, it is necessary to prevent the update of samples while reading the current values. The method for doing register reads without interrupt timing is as follows: 1. 2. 3. Reading Data from Registers Using Interrupts The latest sample data is always available in the data registers and is updated simultaneously at the end of each time slot. The data value for each photodiode channel is available as a 16-bit value in Register 0x64 through Register 0x67 for Time Slot A, and Register 0x68 through Register 0x6B for Time Slot B. If allowed to reach their maximum value, Register 0x64 through Register 0x6B clip. If Register 0x64 through Register 0x6B saturate, the unsaturated (up to 27 bits) values for each channel are available in Register 0x70 through Register 0x77 for Time Slot A and Register 0x78 through Register 0x7F for Time Slot B. Sample interrupts are available to indicate when the registers are updated and can be read. To use the interrupt for a given time slot, use the following procedure: 1. 2. Enable the sample interrupt by writing a 0 to the appropriate bit in Register 0x01. To enable the interrupt for Time Slot A, write 0 to Bit 5. To enable the interrupt for Time Slot B, write 0 to Bit 6. Either or both interrupts can be set. Configure the interrupt pin (GPIOx) by writing the appropriate value to the bits in Register 0x02. An interrupt generates when the data registers are updated. The interrupt handler must perform the following: a. Read Register 0x00 and observe Bit 5 or Bit 6 to confirm which interrupt has occurred. This step is not required if only one interrupt is in use. b. Read the data registers before the next sample can be written. The system must have interrupt latency and service time short enough to respond before the next data update, based on the output data rate. c. Write a 1 to Bit 5 or Bit 6 in Register 0x00 to clear the interrupt. Write a 1 to SLOTA_DATA_HOLD or SLOTB_DATA_ HOLD (Register 0x5F, Bit 1 and Bit 2, respectively) for the time slot requiring access (both time slots can be accessed). This setting prevents sample updates. Read the registers as desired. Write a 0 to the SLOTA_DATA_HOLD or SLOTB_DATA_ HOLD bits (Register 0x5F, Bit 1 and Bit 2, respectively) previously set. Sample updates are allowed again. Because a new sample may arrive while the reads are occurring, this method prevents the new sample from partially overwriting the data being read. CLOCKS AND TIMING CALIBRATION The ADPD188GG operates using two internal time bases. A 32 kHz clock sets the sample timing, and a 32 MHz clock controls the timing of internal functions such as LED pulsing and data capture. Both clocks are internally generated and exhibit device to device variation of approximately 10% (typical). Heart rate monitoring (HRM) applications require an accurate time base to achieve an accurate count of beats per minute. The ADPD188GG provides a simple calibration procedure for both clocks. Calibrating the 32 kHz Clock This procedure calibrates items associated with the output data rate. Calibration of this clock is important for items where an accurate data rate is important, such as heart rate measurements. Rev. B | Page 24 of 61 Data Sheet ADPD188GG To calibrate the 32 kHz clock, 1. Set the sampling frequency to the highest the system can handle, such as 2000 Hz. Because the 32 kHz clock controls sample timing, its frequency is readily accessible via the GPIO0 pin. Configure the interrupt by writing the appropriate value to Bits[2:0] in Register 0x02 and set the interrupt to occur at the sampling frequency by writing 0x0 to Register 0x01, Bit 5 or Bit 6. Monitor the GPIO0 pin. The interrupt frequency must match the set sample frequency. 2. If the monitored interrupt frequency is less than the set sampling frequency, decrease the CLK32K_ADJUST bits (Register 0x4B, Bits[5:0]). If the monitored interrupt frequency is larger than the set sampling frequency, increase the CLK32K_ADJUST bits. 3. Repeat Step 1 until the monitored interrupt signal frequency is close to the set sampling frequency. OPTIONAL TIMING SIGNALS AVAILABLE ON GPIO0 AND GPIO1 The ADPD188GG provides a number of different timing signals, available via the GPIO0 and GPIO1 pins, to enable ease of system synchronization and flexible triggering options. Each GPIOx pin can be configured as an open-drain output if they are sharing the bus with other drivers, or they can be configured to always drive the bus. Both outputs also have polarity control in situations where a timing signal must be inverted from the default. Table 16. GPIOx Control Settings Pin Name GPIO0 Register, Bits 0x02, Bit 0 0x02, Bit 1 0x02, Bit 2 Calibrating the 32 MHz Clock This procedure calibrates items associated with the fine timing within a sample period, such as LED pulse width and spacing, and assumes that the 32 kHz clock is already calibrated. GPIO1 0x02, Bit 8 0x02, Bit 9 To calibrate the 32 MHz clock, 3. 4. 5. 6. 7. Write 0x1 to Register 0x5F, Bit 0. Enable the CLK_RATIO calculation by writing 0x1 to Register 0x50, Bit 5 (CLK32M_CAL_EN). This function counts the number of 32 MHz clock cycles in two cycles of the 32 kHz clock. With this function enabled, this value is stored in Register 0x0A, Bits[11:0] and nominally this ratio is 2000 (0x07D0). Calculate the 32 MHz clock error as follows: Clock Error = 32 MHz x (1 - CLK_RATIO/2000) Adjust the frequency by setting Bits[7:0] in Register 0x4D per the following equation: CLK32M_ADJUST = Clock Error/109 kHz Write 0x0 to Register 0x50, Bit 5 to reset the CLK_RATIO function. Repeat Step 1 through Step 5 until the desired accuracy is achieved. Write 0x1 to Register 0x5F, Bit 0, and set the GPIO0 pin back to the mode desired for normal operation. SLOT A SLOT B 0x4F, Bit 6 The various available timing signals are controlled by the settings in Register 0x0B, Bits[12:8] of this register control the timing signals available on GPIO1, and Bits[4:0] control the timing signals available on GPIO0. All of the timing signals described in this data sheet are available on either (or both) of the GPIO0 and GPIO1 pins. Timing diagrams are shown in Figure 27 and Figure 28. The time slot settings used to generate the timing diagrams are described in Table 17. Table 17. ADPD188GG Settings Used for the Timing Diagrams Shown in Figure 27 and Figure 28 Register 0x31 0x36 0x15 SLEEP Setting 0x0118 0x0418 0x0120 SLOT A Description Time Slot A: 1 LED pulse Time Slot B: 4 LED pulses Time Slot A decimation = 4, Time Slot B decimation = 2 SLOT B 16111-027 1. 2. Setting Description 0: polarity active high 1: polarity active low 0: always drives the bus 1: drives the bus when asserted 0: disables the GPIO0 pin drive 1: enables the GPIO0 pin drive 0: polarity active high 1: polarity active low 0: always drives the bus 1: drives the bus when asserted 0: disables the GPIO1 pin drive 1: enables the GPIO1 pin drive Figure 27. Optional Timing Signals Available on GPIOx--Register 0x0B, Bits[12:8] or Bits[4:0] = 0x02, 0x05, 0x06, 0x07, and 0x0F Rev. B | Page 25 of 61 ADPD188GG SLOT A/B Data Sheet SLEEP SLOT A/B SLEEP SLOT A/B SLEEP SLOT A/B SLEEP SLOT A/B SLEEP SLOT A/B 0x02 0x0C 16111-028 0x0D 0x0E Figure 28. Optional Timing Signals Available on GPIOx--Register 0x0B, Bits[12:8] or Bits[4:0] = 0x02, 0x0C, 0x0D, and 0x0E Interrupt Function fS/2 Output Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x01 configures the respective pin to perform the interrupt function as defined by the settings in Register 0x01. Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x0F configures the respective pin to provide a signal that toggles at half the sampling rate. The fS/2 timing signal always starts in an active low state when the device switches from standby mode to normal operating mode and transitions to a high state at the completion of the first sample. Sample Timing Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x02 configures the respective pin to provide a signal that asserts at the beginning of the first time slot of the current sample and deasserts at the end of the last time slot of the current sample. For example, if both time slots are enabled, this signal asserts at the beginning of Time Slot A and deasserts at the end of Time Slot B. If only a single time slot is enabled, the signal asserts at the beginning of the enabled time slot and deasserts at the end of this same time slot. Pulse Outputs Three options are available to provide a copy of the LED pulse outputs. Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x05 provides a copy of the Time Slot A LED pulses on the respective pin. A setting of 0x06 provides the Time Slot B pulses, and a setting of 0x07 provides the pulse outputs of both time slots. Output Data Cycle Signal There are three options available to provide a signal that indicates when the output data is written to the output data registers or to the FIFO. Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x0C provides a signal that indicates that a data value is written for Time Slot A. A setting of 0x0D provides a signal that indicates that a data value is written for Time Slot B, and 0x0E provides a signal to indicate that a value is written for either time slot. The signal asserts at the end of the time slot, when the output data is already written, and deasserts at the start of the subsequent sample. This timing signal is especially useful in situations where the FIFO is being used. For example, one of the GPIOx pins can be configured to provide an interrupt after the FIFO reaches the FIFO threshold set in Register 0x06, Bits[13:8], while the other GPIOx pin can be configured to provide the output data cycle signal. This signal can be used to trigger a peripheral device, such as an accelerometer, so that time aligned signals are provided to the processor. Logic 0 Output Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x10 configures the respective pin to provide a Logic 0 output. Logic 1 Output Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x11 configures the respective pin to provide a Logic 1 output. 32 kHz Oscillator Output Setting Register 0x0B, Bits[12:8] or Bits[4:0] = 0x13 configures the respective pin to provide a copy of the on-board 32 kHz oscillator. LED DRIVER PINS AND LED SUPPLY VOLTAGE The LED driver pins (LED1/DNC, LED2, and LED3) have an absolute maximum voltage rating of 3.6 V. Any voltage exposure over this rating affects the reliability of the device operation and, in certain circumstances, causes the device to completely cease proper operation. The voltage of the LED driver pins must not be confused with the supply voltages for the LEDs themselves (VLED1 and VLED2). These are the voltages applied to the anodes of the internal LEDs connected at VLED1. LED DRIVER OPERATION The LED drivers for the ADPD188GG are current sinks. Typical LED driver current vs. LED driver voltage is shown in Figure 9. Figure 24 shows the basic schematic of how the ADPD188GG connects to an LED through the LED driver. The Determining the Average Current section and the Determining CVLED section define the requirements for the bypass capacitor (CVLED) and the supply voltages of the LEDs (VLED). Rev. B | Page 26 of 61 Data Sheet ADPD188GG DETERMINING THE AVERAGE CURRENT When the ADPD188GG drives an LED, it drives the LED in a series of short pulses. Figure 29 shows the typical ADPD188GG configuration of a pulse burst sequence. In this sequence, the LED pulse width, tLED_PULSE, is 3 s, and the LED pulse period, tLED_PERIOD, is 19 s. The goal of CVLED is to buffer the LED between individual pulses. In the worst case scenario, where the pulse train shown in Figure 29 is a continuous sequence of short pulses, the VLED supply must supply the average current. Therefore, calculate ILED_AVERAGE as follows: ILED_AVERAGE = (tLED_PULSE/tLED_PERIOD) x ILED_PEAK LED FORWARD-BIAS VOLTAGE (V) 4.5 4.0 3.5 3.0 2.5 where: ILED_AVERAGE is the average current needed from the VLED supply. It is also the VLED supply current rating. ILED_PEAK is the peak current setting of the LED. For the numbers shown in Figure 29, ILED_AVERAGE = 3/19 x ILED_PEAK. For typical LED timing, the average VLED supply current is 3/19 x 250 mA = 39.4 mA, indicating that the VLED supply must support a dc current of 40 mA. 19s 2.0 LED DRIVER CURRENT (mA) 16111-030 (1) Figure 30. Typical LED Forward-Bias Voltage Drop as a Function of the LED Driver Current For the CVLED capacitor to be sized correctly, do not deplete it during the pulse of the LED to the point where the voltage on the capacitor is less than the forward-bias on the LED. To calculate the minimum value for the VLED bypass capacitor, use the following equation: CVLED = 3s t LED_PULSE x I LED _ PEAK VLED _ MIN - (VFB _ LED _ MAX + 0.6) (2) where: tLED_PULSE is the LED pulse width. ILED_PEAK is the maximum forward-bias current on the LED used in operating the device. VLED_MIN is the lowest voltage from the VLED supply with no load. VFB_LED_MAX is the maximum forward-bias voltage required on the LED to achieve ILED_PEAK. 16111-029 ILEAD_PEAK Figure 29. Typical LED Pulse Burst Sequence Configuration DETERMINING CVLED To determine the CVLED capacitor value, determine the maximum forward-bias voltage, VFB_LED_MAX, of the LED in operation. From Figure 30, ILED_PEAK converts to VFB_LED_MAX. For example, with a 200 mA current, VFB_LED_MAX is 3.65 V. Any series resistance in the LED path must also be included in this voltage. When designing the LED path, keep in mind that small resistances can add up to large voltage drops when a 200 mA current is driven through the resistor. These resistances can be unnecessary constraints on the VLED supply. The numerator of the CVLED equation sets up the total discharge amount in coulombs from the bypass capacitor to satisfy a single programmed LED pulse of the maximum current. The denominator represents the difference between the lowest voltage from the VLED supply and the LED required voltage. The LED required voltage is the voltage of the anode of the LED such that the 0.6 V compliance of the LED driver at 200 mA and the forward-bias voltage of the LED operating at the maximum current is satisfied. For a typical ADPD188GG example, assume that the lowest value for the VLED supply is 4.4 V, and that the peak current is 200 mA for two 525 nm LEDs in parallel. The minimum value for CVLED is then equal to 4 F. CVLED = (3 x 10-6 x 0.20)/(4.4 - (3.65 + 0.6)) = 4.0 F (3) As shown in Equation 3, the minimum supply voltage drops close to the maximum anode voltage, and the demands on CVLED become more stringent, forcing the capacitor value higher. It is important to plug the correct values into these equations. For example, using an average value for VLED_MIN instead of the worst-case value for VLED_MIN can cause a problem; therefore, adding sufficient margin on CVLED is strongly recommended. Rev. B | Page 27 of 61 ADPD188GG Data Sheet tSLOTx (sec) = LEDx_OFFSET + LEDx_PERIOD x PULSE_COUNT USING EXTERNAL LEDS The ADPD188GG LED driver is also connected to an external package pin so that the driver can drive external LEDs, if desired. Figure 31 shows a connection diagram that enables driving external LEDs. VDD = 1.8V VLED C2 1F VDD1 VDD2 VLEDx CVLED LED1 C3 0.1F NC ADPD188GG VREF SCL SDA GPIOx where: NUM_CHANNELS is the number of active channels. ILEDX_PK is the peak LED current, expressed in amps, for the LED enabled in that particular time slot. SCALE_X is the scale factor for the LED current drive determined by Bit 13 of the ILED_COARSE register. LEDx_OFFSET is the pulse start time offset expressed in seconds. LEDx_PERIOD is the pulse period expressed in seconds. PULSE_COUNT is the number of pulses. Note that if either Time Slot A or Time Slot B are disabled, IAFE_x = 0 for that respective time slot. TO HOST PROCESSOR LGND DGND AGND LEDx/DNC Average VLEDA Supply Current 16111-031 To calculate the average VLEDA supply current, use Equation 8. ILED_AVG_A = SLOTA_LED_WIDTH x ILEDA_PK x DR x PULSE_COUNT Figure 31. Using the ADPD188GG LED Drivers to Drive External LEDs CALCULATING CURRENT CONSUMPTION The current consumption of the ADPD188GG depends on the user selected operating configuration, as described in the following equations. Total Power Consumption (8) where: SLOTA_LED_WIDTH is the LED pulse width expressed in seconds. ILEDA_PK is the peak current, expressed in amps, for the Time Slot A LED. Average VLEDB Supply Current To calculate the total power consumption, use Equation 4. Total Power = IVDD_AVERAGE x VDD + ILED_AVERAGE x VLED (4) where: IVDD_AVERAGE is the average VDD supply current (supplied at VDD1 and VDD2). VDD is the voltage applied at the VDD1 and VDD2 pins. ILED_AVERAGE is the average LED supply current. VLED is the voltage at the VLEDx pins, respectively. To calculate the average VLEDB supply current, use Equation 9. ILED_AVG_B = SLOTB_LED_WIDTH x ILEDB_PK x DR x PULSE_COUNT (9) where: SLOTB_LED_WIDTH is the LED pulse width expressed in seconds. ILEDB_PK is the peak current, expressed in amps, for the Time Slot B LED. Average VDD Supply Current Optimizing SNR per Watt in a Signal Limited System To calculate the average VDD supply current, use Equation 5. IVDD_AVG = DR x ((IAFE_A x tSLOTA) + (IAFE_B x tSLOTB) + QPROC_x) + IVDD_STANDBY (7) (5) where: DR is the data rate in Hz. IVDD_STANDBY = 0.2 A. QPROC_x is an average charge associated with a processing time, as follows: When only Time Slot A is enabled, QPROC_A (C) = 0.35 x 10-6 When only Time Slot B is enabled, QPROC_B (C) = 0.24 x 10-6 When Time Slot A and Time Slot B are enabled, QPROC_AB (C) = 0.40 x 10-6 IAFE_x (A) = 3.0 x 10-3 + (1.5 x 10-3 x NUM_CHANNELS) + (6) (4.6 x 10-3 x ILEDX_PK/ SCALE_X) In practice, optimizing for peak SNR is not always practical. One scenario in which the PPG signal has a poor SNR is the signal limited regime. In this scenario, the LED current reaches an upper limit before the desired dc return level is achieved. Tuning in this case starts where the peak SNR tuning stops. The starting point is nominally a 50k gain, as long as the lowest LED current setting of 12 mA does not saturate the photodiode and the 50k gain provides enough protection against intense background light. In these cases, use a 25k gain as the starting point. The goal of the tuning process is to bring the dc return signal to a specific ADC range, such as 50% or 60%. The ADC range choice is a function of the margin of headroom needed to prevent saturation as the dc level fluctuates over time. The SNR of the PPG waveform is always some percentage of the dc level. If the target level cannot be achieved at the base gain, increase the gain and repeat the procedure. The tuning system may need to place an upper limit on the gain to prevent saturation from ambient signals. Rev. B | Page 28 of 61 Data Sheet ADPD188GG Tuning the Pulse Count After the LED peak current and TIA gain are optimized, increasing the number of pulses per sample increases the SNR by the square root of the number of pulses. There are two ways to increase the pulse count. The pulse count registers (Register 0x31, Bits[15:8], and Register 0x36, Bits[15:8]) change the number of pulses per internal sample. Register 0x15, Bits[6:4] and Bits[10:8], controls the number of internal samples that are averaged together before the data is sent to the output. Therefore, the number of pulses per sample is the pulse count register multiplied by the number of subsequent samples being averaged. In general, the internal sampling rate increases as the number of internal sample averages increase to maintain the desired output data rate. The SNR/watt is most optimal with pulse count values of 16 or less. Above pulse count values of 16, the square root relationship does not hold in the pulse count register. However, this relationship continues to hold when averaged between samples using Register 0x15. Note that increasing LED peak current increases SNR almost directly proportional to LED power, whereas increasing the number of pulses by a factor of n results in only a nominal (n) increase in SNR. When using the sample sum/average function (Register 0x15), the output data rate decreases by the number of summed samples. To maintain a static output data rate, increase the sample frequency (Register 0x12) by the same factor as that selected in Register 0x15. For example, for a 100 Hz output data rate and a sample sum/average of four samples, set the sample frequency to 400 Hz. Improving SNR Using Integrator Chopping The last stage in the analog front end that is integrated into the ADPD188GG data path is a charge integrator. The integrator uses an on and off integration sequence, synchronized to the emitted light pulse, which acts as an additional high-pass filter to remove offsets, drifts, and low frequency noise from the previous stages. However, the integrating amplifier can itself introduce low frequency signal content at a low level. The ADPD188GG has an integrator chop mode that enables additional chopping in the digital domain to remove this signal. This chopping is achieved by using even numbers of pulses per sample and inverting the integration sequence for half of those sequences. In the calculation to combine the digitized result of each of the pulses of the sample, the sequences with an inverted integrator sequence are subtracted and the sequences with a normal integrator sequence are added. An example diagram of the integrator chopping sequence is shown in Figure 32. The result is that any low frequency signal contribution from the integrator is eliminated, leaving only the integrated signal, which results in higher SNR, especially at higher numbers of pulses and at lower TIA gains where the noise contribution of the integrator becomes more pronounced. Digital chopping is enabled using the registers and bits detailed in Table 18. The bit fields define the chopping operation for the first four pulses. This 4-bit sequence is then repeated for all subsequent pulses. In Figure 32, a sequence is shown where the second and fourth pulses are inverted while the first and third pulses remain in the default polarity (noninverted). This configuration is achieved by setting Register 0x17, Bits[3:0] = 0xA and Register 0x1D, Bits[3:0] = 0xA for Time Slot A and Time Slot B, respectively. To complete the operation, the math must be adjusted using Register 0x58. In this example, set Register 0x58, Bits[9:8] and Register 0x58, Bits[11:10] to b01 to add the third pulse and subtract the fourth pulse for Time Slot A and Time Slot B, respectively. Set Register 0x58, Bits[2:1] and Register 0x58, Bits[6:5] to b01 to add the first pulse and subtract the second pulse for Time Slot A and Time Slot B, respectively. This sequence then repeats for every subsequent sequence of four pulses. An even number of pulses must be used with integrator chop mode. When using integrator chop mode, the ADC offset registers (Register 0x18 through Register 0x1B for Time Slot A, and Register 0x1E through Register 0x21 for Time Slot B) must be set to 0. These settings are required because any digital offsets at the output of the ADC are automatically eliminated when the math is adjusted to subtract the inverted integration sequences while the default integration sequences are added. Integrator chop mode also eliminates the need to manually null the ADC offsets at startup in a typical application. Note that the elimination of the offset using chop mode may clip at least half of the noise signal when no input signal is present, which makes measuring the noise floor during characterization of the system difficult. For this reason, perform noise floor characterization of the system either with chop mode disabled or with chop mode enabled but with a minimal signal present at the input that increases the noise floor enough such that it is no longer clipped. Rev. B | Page 29 of 61 ADPD188GG Data Sheet PULSE 1 PULSE 2 PULSE 3 PULSE 4 LED BAND-PASS FILTER OUTPUT + - - + + - - + ADC + - + - 16111-129 INTEGRATOR SEQUENCE Figure 32. Diagram of Integrator Chopping Sequence Table 18. Register Settings for Integrator Chop Mode Hex Addr. 0x17 Data Bit(s) [3:0] Bit Name INTEG_ORDER_A 0x1D [3:0] INTEG_ORDER_B 0x58 [11:10] FLT_MATH34_B [9:8] FLT_MATH34_A [6:5] FLT_MATH12_B [2:1] FLT_MATH12_A Description Integration sequence order for Time Slot A. Each bit corresponds to the polarity of the integration sequence of a single pulse in a four-pulse sequence. Bit 0 controls the integration sequence of Pulse 1, Bit 1 controls Pulse 2, Bit 2 controls Pulse 3, and Bit 3 controls Pulse 4. After four pulses, the sequence repeats. 0: normal integration sequence. 1: reversed integration sequence. Integration sequence order for Time Slot B. Each bit corresponds to the polarity of the integration sequence of a single pulse in a four-pulse sequence. Bit 0 controls the integration sequence of Pulse 1, Bit 1 controls Pulse 2, Bit 2 controls Pulse 3, and Bit 3 controls Pulse 4. After four pulses, the sequence repeats. 0: normal integration sequence. 1: reversed integration sequence Time Slot B control for adding and subtracting Sample 3 and Sample 4 in a four-pulse sequence (or any multiple of four pulses, for example, Sample 15 and Sample 16 in a 16-pulse sequence). 00: add third and fourth. 01: add third and subtract fourth. 10: subtract third and add fourth. 11: subtract third and fourth. Time Slot A control for adding and subtracting Sample 3 and Sample 4 in a four-pulse sequence (or any multiple of four pulses, for example, Sample 15 and Sample 16 in a 16-pulse sequence). 00: add third and fourth. 01: add third and subtract fourth. 10: subtract third and add fourth. 11: subtract third and fourth. Time Slot B control for adding and subtracting Sample 1 and Sample 2 in a four-pulse sequence (or any multiple of four pulses, for example, Sample 13 and Sample 14 in a 16-pulse sequence). 00: add first and second. 01: add first and subtract second. 10: subtract first and add second. 11: subtract first and second. Time Slot A control for adding and subtracting Sample 1 and Sample 2 in a four-pulse sequence (or any multiple of four pulses, for example, Sample 13 and Sample 14 in a 16-pulse sequence). 00: add first and second. 01: add first and subtract second. 10: subtract first and add second. 11: subtract first and second. Rev. B | Page 30 of 61 Data Sheet ADPD188GG MECHANICAL CONSIDERATIONS FOR COVERING THE ADPD188GG from the photodiode increases, the ADC output decreases toward 0. In some applications, it may be necessary to cover the ADPD188GG to protect it from moisture. The ADPD188GG is designed with this requirement in mind. The unique cross section of the device, as shown in Figure 13, prevents light from going directly from the LED to the detector even with a reasonably thick window. It is recommended that the window thickness be <0.7 mm and the air gap between the module and the window be kept to <0.5 mm for optimal operation. When configuring the integrator as a buffer, there is the option of either using a gain of 1 or a gain of 0.7. Using the gain of 0.7 increases the usable dynamic range at the input to the TIA. The buffer gain is set using Register 0x42, Bit 9 for Time Slot A and Register 0x44, Bit 9 for Time Slot B. Setting this bit to 0 (default) sets a gain of 1. Setting this bit to 1 configures the buffer with a gain of 0.7. The ADC output (ADCOUT) is calculated as follows: TIA ADC MODE Figure 33 shows a way to put the ADPD188GG into a mode that effectively runs the TIA directly into the ADC without using the analog band-pass filter (BPF) and integrator. This mode is referred to as TIA ADC mode. There are two basic applications of TIA ADC mode. In normal operation, all of the background light is blocked from the signal chain, and therefore, cannot be measured. TIA ADC mode can measure the amount of background and ambient light. This mode can also measure other dc input currents, such as leakage resistance. VIN RS ADPD188GG OPTIONAL BUFFER R_IN TIA ADC 16111-032 TIA_VREF Figure 33. TIA ADC Mode Block Diagram When the devices are in TIA ADC mode, the BPF and the integrator stage are bypassed. This bypass effectively wires the TIA directly into the ADC. At the set sampling frequency, the ADC samples Channel 1 through Channel 4 in sequential order, and each sample is taken at 1 s intervals. There are two modes of operation in TIA ADC mode. One mode is an inverting configuration where TIA ADC mode directly drives the ADC. This mode is enabled by setting Register 0x43 (Time Slot A) and/or Register 0x45 (Time Slot B) to 0xB065, which bypasses the BPF and the integrator. With the ADC offset register(s) for the desired channel set to 0 and the TIA_VREF set to 1.265 V, the output of the ADC is at ~13,000 codes for a single pulse and a zero input current condition. As the input current from the photodiode increases, the ADC output decreases toward 0. The recommended TIA ADC mode is one in which the BPF is bypassed and the integrator is configured as a buffer. This mode is enabled by writing 0xAE65 to Register 0x43 (Time Slot A) and/or Register 0x45 (Time Slot B) to bypass the BPF. Additionally, to configure the integrator as a buffer, set Bit 7 of Register 0x42 (Time Slot A) and/or Register 0x44 (Time Slot B) to 1, and set Bit 7 of Register 0x58 to 1. With the ADC offset register(s) for the desired channel set to 0 and TIA_VREF set to 1.265 V, the output of the ADC is at ~13,000 codes for a single pulse and a zero input current condition. As the input current ADCOUT = 8192 (((2 x TIA_VREF - 2 x i x RF - 1.8 V)/ 146 V/LSB) x SLOTx_BUF_GAIN) (11) where: TIA_VREF is the bias voltage for the TIA (the default value is 1.265 V). i is the input current to the TIA. RF is the TIA feedback resistor. SLOTx_BUF_GAIN is either 0.7 or 1, based on the setting of Register 0x42, Bit 9 and Register 0x44, Bit 9. Equation 11 is an approximation and does not account for internal offsets and gain errors. The calculation also assumes that the ADC offset registers are set to 0. One time slot can be used in TIA ADC mode at the same time the other time slot is being used in normal pulsed mode. This capability is useful for monitoring ambient and pulsed signals at the same time. The ambient signal is monitored during the time slot configured for TIA ADC mode, while the pulsed signal, with the ambient signal rejected, is monitored in the time slot configured for normal mode. Protecting Against TIA Saturation in Normal Operation One of the reasons to monitor TIA ADC mode is to protect against environments that may cause saturation. One concern when operating in high light conditions, especially with larger photodiodes, is that the TIA stage may become saturated while the ADPD188GG continue to communicate data. The resulting saturation is not typical. The TIA, based on its settings, can only handle a certain level of photodiode current. Based on the way the ADPD188GG is configured, if there is a current level from the photodiode that is larger than the TIA can handle, the TIA output during the LED pulse effectively extends the current pulse, making it wider. The AFE timing is then violated because the positive portion of the band-pass filter output extends into the negative section of the integration window. Thus, the photosignal is subtracted from itself, causing the output signal to decrease when the effective light signal increases. To measure the response from the TIA and verify that this stage is not saturating, place the device in TIA ADC mode and slightly modify the timing. Specifically, sweep SLOTx_AFE_OFFSET until two or three of the four channels reach a minimum value (note that TIA is in an inverting configuration). All four channels do not reach this minimum value because, typically, 3 s LED pulse widths are used and the ADC samples the four channels Rev. B | Page 31 of 61 ADPD188GG Data Sheet To ensure that the TIA does not saturate, a safe operating region is typically at 3/4 full scale and lower. Use Table 19 to determine how the output codes map to ADC levels on a per channel per pulse basis. These codes are not the same as in normal mode because the band-pass filter and integrator are not unity-gain elements. Measuring PCB Parasitic Input Resistance During the process of mounting the ADPD188GG, undesired resistance can develop on the inputs through assembly errors or debris on the PCB. These resistances can form between the anode and cathode, or between the anode and some other supply or ground. In normal operation, the ambient rejection feature of the ADPD188GG masks the primary effects of these resistances, making it very difficult to detect them. However, even at 1 M to 10 M, such resistance can impact performance significantly through added noise or decreased dynamic range. TIA ADC mode can be used to screen for these assembly issues. Measuring Shunt Resistance on the Photodiode A shunt resistor across the photodiode/EXT_INx does not generally affect the output level of the device in operation because the effective impedance of the TIA is very low, especially if the photodiode is held to 0 V in operation. However, such resistance can add noise to the system, degrading performance. The best way to detect photodiode leakage, also called photodiode shunt resistance, is to place the device in TIA ADC mode in the dark and vary the operation mode cathode voltage. Setting the cathode to 1.3 V places 0 V across the photodiode because the anode is always at 1.3 V while in operation. Setting the cathode to 1.8 V places 0.5 V across the photodiode. Using the register settings in Table 1 to control the cathode voltage, measure the TIA ADC value at both voltages. Next, divide the voltage difference of 0.5 V by the difference of the ADC result after converting it to a current. This result is the approximate shunt resistance. Values greater than 10 M may be difficult to measure, but this method is useful in identifying gross failures. Measuring TIA Input Shunt Resistance A resistance to develop between the TIA input and another supply or ground on the PCB is an example of another problem that can occur. These resistances can force the TIA into saturation prematurely. This premature saturation, in turn, takes away dynamic range from the device in operation and adds a Johnson noise component to the input. To measure these resistances, place the device in TIA ADC mode in the dark and start by measuring the TIA ADC offset level with the photodiode inputs disconnected (Register 0x14, Bits[11:8] = 0 or Register 0x14, Bits[7:4] = 0). From this, subtract the value of TIA ADC mode with the darkened photodiode connected and convert the difference into a current. If the value is positive, and the ADC signal decreased, the resistance is to a voltage higher than 1.3 V, such as VDD. Current entering the TIA causes the output to drop. If the output difference is negative due to an increase of codes at the ADC, current is being pulled out of the TIA and there is a shunt resistance to a lower potential than 1.3 V, such as ground. Using the EXT_IN 1 and EXT_IN 2 Inputs with a Voltage Source The ADPD188GG can be used for voltage inputs. Voltage inputs can be measured in normal mode or in TIA ADC mode. If these inputs are not a result of stimulation from the LED driver, TIA ADC mode is preferred. To understand the conversion gain from a voltage through a series resistor, RS, the current can be determined by following the schematic in Figure 34. VIN ADPD188GG OPTIONAL BUFFER RS R_IN EXT_INx TIA ADC TIA_VREF 16111-033 sequentially at 1 s intervals. This procedure aligns the ADC sampling time with the LED pulse to measure the total amount of light falling on the photodetector (for example, background light + LED pulse). Figure 34. ADPD188GG Used for Voltage Inputs Input Current = (VIN - TIA_VREF)/(RS + R_IN) Values for R_IN are listed in Table 2. R_IN is not needed for photodiode or other current inputs because the current of these inputs are not a function of the input resistance. Conversion from input current in amps to ADC codes (LSBs) follows Table 19 in TIA ADC mode. Current conversion in normal mode is listed in Table 2. The offset level shown in Table 19 represents the expected code value with zero current input. The conversion gain in nA/LSB can be added onto this for nonzero input currents. Table 19. Analog Specifications for TIA ADC Mode and Digital Integrate Mode Parameter TIA ADC Offset Level Test Conditions/Comments Floating input (Input current = 0A); Register 0x43 and Register 0x45 = 0xAE65; Register 0x42 and Register 0x44, Bit 7 = 1, Register 0x58, Bit 7 = 1 TIA_VREF = Register 0x42 and Register 0x44, Bits[5:4] = 0 (1.14 V) TIA_VREF = Register 0x42 and Register 0x44, Bits[5:4] = 1 (1.01 V) TIA_VREF = Register 0x42 and Register 0x44, Bits[5:4] = 2 (0.89 V) TIA_VREF = Register 0x42 and Register 0x44, Bits[5:4] = 3 (1.27 V); recommended for PD inputs Rev. B | Page 32 of 61 Typ Unit 11400 9700 8100 13200 LSB LSB LSB LSB Data Sheet Parameter TIA ADC Saturation Levels 1 TIA ADC Resolution 1 ADPD188GG Test Conditions/Comments Values expressed per channel, per sample; buffer gain = 1 25 k 50 k 100 k 200 k Values expressed per channel, per sample; buffer gain = 1 25 k 50 k 100 k 200 k Typ Unit 38.32 19.16 9.58 4.79 A A A A 2.92 1.5 0.73 0.37 nA/LSB nA/LSB nA/LSB nA/LSB TIA linear dynamic range is 85% of listed saturation levels Table 20. Configuration Registers to Switch Between Normal Sample Mode and TIA ADC Mode Data Bits [15:10] Bit Name SLOTA_AFE_MODE Normal Mode Value 0x07 TIA ADC Mode Value Not applicable [9] SLOTA_BUF_GAIN 0x0 0x0 [7] SLOTA_INT_AS_BUF 0x0 0x1 0x43 [15:0] SLOTA_AFE_CFG 0xADA5 0xAE65 0x44 [15:10 SLOTB_AFE_MODE 0x07 Not applicable [9] SLOTB_BUF_GAIN 0x0 0x0 [7] SLOTB_INT_AS_BUF 0x0 0x1 0x45 [15:0] SLOTB_AFE_CFG 0xADA5 0xAE65 0x58 [7] ENA_INT_AS_BUF 0x0 0x1 Address 0x42 PULSE CONNECT MODE In pulse connect mode, the photodiode input connections are pulsed according to the timing set up in the LED pulse timing registers. In this mode, if the LED pulse timing is set up to provide a 2 s LED pulse, the device pulses the connection to the photodiode input for 2 s instead of providing a 2 s LED pulse. This mode is an alternate to TIA ADC mode, allowing the entire Description In normal mode, this setting configures the integrator block for optimal operation. This setting is not important for TIA ADC mode. 0: buffer gain = 1.0. 1: buffer gain = 0.7. 0: normal integrator configuration. 1: convert integrator to buffer amplifier in TIA ADC mode (required for 0x43 = 0xAE65). Time Slot A AFE connection. 0xAE65: bypasses the band-pass filter. 0xB065: can also be used in TIA ADC mode. This setting bypasses the BPF and the integrator. In normal mode, this setting configures the integrator block for optimal operation. This setting is not important for TIA ADC mode. 0: buffer gain = 1.0. 1: buffer gain = 0.7. 0: normal integrator configuration. 1: convert integrator to buffer amplifier (required for 0x45 = 0xAE65). Time Slot B AFE connection. 0xAE65: bypasses the band-pass filter. 0xB065: can also be used in TIA ADC mode. This setting bypasses the band-pass filter (BPF) and the integrator. Enables the ability to configure the integrator as a buffer in TIA ADC mode signal path, including the band-pass filter and integrator, to be used to measure ambient light as well as other types of measurements with different types of sensors (for example, ECG). To enable pulse connect mode, the device is configured identically to normal mode, except that Register 0x14, Bits[3:2] = 0 for Time Slot B, and Register 0x14, Bits[1:0] = 0 for Time Slot A. Rev. B | Page 33 of 61 ADPD188GG Data Sheet input bias voltage must be set to the 0.90 V setting using Bits[5:4] of Register 0x42 if the ECG signal is on Time Slot A, or Register 0x44 on Time Slot B. The TIA gain setting can be set to optimize the dynamic range of the signal path. The channel used to process the PPG signal is configured in its normal operating mode. Figure 35 shows a plot of a synchronized ECG and PPG measurement using the AD8233 with the ADPD188GG. SYNCHRONOUS ECG AND PPG MEASUREMENT USING TIA ADC MODE In wearable devices developed for monitoring the health care of patients, it is often necessary to have synchronized measurements of biomedical signals. For example, a synchronous measurement of patient ECG and PPG can be used to determine the pulse wave transit time (PWTT), which can then be used to estimate blood pressure. 10000 The circuit shown in Figure 36 shows a synchronous ECG and PPG measurement using the AD8233 and the ADPD188GG. The AD8233 implements a two-pole, high-pass filter with a cutoff frequency at 0.3 Hz, and a two-pole, low-pass filter with a cutoff frequency of 37 Hz. The output of the AD8233 is fed to the EXT_IN1 current input of the ADPD188GG through a 200 k resistor to convert the voltage output of the AD8233 into a current. 52000 9000 PPG (LSBs) PPG 8500 8000 51000 ECG 7500 7000 50500 6500 16111-035 343 325 307 289 271 253 235 217 199 181 163 145 127 91 109 73 55 37 1 6000 19 50000 SAMPLE RATE (ms) Figure 35. Plot of Synchronized ECG and PPG Waveforms 4.7F 10M HPDRIVE 10M LA 180k HPSENSE 10M +IN IAOUT -IN REFIN 180k RA 360k RLD 1M 100k 0.1F 10M 0.1F 1nF SW 1M +VS RLDFB GND AD8233 OPAMP+ FR 1.8V AC/DC 6.8nF REFOUT SDN OPAMP- RLD SDN 250k 2.7nF 1M OUT TO DIGITAL INTERFACE 1.8V LOD ADPD188GG 200k EXT_IN1 VDD1 0.1F VDD2 5V 0.1F VLED1 AGND DGND LGND CVLED LED1/DNC VREF 1F 1.8V 10k 10k SCL SDA GPIO0 GPIO1 Figure 36. Synchronized PPG and ECG Measurement Using the ADPD188GG with the AD8233 Rev. B | Page 34 of 61 TO DIGITAL INTERFACE 16111-034 RL 1.8V 10M 4.7F ECG (LSBs) 51500 The ADPD188GG is configured to alternately measure the photodiode signal and the ECG signal from the AD8233 on consecutive time slots to provide fully synchronized PPG and ECG measurements. Data can be read out of the on-chip FIFO or straight from data registers. The ADPD188GG channel used to process the ECG signal is set up in TIA ADC mode and the 1.8V 9500 Data Sheet ADPD188GG FLOAT MODE Float Mode Measurement Cycle The ADPD188GG has a unique operating mode, float mode, that allows excellent SNR at low power in low light situations. In float mode, the photodiode is first preconditioned to a known state and then the photodiode anode is disconnected from the receive path of the ADPD188GG for a preset amount of float time. During the float time, light falls on the photodiode, either from ambient light, pulsed LED light, or a combination of the two depending on the operating mode. Charge from the sensor is stored directly on the capacitance of the sensor. At the end of the float time, the photodiode switches back into the receive path of the ADPD188GG and an inrush of the accumulated charge occurs, which is subsequently integrated by the integrator of the ADPD188GG, allowing the maximum amount of charge to be processed per pulse with the minimum amount of noise added by the signal path. The charge is integrated externally on the capacitance of the photodiode for as long as it takes to acquire maximum charge, independent of the amplifiers of the signal path, which adds noise to the signal. Figure 37 shows the float mode measurement cycle timing diagram, and the following details the points shown: Amplifier and ADC noise values are constant for a given measurement. For optimal SNR, it is desirable to have a greater amount of signal (charge) per measurement. In normal mode, because the pulse time is fixed, the charge per measurement can be increased only by increasing the LED drive current. For high light conditions, this is sufficient. In low light conditions, however, there is a limit to the available current. In addition, high current pulses can cause ground noise in some systems. Green LEDs have lower efficiency at high currents, and many battery designs do not deliver high current pulses as efficiently. Float mode allows the user the flexibility to increase the amount of charge per measurement by either increasing the LED drive current or by increasing the float time. This flexibility is especially useful in low current transfer ratio (CTR) conditions, for example, 10 nA/mA, where normal mode requires multiple pulses to achieve an acceptable level of SNR. In float mode, the signal path bypasses the BPF and uses only the TIA and integrator. In normal mode, the shape of the pulse is known (typically either 2 s or 3 s) and is consistent across devices and conditions. The shape of the signal coming through the BPF is also predictable, which allows a user to align the integrator timing with the zero crossing of the filtered signal. In float mode, the shape of the signal produced by the charge dump can differ across devices and conditions. A filtered signal cannot be reliably aligned; therefore, the BPF cannot be used. In float mode, the entire charge dump is integrated in the negative cycle of the integrator and the positive cycle cancels any offsets. * * * * * * * Rev. B | Page 35 of 61 The precondition period is shown prior to Point A. The photodiode is connected to the TIA, and the photocurrent flows into the TIA. The photodiode anode is held at 0.9 V (Register 0x42 and Register 0x44, Bits[5:4] = 0x2 sets TIA_ VREF = 0.9 V). The photodiode is reverse biased to a maximum reverse bias of ~250 mV by setting Register 0x54, Bit 7 = 1 and Register 0x54, Bits[9:8] = 0x2 (for Time Slot A). At this point, the output of the TIA (TIA_OUT) = TIA_VREF - (IPD x RF), where IPD is the current flowing from the PD into the ADPD1080/ADPD1081 input, and the integrator is off. At Point A, the photodiode is disconnected from the receive path. Light continues to fall on the photodiode producing a charge that accumulates directly on the photodiode capacitance. As the charge accumulates, the voltage at the floating photo-diode anode rises. The TIA is disconnected from the input to the ADPD188GG so that no current flows through the TIA, and the TIA output is at TIA_VREF. Just prior to Point B, the integrator resets to 0. In the Float Mode for Synchronous LED Measurements section, the LED pulses during the time period between Point A and Point D. Float times of <4 s are not allowed. At Point B, the integrator begins its positive integration phase. Small dc offsets between the TIA output and the integrator reference causes the integrator output to ramp up for positive offsets or ramp down for negative offsets. The photodiode continues to accumulate charge during this period. At Point C, the integrator begins its negative integration phase. This reversal in polarity begins to cancel any signal caused by offsets. This offset cancellation continues through Point F, where all offsets are cancelled completely. At Point D, the photodiode switches into the receive path where all the charge that has accumulated on the photodiode capacitance during the float time is dumped into the TIA. The typical charge dump time is less than 2 s. As the current flows through the TIA, the output of the TIA responds with a large negative signal. Because the integrator is in the negative integration phase at this point, the output of the integrator rises as the input current to the device integrates back to total charge. Between Point D and Point E, any light incident on the photodiode produces additional photocurrent, which is immediately integrated by the integrator as charge. At Point E, the TIA disconnects from the receive path and the TIA output returns to TIA_VREF. Between Point E and Point F, the integrator completes the negative integration phase and cancellation of the offsets. At Point F, the integrator output is held until sampled by the ADC. ADPD188GG Data Sheet 25.0s 30.0s 35.0s A D E CONNECT FLOAT B + PHASE INTEGRATOR F C PHASE CHARGE ON PD TIA OUTPUT INTEGRATOR RESPONSE DON'T CARE 16111-036 INTEGRATOR RESET ADC READ Figure 37. Float Mode Measurement Cycle Timing Diagram Float Mode Limitations PD BEGINS TO FORWARD BIAS RECOMMENDED FLOAT MODE OPERATING REGION FLOAT TIME (s) Figure 38. Transfer Function of Integrated Charge on the Photodiode vs. Float Time The maximum amount of charge that can be stored on the photodiode capacitance and remain in the linear operating region of the sensor can be estimated by Q = CV where: Q is the integrated charge. C is the capacitance of the photodiode. In addition, consider the maximum amount of charge the integrator of the ADPD188GG can integrate. The integrator can integrate up to 7.6 pC. When this charge is referred back to the input, consider the TIA gain. When the TIA gain is at 200 k, the input referred charge is at a 1:1 ratio to the integrated charge on the integrator. For 100 k gain, it is 2:1; for 50 k gain, it is 4:1; and for 25 k gain, it is 8:1. For the previous example using a photodiode with 70 pF capacitance, use 50 k TIA gain and set the float timing such that, for a single pulse, the output of the ADC is at 70% of full scale, which is a typical operating condition. Under these operating conditions, 5.3 pC integrates per pulse by the integrator for 21.2 pC of charge accumulated on the photodiode capacitance. For small CTR, however, it can take a long time to accumulate 21.2 pC of charge on the photodiode capacitance, in which case, use higher TIA gains according to how much charge can be accumulated in a given amount of time. Ultimately, float times are determined by the type of measurement being made (ambient or pulsed LED), the photodiode capacitance, and the CTR of the system. Float Mode for Ambient Light Measurements 16111-037 INTEGRATED CHARGE ON PD (pC) When using float mode, the limitations of the mode must be well understood. For example, there is a finite amount of charge that can accumulate on the capacitance of the photodiode, and there is also a maximum amount of charge that can be integrated by the integrator. Based on an initial reverse bias of 250 mV on the photodiode and assuming that the photodiode begins to become nonlinear at ~200 mV of forward bias, there is ~450 mV of headroom for the anode voltage to increase from its starting point at the beginning of the float time before the charge ceases to accumulate in a linear fashion. It is desirable to operate only in the linear region of the photodiode (see Figure 38). To verify that float mode is operating in the linear region of the diode, the user can perform a simple check. Record data at a desired float time, and then record data at half the float time. It is recommended that the ratio of the two received signals be 2:1. If this ratio does not hold true, the diode is likely beginning to forward bias at the longer float time and becomes nonlinear. V is the amount of voltage change across the photodiode before the photodiode becomes nonlinear. For a typical discrete optical design using a 7 mm2 photodiode with 70 pF capacitance and 450 mV of headroom, the maximum amount of charge that can be stored on the photodiode capacitance is 31.5 pC. Float mode is used for ambient light measurements where the background light is sufficiently small. Use TIA ADC mode for ambient light measurements of higher intensities. Small amounts of light can be measured with adequate float times, allowing the incoming charge to accumulate to levels large enough to be measured above the noise floor of the system. The source of this light can be any combination of synchronous light (for example, from a pulsed LED) and asynchronous light (that is, background). If there is no system generated light source, the measurement is simply a measure of the background light. Rev. B | Page 36 of 61 Data Sheet ADPD188GG Use a two pulse differential measurement technique to cancel out electrical drifts and offsets. Take two measurements, each of a different float time. The first float time is considerably shorter than the second pulse. After the two measurements are taken, Measurement 1 is subtracted from Measurement 2, which effectively cancels out any offset and drift common to both measurements. What is left is an ambient light measurement based on an amount of charge that is integrated over a time that is the difference of the first and second float times. For example, if Float Time 1 is 6 s and Float Time 2 is 0x59[12:8]/0x5E[12:8] PRECONDITION TIME (FLT_PRECON_x) 26 s, the ambient light measurement is based on 20 s of charge integrated on the photodiode capacitance with any offset and drift removed. In float mode for ambient light, the number of pulses must be set to two to cancel drifts and offsets because only the first pulse can be short. More than two pulses can be used; however, pulses two through n are always the same length. If drift cancellation is not required, any number of pulses can be used and added together. Figure 39 shows an example of float ambient mode timing, and Table 21 details the relevant registers that must be configured. 0x30[12:8]/0x35[12:8] CHARGE DUMP TIME (SLOTx_LED_WIDTH) FLOAT 1 TIME CONNECT/FLOAT 0x31[7:0]/0x36[7:0] FLOAT 2 TIME (SLOTx_PERIOD) 0x30[7:0]/0x35[7:0] TIMETO FIRST CHARGE DUMP (SLOTx_LED OFFSET) INTEGRATOR SEQUENCE 0x39[15:11]/0x3B[15:11] INTEGRATION TIME (SLOTx_AFE_WIDTH) 16111-038 ACCUMULATED CHARGE ON PD Figure 39. Example of Float Ambient Mode Timing Table 21. Float Ambient Mode Registers Group Float Mode Operation Float Mode Timing Register Name SLOTx_LED_SEL Register Time Slot A Time Slot B 0x14, Bits[1:0] 0x14, Bits[3:2] FLT_EN_x FLT_MATH12_x SLOTx_AFE_CFG SLOTx_TIA_VREF SLOTx_V_CATHODE 0x5E, Bits[14:13] 0x58, Bits[2:1] 0x43, Bits[15:0] 0x42, Bits[5:4] 0x54, Bits[9:8] 0x59, Bits[14:13] 0x58, Bits[6:5] 0x45, Bits[15:0] 0x44, Bits[5:4] 0x54, Bits[11:10] REG54_VCAT_ENABLE 0x54, Bit 7 0x54, Bit 7 FLT_PRECON_x 0x5E, Bits[12:8] 0x59, Bits[12:8] SLOTx_PERIOD SLOTx_PERIOD SLOTx_LED_WIDTH 0x31, Bits[7:0] 0x37, Bits[1:0] 0x30, Bits[12:8] 0x36, Bits[7:0] 0x37, Bits[9:8] 0x35, Bits[12:8] SLOTx_LED_OFFSET 0x30, Bits[7:0] 0x35, Bits[7:0] SLOTx_AFE_WIDTH SLOTx_AFE_OFFSET 0x39, Bits[15:11] 0x39, Bits[10:0] 0x3B, Bits[15:11] 0x3B, Bits[10:0] SLOTx_PULSES 0x31, Bits[15:8] 0x36, Bits[15:8] Rev. B | Page 37 of 61 Float Mode Description Set to 0 to enable float mode. Set to 3 to enable float between connect pulses. Set to 2 to subtract first pulse and add second pulse. Set to 0xAE65 for TIA and integrator, bypass BPF. Set to 2 for TIA_VREF = 0.9 V. Set to 2 for 250 mV reverse bias on the photodiode at the precondition. Set to 1 to override Register 0x3C cathode voltage settings. Precondition time (to start of Float 1 time). 8 LSBs of float period in s; Float 2 time = SLOTx_PERIOD 2 MSBs of float period. Connect time in s; this is the amount of time given to dump the accumulated charge from the photodiode capacitance; typically, this is set to 2 s. Time to first charge dump; Float 1 time = (SLOTx_LED_OFFSET + SLOTx_LED_WIDTH) - FLT_PRECONx. Integration time in s; set to FLT_CONNx + 1. Integrator start time in 31.25 ns increments; set to (SLOTx_LED_OFFSETx - SLOTx_AFE_WIDTH - 9.25) s. Number of pulses; set to 2 for float ambient mode. ADPD188GG Data Sheet Float Mode for Synchronous LED Measurements In float LED mode, photocurrent is generated from ambient light and pulsed LED light during the float time. Float LED mode is desirable in low signal conditions where the CTR is <10 nA/mA. In addition, float mode is a good option in situations where the user wants to limit the LED drive current of the green LEDs in a heart rate measurement to keep the forward voltage drop of the green LED to a level that allows the elimination of a boost converter for the LED supply. For example, the LED current can be limited to 10 mA to ensure that the LED voltage drop is ~3 V so that it can operate directly from the battery without the need of a boost converter. Float mode accumulates the received charge during longer LED pulses without adding noise from the signal path, effectively yielding the highest SNR and/or photon attainable. As with float ambient mode, multiple pulses cancel electrical offsets and drifts; however, in float LED mode, the ambient light must also be cancelled because only the reflected return from the LED pulses is desired. To achieve this, use an even number of equal length pulses. For every pair of pulses, the LED flashes in one of the pulses and does not flash in the other. The return from the LED + ambient + offset is present in one of the pulses. In the other, only the ambient light and offset is present. A subtraction of the two pulses is made that eliminates ambient light as well as any offset and drift. It is recommended to use groups of four pulses for measurement where the LED is flashed on Pulse 2 and Pulse 3. The accumulator adds Pulse 2 and Pulse 3 and then subtract Pulse 1 and Pulse 4. To gain additional SNR, use multiple groups of four pulses. The settings of FLT_LED_FIRE_x, Register 0x5A, Bits[15:8] determine if the LED fires in which pulse position. Which pulse positions are added or subtracted is configured in the FLT_ MATH12x and FLT_MATH34x bits of Register 0x58. These sequences are repeated in groups of four pulses. The value written to the FIFO or data registers is dependent on the total number of pulses per sample period. For example, if the device is setup for 32 pulses, the 4 pulse sequence, as defined in FLT_ LED_FIRE_x and FLT_MATHxxx, repeats eight times and a single register or FIFO write of the final value based on 32 pulses executes. Table 22 details the relevant registers for float LED mode. Table 22. Float LED Mode Registers Group Float Mode Operation Float Mode Timing Register Name SLOTx_LED_SEL FLT_EN_x FLT_MATH12_x FLT_MATH34_x SLOTx_AFE_CFG SLOTx_TIA_VREF SLOTx_V_CATHODE Register Address Time Slot A Time Slot B 0x14, Bits[1:0] 0x14, Bits[3:2] 0x5E, Bits[14:13] 0x59, Bits[14:13] 0x58, Bits[2:1] 0x58, Bits[6:5] 0x58, Bits[9:8] 0x58, Bits[11:10] 0x43, Bits[15:0] 0x45, Bits[15:0] 0x42, Bits[5:4] 0x44, Bits[5:4] 0x54, Bits[9:8] 0x54, Bits[11:10] REG54_VCAT_ENABLE FLT_LED_SELECT_x 0x54, Bit 7 0x3E, Bits[15:14] 0x54, Bit 7 0x3F[15:14] FLT_PRECON_x SLOTx_PERIOD 0x5E, Bits[12:8] 0x31, Bits[7:0] 0x59, Bits[12:8] 0x36, Bits[7:0] SLOTx_PERIOD SLOTx_LED_WIDTH 0x37, Bits[1:0] 0x30, Bits[12:8] 0x37, Bits[9:8] 0x35, Bits[12:8] SLOTx_LED_OFFSET 0x30, Bits[7:0] 0x35, Bits[7:0] Rev. B | Page 38 of 61 Float Mode Description Set to 0 to enable float mode. Set to 3 to enable float between connect pulses. Set to 2 to subtract first pulse and add second pulse. Set to 1 to add third pulse and subtract fourth pulse. Set to 0xAE65 for TIA + integrator, bypass BPF. Set to 2 for TIA_VREF = 0.9 V. Set to 2 for 250 mV reverse bias on the photodiode at the precondition. Set to 1 to override Register 0x3C cathode voltage settings. LED selection for float LED mode. 00 = no LED. 01 = LED1. 10 = LED2. 11 = LED3. Precondition time (to start of float 1 time). 8 LSBs of float period in s. Float 2 time = SLOTx_PERIOD. Float 2 time is valid for every pulse subsequent to the first pulse. Float 1 time must be set equal to Float 2 time in float LED mode. 2 MSBs of float period. Connect time in s, which is the amount of time given to dump the accumulated charge from the photodiode capacitance. Typically, it is set to 2 s. Time to first charge dump. Float 1 time = (SLOTx_LED_OFFSET + SLOTx_LED_WIDTH) - FLT_PRECONx. Float 1 time must be equal to Float 2 time for float LED mode. Data Sheet Group ADPD188GG Register Name SLOTx_AFE_WIDTH SLOTx_AFE_OFFSET Register Address Time Slot A Time Slot B 0x39,Bits[15:11] 0x3B, Bits[15:11] 0x39, Bits[10:0] 0x3B, Bits[10:0] SLOTx_PULSES 0x31, Bits[15:8] 0x36, Bits[15:8] FLT_LED_WIDTH_x FLT_LED_OFFSET_x FLT_LED_FIRE_x 0x3E, Bits[12:8] 0x3E, Bits[7:0] 0x5A, Bits[11:8] 0x3F, Bits[12:8] 0x3F, Bits[7:0] 0x5A, Bits[15:12] A timing diagram for a four pulse float LED sequence for Time Slot B is shown in Figure 40. In this example, the device is set up for LED pulses of 12 s that fall within a float period of 16 s, 2 s of which are used for dumping of the accumulated charge on the photodiode. The integration time is set to 3 s, which is 1 s more than the charge dump time to allow for timing margin when integrating the incoming charge. Note, there is a 9 s offset built into the integration start time. Take this offset into account when setting the SLOTx_AFE_OFFSET value. As shown in Figure 40, the time of the first charge dump is set to 30 s. SLOTx_ AFE_OFFSET is set to 0x238 (17.75 s), taking into account the 3 s integration time, the 9 s offset, and an additional 250 ns for edge placement margin. Float Mode Description Integration time in s. set to FLT_CONN + 1. Integrator start time in 31.25 ns increments. Set to (SLOTx_LED_OFFSET - SLOTx_AFE_WIDTH - 9.25) s. Number of pulses; must be set in multiples of 2, minimum 2. LED pulse width for float LED mode in s. Time of first LED pulse in float LED mode. In any given sequence of four pulses, fire the LED in the selected position. Selections are active low (that is, fire LED if 0). For example, in a sequence of four pulses on Time Slot B, Register 0x5A, Bit 12 is the first pulse, and Register 0x5A, Bit 15 is the fourth pulse. For a sequence of four pulses, fire the LED in the second and third pulses by writing 0x9 to Register 0x5A, Bits[15:12]. To calculate SLOTx_AFE_OFFSET, use the following equation: SLOTx_AFE_OFFSET = SLOTx_LED_OFFSET - SLOTx_AFE_WIDTH - 9.25 s Placement of the integration period is such that the negative phase of the integration is centered on the charge dump phase. The TIA is an inverting stage, therefore, placing the negative phase of the integration during the dumping of the charge from the photodiode causes the integrator to increase with the negative going output signal from the TIA. The LED flashes in the second and third pulses of the four pulse sequence. Setting Register 0x58, Bits[6:5] = 2 and Register 0x58, Bits[11:10] = 1 forces the device to add the second and third pulses while subtracting the first and fourth pulses, effectively cancelling out the ambient light and electrical offsets and drift. Rev. B | Page 39 of 61 ADPD188GG Data Sheet PRECONDITION 0x35[12:8] = 0x2 CHARGE DUMPTIME = 2s 0x36[7:0] = 0x10 FLOAT PERIOD = 16s CONNECT/FLOAT MASKED LED PULSE LED PULSES 0x5A[15:12] = 0x9 MASK PULSE 1 AND MASK PULSE 4 FLASH PULSE 2 AND FLASH PULSE 3 FLASH LED FLASH LED MASKED LED PULSE 0x3F[12:8] = 0xC LED PW = 12s ACCUMULATED CHARGE ON PD INTEGRATOR OUTPUT INTEGRATOR SEQUENCE 0x3B[15:11] = 0x3 INTEGRATION TIME = 3s INTEGRATOR RESET ADC READ t=0 t = 16s, 0x59[12:8] = 0x10 PRECONDITIONING TIME t = 17s, 0x3F[7:0] = 0x11 LED PULSE OFFSET 16111-039 t = 26.75s, 0x3B[10:0] = 0x238 START OF INTEGRATION TIME t = 30s, 0x35[7:0] = 0x1E TIME OF FIRST CHARGE DUMP Figure 40. Example Timing Diagram of Four Pulse Float LED Mode Sequence A comparison of float ambient mode vs. float LED mode is shown in Table 23 and Table 24. Table 23. Float Ambient Mode--Measure Ambient Light Level Pulse 1 2 3 4 Float Time Shorter Longer Not applicable Not applicable Integrated Charge Offset, Ambient 1 (shorter time) Offset, Ambient 1 (shorter time) Not applicable Not applicable Calculation Subtract Add Not applicable Not applicable Result Ambient Measurement = Ambient 2 - Ambient 1 (offset cancels) Table 24. Float LED Mode--Measurement Synchronous Reflected Light from LED Pulse 1 2 3 4 Float Time Equal Equal Equal Equal Integrated Charge Offset + Ambient Offset + Ambient + LED Offset + Ambient + LED Offset + Ambient Calculation Subtract Add Add Subtract Result Sync LED response = reflected LED return (offset and ambient cancel) Rev. B | Page 40 of 61 Data Sheet ADPD188GG Monitoring Ambient Light Levels in Float LED Mode In real-world applications, it is common for the ambient light levels to change constantly. When using float LED mode, increasing amounts of ambient light can approach levels where it uses an unacceptable amount of the dynamic range of the charge that can stored on the photodiode capacitance. For this reason, it is required that the ambient light level is monitored so that configuration changes can be made when necessary, for example, float time, TIA gain, and operating mode. There are two ways to monitor ambient light levels. One way is to use TIA ADC mode in the alternate time slot and continuously monitor the ambient light level. The other way is to use a feature of the ADPD188GG where the ambient light level is automatically monitored in the background during float mode operation and is compared against a user-defined threshold. If the ambient light level exceeds this threshold by some userdefined number of times, a flag is set by the device that can be read by the user or can be output to a GPIO. Table 25 lists all the registers used to monitor the ambient light level while in float LED mode. The user sets an ambient level threshold in the BG_THRESH register, which is the threshold by which the ADC result of the subtract cycles in float LED mode are compared against. The subtract cycles in float LED mode are the positions in the pulse sequence in which the LED pulse is masked; therefore, it is the background level measurement. The ADC result is equal to the raw ADC output minus the contents of the ADC offset register (Register 0x18 to Register 0x1B and Register 0x1E to Register 0x21). In the BG_COUNT register, the user sets a limit on the number of cycles that BG_THRESH is exceeded by the ADC result before the BG_STATUS bit is set for any particular channel. Every time the BG_THRESH value is exceeded by the ADC result during a subtract cycle, an internal counter increments. Each channel has its own counter. When this count exceeds the limit set in the BG_COUNT register, the BG_STATUS bit is set for the channel. The user can periodically monitor the BG_STATUS register to check for asserted bits. Alternatively, a GPIOx pin can be asserted if a BG_STATUS flag is set. See Table 25 for the various logical combinations of BG_STATUS flags and interrupts that can be brought out on a GPIOx. Table 25. Registers for Monitoring the Ambient Light Level in Float LED Mode Float Mode Register Name BG_STATUS_x Register Time Slot A Time Slot B 0x04, Bits[3:0] 0x04, Bits[7:4] BG_THRESH_x 0x16, Bits[13:0] 0x1C[13:0] BG_COUNT_x 0x16, Bits[15:14] 0x1C[15:14] GPIO0_ALT_CFG 0x0B[4:0] 0x0B[4:0] GPIO1_ALT_CFG 0x0B[12:8] 0x0B[12:8] Description Status of comparison between background light level and background threshold value (BG_THRESH). A 1 in any bit location means the threshold has been crossed BG_COUNT number of times. This register is cleared once it is read. Bit 0: Time Slot A, Channel 1 exceeded threshold count. Bit 1: Time Slot A, Channel 2 exceeded threshold count. Bit 2: Time Slot A, Channel 3 exceeded threshold count. Bit 3: Time Slot A, Channel 4 exceeded threshold count. Bit 4: Time Slot B, Channel 1 exceeded threshold count. Bit 5: Time Slot B, Channel 2 exceeded threshold count. Bit 6: Time Slot B, Channel 3 exceeded threshold count. Bit 7: Time Slot B, Channel 4 exceeded threshold count. The background threshold that is compared against the ADC result during the subtract cycles during float mode. If the ADC result exceeds the value in this register, BG_COUNT is incremented. This is the number of times the ADC value exceeds the BG_THRESH_x value during the float mode subtract cycles before the BG_STATUS bit is set. 0x0: never set BG_STATUS. 0x1: set when BG_THRESH_x is exceeded 1 time. 0x02: set when BG_THRESH_x is exceeded 4 times. 0x03: set when BG_THRESH_x is exceeded 16 times. GPIO0 asserts for the following conditions: 0x10: logical OR of BG_STATUS_x, Bits[3:0]. 0x1A: logical OR of BG_STATUS_x, Bits[7:4]. 0x1B: logical OR of BG_STATUS_x, Bits[7:0]. 0x1C: logical OR of BG_STATUS_x, Bits[7:0] and INT. GPIO1 asserts for the following conditions: 0x10: logical OR of BG_STATUS_x, Bits[3:0]. 0x1A: logical OR of BG_STATUS_x, Bits[7:4]. 0x1B: logical OR of BG_STATUS_x, Bits[7:0]. 0x1C: logical OR of BG_STATUS_x, Bits[7:0] and INT. Rev. B | Page 41 of 61 ADPD188GG Data Sheet REGISTER LISTING The recommended values are not shown. Only power-on reset values are shown in Table 26. The recommended values are largely dependent on use case. Table 26. Numeric Register Listing Hex. Addr. Name 0x00 Status 0x01 0x02 0x04 0x06 INT_MASK GPIO_ DRV BG_ STATUS FIFO_ THRESH 0x08 DEVID 0x09 I2CS_ID 0x0A CLK_ RATIO 0x0B GPIO_ CTRL 0x0D SLAVE_ ADDRESS_ KEY SW_RESET 0x0F 0x10 Mode 0x11 SLOT_EN 0x12 FSAMPLE 0x14 PD_LED_ SELECT 0x15 NUM_ AVG 0x16 BG_ MEAS_A 0x17 INT_SEQ_A 0x18 SLOTA_ CH1_ OFFSET SLOTA_ CH2_ OFFSET SLOTA_ CH3_ OFFSET SLOTA_ CH4_ OFFSET BG_MEAS_B 0x19 0x1A 0x1B 0x1C Bit 15 Bits Bit 7 [15:8] [7:0] Reserved [15:8] Bit 14 Bit 6 Bit 13 Bit 5 SLOTB_INT SLOTA_INT [7:0] SLOTB_INT_ MASK [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] Reserved Bit 12 Bit 11 Bit 4 Bit 3 FIFO_SAMPLES[7:0] Bit 10 Bit 2 Bit 9 Bit 1 Bit 8 Bit 0 Reset 0x0000 R/W R/W FIFO_INT_ MASK 0x00FF R/W GPIO1_POL GPIO0_POL 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0A16 R 0x00C8 R/W 0x0000 R 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x0000 R/W 0x1000 R/W 0x0028 R/W 0x0541 R/W 0x0600 R/W 0x0000 R/W 0x0000 0x2000 R/ W R/W Reserved Reserved SLOTA_INT_ MASK Reserved Reserved Reserved GPIO0_ENA GPIO1_DRV GPIO0_DRV Reserved BG_STATUS_B[3:0] BG_STATUS_A[3:0] FIFO_THRESH[5:0] Reserved Reserved REV_NUM[7:0] DEV_ID[7:0] ADDRESS_WRITE_KEY[7:0] SLAVE_ADDRESS[6:0] Reserved Reserved CLK_RATIO[11:8] CLK_RATIO[7:0] Reserved Reserved Reserved GPIO1_ALT_CFG[4:0] GPIO0_ALT_CFG[4:0] SLAVE_ADDRESS_KEY[15:8] SLAVE_ADDRESS_KEY[7:0] Reserved Reserved Reserved Reserved RDOUT_ FIFO_OVRN_ MODE PREVENT SW_RESET Reserved Mode[1:0] SLOTB_ FIFO_ MODE[2] Reserved SLOTA_EN [7:0] SLOTB_FIFO_MODE[1:0] SLOTB_EN SLOTA_FIFO_MODE[2:0] [15:8] FSAMPLE[15:8] [7:0] FSAMPLE[7:0] [15:8] Reserved SLOTB_PD_SEL[3:0] [7:0] SLOTA_PD_SEL[3:0] SLOTB_LED_SEL[1:0] SLOTA_LED_SEL[1:0] [15:8] Reserved SLOTB_NUM_AVG[2:0] [7:0] Reserved SLOTA_NUM_AVG[2:0] Reserved [15:8] BG_COUNT_A[1:0] BG_THRESH_A[13:8] [7:0] BG_THRESH_A[7:0] [15:8] Reserved [7:0] Reserved INTEG_ORDER_A[3:0] [15:8] SLOTA_CH1_OFFSET[15:8] [7:0] SLOTA_CH1_OFFSET[7:0] [15:8] [7:0] SLOTA_CH2_OFFSET[15:8] SLOTA_CH2_OFFSET[7:0] 0x2000 R/W [15:8] [7:0] SLOTA_CH3_OFFSET[15:8] SLOTA_CH3_OFFSET[7:0] 0x2000 R/W [15:8] [7:0] SLOTA_CH4_OFFSET[15:8] SLOTA_CH4_OFFSET[7:0] 0x2000 R/W 0x0000 R/W [15:8 BG_COUNT_B[1:0] BG_THRESH_B[13:8] BG_THRESH_B[7:0] Rev. B | Page 42 of 61 Data Sheet Hex. Addr. Name 0x1D INT_SEQ_B 0x1E SLOTB_CH1_ OFFSET 0x1F SLOTB_CH2_ OFFSET 0x20 SLOTB_CH3_ OFFSET 0x21 SLOTB_CH4_ OFFSET 0x22 ILED3_ COARSE 0x23 ILED1_ COARSE 0x24 ILED2_ COARSE 0x25 ILED_FINE 0x30 SLOTA_LED_ PULSE 0x31 SLOTA_ NUMPULSES 0x34 LED_ DISABLE 0x35 SLOTB_ LED_PULSE 0x36 SLOTB_ NUMPULSES 0x37 ALT_PWR_ DN 0x38 EXT_SYNC_ STARTUP 0x39 SLOTA_AFE_ WINDOW 0x3B SLOTB_ AFE_ WINDOW AFE_PWR_ CFG1 0x3C 0x3E SLOTA_ FLOAT_LED 0x3F SLOTB_ FLOAT_LED 0x42 SLOTA_ TIA_CFG ADPD188GG Bits [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] 0x43 SLOTA_ AFE_CFG 0x44 SLOTB_ TIA_CFG SLOTB_ AFE_CFG 0x4B SAMPLE_ CLK Bit 14 Bit 6 Bit 13 Bit 5 Bit 11 Bit 3 Reserved Bit 10 Bit 2 Bit 9 Bit 1 Bit 8 Bit 0 Reserved Reserved Reserved Reserved Reserved Reserved ILED3_SCALE ILED3_SLEW[2:0] ILED1_SCALE ILED1_SLEW[2:0] ILED2_SCALE ILED2_SLEW[2:0] ILED3_FINE[4:0] Reserved Reserved ILED3_COARSE[3:0] Reserved ILED1_COARSE[3:0] Reserved ILED2_COARSE[3:0] ILED2_FINE[4:2] ILED2_FINE[1:0] ILED1_FINE[4:0] Reserved SLOTA_LED_WIDTH[4:0] SLOTA_LED_OFFSET[7:0] SLOTA_PULSES[7:0] SLOTA_PERIOD[7:0] Reserved SLOTB_ SLOTA_ LED_DIS LED_DIS Reserved Reserved SLOTB_LED_WIDTH[4:0] SLOTB_LED_OFFSET[7:0] SLOTB_PULSES[7:0] SLOTB_PERIOD[7:0] CH34_DISABLE[15:13] CH2_DISABLE[12:10] SLOTB_PERIOD[9:8] Reserved SLOTA_PERIOD[9:8] EXT_SYNC_STARTUP[15:8] EXT_SYNC_STARTUP[7:0] SLOTA_AFE_WIDTH[4:0] SLOTA_AFE_OFFSET[10:8] SLOTA_AFE_OFFSET[7:0] SLOTB_AFE_WIDTH[4:0] SLOTB_AFE_OFFSET[10:8] SLOTB_AFE_OFFSET[7:0] Reserved Reserved Reserved V_CATHODE AFE_ POWERDOWN[5] Reserved FLT_LED_WIDTH_A[4:0] AFE_POWERDOWN[4:0] FLT_LED_SELECT_A[1:0] Reserved FLT_LED_SELECT_B[1:0] SLOTA_INT_ SLOTA_TIA_ AS_BUF IND_EN FLT_LED_OFFSET_A[7:0] Reserved FLT_LED_WIDTH_B[4:0] FLT_LED_OFFSET_B[7:0] SLOTA_AFE_MODE[5:0] SLOTA_ Reserved BUF_GAIN SLOTA_TIA_VREF[1:0] Reserved (write 0x1) SLOTA_TIA_GAIN[1:0] SLOTA_AFE_CFG[15:8] SLOTA_AFE_CFG[7:0] SLOTB_AFE_MODE[5:0] SLOTB_INT_ AS_BUF SLOTB_ TIA_IND_EN SLOTB_TIA_VREF[1:0] Reserved (write 0x1) SLOTB_AFE_CFG[15:8] SLOTB_AFE_CFG[7:0] Reserved CLK32K_EN Reset 0x0000 0x2000 R/W R/ W R/W 0x2000 R/W 0x2000 R/W 0x2000 R/W 0x3000 R/W 0x3000 R/W 0x3000 R/W 0x630C R/W 0x0320 R/W 0x0818 R/W 0x0000 R/W 0x0320 R/W 0x0818 R/W 0x0000 R/W 0x000 R/W 0x22FC R/W 0x22FC R/W 0x3006 R/W 0x0320 R/W 0x0320 R/W 0x1C38 R/W INTEG_ORDER_B[3:0] SLOTB_CH1_OFFSET[15:8] SLOTB_CH1_OFFSET[7:0] SLOTB_CH2_OFFSET[15:8] SLOTB_CH2_OFFSET[7:0] SLOTB_CH3_OFFSET[15:8] SLOTB_CH3_OFFSET[7:0] SLOTB_CH4_OFFSET[15:8] SLOTB_CH4_OFFSET[7:0] [15:8] [7:0] [15:8] [7:0] Bit 12 Bit 4 Reserved [15:8] [7:0] [15:8] [7:0] 0x45 Bit 15 Bit 7 Reserved CLK32K_ADJUST[5:0] Rev. B | Page 43 of 61 0xADA5 R/W SLOTB_ Reserved BUF_GAIN SLOTB_TIA_GAIN[1:0] CLK32K_ BYP 0x1C38 R/W 0xADA5 R/W 0x2612 R/W ADPD188GG Hex. Addr. Name 0x4D CLK32M_ ADJUST 0x4F 0x50 EXT_SYNC_ SEL CLK32M_ CAL_EN 0x54 AFE_PWR_ CFG2 0x55 TIA_INDEP_ GAIN 0x58 Math 0x59 FLT_ CONFIG_B 0x5A FLT_ LED_FIRE 0x5E FLT_ CONFIG_A 0x5F DATA_ ACCESS_CTL 0x60 FIFO_ ACCESS 0x64 SLOTA_ PD1_16BIT 0x65 SLOTA_ PD2_16BIT 0x66 SLOTA_ PD3_16BIT 0x67 SLOTA_ PD4_16BIT 0x68 SLOTB_ PD1_16BIT 0x69 SLOTB_ PD2_16BIT 0x6A SLOTB_ PD3_16BIT 0x6B SLOTB_ PD4_16BIT 0x70 A_PD1_LOW 0x71 A_PD2_LOW 0x72 A_PD3_LOW 0x73 A_PD4_LOW 0x74 A_PD1_HIGH 0x75 A_PD2_HIGH 0x76 A_PD3_HIGH 0x77 A_PD4_HIGH Data Sheet Bit 15 Bit 7 Bits [15:8] [7:0] [15:8] [7:0] Reserved [15:8] [7:0] Reserved Bit 14 Bit 6 Bit 13 Bit 5 GPIO1_OE GPIO1_IE Bit 12 Bit 4 Bit 11 Bit 10 Bit 9 Bit 3 Bit 2 Bit 1 Reserved CLK32M_ADJUST[7:0] Reserved Reserved EXT_SYNC_SEL[1:0] GPIO0_IE Reserved Reserved GPIO1_CTRL CLK32M_ CAL_EN Reserved SLEEP_V_CATHODE[1:0] Bit 8 Bit 0 R/W R/W 0x2090 R/W 0x0000 R/W 0x0020 R/W 0x0000 R/W 0x0000 R/W 0x0808 R/W 0x0010 R/W 0x0808 R/W 0x0000 R/W 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R Reserved [15:8] SLOTB_V_CATHODE[1:0] SLOTA_V_CATHODE[1:0] [7:0] REG54_ Reserved VCAT_ ENABLE [15:8] Reserved SLOTB_TIA_GAIN_4[1:0] SLOTB_TIA_GAIN_3[1:0] [7:0] SLOTB_TIA_GAIN_2[1:0] SLOTA_TIA_GAIN_4[1:0] SLOTA_TIA_GAIN_3[1:0] SLOTA_TIA_GAIN_2[1:0] [15:8] Reserved FLT_MATH34_B[1:0] FLT_MATH34_A[1:0] [7:0] ENA_INT_ FLT_MATH12_B[1:0] Reserved Reserved FLT_MATH12_A[1:0] Reserved AS_BUF [15:8] Reserved FLT_EN_B[1:0] FLT_PRECON_B[4:0] [7:0] Reserved [15:8] FLT_LED_FIRE_B[3:0] FLT_LED_FIRE_A[3:0] [7:0] Reserved (write 0x10) [15:8] Reserved FLT_EN_A[1:0] FLT_PRECON_A[4:0] [7:0] Reserved [15:8] Reserved [7:0] Reserved SLOTB_ SLOTA_ DIGITAL_ DATA_ DATA_ CLOCK_ HOLD HOLD ENA [15:8] FIFO_DATA[15:8] [7:0] FIFO_DATA[7:0] [15:8] SLOTA_CH1_16BIT[15:8] [7:0] SLOTA_CH1_16BIT[7:0] [15:8] SLOTA_CH2_16BIT[15:8] [7:0] SLOTA_CH2_16BIT[7:0] [15:8] SLOTA_CH3_16BIT[15:8] [7:0] SLOTA_CH3_16BIT[7:0] [15:8] SLOTA_CH4_16BIT[15:8] [7:0] SLOTA_CH4_16BIT[7:0] [15:8] SLOTB_CH1_16BIT[15:8] [7:0] SLOTB_CH1_16BIT[7:0] [15:8] SLOTB_CH2_16BIT[15:8] [7:0] SLOTB_CH2_16BIT[7:0] [15:8] SLOTB_CH3_16BIT[15:8] [7:0] SLOTB_CH3_16BIT[7:0] [15:8] SLOTB_CH4_16BIT[15:8] [7:0] SLOTB_CH4_16BIT[7:0] [15:8] SLOTA_CH1_LOW[15:8] [7:0] SLOTA_CH1_LOW[7:0] [15:8] SLOTA_CH2_LOW[15:8] [7:0] SLOTA_CH2_LOW[7:0] [15:8] SLOTA_CH3_LOW[15:8] [7:0] SLOTA_CH3_LOW[7:0] [15:8] SLOTA_CH4_LOW[15:8] [7:0] SLOTA_CH4_LOW[7:0] [15:8] SLOTA_CH1_HIGH[15:8] [7:0] SLOTA_CH1_HIGH[7:0] [15:8] SLOTA_CH2_HIGH[15:8] [7:0] SLOTA_CH2_HIGH[7:0] [15:8] SLOTA_CH3_HIGH[15:8] [7:0] SLOTA_CH3_HIGH[7:0] [15:8] SLOTA_CH4_HIGH[15:8] [7:0] SLOTA_CH4_HIGH[7:0] Rev. B | Page 44 of 61 Reset 0x0098 Data Sheet Hex. Addr. Name 0x78 B_PD1_LOW 0x79 B_PD2_LOW 0x7A B_PD3_LOW 0x7B B_PD4_LOW 0x7C B_PD1_HIGH 0x7D B_PD2_HIGH 0x7E B_PD3_HIGH 0x7F B_PD4_HIGH ADPD188GG Bit 15 Bit 7 Bits [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] [15:8] [7:0] Bit 14 Bit 6 Bit 13 Bit 5 Bit 12 Bit 11 Bit 10 Bit 4 Bit 3 Bit 2 SLOTB_CH1_LOW[15:8] SLOTB_CH1_LOW[7:0] SLOTB_CH2_LOW[15:8] SLOTB_CH2_LOW[7:0] SLOTB_CH3_LOW[15:8] SLOTB_CH3_LOW[7:0] SLOTB_CH4_LOW[15:8] SLOTB_CH4_LOW[7:0] SLOTB_CH1_HIGH[15:8] SLOTB_CH1_HIGH[7:0] SLOTB_CH2_HIGH[15:8] SLOTB_CH2_HIGH[7:0] SLOTB_CH3_HIGH[15:8] SLOTB_CH3_HIGH[7:0] SLOTB_CH4_HIGH[15:8] SLOTB_CH4_HIGH[7:0] Rev. B | Page 45 of 61 Bit 9 Bit 1 Bit 8 Bit 0 Reset 0x0000 R/W R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R 0x0000 R ADPD188GG Data Sheet LED CONTROL REGISTERS Table 27. LED Control Registers Address 0x14 0x22 0x23 Data Bit [15:12] [11:8] Default Value 0x0 0x5 Access R/W R/W Name Reserved SLOTB_PD_SEL [7:4] 0x4 R/W SLOTA_PD_SEL [3:2] 0x0 R/W SLOTB_LED_SEL [1:0] 0x1 R/W SLOTA_LED_SEL [15:14] 13 0x0 0x1 R/W R/W Reserved ILED3_SCALE 12 [11:7] [6:4] 0x1 0x0 0x0 R/W R/W R/W Reserved Reserved ILED3_SLEW [3:0] 1 0x0 R/W ILED3_COARSE [15:14] 13 0x0 0x1 R/W R/W Reserved ILED1_SCALE 12 [11:7] 0x1 0x0 R/W R/W Reserved Reserved Description Write 0x0 to these bits for proper operation. PDx connection selection for Time Slot B. See the Time Slot Switch section for detailed descriptions. PDx connection selection for Time Slot A. See the Time Slot Switch section for detailed descriptions. Time Slot B LED configuration. These bits determine which LED is associated with Time Slot B. 0x0: pulse PDx connection to AFE. Float mode and pulse connect mode enable. 0x1: LEDX1 pulses during Time Slot B. 0x2: LEDX2 pulses during Time Slot B. 0x3: LEDX3 pulses during Time Slot B. Time Slot A LED configuration. These bits determine which LED is associated with Time Slot A. 0x0: pulse PDx connection to AFE. Float mode and pulse connect mode enable. 0x1: LEDX1 pulses during Time Slot A. 0x2: LEDX2 pulses during Time Slot A. 0x3: LEDX3 pulses during Time Slot A. Write 0x0. LEDX3 current scale factor. 1: 100% strength. 0: 10% strength; sets the LEDX3 driver in low power mode. LEDX3 Current Scale = 0.1 + 0.9 x (Register 0x22, Bit 13). Write 0x1. Write 0x0. LEDX3 driver slew rate control. The slower the slew rate, the safer the performance in terms of reducing the risk of overvoltage of the LED driver. 0x0: the slowest slew rate. ... 0x7: the fastest slew rate. LEDX3 coarse current setting. Coarse current sink target value of LEDX3 in standard operation. 0x0: lowest coarse setting. ... 0xF: highest coarse setting. LED3PEAK = LED3COARSE x LED3FINE x LED3SCALE where: LED3PEAK is the LEDX3 peak target value (mA). LED3COARSE = 44.5 + 17.8 x (Register 0x22, Bits[3:0]). LED3FINE = 0.73 + 0.022 x (Register 0x25, Bits[15:11]). LED3SCALE = 0.1 + 0.9 x (Register 0x22, Bit 13). Write 0x0. LEDX1 current scale factor. 1: 100% strength. 0: 10% strength; sets the LEDX1 driver in low power mode. LEDX1 Current Scale = 0.1 + 0.9 x (Register 0x23, Bit 13). Write 0x1. Write 0x0. Rev. B | Page 46 of 61 Data Sheet Address 0x24 0x251 ADPD188GG Data Bit [6:4] Default Value 0x0 Access R/W Name ILED1_SLEW [3:0]1 0x0 R/W ILED1_COARSE [15:14] 13 0x0 0x1 R/W R/W Reserved ILED2_SCALE 12 [11:7] [6:4] 0x1 0x0 0x0 R/W R/W R/W Reserved Reserved ILED2_SLEW [3:0]1 0x0 R/W ILED2_COARSE [15:11] 0xC R/W ILED3_FINE [10:6] 0xC R/W ILED2_FINE 5 [4:0] 0x0 0xC R/W R/W Reserved ILED1_FINE Description LEDX1 driver slew rate control. The slower the slew rate, the safer the performance in terms of reducing the risk of overvoltage of the LED driver. 0: the slowest slew rate. ... 7: the fastest slew rate. LEDX1 coarse current setting. Coarse current sink target value of LEDX1 in standard operation. 0x0: lowest coarse setting. ... 0xF: highest coarse setting. LED1PEAK = LED1COARSE x LED1FINE x LED1SCALE where: LED1PEAK is the LEDX1 peak target value (mA). LED1COARSE = 44.5 + 17.8 x (Register 0x23, Bits[3:0]). LED1FINE = 0.73 + 0.022 x (Register 0x25, Bits[4:0]). LED1SCALE = 0.1 + 0.9 x (Register 0x23, Bit 13). Write 0x0. LEDX2 current scale factor. 1: 100% strength. 0: 40% strength; sets the LEDX2 driver in low power mode. LED2 Current Scale = 0.1 + 0.9 x (Register 0x24, Bit 13) Write 0x1. Write 0x0. LEDX2 driver slew rate control. The slower the slew rate, the safer the performance in terms of reducing the risk of overvoltage of the LED driver. 0: the slowest slew rate. ... 7: the fastest slew rate. LEDX2 coarse current setting. Coarse current sink target value of LEDX2 in standard operation. 0x0: lowest coarse setting. ... 0xF: highest coarse setting. LED2PEAK = LED2COARSE x LED2FINE x LED2SCALE where: LED2PEAK is the LEDX2 peak target value (mA). LED2COARSE = 44.5 + 17.8 x (Register 0x24, Bits[3:0]). LED2FINE = 0.73 + 0.022 x (Register 0x25, Bits[10:6]). LED2SCALE = 0.1 + 0.9 x (Register 0x24, Bit 13). LEDX3 fine adjust. Current adjust multiplier for LED3. LEDX3 fine adjust = 0.73 + 0.022 x (Register 0x25, Bits[15:11]). See Register 0x22, Bits[3:0], for the full LED3 formula. LEDX2 fine adjust. Current adjust multiplier for LED2. LEDX2 fine adjust = 0.73 + 0.022 x (Register 0x25, Bits[10:6]). See Register 0x24, Bits[3:0], for the full LED2 formula. Write 0x0. LEDX1 fine adjust. Current adjust multiplier for LED1. LEDX1 Fine Adjust = 0.73 + 0.022 x (Register 0x25, Bits[4:0]). See Register 0x23, Bits[3:0], for the full LED1 formula. Rev. B | Page 47 of 61 ADPD188GG Address 0x30 0x31 0x34 0x35 0x36 1 Data Sheet Data Bit [15:13] [12:8] [7:0] [15:8] Default Value 0x0 0x3 0x20 0x08 Access R/W R/W R/W R/W Name Reserved SLOTA_LED_WIDTH SLOTA_LED_OFFSET SLOTA_PULSES [7:0] [15:10] 9 0x18 0x00 0x0 R/W R/W R/W SLOTA_PERIOD Reserved SLOTB_LED_DIS 8 0x0 R/W SLOTA_LED_DIS [7:0] [15:13] [12:8] [7:0] [15:8] [7:0] 0x00 0x0 0x3 0x20 0x08 0x18 R/W R/W Reserved Reserved SLOTB_LED_WIDTH SLOTB_LED_OFFSET SLOTB_PULSES SLOTB_PERIOD R/W R/W Description Write 0x0. LED pulse width (in 1 s step) for Time Slot A. LED offset width (in 1 s step) for Time Slot A. LED Time Slot A pulse count. nA: number of LED pulses in Time Slot A. 8 LSBs of LED Time Slot A pulse period (in 1 s step). Write 0x0. Time Slot B LED disable. 1: disables the LED assigned to Time Slot B. Register 0x34 keeps the drivers active and prevents them from pulsing current to the LEDs. Disabling both LEDs via this register is often used to measure the dark level. Use Register 0x11 instead to enable or disable the actual time slot usage and not only the LED. Time Slot A LED disable. 1: disables the LED assigned to Time Slot A. Use Register 0x11 instead to enable or disable the actual time slot usage and not only the LED. Write 0x00. Write 0x0. LED pulse width (in 1 s step) for Time Slot B. LED offset width (in 1 s step) for Time Slot B. LED Time Slot B pulse count. nB: number of LED pulses in Time Slot B. 8 LSBs of LED Time Slot B pulse period (in 1 s step). LED equations provide an estimate of the LED current to within 20% at 25C when applying 5.0 V on the VLEDx pin. This current varies with the VLEDx supply level and temperature. AFE CONFIGURATION REGISTERS Table 28. AFE Global Configuration Registers Address 0x37 0x3C Data Bit [15:13] Default Value 0x0 Access R/W Name CH34_DISABLE [12:10] 0x0 R/W CH2_DISABLE [9:8] [7:2] [1:0] [15:14] [13:11] 10 9 0x0 0x00 0x0 0x0 0x6 0x0 0x0 R/W R/W R/W R/W R/W R/W R/W SLOTB_PERIOD Reserved SLOTA_PERIOD Reserved Reserved Reserved V_CATHODE Rev. B | Page 48 of 61 Description Power-down options for Channel 3 and Channel 4 only. Bit 13: power down Channel 3, Channel 4 TIA op amp. Bit 14: power down Channel 3, Channel 4 BPF op amp. Bit 15: power down Channel 3, Channel 4 integrator op amp. Bit 10: power down Channel 2 TIA op amp. Bit 11: power down Channel 2 BPF op amp. Bit 12: power down Channel 2 integrator op amp. 8 MSBs of LED Time Slot B pulse period. Write 0x00 8 MSBs of LED Time Slot A pulse period. Write 0x0. Write 0x6. Reserved. 0x0: 1.3 V (identical to anode voltage). 0x1: 1.8 V (reverse bias photodiode by 550 mV). This setting may add noise. Data Sheet Address 0x54 0x55 ADPD188GG Data Bit [8:3] Default Value 0x00 Access R/W Name AFE_POWERDOWN [2:0] [15:14] [13:12] 0x6 0x0 0x0 R/W R/W R/W Reserved Reserved SLEEP_V_CATHODE [11:10] 0x0 R/W SLOTB_V_CATHODE [9:8] 0x0 R/W SLOTA_V_CATHODE 7 0x0 R/W REG54_VCAT_ENABLE [6:0] [15:12] [11:10] 0x20 0x0 0x0 R/W R/W R/W Reserved Reserved SLOTB_TIA_GAIN_4 [9:8] 0x0 R/W SLOTB_TIA_GAIN_3 Rev. B | Page 49 of 61 Description AFE channels power-down select. 0x0: keeps all channels on. Bit 3: power down Channel 1 TIA op amp. Bit 4: power down Channel 1 BPF op amp. Bit 5: power down Channel 1 integrator op amp. Bit 6: power down Channel 2, Channel 3, and Channel 4 TIA op amp. Bit 7: power down Channel 2, Channel 3, and Channel 4 BPF op amp. Bit 8: power down Channel 2, Channel 3, and Channel 4 integrator op amp. Write 0x6. Write 0x0. If Bit 7 = 1; this setting is applied to the cathode voltage while the device is in sleep mode. 0x0: VDD. 0x1:AFE VREF during idle, VDD during sleep. 0x2: floating. 0x3: 0.0 V. If Bit 7 = 1; this setting is applied to the cathode voltage while the device is in Time Slot B operation. The anode voltage is determined by Register 0x44, Bits[5:4]. 0x0: VDD (1.8 V). 0x1: equal to PD anode voltage. 0x2: sets a reverse PD bias of ~250 mV (recommended setting). 0x3: 0.0 V (this forward biases a diode at the input). If Bit 7 = 1; this setting is applied to the cathode voltage while the device is in Time Slot A operation. The anode voltage is determined by Register 0x42, Bits[5:4]. 0x0: VDD (1.8 V). 0x1: equal to PD anode voltage. 0x2: sets a reverse PD bias of ~250 mV (recommended setting). 0x3: 0.0 V (this forward biases a diode at the input). 0: use the cathode voltage settings defined by Register 0x3C, Bit 9. 1: override Register 0x3C, Bit 9 with cathode settings defined by Register 0x54, Bits[13:8]. Reserved. Write 0x0. TIA gain for Time Slot B, Channel 4 when Register 0x44, Bit 6 = 1. 0: 200 k. 1: 100 k. 2: 50 k. 3: 25 k. TIA gain for Time Slot B, Channel 3 when Register 0x44, Bit 6 = 1. 0: 200 k 1: 100 k. 2: 50 k. 3: 25 k. ADPD188GG Address Data Sheet Data Bit [7:6] Default Value 0x0 Access R/W Name SLOTB_TIA_GAIN_2 [5:4] 0x0 R/W SLOTA_TIA_GAIN_4 [3:2] 0x0 R/W SLOTA_TIA_GAIN_3 [1:0] 0x0 R/W SLOTA_TIA_GAIN_2 Description TIA gain for Time Slot B, Channel 2 when Register 0x44, Bit 6 = 1. 0: 200 k 1: 100 k. 2: 50 k. 3: 25 k. TIA gain for Time Slot A, Channel 4 when Register 0x42, Bit 6 = 1. 0: 200 k 1: 100 k. 2: 50 k. 3: 25 k. TIA gain for Time Slot A, Channel 3 when Register 0x42, Bit 6 = 1. 0: 200 k 1: 100 k. 2: 50 k. 3: 25 k. TIA gain for Time Slot A, Channel 2 when Register 0x42, Bit 6 = 1. 0: 200 k 1: 100 k. 2: 50 k. 3: 25 k. Table 29. AFE Configuration Registers, Time Slot A Address 0x17 0x39 0x42 Data Bit [15:4] [3:0] Default Value 0x000 0x0 Access R/W R/W Name Reserved INTEG_ORDER_A [15:11] [10:0] [15:10] 9 0x4 0x2FC 0x07 0x0 R/W R/W R/W R/W SLOTA_AFE_WIDTH SLOTA_AFE_OFFSET SLOTA_AFE_MODE SLOTA_BUF_GAIN 8 7 0x0 0x0 R/W R/W Reserved SLOTA_INT_AS_BUF 6 0x0 R/W SLOTA_TIA_IND_EN [5:4] 0x3 R/W SLOTA_TIA_VREF Description Write 0x000 Integration sequence order for Time Slot A. Each bit corresponds to the polarity of the integration sequence of a single pulse in a four-pulse sequence. Bit 0 controls the integration sequence of Pulse 1, Bit 1 controls Pulse 2, Bit 2 controls Pulse 3, and Bit 3 controls Pulse 4. After four pulses, the sequence repeats. 0: normal integration sequence. 1: reversed integration sequence. AFE integration window width (in 1 s step) for Time Slot A. AFE integration window offset for Time Slot A in 31.25 ns steps. Set to 0x07. 0: integrator as buffer gain = 1. 1: integrator as buffer gain = 0.7. Set to 0. 0: normal integrator configuration. 1: converts integrator to buffer amplifier (used in TIA ADC mode only). Enable Time Slot A TIA gain individual settings. When it is enabled, the Channel 1 TIA gain is set via Register 0x42, Bits[1:0], and the Channel 2 through Channel 4 TIA gain is set via Register 0x55, Bits[5:0]. 0: disable TIA gain individual setting. 1: enable TIA gain individual setting. Set VREF of the TIA for Time Slot A. 0: 1.14 V. 1: 1.01 V. 2: 0.90 V. 3: 1.27 V (default recommended). Rev. B | Page 50 of 61 Data Sheet Address 0x43 ADPD188GG Data Bit [3:2] [1:0] Default Value 0x2 0x0 Access R/W R/W Name Reserved SLOTA_TIA_GAIN [15:0] 0xADA5 R/W SLOTA_AFE_CFG Description Reserved. Write 0x1. Transimpedance amplifier gain for Time Slot A. When SLOTA_TIA_IND_EN is enabled, this value is for Time Slot B, Channel 1 TIA gain. When SLOTA_TIA_IND_EN is disabled, it is for all four Time Slot A channel TIA gain settings. 0: 200 k. 1: 100 k. 2: 50 k. 3: 25 k. AFE connection in Time Slot A. 0xADA5: analog full path mode (TIABPFINTADC). 0xAE65: TIA ADC mode (must set Register 0x42, Bit 7 = 1 and Register 0x58, Bit 7 = 1). 0xB065: TIA ADC mode (if Register 0x42, Bit 7 = 0). Others: reserved. Table 30. AFE Configuration Registers, Time Slot B Address 0x1D 0x3B 0x44 Data Bit [15:4] [3:0] Default Value 0x000 0x0 Access R/W R/W Name Reserved INTEG_ORDER_B [15:11] [10:0] [15:10] 9 0x04 0x17 0x07 0x0 R/W R/W R/W R/W SLOTB_AFE_WIDTH SLOTB_AFE_OFFSET SLOTB_AFE_MODE SLOTB_BUF_GAIN 8 7 0x0 0x0 R/W R/W Reserved SLOTB_INT_AS_BUF 6 0x0 R/W SLOTB_TIA_IND_EN [5:4] 0x3 R/W SLOTB_TIA_VREF [3:2] 0x2 R/W Reserved Description Write 0x000 Integration sequence order for Time Slot B. Each bit corresponds to the polarity of the integration sequence of a single pulse in a four-pulse sequence. Bit 0 controls the integration sequence of Pulse 1, Bit 1 controls Pulse 2, Bit 2 controls Pulse 3, and Bit 3 controls Pulse 4. After four pulses, the sequence repeats. 0: normal integration sequence. 1: reversed integration sequence AFE integration window width (in 1 s step) for Time Slot B. AFE integration window offset for Time Slot B in 31.25 ns steps. Set to 0x07. 0: integrator as buffer gain = 1. 1: integrator as buffer gain = 0.7. Set to 0. 0: normal integrator configuration. 1: convert integrator to buffer amplifier (used in TIA ADC mode only). Enable Time Slot B TIA gain individual settings. When it is enabled, the Channel 1 TIA gain is set via Register 0x44, Bits[1:0], and the Channel 2 through Channel 4 TIA gain is set via Register 0x55, Bits[11:6]. 0: disable TIA gain individual setting. 1: enable TIA gain individual setting. Set VREF of the TIA for Time Slot B. 0: 1.14 V. 1: 1.01 V. 2: 0.90 V. 3: 1.27 V (default recommended). Write 0x1. Rev. B | Page 51 of 61 ADPD188GG Data Sheet Address Data Bit [1:0] Default Value 0x0 Access R/W Name SLOTB_TIA_GAIN 0x45 [15:0] 0xADA5 R/W SLOTB_AFE_CFG Description Transimpedance amplifier gain for Time Slot B. When SLOTB_TIA_ IND_EN is enabled, this value is for Time Slot B, Channel 1 TIA gain. When SLOTB_TIA_IND_EN is disabled, it is for all four Time Slot B channel TIA gain settings. 0: 200 k. 1: 100 k. 2: 50 k. 3: 25 k. AFE connection in Time Slot B. 0xADA5: analog full path mode (TIABPFINTADC). 0xAE65: TIA ADC mode (must set Register 0x44, Bit 7 = 1 and Register 0x58, Bit 7 = 1). 0xB065: TIA ADC mode (if Register 0x44, Bit 7 = 0). Others: reserved. FLOAT MODE REGISTERS Table 31. Float Mode Registers Address 0x04 0x16 Data Bit [15:8] [7:4] Default Value 0x0 0x0 Access R R Name Reserved BG_STATUS_B [3:0] 0x0 R BG_STATUS_A [15:14] 0x0 R/W BG_COUNT_A [13:0] 0x0 R/W BG_THRESH_A Description Not applicable. Status of comparison between background light level and background threshold value for Time Slot B (BG_THRESH_B). A 1 in any bit location means the threshold has been crossed BG_COUNT_B number of times. This register is cleared once it is read. Bit 4: Time Slot B, Channel 1 exceeded threshold count. Bit 5: Time Slot B, Channel 2 exceeded threshold count. Bit 6: Time Slot B, Channel 3 exceeded threshold count. Bit 7: Time Slot B, Channel 4 exceeded threshold count. Status of comparison between background light level and background threshold value for Time Slot A (BG_THRESH_A). A 1 in any bit location means the threshold has been crossed BG_COUNT_A number of times. This register is cleared once it is read. Bit 0: Time Slot A, Channel 1 exceeded threshold count. Bit 1: Time Slot A, Channel 2 exceeded threshold count. Bit 2: Time Slot A, Channel 3 exceeded threshold count. Bit 3: Time Slot A, Channel 4 exceeded threshold count. For Time Slot A, this is the number of times the ADC value exceeds the BG_THRESH_A value during the float mode subtract cycles before the BG_STATUS_A bit is set. 0: never set BG_STATUS_A. 1: set when BG_THRESH_A is exceeded 1 time. 2: set when BG_THRESH_A is exceeded 4 times. 3: set when BG_THRESH_A is exceeded 16 times. The background threshold for Time Slot A that is compared against the ADC result during the subtract cycles during float mode. If the ADC result exceeds the value in this register, BG_COUNT_A is incremented. Rev. B | Page 52 of 61 Data Sheet ADPD188GG Data Bit [15:14] Default Value 0x0 Access R/W Name BG_COUNT_B [13:0] 0x0 R/W BG_THRESH_B 0x3E [15:14] 0x0 R/W FLT_LED_SELECT_A 0x3F 13 [12:8] [7:0] [15:14] 0 0x03 0x20 0x0 R/W R/W R/W R/W Reserved FLT_LED_WIDTH_A FLT_LED_OFFSET_A FLT_LED_SELECT_B 13 [12:8] [7:0] [15:12] [11:10] 0 0x03 0x20 0x0 0x0 R/W R/W R/W R/W R/W Reserved FLT_LED_WIDTH_B FLT_LED_OFFSET_B Reserved FLT_MATH34_B [9:8] 0x0 R/W FLT_MATH34_A 7 0x0 R/W ENA_INT_AS_BUF [6:5] 0x0 R/W FLT_MATH12_B [4:3] 0x0 R/W Reserved Address 0x1C 0x58 Description For Time Slot B, this is the number of times the ADC value exceeds the BG_THRESH_B value during the float mode subtract cycles before the BG_STATUS_B bit is set. 0: never set BG_STATUS_B. 1: set when BG_THRESH_B is exceeded 1 time. 2: set when BG_THRESH_B is exceeded 4 times. 3: set when BG_THRESH_B is exceeded 16 times. The background threshold for Time Slot B that is compared against the ADC result during the subtract cycles during float mode. If the ADC result exceeds the value in this register, BG_COUNT_B is incremented. Time Slot A LED selection for float LED mode. 0: no LED selected. 1: LED1. 2: LED2. 3: LED3. Write 0x0. Time Slot A LED pulse width for LED float mode in 1 s steps. Time to first LED pulse in float mode for Time Slot A. Time Slot B LED selection for float LED mode. 0: no LED selected. 1: LED1. 2: LED2. 3: LED3. Write 0x0. Time Slot B LED pulse width for LED float mode in 1 s steps. Time to first LED pulse in Float mode for Time Slot A. Reserved. Time Slot B control for adding and subtracting Sample 3 and Sample 4 in a four-pulse sequence (or any multiple of four pulses, for example, Sample 15 and Sample 16 in a 16-pulse sequence). 00: add third and fourth. 01: add third and subtract fourth. 10: subtract third and add fourth. 11: subtract third and fourth. Time Slot A control for adding and subtracting Sample 3 and Sample 4 in a four-pulse sequence (or any multiple of four pulses, for example, Sample 15 and Sample 16 in a 16-pulse sequence). 00: add third and fourth. 01: add third and subtract fourth. 10: subtract third and add fourth. 11: subtract third and fourth. Set to 1 to enable the configuration of the integrator as a buffer in TIA ADC mode. Time Slot B control for adding and subtracting Sample 1 and Sample 2 in a four-pulse sequence (or any multiple of four pulses, for example, Sample 13 and Sample 14 in a 16-pulse sequence). 00: add first and second. 01: add first and subtract second. 10: subtract first and add second. 11: subtract first and second. Write 0x0. Rev. B | Page 53 of 61 ADPD188GG Address 0x59 0x5A 0x5E Data Sheet Data Bit [2:1] Default Value 0x0 Access R/W Name FLT_MATH12_A 0 15 [14:13] 0x0 0x0 0x0 R/W R/W R/W Reserved Reserved FLT_EN_B [12:8] 0x08 R/W FLT_PRECON_B [7:0] [15:12] 0x08 0x0 R/W R/W Reserved FLT_LED_FIRE_B [11:8] 0x0 R/W FLT_LED_FIRE_A [7:0] 15 [14:13] 0x10 0x0 0x0 R/W R/W R/W Reserved Reserved FLT_EN_A [12:8] 0x08 R/W FLT_PRECON_A [7:0] 0x08 R/W Reserved Description Time Slot A control for adding and subtracting Sample 1 and Sample 2 in a four-pulse sequence (or any multiple of four pulses, for example, Sample 13 and Sample 14 in a 16-pulse sequence). 00: add first and second. 01: add first and subtract second. 10: subtract first and add second. 11: subtract first and second. Write 0x0. Write 0x0. 0: default setting, float disabled for Time Slot B. 1: reserved. 2: reserved. 3: enable float mode. Float mode preconditioning time for Time Slot B. Time to start of first float time, which is typically 16 s. Write 0x08. In any given sequence of four pulses, fire the LED in the selected position by writing a zero into that pulse position. Mask the LED pulse (that is, do not fire LED) by writing a 1 into that position. In a sequence of four pulses on Time Slot B, Register 0x5A, Bit 12, is the first pulse, Bit 13 is the second pulse, Bit 14 is the third pulse, and Bit 15 is the fourth pulse. In any given sequence of four pulses, fire the LED in the selected position by writing a zero into that pulse position. Mask the LED pulse (that is, do not fire LED) by writing a 1 into that position. In a sequence of four pulses on Time Slot A, Register 0x5A, Bit 8, is the first pulse, Bit 9 is the second pulse, Bit 10 is the third pulse, and Bit 11 is the fourth pulse. Write 0x10. Write 0x0. 0: default setting, float disabled for Time Slot A. 1: reserved 2: reserved 3: enable float mode in Time Slot A. Float mode preconditioning time for Time Slot A. Time to start of first float time, which is typically 16 s. Write 0x08. Rev. B | Page 54 of 61 Data Sheet ADPD188GG SYSTEM REGISTERS Table 32. System Registers Address 0x00 0x01 0x02 Data Bit [15:8] Default Value 0x00 Access R/W Name FIFO_SAMPLES 7 6 0x0 0x0 R/W R/W Reserved SLOTB_INT 5 0x0 R/W SLOTA_INT [4:0] [15:9] 8 0x00 0x00 0x1 R/W R/W R/W Reserved Reserved FIFO_INT_MASK 7 6 0x1 0x1 R/W R/W Reserved SLOTB_INT_MASK 5 0x1 R/W SLOTA_INT_MASK [4:0] [15:10] 9 0x1F 0x00 0x0 R/W R/W R/W Reserved Reserved GPIO1_DRV 8 0x0 R/W GPIO1_POL [7:3] 2 0x00 0x0 R/W R/W Reserved GPIO0_ENA 1 0x0 R/W GPIO0_DRV 0 0x0 R/W GPIO0_POL Description FIFO status. Number of available bytes to be read from the FIFO. When comparing this to the FIFO length threshold (Register 0x06, Bits[13:8]), note that the FIFO status value is in bytes and the FIFO length threshold is in words, where one word = two bytes. Write 1 to Bit 15 to clear the contents of the FIFO. Write 0x1 to clear this bit to 0x0. Time Slot B interrupt. Describes the type of interrupt event. A 1 indicates an interrupt of a particular event type has occurred. Write a 1 to clear the corresponding interrupt. After clearing, the register goes to 0. Writing a 0 to this register has no effect. Time Slot A interrupt. Describes the type of interrupt event. A 1 indicates an interrupt of a particular event type has occurred. Write a 1 to clear the corresponding interrupt. After clearing, the register goes to 0. Writing a 0 to this register has no effect. Write 0x1F to clear these bits to 0x00. Write 0x00. Sends an interrupt when the FIFO data length has exceeded the FIFO length threshold in Register 0x06, Bits[13:8]. A 0 enables the interrupt. Write 0x1. Sends an interrupt on the Time Slot B sample. Write a 1 to disable the interrupt. Write a 0 to enable the interrupt. Sends an interrupt on the Time Slot A sample. Write a 1 to disable the interrupt. Write a 0 to enable the interrupt. Write 0x1F. Write 0x0000. GPIO1 drive. 0: the GPIO1 pin is always driven. 1: the GPIO1 pin is driven when the interrupt is asserted; otherwise, it is left floating and requires a pull-up or pull-down resistor, depending on polarity (operates as open drain). Use this setting if multiple devices must share the GPIO1 pin. GPIO1 polarity. 0: the GPIO1 pin is active high. 1: the GPIO1 pin is active low. Write 0x00. GPIO0 pin enable. 0: disable the GPIO0 pin. The GPIO0 pin floats, regardless of interrupt status. The status register (Address 0x00) remains active. 1: enable the GPIO0 pin. GPIO0 drive. 0: the GPIO0 pin is always driven. 1: the GPIO0 pin is driven when the interrupt is asserted; otherwise, it is left floating and requires a pull-up or pull-down resistor, depending on polarity (operates as open drain). Use this setting if multiple devices must share the GPIO0 pin. GPIO0 polarity. 0: the GPIO0 pin is active high. 1: the GPIO0 pin is active low. Rev. B | Page 55 of 61 ADPD188GG Address 0x06 0x08 0x09 0x0A 0x0B Data Sheet Data Bit [15:14] [13:8] Default Value 0x0 0x00 Access R/W R/W Name Reserved FIFO_THRESH [7:0] [15:8] [7:0] [15:8] [7:1] 0 [15:12] [11:0] 0x00 0x0A 0x16 0x00 0x64 0x0 0x0 0x000 R/W R R W R/W R R R Reserved REV_NUM DEV_ID ADDRESS_WRITE_KEY SLAVE_ADDRESS Reserved Reserved CLK_RATIO [15:13] [12:8] 0x0 0x00 R/W R/W Reserved GPIO1_ALT_CFG [7:5] [4:0] 0x0 0x00 R/W R/W Reserved GPIO0_ALT_CFG Description Write 0x0. FIFO length threshold. An interrupt is generated when the number of data-words in the FIFO exceeds the value in FIFO_THRESH. The interrupt pin automatically deasserts when the number of data-words available in the FIFO no longer exceeds the value in FIFO_THRESH. Write 0x00. Revision number. Device ID. Write 0xAD when writing to SLAVE_ADDRESS. Otherwise, do not access. I2C slave address. Do not access. Write 0x0. When the CLK32M_CAL_EN bit (Register 0x50, Bit 5) is set, the device calculates the number of 32 MHz clock cycles in two cycles of the 32 kHz clock. The result, nominally 2000 (0x07D0), is stored in the CLK_RATIO bits. Write 0x0. Alternate configuration for the GPIO1 pin. 0x00: GPIO1 is backward compatible to the ADPD103 PDSO pin functionality. 0x01: interrupt function provided on GPIO1, as defined in Register 0x01. 0x02: asserts at the start of the first time slot, deasserts at end of last time slot. 0x05: Time Slot A pulse output. 0x06: Time Slot B pulse output. 0x07: pulse output of both time slots. 0x0C: output data cycle occurred for Time Slot A. 0x0D: output data cycle occurred for Time Slot B. 0x0E: output data cycle occurred. 0x0F: toggles on every sample, which provides a signal at half the sampling rate. 0x10: output = 0. 0x11: output = 1. 0x13: 32 kHz oscillator output. Remaining settings are not supported. Write 0x0. Alternate configuration for the GPIO0 pin. 0x0: GPIO0 is backward compatible to the ADPD103 INT pin functionality. 0x1: interrupt function provided on GPIO0, as defined in Register 0x01. 0x2: asserts at the start of the first time slot, deasserts at end of last time slot. 0x5: Time Slot A pulse output. 0x6: Time Slot B pulse output. 0x7: pulse output of both time slots. 0xC: output data cycle occurred for Time Slot A. 0xD: output data cycle occurred for Time Slot B. 0xE: output data cycle occurred. 0xF: toggles on every sample, which provides a signal at half the sampling rate. 0x10: output = 0. 0x11: output = 1. 0x13: 32 kHz oscillator output. Remaining settings are not supported. Rev. B | Page 56 of 61 Data Sheet ADPD188GG Address 0x0D Data Bit [15:0] Default Value 0x0000 Access R/W Name SLAVE_ADDRESS_KEY 0x0F [15:1] 0 0x0000 0x0 R R/W Reserved SW_RESET 0x10 [15:2] [1:0] 0x0000 0x0 R/W R/W Reserved Mode 0x11 [15:14] 13 0x0 0x0 R/W R/W Reserved RDOUT_MODE 12 0x1 R/W FIFO_OVRN_PREVENT [11:9] [8:6] 0x0 0x0 R/W R/W Reserved SLOTB_FIFO_MODE 5 [4:2] 0x0 0x0 R/W R/W SLOTB_EN SLOTA_FIFO_MODE 1 0 [15:0] [15:9] 8 0x0 0x0 0x0000 0x13 0x0 R/W R/W R/W R/W R/W Reserved SLOTA_EN EXT_SYNC_STARTUP Reserved CLK32K_BYP 7 0x0 R/W CLK32K_EN 6 0x0 R/W Reserved 0x38 0x4B Description Enable changing the I2C address using Register 0x09. 0x04AD: enable address change always. 0x44AD: enable address change if GPIO0 is high. 0x84AD: enable address change if GPIO1 is high. 0xC4AD: enable address change if both GPIO0 and GPIO1 are high. Write 0x0000. Software reset. Write 0x1 to reset the device. This bit clears itself after a reset. For I2C communications, this command returns an acknowledge and the device subsequently returns to standby mode with all registers reset to the default state. Write 0x000. Determines the operating mode of the ADPD1080/ADPD1081. 0x0: standby. 0x1: program. 0x2: normal operation. Reserved. Readback data mode for extended data registers. 0x0: block sum of N samples. 0x1: block average of N samples. 0x0: wrap around FIFO, overwriting old data with new. 0x1: new data if FIFO is not full (recommended setting). Reserved. Time Slot B FIFO data format. 0: no data to FIFO. 1: 16-bit sum of all four channels. 2: 32-bit sum of all four channels. 4: four channels of 16-bit sample data for Time Slot B. 6: four channels of 32-bit extended sample data for Time Slot B. Others: reserved. The selected Time Slot B data is saved in the FIFO. Available only if Time Slot A has the same averaging factor, N (Register 0x15, Bits[10:8] = Bits[6:4]), or if Time Slot A is not saving data to the FIFO (Register 0x11, Bits[4:2] = 0). Time Slot B enable. 1: enables Time Slot B. Time Slot A FIFO data format. 0: no data to FIFO. 1: 16-bit sum of all four channels. 2: 32-bit sum of all four channels. 4: four channels of 16-bit sample data for Time Slot A. 6: four channels of 32-bit extended sample data for Time Slot A. Others: reserved. Write 0x0. Time Slot A enable. 1: enables Time Slot A. Write 0x4000 when EXT_SYNC_SEL is 01 or 10. Otherwise, write 0x0. Write 0x13. Bypass internal 32 kHz oscillator. 0x0: normal operation. 0x1: provide external clock on the GPIO1 pin. The user must set Register 0x4F, Bits[6:5] = 01 to enable the GPIO1 pin as an input. Sample clock power-up. Enables the data sample clock. 0x0: clock disabled. 0x1: normal operation. Write 0x0. Rev. B | Page 57 of 61 ADPD188GG Data Sheet Address Data Bit [5:0] Default Value 0x12 Access R/W Name CLK32K_ADJUST 0x4D [15:8] [7:0] 0x00 0x98 R/W R/W Reserved CLK32M_ADJUST 0x4F [15:8] 7 6 5 4 [3:2] 0x20 0x1 0x0 0x0 0x1 0x0 R/W R/W R/W R/W R/W R/W Reserved Reserved GPIO1_OE GPIO1_IE Reserved EXT_SYNC_SEL 1 0 [15:7] 6 0x0 0x0 0x000 0x0 R/W R/W R/W R/W GPIO0_IE Reserved Reserved GPIO1_CTRL 5 0x0 R/W CLK32M_CAL_EN [4:0] [15:3] 2 0x00 0x0000 0x0 R/W R/W R/W Reserved Reserved SLOTB_DATA_HOLD 0x50 0x5F Description Data sampling (32 kHz) clock frequency adjust. This register is used to calibrate the sample frequency of the device to achieve high precision on the data rate as defined in Register 0x12. Adjusts the sample master 32 kHz clock by 0.6 kHz per LSB. For a 100 Hz sample rate as defined in Register 0x12, 1 LSB of Register 0x4B, Bits[5:0], is 1.9 Hz. Note that a larger value produces a lower frequency. See the Clocks and Timing Calibration section for more information regarding clock adjustment. 00 0000: maximum frequency. 10 0010: typical center frequency. 11 1111: minimum frequency. Write 0x00. Internal timing (32 MHz) clock frequency adjust. This register is used to calibrate the internal clock of the device to achieve precisely timed LED pulses. Adjusts the 32 MHz clock by 109 kHz per LSB. See the Clocks and Timing Calibration section for more information regarding clock adjustment. 0000 0000: minimum frequency. 1001 1000: default frequency. 1111 1111: maximum frequency. Write 0x20. Write 0x1. GPIO1 pin output enable. GPIO1 pin input enable. Write 0x1. Sample sync select. 00: use the internal 32 kHz clock with FSAMPLE to select sample timings. 01: use the GPIO0 pin to trigger sample cycle. 10: use the GPIO1 pin to trigger sample cycle. 11: reserved. GPIO0 pin input enable. Write 0x0. Write 0x000. Controls the GPIO1 output when the GPIO1 output is enabled (GPIO1_OE = 0x1). 0x0: GPIO1 output driven low. 0x1: GPIO1 output driven by the AFE power-down signal. As part of the 32 MHz clock calibration routine, write 1 to begin the clock ratio calculation. Read the result of this calculation from the CLK_RATIO bits in Register 0x0A. Reset this bit to 0 prior to reinitiating the calculation. Write 0x0. Write 0x0000. Setting this bit prevents the update of the data registers corresponding to Time Slot B. Set this bit to ensure that unread data registers are not updated, guaranteeing a contiguous set of data from all four photodiode channels. 1: hold data registers for Time Slot B. 0: allow data register update. Rev. B | Page 58 of 61 Data Sheet Address ADPD188GG Data Bit 1 Default Value 0x0 Access R/W Name SLOTA_DATA_HOLD 0 0x0 R/W DIGITAL_CLOCK_ENA Description Setting this bit prevents the update of the data registers corresponding to Time Slot A. Set this bit to ensure that unread data registers are not updated, guaranteeing a contiguous set of data from all four photodiode channels. 1: hold data registers for Time Slot A. 0: allow data register update. Set to 1 in order to enable the 32 MHz clock when calibrating the 32 MHz clock. Always disable the 32 MHz clock following the calibration by resetting this bit to 0. ADC REGISTERS Table 33. ADC Registers Address 0x12 Data Bits [15:0] Default Value 0x0028 Access R/W Name FSAMPLE 0x15 [15:11] [10:8] 0x00 0x6 R/W R/W Reserved SLOTB_NUM_AVG 7 [6:4] 0x0 0x0 R/W R/W Reserved SLOTA_NUM_AVG 0x18 [3:0] [15:0] 0x0 0x2000 R/W R/W Reserved SLOTA_CH1_OFFSET 0x19 [15:0] 0x2000 R/W SLOTA_CH2_OFFSET 0x1A [15:0] 0x2000 R/W SLOTA_CH3_OFFSET 0x1B [15:0] 0x2000 R/W SLOTA_CH4_OFFSET 0x1E [15:0] 0x2000 R/W SLOTB_CH1_OFFSET 0x1F [15:0] 0x2000 R/W SLOTB_CH2_OFFSET 0x20 [15:0] 0x2000 R/W SLOTB_CH3_OFFSET 0x21 [15:0] 0x2000 R/W SLOTB_CH4_OFFSET Description Sampling frequency: fSAMPLE = 32 kHz/(Register 0x12, Bits[15:0] x 4). For example, 100 Hz = 0x0050; 200 Hz = 0x0028. Write 0x0. Sample sum/average for Time Slot B. Specifies the averaging factor, NB, which is the number of consecutive samples that is summed and averaged after the ADC. Register 0x70 to Register 0x7F hold the data sum. Register 0x64 to Register 0x6B and the data buffer in Register 0x60 hold the data average, which can be used to increase SNR without clipping, in 16-bit registers. The data rate is decimated by the value of the SLOTB_NUMB_AVG bits. 0: 1. 1: 2. 2: 4. 3: 8. 4: 16. 5: 32. 6: 64. 7: 128. Write 0x0. Sample sum/average for Time Slot A. NA: same as Bits[10:8] but for Time Slot A. See description in Register 0x15, Bits[10:8]. Write 0x0. Time Slot A Channel 1 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot A Channel 2 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot A Channel 3 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot A Channel 4 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot B Channel 1 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot B Channel 2 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot B Channel 3 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Time Slot B Channel 4 ADC offset. The value to subtract from the raw ADC value. A value of 0x2000 is typical. Rev. B | Page 59 of 61 ADPD188GG Data Sheet DATA REGISTERS Table 34. Data Registers Address 0x60 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F Data Bits [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] [15:0] Access R R R R R R R R R R R R R R R R R R R R R R R R R Name FIFO_DATA SLOTA_CH1_16BIT SLOTA_CH2_16BIT SLOTA_CH3_16BIT SLOTA_CH4_16BIT SLOTB_CH1_16BIT SLOTB_CH2_16BIT SLOTB_CH3_16BIT SLOTB_CH4_16BIT SLOTA_CH1_LOW SLOTA_CH2_LOW SLOTA_CH3_LOW SLOTA_CH4_LOW SLOTA_CH1_HIGH SLOTA_CH2_HIGH SLOTA_CH3_HIGH SLOTA_CH4_HIGH SLOTB_CH1_LOW SLOTB_CH2_LOW SLOTB_CH3_LOW SLOTB_CH4_LOW SLOTB_CH1_HIGH SLOTB_CH2_HIGH SLOTB_CH3_HIGH SLOTB_CH4_HIGH Description Next available word in FIFO. 16-bit value of Channel1 in Time Slot A. 16-bit value of Channel 2 in Time Slot A. 16-bit value of Channel 3 in Time Slot A. 16-bit value of Channel 4 in Time Slot A. 16-bit value of Channel 1 in Time Slot B. 16-bit value of Channel 2 in Time Slot B. 16-bit value of Channel 3 in Time Slot B. 16-bit value of Channel 4 in Time Slot B. Low data-word for Channel 1 in Time Slot A. Low data-word for Channel 2 in Time Slot A. Low data-word for Channel 3 in Time Slot A. Low data-word for Channel 4 in Time Slot A. High data-word for Channel 1 in Time Slot A. High data-word for Channel 2 in Time Slot A. High data-word for Channel 3 in Time Slot A. High data-word for Channel 4 in Time Slot A. Low data-word for Channel 1 in Time Slot B. Low data-word for Channel 2 in Time Slot B. Low data-word for Channel 3 in Time Slot B. Low data-word for Channel 4 in Time Slot B. High data-word for Channel 1 in Time Slot B. High data-word for Channel 2 in Time Slot B. High data-word for Channel 3 in Time Slot B. High data-word for Channel 4 in Time Slot B. Rev. B | Page 60 of 61 Data Sheet ADPD188GG OUTLINE DIMENSIONS 3.90 3.80 3.70 PIN 1 INDEX AREA 2.42 BSC 0.87 REF 5.10 5.00 4.90 20 24 19 1 13 7 3.00 REF 2.20 BSC 1.00 BSC 12 8 BOTTOM VIEW TOP VIEW 3.13 BSC 0.10 2.00 REF 1.60 BSC 0.70 BSC END VIEW 0.20 BSC COPLANARITY 0.08 SEATING PLANE 11-14-2016-A PKG-005283 PIN 1 INDEX AREA 0.50 BSC 1.68 REF 1.00 0.90 0.80 0.30 0.25 0.20 0.45 0.40 0.35 Figure 41. 24-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV] 3.80 mm x 5.00 mm Body and 0.9 mm Package Height (CE-24-1) Dimensions shown in millimeters ORDERING GUIDE Model 1, 2 ADPD188GG-ACEZR7 ADPD188GG-ACEZRL EVAL-ADPD188GGZ 1 2 Temperature Range -40C to +85C -40C to +85C Package Description 24-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV], 7" Tape and Reel 24-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV], 13" Tape and Reel Evaluation Board Z = RoHS Compliant Part. EVAL-ADPDUCZ is the microcontroller board, ordered separately, required to interface with the EVAL-ADPD188GGZ evaluation board. (c)2018-2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16111-4/20(B) Rev. B | Page 61 of 61 Package Option CE-24-1 CE-24-1