FA3687V Dimensions, mm TSSOP-16 9 8 1 * Wide range of supply voltage: VCC=2.5 to 20V * MOSFET direct driving * Selectable output stage for Pch/Nch MOSFET on each channel * Low operating current by CMOS process: 2.5mA (typ.) * 2ch PWM control IC * High frequency operation: 300kHz to 1.5MHz * Simple setting of operation frequency by timing resistor * Soft start function at each channel * Adjustable maximum duty cycle at each channel * Built-in undervoltage lockout * High accuracy reference voltage: VREF: 1.00V1% VREG: 2.20V1% * Adjustable built-in timer latch for short-circuit protection * Thin and small package: TSSOP-16 0.220.02 0~8 5 0.50.08 1.1max Features 0.105 to 0.145 4.4 6.40.2 16 0.100.05 Description FA3687V is a PWM type DC-to-DC converter control IC with 2ch outputs that can directly drive power MOSFETs. CMOS devices with high breakdown voltage are used in this IC and low power consumption is achieved. This IC is suitable for very small DC-to-DC converters because of their small and thin package (1.1mm max.), and high frequency operation (up to 1.5MHz). You can select Pch or Nch of MOSFETs driven, and design any topology of DC-to-DC converter circuit like a buck, a boost, inverting, a fly-back, or a forward. CMOS IC For Switching Power Supply Control FA3687V 0.65 Block diagram Pin No. Pin symbol Description 1 CP Timer latched short circuit protection 2 SEL2 Selection of type of driven MOSFET (OUT2) 3 FB2 Ch.2 output of error amplifier 4 IN2- Ch.2 inverting input to error amplifier 5 IN2+ Ch.2 non-inverting input to error amplifier 6 VCC Power supply 7 CS2 Soft start for Ch.2 8 OUT2 Ch.2 output 9 OUT1 Ch.1 output 10 CS1 Soft start for Ch.1 11 GND Ground 12 RT Oscillator timing resistor 13 VREG Regulated voltage output 14 IN1- Ch.1 inverting input to error amplifier 15 FB1 Ch.1 output of error amplifier 16 SEL1 Selection of type of driven MOSFET (OUT1) 1 FA3687V Absolute maximum ratings Power supply voltage SEL1, SEL2 pin voltage FB1, IN1-, FB2, IN2-, IN2+ pin voltage CS1, CS2, CP, RT, VREG pin voltage OUT1/2 OUT pin source current OUT pin sink current OUT1/2 OUT pin source current OUT pin sink current Power dissipation * Operating junction temperature Operating ambient temperature Storage temperature Symbol VCC VSEL VEA_IN VCTR_IN IOUT- IOUT+ IOUT- IOUT+ Pd TJ TOPR TSTG Rating 20 -0.3 to 5.0 -0.3 to 5.0 -0.3 to 5.0 -400 (peak) 150 (peak) -50 (continuous) 50 (continuous) 300 (Ta25C) +125 -30 to +85 -40 to +125 Unit V V V V mA mA mA mA mW C C C Maximum power dissipation curve Maximun power dissipation [mW] Item 350 300 250 200 150 100 50 0 -30 0 30 60 90 120 Ambient temperature [C] * Derating factor Ta25C: 3mW/C Recommended operating condition Item Symbol Supply voltage VCC CS1, CS2, CP pin voltage VCTR_IN SEL1, SEL2 pin voltage Max. Unit 2.5 18 V 0.0 2.5 V VSEL_IN 0.0 2.5 V IN1-, IN2-, IN2+ pin voltage VEA_IN 0.0 2.5 V Oscillation frequency fOSC 300 1500 kHz VREG pin capacitance CREG VREG pin current Test condition Min. Typ. 500 Vcc<10V 0.1 1.0 4.7 F 10VVcc<18V 0.47 1.0 4.7 F 1.0 mA IREG VCC pin capacitance CVCC CS1 pin capacitance CCS1 Between CS1 and GND 1.0 0.01 F F CS2 pin capacitance CCS2 Between CS2 and VREG 0.01 F CP pin capacitance CCP Between CP and VREG * 0.01 F * If the timer latched mode is not needed, connect the CP pin to GND. Electrical characteristics (VCC=3.3V, CREG=1.0F, RT=12k, Ta=+25C) Regulated voltage for internal control blocks (VREG pin) Item Symbol Regulated voltage VREG Test condition Line regulation VREG_LINE VCC=2.5 to 18V Load regulation VREG_LOAD IREG=0 to 1mA Variation with temperature VREG_TC Ta= -30 to +85C Item Symbol Test condition Oscillation frequency fOSC Line regulation fOSC_LINE Variation with temperature fOSC_TC1 Min. Typ. Max. Unit 2.178 2.200 2.222 V 5 15 -5 mV -1 mV 0.5 % Oscillator section (RT pin) 2 Min. Typ. Max. Unit 435 500 565 kHz VCC=2.5 to 18V 1 5 % Ta= -30 to +85C 3 % 150 FA3687V Error amplifier section (IN1-, FB1, IN2-, IN2+, FB2 pin) Item Symbol Test condition Min. Reference voltage (ch.1) VREF1 * 0.99 VREF1 Line regulation (ch.1) VREF_LINE VCC=2.5 to 18V VREF1 Variation with temperature (ch.1) VREF_TC1 Ta= -30 to +85C 0.5 Input offset voltage (ch.2) VOFFSET VIN2+=1.0V, IN2+, IN2- VOFFSET VOFF_LINE VCC=2.5 to 18V Input bias current IIN- VINx- =0.0 to 2.5V Common mode input voltage VCOM IN2+, IN2- Open loop gain AVO Line regulation (ch.2) Unity gain bandwidth fT Output current (sink) ISIFB Typ. Max. Unit 1.00 1.01 V 2 5 mV % 10 0 0.0 0.7 mA 1.5 70 V dB 1.5 VFB1=0.5V, VIN1- =VREG mV mV MHz 2.3 3.5 4.7 mA -360 -270 -180 A VFB2=0.5V, VIN2- =VREG, VIN2+=1V Output current (source) ISOFB VFB1=VREG-0.5V, VIN1- =0V VFB2=VREG-0.5V, VIN2- =0V, VIN2+ =1V * The FB1 voltage is measured under the condition that IN1- pin and FB1 pin are shorted. The input offset voltage of the error amplifier is included. Soft start section (CS1, CS2 pin) Item Symbol Test condition Threshold voltage (CS1) VCS1D0N Duty cycle=0%, VFB1=1.4V Min. Typ. Max. (Driving Nch-MOSFET) VCS1D20N Duty cycle=20%, VFB1=1.4V 0.89 VCS1D80N Duty cycle=80%, VFB1=1.4V 1.25 VCS1D100N Duty cycle=100%, VFB1=1.4V Threshold voltage (CS1) VCS1D0P Duty cycle=0%, VFB1=1.4V (Driving Pch-MOSFET) VCS1D20P Duty cycle=20%, VFB1=1.4V 0.90 0.935 0.97 V VCS1D80P Duty cycle=80%, VFB1=1.4V 1.26 1.295 1.33 V 0.82 Unit V 0.925 0.96 1.285 1.32 1.38 V V V 0.82 V VCS1D100P Duty cycle=100%, VFB1=1.4V 1.38 V Threshold voltage (CS2) VCS2D0N Duty cycle=0%, VFB2=0.7V 1.33 V (Driving Nch-MOSFET) VCS2D20N Duty cycle=20%, VFB2=0.7V 1.21 1.245 1.28 VCS2D80N Duty cycle=80%, VFB2=0.7V 0.85 0.885 0.92 VCS2D100N Duty cycle=100%, VFB2=0.7V Threshold voltage (CS2) VCS2D0P Duty cycle=0%, VFB2=0.7V (Driving Pch-MOSFET) VCS2D20P Duty cycle=20%, VFB2=0.7V 1.20 VCS2D80P Duty cycle=80%, VFB2=0.7V 0.84 VCS2D100P Duty cycle=100%, VFB2=0.7V 0.80 V V V 1.33 V 1.23 1.27 0.875 0.91 0.80 V V V Pulse width modulation (PWM) section (FB1, FB2 pin) Item Symbol Test condition Threshold voltage (FB1) VFB1D0N Duty cycle=0%, VCS1=VREG Min. 0.82 Typ. Max. V Unit (Driving Nch-MOSFET) VFB1D20N Duty cycle=20%, VCS1=VREG 0.925 V VFB1D80N Duty cycle=80%, VCS1=VREG 1.285 V VFB1D100N Duty cycle=100%, VCS1=VREG 1.38 V Threshold voltage (FB1) VFB1D0P Duty cycle=0%, VCS1=VREG 0.82 V (Driving Pch-MOSFET) VFB1D20P Duty cycle=20%, VCS1=VREG 0.935 V VFB1D80P Duty cycle=80%, VCS1=VREG 1.295 V VFB1D100P Duty cycle=100%, VCS1=VREG 1.38 V Threshold voltage (FB2) VFB2D0N Duty cycle=0%, VCS2=0V 1.33 V (Driving Nch-MOSFET) VFB2D20N Duty cycle=20%, VCS2=0V 1.245 V VFB2D80N Duty cycle=80%, VCS2=0V 0.885 V VFB2D100N Duty cycle=100%, VCS2=0V 0.80 V Threshold voltage (FB2) VFB2D0P Duty cycle=0%, VCS2=0V 1.33 V (Driving Pch-MOSFET) VFB2D20P Duty cycle=20%, VCS2=0V 1.235 V VFB2D80P Duty cycle=80%, VCS2=0V 0.875 V VFB2D100P Duty cycle=100%, VCS2=0V 0.80 V 3 FA3687V Timer latch protection section (CS pin) Item Symbol Test condition Min. Threshold voltage of FB1 VTHFB1TL *1 Threshold voltage of FB2 VTHFB2TL *2 Threshold voltage of CS1 VTHFB3TL Threshold voltage of CS2 Charge current of CP Threshold voltage of CP VTHCPTL *1 *2 *3 *4 Typ. Max. Unit 1.5 2.0 V 0.2 0.6 V *3 0.2 0.6 V VVTHCS1TL *4 1.5 2.0 V ICP VCP=0.5V, VFB1=2.1V -2.4 -1.5 A 2.1 V -2.0 1.6 The current source of the CP pin operates when the voltage of FB1 exceeds the threshold voltage as shown in the table. The current source of the CP pin operates when the voltage of FB2 falls below the threshold voltage as shown in the table. The timer latch of FB1 is disabled when the CS1 voltage is below the threshold voltage as shown in the table. The timer latch of FB2 is disabled when the CS2 voltage is above the threshold voltage as shown in the table. Undervoltage lockout circuit section (VCC pin) Item Symbol ON threshold voltage of VCC VUVLO Hysteresis voltage VUVLO Test condition Min. Typ. Max. Unit 2.0 2.2 2.35 V 0.1 V Output section (OUT1, OUT2, SEL1, SEL2 pin) Item Symbol Test condition High side on resistance of OUT1/2 RONHI Low side on resistance of OUT1/2 RONLO Min. Typ. Max. Unit IOUT2= -50mA 10 20 IOUT1= -50mA, VCC=5V 9 IOUT1= -50mA, VCC=15V 8 IOUT1=50mA 5 IOUT2=50mA, VCC=5V 5 10 IOUT2=50mA, VCC=15V 5 tRISE CL=1000pF 25 ns Fall time of OUT1/2 tFALL CL=1000pF SEL pin voltage for driving Nch-MOSFET VSELN 0.0 0.2 V SEL pin voltage for driving Pch-MOSFET VSELP VREG-0.2 VREG V Rise time of OUT1/2 40 ns Overall section Item Symbol Test condition Typ. Max. Unit Operating mode supply current ICCA Ch.1, Ch.2 operating mode 2.5 3.5 mA ICCA1 Ch.1, Ch.2 off mode 2.0 mA ICCA2 Ch.1, Ch.2 operating mode, Vcc=18V 3.0 mA ICCA3 Latch mode 2.0 mA 4 Min. FA3687V Characteristic curves Oscillation frequency vs. supply voltage VCC Ta=25C, RT=12k (fOSC=500kHz) 1800 510 1600 508 Oscillation frequency [kHz] Oscillation frequency [kHz] Oscillation frequency vs. timing resistor VCC=3.3V, Ta=25C 1400 1200 1000 800 600 400 506 504 502 500 498 496 494 492 200 490 0 0 1 10 5 10 15 20 Vcc [V] 100 Timing resistor RT [k] Oscillation frequency vs. ambient temperature VCC=3.3V, RT=12k (fOSC=500kHz) Regulated voltage vs. supply voltage VCC Ta=25C, RT=12k (fOSC=500kHz) 2.23 550 Regulated voltage VREG [V] Oscillation frequency [kHz] 570 530 510 490 470 450 430 -50 -25 0 25 50 75 100 125 150 Load current IREG=0A 2.22 2.21 2.20 2.19 2.18 2.17 0 Ambient temperature Ta [C] 5 10 15 20 Vcc [V] Regulated voltage vs. ambient temperature VCC=3.3V, RT=12k (fOSC=500kHz) Regulated voltage vs. load current VCC=3.3V, RT=12k (fOSC=500kHz) 2.23 Regulated voltage VREG [V] Regulated voltage VREG [V] 2.23 2.22 2.21 2.20 2.19 2.18 2.17 -50 2.22 Ta=85C 2.21 2.20 Ta=25C 2.19 Ta=-30C 2.18 2.17 -25 0 25 50 75 100 Ambient temperature Ta [C] 125 150 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Load current IREG [mA] 5 FA3687V Reference voltage vs. ambient temperature VCC=3.3V, RT=12k (fOSC=500kHz) 1.020 1.020 1.015 1.015 Reference voltage VREF [V] Reference voltage VREF [V] Reference voltage vs. supply voltage VCC Ta=25C, RT=12k (fOSC=500kHz) 1.010 1.005 1.000 0.995 0.990 0.985 0.980 1.010 1.005 1.000 0.995 0.990 0.985 0 5 10 15 20 0.980 -50 25 -25 Vcc [V] 50 75 100 125 150 Error amp. output current (source) vs. ambient temperarure VCC=3.3V, RT=12k (fOSC=500kHz) -150 Output current (source) ISOFB [uA] 5.0 Output current (sink) ISIFB [mA] 25 Ambient temperature Ta [C] Error amp. output current (sink) vs. ambient temperature VCC=3.3V, RT=12k (fOSC=500kHz) 4.5 4.0 3.5 3.0 2.5 2.0 -50 0 -25 0 25 50 75 100 125 -200 -250 -300 -350 -50 150 Ambient temperature Ta [C] -25 0 25 50 75 100 125 150 Ambient temperature Ta [C] Charge current of CP vs. ambient temperature VCC=3.3V, RT=12k (fOSC=500kHz) Threshold voltage of CP vs. ambient temperature VCC=3.3V, RT=12k (fOSC=500kHz) 2.3 -1.0 Threshold voltage of CP [V] Charge current of CP [uA] 2.2 -1.5 -2.0 -2.5 -3.0 -50 2.1 2.0 1.9 1.8 1.7 1.6 -25 0 25 50 75 100 Ambient temperature Ta [C] 125 150 1.5 -50 -25 0 25 50 75 100 Ambient temperature Ta [C] 6 125 150 FA3687V Output duty cycle vs. Cs voltage (ch. 1) Driving Nch MOSFET VCC=3.3V, Ta=25C Output duty cycle vs. oscillation frequency (ch. 1) Driving Nch MOSFET VCC=3.3V, Ta=25C 100 100 VCS1=1.35V fosc=300kHz 90 90 fosc=500kHz VCS1=1.30V 80 70 fosc=760kHz 60 fosc=1.5MHz 50 40 30 20 Output duty cycle (ch.1) [%] Output duty cycle (ch.1) [%] 80 VCS1=1.25V 70 VCS1=1.20V 60 VCS1=1.15V 50 VCS1=1.10V VCS1=1.05V 40 VCS1=1.00V 30 VCS1=0.95V 20 VCS1=0.90V 10 VCS1=0.85V 10 0 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 0 300 VCS1 [V] 500 700 900 1100 1300 1500 Oscillation frequency [kHz] Output duty cycle vs. Cs voltage (ch. 1) Driving Nch MOSFET VCC=3.3V, Ta=25C Output duty cycle vs. oscillation frequency (ch. 1) Driving Nch MOSFET VCC=3.3V, Ta=25C 100 100 fosc=300kHz 90 90 VCS1=1.35V 80 VCS1=1.30V fosc=500kHz 70 60 fosc=760kHz 50 fosc=1.5MHz 40 30 20 Output duty cycle (ch.1) [%] Output duty cycle (ch.1) [%] 80 70 VCS1=1.25V VCS1=1.20V 60 VCS1=1.15V 50 40 30 VCS1=1.10V VCS1=1.05V VCS1=1.00V VCS1=0.95V 20 VCS1=0.90V 10 10 0 0.80 0.90 1.00 1.10 1.20 VCS1 [V] 1.30 1.40 1.50 0 300 VCS1=0.85V 500 700 900 1100 1300 1500 Oscillation frequency [kHz] 7 FA3687V Output duty cycle vs. Cs voltage (ch. 2) Driving Nch MOSFET VCC=3.3V, Ta=25C Output duty cycle vs. oscillation frequency (ch. 2) Driving Nch MOSFET VCC=3.3V, Ta=25C 100 100 fosc=300kHz VCS2=0.80V 90 90 fosc=500kHz 80 Output duty cycle (ch.2) [%] Output duty cycle (ch.2) [%] 80 70 fosc=760kHz 60 50 fosc=1.5MHz 40 30 20 0 0.70 VCS2=0.90V 70 VCS2=0.95V 60 50 40 VCS2=1.00V VCS2=1.05V VCS2=1.10V VCS2=1.15V 30 VCS2=1.20V 20 10 VCS2=0.85V VCS2=1.25V 10 0.80 0.90 1.00 1.10 1.20 1.30 0 300 1.40 VCS2=1.30V 500 VCS2 [V] 1300 1500 100 90 90 fosc=300kHz VCS2=0.80V 80 80 fosc=500kHz Output duty cycle (ch.2) [%] Output duty cycle (ch.2) [%] 1100 Output duty cycle vs. oscillation frequency (ch. 2) Driving Nch MOSFET VCC=3.3V, Ta=25C 100 70 60 fosc=760kHz 50 40 fosc=1.5MHz 30 VCS2=0.85V 70 VCS2=0.90V 60 VCS2=0.95V 50 VCS2=1.00V VCS2=1.05V 40 VCS2=1.10V 30 VCS2=1.15V 20 20 VCS2=1.20V 10 10 0 0.70 900 Oscillation frequency [kHz] Output duty cycle vs. Cs voltage (ch. 2) Driving Nch MOSFET VCC=3.3V, Ta=25C VCS2=1.25V VCS2=1.30V 0.80 0.90 1.00 1.10 VCS2 [V] 8 700 1.20 1.30 1.40 0 300 500 700 900 1100 Oscillation frequency [kHz] 1300 1500 FA3687V OUT1 terminal source current vs. H level output voltage Ta=25C OUT2 terminal source current vs. H level output voltage Ta=25C 0 0 -50 -50 -100 -100 Vcc=2.5V -200 Vcc= 3V -250 -300 Vcc= 5V -350 -200 Vcc= 3V -250 -300 Vcc= 5V -350 -400 -400 Vcc=12V -450 -500 0.0 Vcc=2.5V -150 IOUT2 [mA] IOUT1 [mA] -150 Vcc=12V -450 1.0 2.0 3.0 4.0 5.0 -500 0.0 6.0 1.0 Vcc-VOUT1 [V] 3.0 4.0 OUT2 terminal sink current vs. H level output voltage VCC=3.3V 0 0 -50 -50 -100 IOUT2 [mA] -100 Ta=85C -150 Ta=25C -200 Ta=85C -150 -200 Ta=-30C Ta=-30C 0.5 1.0 1.5 2.0 2.5 -300 0.0 3.0 0.5 Vcc-VOUT1 [V] -100 -100 IOUT2 [mA] IOUT1 [mA] 0 -200 Ta=85C Ta=-30C -400 1.5 2.0 2.0 -300 Ta=85C Ta=-30C -400 3.0 Vcc-VOUT1 [V] 3.0 -200 Ta=25C 1.0 2.5 OUT2 terminal sink current vs. H level output voltage VCC=12V 0 -300 1.0 Vcc-VOUT2 [V] OUT1 terminal sink current vs. H level output voltage VCC=12V -500 0.0 Ta=25C -250 -250 -300 0.0 5.0 Vcc-VOUT2 [V] OUT1 terminal sink current vs. H level output voltage VCC=3.3V IOUT1 [mA] 2.0 4.0 Ta=25C 5.0 -500 0.0 1.0 2.0 3.0 4.0 5.0 Vcc-VOUT2 [V] 9 FA3687V OUT1 terminal sink current vs. L level voltage OUT2 terminal sink current vs. L level voltage 200 200 Ta=85C 100 Ta=85C 100 50 50 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 0.0 1.4 0.2 0.4 1.0 1.2 1.4 60 OUT2 terminal rise time tRISE [ns] 60 OUT1 terminal rise time tRISE [ns] 0.8 OUT2 terminal rise time vs. supply voltage VCC CL=1000pF OUT1 terminal rise time vs. supply voltage VCC CL=1000pF 50 Ta=85C 40 Ta=25C 30 Ta=-30C 20 10 50 Ta=85C 40 Ta=25C 30 20 Ta=-30C 10 0 0 0 5 10 15 20 0 5 Vcc [V] 10 15 20 Vcc [V] OUT2 terminal fall time vs. supply voltage VCC CL=1000pF OUT1 terminal fall time vs. supply voltage VCC CL=1000pF 200 200 OUT2 terminal fall time tFALL [ns] OUT1 terminal fall time tFALL [ns] 0.6 VOUT2 [V] VOUT1 [V] Ta=85C 150 Ta=25C 100 Ta=-30C 50 Ta=85C 150 Ta=25C 100 Ta=-30C 50 0 0 0 5 10 Vcc [V] 10 Ta=25C Ta=-30C 150 IOUT2 [mA] IOUT1 [mA] Ta=25C Ta=-30C 150 15 20 0 5 10 Vcc [V] 15 20 FA3687V UVLO ON threshold vs. ambient temperature 6.0 2.5 Vcc=18V Vcc=12V 5.0 Vcc=5V 4.0 3.0 Vcc=3.3V UVLO ON threshold VUVLO [V] Operating mode supply current ICCA [mA] Operating mode supply current vs. oscillation frequency Ta=25C Vcc=2.5V 2.0 300 500 700 900 1100 1300 2.4 2.3 2.2 2.1 2.0 1.9 1.8 -50 1500 -25 0 25 50 75 100 125 150 Ambient temperature Ta [C] Oscillation frequency [kHz] CS1 internal discharge switch current vs. voltage VCC=3.3V, RT=12k (fOSC=500kHz) CS2 internal discharge switch current vs. voltage VCC=3.3V, RT=12k (fOSC=500kHz) 0 400 Ta=-30C 350 300 -50 250 ICS2 off [A] ICS1off [A] Ta=25C Ta=85C 200 150 100 -100 Ta=85C -150 Ta=25C 50 Ta=-30C 0 0.00 0.50 1.00 1.50 2.00 2.50 -200 0.00 0.50 1.00 1.50 2.00 VCS1 [V] VREG -VCS2 [V] Error amplifier gain and phase vs. frequency 11 FA3687V Description of each circuit 1. Reference voltage circuit (VREF) This circuit generates the reference voltage of 1.00V1% compensated in temperature from VCC voltage, and is connected to the non-inverting input of the error amplifier. The voltage cannot be observed directly because there is no external pin for this purpose. 2. Regulated voltage circuit (VREG) This circuit generates 2.20V1% based on the reference voltage VREF, and is used as the power supply of the internal IC circuits. The voltage is generated when the supply voltage, VCC is input. The VREG voltage is also used as a regulated power supply for soft start, maximum duty cycle limitation, and others. The output current for external circuit should be within 1mA. A capacitor connected between VREG pin and GND pin is necessary to stabilize the VREG voltage (To determine capacitance, refer to recommended operating conditions). The VREG voltage is regulated in VCC voltage of 2.4V or above. 3. Oscillator The oscillator generates a triangular waveform by charging and discharging the built-in capacitor. A desired oscillation frequency can be set by the value of the resistor connected to the RT pin (Fig. 1). The built-in capacitor voltage oscillates between approximately 0.82V and 1.38V at fosc=500kHz (that of ch1 and ch2 are slightly different) with almost the same charging and discharging gradients (Fig. 2). You can set the desired oscillation frequency by changing the gradients using the resistor connected to the RT pin (Large RT: Low frequency, Small RT: High frequency). The oscillator waveform cannot be observed from the outside because a pin for this purpose is not provided. The RT pin voltage is approximately 1V DC in normal operation. The oscillator output is connected to the PWM comparator. 4. Error amplifier circuit The error amplifier 1 has the inverting input of IN1(-) pin (Pin14). The non-inverting input is internally connected to the reference voltage VREF (1.00V1%; 25C). The error amplifier 2 has the inverting input IN2(-) pin (Pin4) and non-inverting input IN2(+) pin (Pin5) externally. Since each input of error amplifier 2 is connected to the pins, CH2 is suitable for any circuit topology. The FB pins (Pin3, Pin15) are the output of the error amplifier. An external RC network is connected between FB pin and IN-pin for gain and phase compensation setting. (Fig. 3) For connecting of each topology, see "Design advice". OSC 12 RT RT Fig. 1 RT value:Small 0.82V Fig. 2 Vout1 RNF1 R1 Er. Amp.1 14 FB1 15 IN1R2 + VREF (1.0V) Vout2 Comp VREG 13 R3 R5 Er. Amp.2 Comp IN2+ FB2 5 IN2R4 3 4 R6 RNF2 Fig. 3 12 RT value:Large 1.38V FA3687V 5. PWM comparator The PWM output generates from the oscillator output, the error amplifier output (FB1, FB2) and CS voltage (CS1, CS2) (Fig. 4). The oscillator output is compared with the preferred lower voltage between FB1 and CS1 for ch1. While the preferred voltage is lower than oscillator output, the PWM output is low. While the preferred voltage is higher than oscillator output, the PWM output is high. Since the phase of Ch2 is the opposite phase of Ch1, higher voltage between FB2 and CS2 is preferred and while the preferred voltage is lower than the oscillator output, the PWM output 2 is high. (Cannot be observed externally) The output polarity of OUT1, OUT2 changes according to the condition of SEL pin. (See Fig. 6) 6. Soft start function This IC has a soft start function to protect DC-to-DC converter circuits from damage when starting operation. CS1 pin (Pin10), and CS2 pin (Pin7) are used for soft start function of ch1 and ch2 respectively (Fig. 5). When the supply voltage is applied to the VCC pin and UVLO is cancelled, capacitor CCS1 and CCS2 is charged by VREG through the resistor R7 or R9. Therefore, CS1 voltage gradually increases and CS2 voltage gradually decreases. Since CS1 and CS2 pin are connected to the PWM comparator internally, the pulses gradually widen and then the soft start function operates (Fig. 6). The maximum duty cycle can be set by using the CS pins. (See "Design advice" about the detail) PWM output1 PWM Comp.1 FB1 OUT1 N/P ch. drive 9 CS1 16 SEL1 Oscillator output UVLO CS2 PWM output2 OUT2 N/P ch. drive FB2 8 PWM Comp.2 2 SEL2 Fig. 4 VREG R7 VREG 13 13 CCS2 10 7 CS2 CCS1 CS1 R9 Fig. 5 Er. Amp.1 output CS1 pin voltage Oscillator output PWM output 1 OUT1 Pch.drive (SEL1:VREG) OUT1 Nch.drive (SEL1:GND) CS2 pin voltage Oscillator output Er. Amp.2 output PWM output2 OUT2 Pch.drive (SEL2:VREG) OUT2 Nch.drive (SEL2:GND) Fig. 6 13 FA3687V tp [s] = CCP VTHCPTL ICP VTHCPTL: CP pin latched mode threshold voltage [V] ICP: CP charge source current [A] Capacitance of CP pin capacitor CCP: You can reset off latched mode of the short-circuit protection by either of the following ways about 1) CP pin, or 2) VCC pin, or 3) CS1or CS2 pin: 1) CP voltage = 0V 2) VCC voltage UVLO voltage (2.2V typ.) or below 3) Set the CS pin of the cause of off latched mode as follows CS1 pin voltage = 0V, CS2 pin voltage = VREG If the timer-latched mode is not necessary, connect the CP pin to GND. 8. Output circuit The IC contains a push-pull output stage and can directly drive MOSFETs. The maximum peak current of the output stage is sink current of +150mA, and source current of -400mA. The IC can also drive NPN and PNP transistors. The maximum current in such cases is 50mA. You must design the output current considering the rating of power dissipation. (See "Design advice') You can switch the types of external discrete MOSFETs by wiring of the SEL pins (Pin 2, Pin 16). For driving Nch MOS, connect the SEL pins to GND. For driving Pch MOS, connect the SEL pins to VREG. You can design buck converter or inverting converter by driving Pch MOS, and boost converter by driving Nch MOS. Connect them either to GND or to VREG surely. 9. Undervoltage lockout circuit The IC contains a undervoltage lockout circuit to protect the circuit from the damage caused by malfunctions when the supply voltage drops. When the supply voltage rises from 0V, the IC starts to operate at VCC of 2.2V (typ.) and outputs generate pulses. If a drop of the supply voltage occurs, it stops output at VCC of 2.1V (typ.). When it occurs, the CS1 pin is turned to low level and the CS2 pin to high level, and then these pins are reset. 14 Icp Vcp 1 CP CCP Fig. 7 Momentary short circuit CP pin voltage [V] 7. Timer latch short-circuit protection circuit This IC has the timer latch short-circuit protection circuit. This circuit cuts off the output of all channels when the output voltage of DC-to-DC converter drops due to short circuit or overload. To set delay time for timer latch operation, a capacitor CCP should be connected to the CP pin (Fig. 7). When one of the output voltage of the DC-to-DC converter drops due to short circuit or overload, the FB1 pin voltage increases up to around the VREG voltage for ch1, or the FB2 pin voltage drops down to around 0V for ch2. When FB1 pin voltage exceeds 2.0V (max.) or FB2 pin voltage falls below 0.2V (min.), constant-current source (2A typ.) starts charging the capacitor CCP connected to the CP pin. If the voltage of the CP pin exceeds 2.1 V (max.), the circuit regards the case as abnormal. Then the IC is set to off latch mode and the output of all channels is shut off (Fig. 8), and the current consumption becomes 2mA (typ.). The period (tp) between the occurrence of short-circuit in the converter output and setting to off latched mode can be calculated by the following equation: Short circuit VREG pin voltag 2.1V (max) 2.0 Start-up Short circuit protection 1.0 tp Time t Fig. 8 FA3687V Design advice 1. Setting the oscillation frequency As described in item 1 of "Description of each circuit," a desired oscillation frequency can be determined by the value of the resistor connected to the RT pin. When designing an oscillation frequency, you can set any frequency between 300kHz and 1.5MHz. You can obtain the oscillation frequency from the characteristic curve "Oscillation frequency (fosc) vs. timing resistor resistance (RT)" or the value can be approximately calculated by the following expression. fOSC = 4050 RT -0.86 RT = ( ) 4050 fOSC fOSC: Oscillation frequency [kHz] RT: Timing resistor [k] 1.16 This expression, however, can be used for rough calculation, the obitained value is not guaranteed. The operation frequency varies due to the conditions such as tolerance of the characteristics of the ICs, influence of noises, or external discrete components. When determining the values, examine the effectiveness of the values in an actual circuit. The timing resistor RT should be wired to the GND pin as shortly as possible because the RT pin is a high impedance pin and is easy affected by noises. 2. Operation near the maximum or the minimum output duty cycle As described in "Output duty cycle vs. voltage", the output duty cycle of this IC changes sharply near the minimum and the maximum output duty cycle. Note that these phenomena are conspicuous for high frequency operation (when the pulse width is narrow). 3. Determining soft start period The period from the start of charging the capacitor CCS to widening n% of output duty cycle can be roughly calculated by the following expression: (see Fig. 5 for symbols) ( t [ms] = R7 CCS1 1n 1 - t [ms] = R9 CCS2 1n ( VV VCS1n VREG CS2n REG ) ) For CS1 pin For CS2 pin CCS1, CCS2: Capacitance connected to CS1or CS2 pin [F] R7, R9: Resistance connected to CS1 or CS2 pin [k] VCS1n and VCS2n are the voltage of the CS1 and CS2 pins in n% of output duty cycle, and vary in accordance with operating frequency. The value can be obtained from the characteristic curve "Output duty cycle vs. CS voltage" To reset the soft start function, the supply voltage VCC is lowered below the UVLO voltage (2.1V typ.) and then the internal switch discharges the CS capacitor. The characteristics of the internal switch for discharge are shown in following the characteristics curves of "Characteristics of CS1 internal discharge switch current vs. voltage" and "Characteristics of CS2 internal discharge switch current vs. voltage". Therefore, when determining the period of soft start at restarting the power supply, consider the characteristics carefully. 15 FA3687V 4. Setting maximum duty cycle As described in the Fig. 9, you can limit maximum duty cycle by connecting a resistor divider "R7, R8 or R9, R10" between CS1, CS2 and VREG pin. Set the maximum duty cycle considering that relation between the maximum output duty cycle and the CS pin voltage changes with operation frequency as described in the characteristic curves of "Output duty cycle vs. oscillation frequency" and "Output duty cycle vs. CS voltage". When the maximum duty cycle is limited, CS pin voltage at start-up is described in Fig. 10, and the approximate value of soft start period can be obtained by the following expressions: VREG R7 R10 10 13 7 CS2 CS1 R8 VREG CCS2 13 R9 CCS1 Fig. 9 Ch1 ( t [ms] = R0 CCS1 1n 1- VCS1n VCS1 ) R0 = R7R8 R7+R8 For CS1 Vcc Threshold voltage R8 The divided CS1 voltage is obtained by: VCS1 = R7+R8 VREG VCS1N R8 VREG R7 + R8 t [ms] = R0 CCS2 1n (VV CS2n REG - VCS2 - VCS2 ) R0 = R9R10 R9+R10 For CS2 t0 The divided CS2 voltage is obtained by: VCS2 = R9 VREG R9 + R10 CCS1, CCS2: Capacitance connected to the CS1 or CS2 pin [F] R7, R8, R9, R10: Resistance connected to CS1 or CS2 pin [k] VCS1n and VCS2n are the voltages of CS1 and CS2 under a certain output duty cycle and varies with operation frequencies. The values of VCS1n and VCS2n can be obtained from the characteristic curves of "Output duty cycle vs. CS voltage". The charging of CCS1 and CCS2 after UVLO is unlocked. Therefore, the period from power-on of Vcc to widening n% of output duty cycle is the sum of t0 and t. 5. Determining the output voltage of DC-DC converters The ways to determine the output voltage of the DC-DC converter of each channel is shown in Fig. 10 and the following equations. For ch1: The positive output voltage of DC-to-DC converter (a buck, a boost) is determined by: Vout1 = R1 + R2 VREF R2 For ch2: The positive output voltage of DC-to-DC converter is determined by: Vout2 = V1 R3 + R4 R3 Here, V1 = VREG R6 R5 + R6 When R5=R6, Vout2 = VREG 16 + R4 ( R32R3 ) t Ch2 VCC VREG pin voltage Threshold voltage R9 R9+R10 VCS2n VREG t0 t t0: Time from power-on of VCC to reaching unlock voltage of UVLO. Fig. 10 FA3687V The negative output voltage of DC-to-DC converter (inverting) is determined by: OUT1 Vout1 9 SEL1 R3 + R4 R4 Vout2 = V1 - VREG R3 R3 R1 The ratio of resistances is determined by: R2 VREG 16 Vout1 IN114 FB1 15 + VREF (1.0V) Buck R3 VREG - V1 = R4 Vout2 + V1 (Use the absolute value of the Vout2 voltage.) OUT1 Vout1 9 Vout1 SEL1 When R5 = R6, 16 R1 IN1- GND FB1 14 R3 - R4 Vout2 = VREG 2R3 ( ) 15 + R2 VREF (1.0V) Boost Connect the SEL1 and SEL2 pin to GND or VREG surely. 6. Restriction of external discrete components and recommended operating conditions To achieve a stable operation of the IC, the value of external discrete components connected to VCC, VREG, CS, CP pins should be within the recommended operating conditions. And the voltage and the current applied to each pin should be also within the recommended operating conditions. If the pin voltage of OUT1, OUT2, or VREG becomes higher than the VCC pin voltage, the current flows from the pins to the VCC pin because parasitic three diodes exist between the VCC pin and these pins. Be careful not to allow this current to flow. OUT2 8 Vout2 VREG SEL2 13 VREG Vout2 2 R4 R5 IN2+ FB2 5 3 IN2- 4 V1 R3 Buck R6 OUT2 8 Vout2 Vout2 VREG SEL2 13 2 7. Loss calculation Since it is hard to measure IC loss directly, the calculation to obtain the approximate loss of the IC connected directly to a MOSFET is described below. When the supply voltage is VCC, the current consumption of the IC is ICCA, the total input gate charge of the driven MOSFET is Qg and the switching frequency is fsw, the total loss Pd of the IC can be calculated by: R4 R5 IN2+ FB2 5 IN2V1 R3 GND 3 4 Boost R6 OUT2 8 VREG SEL2 13 VREG Vout2 2 Pd VCC (ICCA + Qg fsw). R3 R5 V1 IN2+ FB2 5 3 4 The value in this expression is influenced by the effects of the dependency of supply voltage, the characteristics of temperature, or the tolerance of parameter. Therefore, evaluate the appropriateness of IC loss sufficiently considering the range of values of above parameters under all conditions. R4 R6 IN2- Inverting Vout2 Fig. 11 Example ICCA=2.5mA for VCC=3.3V in the case of a typical IC from the characteristic curves. Qg=6nC, fsw=500kHz, the IC loss "Pd" is as follows. Pd 3.3 (2.5mA + 6nC 500kHz) 18.2mW If two MOSFETs are driven under the same condition for 2 channels, Pd is as follows: Pd 3.3 {2.5mA+2 (6nC 500kHz)} = 28.1mW 17 FA3687V Application circuit 5V/500mA 7to18V 40k 10F GND 10F GND 10k 0.1uF 10k 0.01F CP SEL2 FB2 IN2- IN2+ VCC CS2 OUT2 8 2 1 7 3 5 4 6 1F FA3687V 6.2k 3.3V/500mA 0.01F 100k 16 13 14 15 9 12 10 11 SEL1 FB1 IN1- VREG RT GND CS1 OUT1 0.1F 100k 0.47F 11k 10k 1M 10k 0.01F 10k 0.068F Parts tolerances characteristics are not defined in the circuit design sample shown above. When designing an actual circuit for a product, you must determine parts tolerances and characteristics for safe and economical operation. 18 22k 100 10F