Integrated Circuit
True RMS-to-DC Converter
Data Sheet AD536A
Rev. G Document Feedback
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FEATURES
True rms-to-dc conversion
Laser trimmed to high accuracy
±0.2% maximum error (AD536AK)
±0.5% maximum error (AD536AJ)
Wide response capability
Computes rms of ac and dc signals
450 kHz bandwidth: V rms > 100 mV
2 MHz bandwidth: V rms > 1 V
Signal crest factor of 7 for 1% error
dB output with 60 dB range
Low power: 1.2 mA quiescent current
Single- or dual-supply operation
Monolithic integrated circuit
−55°C to +125°C operation (AD536AS)
GENERAL DESCRIPTION
The AD536A is a complete monolithic integrated circuit that
performs true rms-to-dc conversion. It offers performance
comparable or superior to that of hybrid or modular units costing
much more. The AD536A directly computes the true rms value of
any complex input waveform containing ac and dc components.
A crest factor compensation scheme allows measurements with 1%
error at crest factors up to 7. The wide bandwidth of the device
extends the measurement capability to 300 kHz with less than 3 dB
errors for signal levels greater than 100 mV.
An important feature of the AD536A, not previously available
in rms converters, is an auxiliary dB output pin. The logarithm
of the rms output signal is brought out to a separate pin to allow
the dB conversion, with a useful dynamic range of 60 dB. Using
an externally supplied reference current, the 0 dB level can be
conveniently set to correspond to any input level from 0.1 V to
2 V rms.
The AD536A is laser trimmed to minimize input and output offset
voltage, to optimize positive and negative waveform symmetry
(dc reversal error), and to provide full-scale accuracy at 7 V rms.
As a result, no external trims are required to achieve the rated
unit accuracy.
The input and output pins are fully protected. The input circuitry
can take overload voltages well beyond the supply levels. Loss of
supply voltage with the input connected to external circuitry does
not cause the device to fail. The output is short-circuit protected.
FUNCTIONAL BLOCK DIAGRAM
dB
BUFFER IN
V
IN
25kΩ
80kΩ
25kΩ
C
AV
+V
S
–V
S
+V
S
COM
AD536A
R
L
I
OUT
BUFFER
OUT
CURRENT
MIRROR
SQUARER/
DIVIDER
ABSOLUTE
VALUE
00504-001
+
BUF
Figure 1.
The AD536A is available in two accuracy grades (J and K) for
commercial temperature range (0°C to 70°C) applications, and
one grade (S) rated for the −55°C to +125°C extended range.
The AD536AK offers a maximum total error of ±2 mV ± 0.2%
of reading, while the AD536AJ and AD536AS have maximum
errors of ±5 mV ± 0.5% of reading. All three versions are available
in a hermetically sealed 14-lead DIP or a 10-pin TO-100 metal
header package. The AD536AS is also available in a 20-terminal
leadless hermetically sealed ceramic chip carrier.
The AD536A computes the true root-mean-square level of a
complex ac (or ac plus dc) input signal and provides an equiva-
lent dc output level. The true rms value of a waveform is a more
useful quantity than the average rectified value because it relates
directly to the power of the signal. The rms value of a statistical
signal also relates to its standard deviation.
An external capacitor is required to perform measurements to the
fully specified accuracy. The value of this capacitor determines the
low frequency ac accuracy, ripple amplitude, and settling time.
The AD536A operates equally well from split supplies or a
single supply with total supply levels from 5 V to 36 V. With
1 mA quiescent supply current, the device is well suited for a
wide variety of remote controllers and battery-powered
instruments.
AD536A Data Sheet
Rev. G | Page 2 of 15
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Theory of Operation ........................................................................ 8
Connections for dB Operation ................................................... 8
Frequency Response .....................................................................9
AC Measurement Accuracy and Crest Factor ...........................9
Applications Information .............................................................. 11
Typical Connections .................................................................. 11
Optional External Trims For High Accuracy ......................... 11
Single-Supply Operation ........................................................... 12
Choosing the Averaging Time Constant ................................. 12
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 15
REVISION HISTORY
3/2019—Rev. F to Rev. G
Changes to Figure 5 and Table 5 ..................................................... 7
Change to Figure 16 ....................................................................... 12
Changes to Ordering Guide .......................................................... 15
11/2014—Rev. E to Rev. F
Change to Figure 1 ........................................................................... 1
Changes to Table 1 ............................................................................ 3
Change to Figure 16 ....................................................................... 12
Changes to Ordering Guide .......................................................... 15
7/2012—Rev. D to Rev. E
Reorganized Layout ............................................................ Universal
Changes to Figure 1 .......................................................................... 1
Changes to Figure 6 .......................................................................... 8
Changes to Figure 7 .......................................................................... 9
Changes to Figure 13, Figure 14, and Figure 15 ......................... 11
Changes to Figure 16, Figure 17, and Single-Supply Operation
Section .............................................................................................. 12
Changes to Figure 21 ...................................................................... 13
Updated Outline Dimensions ....................................................... 14
8/2008—Rev. C to Rev. D
Changes to Features Section............................................................ 1
Changes to General Description Section ...................................... 1
Changes to Figure 1 .......................................................................... 1
Changes to Table 2 ............................................................................ 5
Change to Figure 2 ............................................................................ 5
Changes to Figure 15 ...................................................................... 10
Changes to Connections for dB Operation Section .................. 11
Changes to Figure 17 ...................................................................... 12
Changes to Frequency Response Section .................................... 12
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 15
3/2006—Rev. B to Rev. C
Updated Format .................................................................. Universal
Changed Product Description to General Description ................ 1
Changes to General Description ..................................................... 1
Changes to Table 1 ............................................................................. 3
Changes to Table 2 ............................................................................. 5
Added Pin Configurations and Function Descriptions ............... 6
Changed Standard Connection to Typical Connections ............. 8
Changed Single Supply Connection to Single Supply
Operation ............................................................................................ 9
Changes to Connections for dB Operation................................. 11
Changes to Figure 17 ...................................................................... 12
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 15
6/1999—Rev. A to Rev. B
1/1976—Revision 0: Initial Version
Data Sheet AD536A
Rev. G | Page 3 of 15
SPECIFICATIONS
TA = +25°C and ±15 V dc, unless otherwise noted.
Table 1.
AD536AJ AD536AK AD536AS
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
TRANSFER FUNCTION VOUT = √Avg(VIN)2 V
OUT = √Avg(VIN)2 V
OUT = √Avg(VIN)2
CONVERSION ACCURACY
Total Error, Internal Trim1
(See Figure 13)
±5 ± 0.5 ±2 ± 0.2 ±5 ± 0.5 mV ± % of rdg
vs. Temperature
TMIN to +70°C ±0.1 ± 0.01 ±0.05 ±
0.005
±0.1 ±
0.005
mV ± % of rdg/°C
+70°C to +125°C ±0.3 ±
0.005
mV ± % of rdg/°C
vs. Supply Voltage ±0.1 ± 0.01 ±0.1 ± 0.01 ±0.1 ± 0.01 mV ± % of rdg/V
DC Reversal Error ±0.2 ±0.1 ±0.2 mV ± % of rdg
Total Error, External Trim1
(See Figure 16)
±3 ± 0.3 ±2 ± 0.1 ±3 ± 0.3 mV ± % of rdg
ERROR VS. CREST FACTOR2
Crest Factor 1 to Crest Factor 2 Specified accuracy Specified accuracy Specified accuracy
Crest Factor = 3 −0.1 −0.1 −0.1 % of rdg
Crest Factor = 7 −1.0 −1.0 −1.0 % of rdg
FREQUENCY RESPONSE3
Bandwidth for 1% Additional
Error (0.09 dB)
VIN = 10 mV 5 5 5 kHz
VIN = 100 mV 45 45 45 kHz
VIN = 1 V 120 120 120 kHz
±3 dB Bandwidth
VIN = 10 mV 90 90 90 kHz
VIN = 100 mV 450 450 450 kHz
VIN = 1 V 2.3 2.3 2.3 MHz
AVERAGING TIME CONSTANT
(See Figure 19)
25 25 25 ms/µF
INPUT CHARACTERISTICS
Signal Range, ±15 V Supplies
Continuous RMS Level 0 to 7 0 to 7 0 to 7 V rms
Peak Transient Input ±20 ±20 ±20 V peak
Continuous RMS Level,
VS = ±5 V
0 to 2 0 to 2 0 to 2 V rms
Peak Transient Input,
VS = ±5 V
±7 ±7 ±7 V peak
Maximum Continuous
Nondestructive Input Level
(All Supply Voltages)
±25 ±25 ±25 V peak
Input Resistance 13.33 16.67 20 13.33 16.67 20 13.33 16.67 20 kΩ
Input Offset Voltage 0.8 ±2 0.5 ±1 0.8 ±2 mV
OUTPUT CHARACTERISTICS
Offset Voltage, VIN = COM
(See Figure 13)
±1 ±2 ±0.5 ±1 ±2 mV
vs. Temperature ±0.1 ±0.1 ±0.2 mV/°C
vs. Supply Voltage ±0.1 ±0.1 ±0.2 mV/V
Voltage Swing, ±15 V Supplies 0 to +11 +12.5 0 to +11 +12.5 0 to +11 +12.5 V
± 5 V Supply 0 to +2 0 to +2 0 to +2 V
dB OUTPUT, 0 dB = 1 V rms
(See Figure 7)
Error, 7 mV < VIN < 7 V rms ±0.4 ±0.6 ±0.2 ±0.3 ±0.5 ±0.6 dB
Scale Factor −3 −3 −3 mV/dB
Scale Factor Temperature
Coefficient
−0.033 −0.033 −0.033 dB/°C
Uncompensated +0.33 +0.33 +0.33 % of rdg/°C
IREF for 0 dB = 1 V rms 5 20 80 5 20 80 5 20 80 µA
IREF Range 1 100 1 100 1 100 µA
AD536A Data Sheet
Rev. G | Page 4 of 15
AD536AJ AD536AK AD536AS
Parameter Min Typ Max Min Typ Max Min Typ Max Unit
IOUT TERMINAL
IOUT Scale Factor 40 40 40 µA/V rms
IOUT Scale Factor Tolerance ±10 ±20 ±10 ±20 ±10 ±20 %
Output Resistance 20 25 30 20 25 30 20 25 30 kΩ
Voltage Compliance −VS to
(+VS − 2.5 V)
−VS to
(+VS − 2.5 V)
−VS to
(+VS − 2.5 V)
V
BUFFER AMPLIFIER
Input and Output Voltage
Range
−VS to
(+VS − 2.5V)
−VS to
(+VS − 2.5V)
−VS to
(+VS − 2.5V)
V
Input Offset Voltage, RS = 25 kΩ ±0.5 ±4 ±0.5 ±4 ±0.5 ±4 mV
Input Bias Current 20 60 20 60 20 60 nA
Input Resistance 108 108 108 Ω
Output Current (+5 mA, (+5 mA, (+5 mA,
−130 µA) −130 µA) −130 µA)
Short-Circuit Current 20 20 20 mA
Output Resistance 0.5 0.5 0.5 Ω
Small-Signal Bandwidth 1 1 1 MHz
Slew Rate4 5 5 5 V/µs
POWER SUPPLY
Voltage Rated Performance ±15 ±15 ±15 V
Dual Supply ±3.0 ±18 ±3.0 ±18 ±3.0 ±18 V
Single Supply +5 +36 +5 +36 +5 +36 V
Quiescent Current
Total VS, 5 V to 36 V, TMIN to TMAX 1.2 2 1.2 2 1.2 2 mA
TEMPERATURE RANGE
Rated Performance 0 +70 0 +70 −55 +125 °C
Storage −55 +150 −55 +150 −55 +150 °C
NUMBER OF TRANSISTORS 65 65 65
1 Accuracy is specified for 0 V to 7 V rms, dc or 1 kHz sine wave input with the AD536A connected as in the figure referenced.
2 Error vs. crest factor is specified as an additional error for 1 V rms rectangular pulse input, pulse width = 200 s.
3 Input voltages are expressed in volts rms, and error is expressed as a percentage of the reading.
4 With 2 kΩ external pull-down resistor.
Data Sheet AD536A
Rev. G | Page 5 of 15
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage
Dual Supply ±18 V
Single Supply +36 V
Internal Power Dissipation 500 mW
Maximum Input Voltage ±25 V peak
Buffer Maximum Input Voltage ±VS
Maximum Input Voltage ±25 V peak
Storage Temperature Range −55°C to +150°C
Operating Temperature Range
AD536AJ/AD536AK 0°C to +70°C
AD536AS −55°C to +125°C
Lead Temperature (Soldering, 60 sec) 300°C
ESD Rating 1000 V
Thermal Resistance θJA1
10-Pin Header (H-10 Package) 150°C/W
20-Terminal LCC (E-20 Package) 95°C/W
14-Lead SBDIP (D-14 Package) 95°C/W
14-Lead CERDIP (Q-14 Package) 95°C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
1 θJA is specified for the worst-case conditions, that is, a device soldered in a
circuit board for surface-mount packages.
PAD NUMBERS CORRESPOND TO PIN NUMBERS FOR THE
TO-100 14-LEAD CERAMIC DIP PACKAGE.
1
BOTH PADS SHOWN MUST BE CONNECTED TO V
IN
.
THE AD536A IS AVAILABLE IN LASER-TRIMMED CHIP FORM.
SUBSTRATE CONNECTED TO –V
S
.
+V
S
14
V
IN
1A
1
V
IN
1B
1
COM
10
I
OUT
8
BUF IN
7
BUF OUT
6
dB
5
C
AV
4
–V
S
3
R
L
9
0.1315 (3.340)
0.0807
(2.050)
00504-002
Figure 2. Die Dimensions and Pad Layout
Dimensions shown in inches and (millimeters)
AD536A Data Sheet
Rev. G | Page 6 of 15
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VIN 1
NC 2
–VS3
CAV 4
+VS
14
NC13
NC12
NC11
dB 5COM10
BUF OUT 6RL
9
BUF IN 7IOUT
8
NC = NO CONNECT
AD536A
TOP VIEW
(Not to Scale)
00504-003
Figure 3. D-14 and Q-14 Packages Pin Configuration
Table 3. D-14 and Q-14 Packages Pin Function Descriptions
Pin No. Mnemonic Description
1 VIN Input Voltage
2 NC No Connection
3 −VS Negative Supply Voltage
4 CAV Averaging Capacitor
5 dB Log (dB) Value of the RMS Output Voltage
6 BUF OUT Buffer Output
7 BUF IN Buffer Input
8 IOUT RMS Output Current
9 RL Load Resistor
10 COM Common
11 NC No Connection
12 NC No Connection
13 NC No Connection
14 +VS Positive Supply Voltage
10
5
91
82
64
73
I
OUT
–V
S
V
IN
C
AV
+V
S
dB
COM BUF OUT
R
L
BUF IN
AD536A
TOP VIEW
(Not to Scale)
00504-004
Figure 4. H-10 Package Pin Configuration
Table 4. H-10 Package Pin Function Descriptions
Pin No. Mnemonic Description
1 RL Load Resistor
2 COM Common
3 +VS Positive Supply Voltage
4 VIN Input Voltage
5 −VS Negative Supply Voltage
6 CAV Averaging Capacitor
7 dB Log (dB) Value of the RMS Output Voltage
8 BUF OUT Buffer Output
9 BUF IN Buffer Input
10 IOUT RMS Output Current
Data Sheet AD536A
Rev. G | Page 7 of 15
V
IN
NC
–V
S
C
AV
+V
S
NC
NC
NC
dB COM
BUF OUT
R
L
BUF IN
I
OUT
NC = NO CONNECT
AD536A
TOP VIEW
(Not to Scale)
20 19123
4
5
6
7
8
131211109
14
15
16
17
18
NC
NC
NC
NC
NC
NC
00504-005
Figure 5. E-20-1 Package Pin Configuration
Table 5. E-20-1 Package Pin Function Descriptions
Pin No. Mnemonic Description
1 NC No Connection
2 VIN Input Voltage
3 NC No Connection
4 −VS Negative Supply Voltage
5 NC No Connection
6 CAV Averaging Capacitor
7 NC No Connection
8 dB Log (dB) Value of the RMS Output Voltage
9 BUF OUT Buffer Output
10 BUF IN Buffer Input
11 NC No Connection
12 IOUT RMS Output Current
13 RL Load Resistor
14 COM Common
15 NC No Connection
16 NC No Connection
17 NC No Connection
18 NC No Connection
19 NC No Connection
20 +VS Positive Supply Voltage
AD536A Data Sheet
Rev. G | Page 8 of 15
THEORY OF OPERATION
The AD536A embodies an implicit solution of the rms equation
that overcomes the dynamic range as well as other limitations
inherent in a straightforward computation of rms. The actual
computation performed by the AD536A follows the equation
rmsV
V
AvgrmsV IN
2
Figure 6 is a simplified schematic of the AD536A. Note that it is
subdivided into four major sections: absolute value circuit
(active rectifier), squarer/divider, current mirror, and buffer
amplifier. The input voltage (VIN), which can be ac or dc, is
converted to a unipolar current (I1) by the active rectifiers
(A1, A2). I1 drives one input of the squarer/divider, which has
the transfer function
I4 = II2/I3
The output current, I4, of the squarer/divider drives the current
mirror through a low-pass filter formed by R1 and the exter-
nally connected capacitor, CAV. If the R1 CAV time constant is
much greater than the longest period of the input signal, then
I4 is effectively averaged. The current mirror returns a current
I3, which equals Avg[I4], back to the squarer/divider to complete
the implicit rms computation. Thus,
I4 = Avg[II2/I4] = II rms
14
+V
S
–V
S
I
3
I
2
I
1
I
OUT
R
L
V
IN
|V
IN
|R
–1
ABSOLUTE VALUE;
VOLTAGE-CURRENT
CONVERTER
ONE-QUADRANT
SQUARER/DIVIDER
CURRENT MIRRO
R
Q1
Q2
Q3
Q4 Q5
COM
49
dB
OUT
5
BUF
OUT
6
3
8
1
BUF
IN BUFFER
7
10
0.4mA
FS
A3
NOTES
1. PINOUTS ARE FOR 14-LEAD DIP.
0.2mA
FS
R1
25kΩ
R2
25kΩ
12kΩ25kΩ
12kΩ
R4
50kΩ
R3
25kΩ80kΩ
00504-106
A4
A2
A1
Figure 6. Simplified Schematic
The current mirror also produces the output current, IOUT, which
equals 2I4. IOUT can be used directly or can be converted to a
voltage with R2 and buffered by A4 to provide a low impedance
voltage output. The transfer function of the AD536A results in
the following:
VOUT = 2R2 × I rms = VIN rms
The dB output is derived from the emitter of Q3 because the
voltage at this point is proportional to –log VIN. The emitter
follower, Q5, buffers and level shifts this voltage so that the dB
output voltage is zero when the externally supplied emitter
current (IREF) to Q5 approximates I3.
CONNECTIONS FOR dB OPERATION
The logarithmic (or decibel) output of the AD536A is one of
its most powerful features. The internal circuit computing dB
works accurately over a 60 dB range. The connections for dB
measurements are shown in Figure 7.
Select the 0 dB level by adjusting R1 for the proper 0 dB reference
current (which is set to cancel the log output current from the
squarer/divider at the desired 0 dB point). The external op amp
provides a more convenient scale and allows compensation of
the +0.33%/°C scale factor drift of the dB output pin.
The temperature-compensating resistor, R2, is available online
in several styles from Precision Resistor Company, Inc., (Part
Number AT35 and Part Number ST35). The average temperature
coefficients of R2 and R3 result in the +3300 ppm required to
compensate for the dB output. The linear rms output is available
at Pin 8 on the DIP or Pin 10 on the header device with an output
impedance of 25 kΩ. Some applications require an additional
buffer amplifier if this output is desired.
For dB calibration,
1. Set VIN = 1.00 V dc or 1.00 V rms.
2. Adjust R1 for dB output = 0.00 V.
3. Set VIN = +0.1 V dc or 0.10 V rms.
4. Adjust R5 for dB output = −2.00 V.
Any other desired 0 dB reference level can be used by setting
VIN and adjusting R1 accordingly. Note that adjusting R5 for the
proper gain automatically provides the correct temperature
compensation.
Data Sheet AD536A
Rev. G | Page 9 of 15
14
13
12
11
10
9
8
1
2
3
4
5
6
7
AD536A
25kΩ
ABSOLUTE
VALUE
SQUARER/
DIVIDER
CURRENT
MIRROR
00504-107
BUF
V
IN
NC
–V
S
C1, C
AV
C
AV
C2
+V
S
NC
NC
NC
dB COM
R
L
I
OUT
+V
S
4.6V TO 18V
E
OUT
–E
+E
2.5V
OP77
AD580J
R1
500kΩ
0dB
REF
ADJUST
dB SCALE
FACTOR ADJUST
TEMPERATURE
COMPENSATED
dB OUTPUT
+100mV/dB
–V
S
+V
S
–V
S
+V
S
dB OUT
3mV/dB
1
SPECIAL TC COMPENSATION RESISTOR, +3300ppm/°C,
PRECISION RESISTOR COMPANY PART NUMBER AT 35 OR PART NUMBER ST35.
LINEAR
rms
OUTPUT
R6
24.9kΩ
R3
60.4Ω
R2
1
1kΩ
R4
33.2kΩ
R5
5kΩ
BUF OUT
BUF IN
+
0.1µF
7
4
3
6
2
Figure 7. dB Connection
FREQUENCY RESPONSE
The AD536A utilizes a logarithmic circuit in performing the
implicit rms computation. As with any log circuit, bandwidth
is proportional to signal level. The solid lines in the graph of
Figure 8 represent the frequency response of the AD536A at
input levels from 10 mV rms to 7 V rms. The dashed lines indicate
the upper frequency limits for 1%, 10%, and ±3 dB of reading
additional error. For example, note that a 1 V rms signal produces
less than 1% of reading additional error up to 120 kHz. A 10 mV
signal can be measured with 1% of reading additional error
(100 µV) up to only 5 kHz.
100k 1M 10M1k 10k
10
1
0.1
0.01
V
OUT
(V)
1%
10%
±3dB
FREQUENCY (Hz)
7V rms INPUT
1V rms INPUT
100mV rms INPUT
10mV rms INPUT
00504-016
Figure 8. High Frequency Response
AC MEASUREMENT ACCURACY AND CREST
FACTOR
Crest factor is often overlooked when determining the accuracy
of an ac measurement. The definition of crest factor is the ratio
of the peak signal amplitude to the rms value of the signal
(CF = VP/V rms). Most common waveforms, such as sine and
triangle waves, have relatively low crest factors (<2). Waveforms
that resemble low duty cycle pulse trains, such as those occurring
in switching power supplies and SCR circuits, have high crest
factors. For example, a rectangular pulse train with a 1% duty
cycle has a crest factor of 10 (CF = 1√n).
Figure 9 illustrates a curve of reading error for the AD536A for
a 1 V rms input signal with crest factors from 1 to 11. A rectan-
gular pulse train (pulse width = 100 µs) was used for this test
because it is the worst-case waveform for rms measurement (all
of the energy is contained in the peaks). The duty cycle and
peak amplitude were varied to produce crest factors from 1 to
11 while maintaining a constant 1 V rms input amplitude.
η = DUTY CYCLE =
CF = 1/√η
ө
IN
(rms) = 1 V rms
100µs
T
ө
O
V
P
0
100µs
T
1
0
–1
–2
–3
–4
INCREASE IN ERROR
(
% of Reading)
12345 67891011
CREST FACTOR
00504-017
Figure 9. Error vs. Crest Factor
INCREASE IN ERRO
R
(% OF READING)
1µs 10µs 100µs 1000µs
PULSE WIDTH (µs)
10
1
0.1
1V rms CF = 3
1V rms CF = 10
00504-018
Figure 10. Error vs. Pulse Width Rectangular Pulse
AD536A Data Sheet
Rev. G | Page 10 of 15
±6 ±10 ±16 ±18
VOLTS (DUAL SUPPLY)
25
20
15
10
5
0
±PEAK INPUT OR OUTPUT (V)
V
OUT
V
IN
00504-019
Figure 11. Input and Output Voltage Ranges vs.
Dual Supply
10 20 30
VOLTS (SINGLE SUPPLY)
25
20
15
10
5
0
±PEAK INPUT OR OUTPUT (V)
2.5
5
V
OUT
V
IN
00504-022
Figure 12. Input and Output Voltage Ranges vs.
Single Supply
Data Sheet AD536A
Rev. G | Page 11 of 15
APPLICATIONS INFORMATION
TYPICAL CONNECTIONS
The AD536A is simple to connect to for the majority of high
accuracy rms measurements, requiring only an external capaci-
tor to set the averaging time constant. The standard connection
is shown in Figure 13 through Figure 15. In this configuration,
the AD536A measures the rms of the ac and dc levels present at
the input, but shows an error for low frequency input as a function
of the filter capacitor, CAV, as shown in Figure 19. Thus, if a 4 µF
capacitor is used, the additional average error at 10 Hz is 0.1%;
at 3 Hz, the additional average error is 1%.
The accuracy at higher frequencies is according to specification.
To reject the dc input, add a capacitor in series with the input,
as shown in Figure 17. Note that the capacitor must be nonpolar.
If the AD536A supply rails contain a considerable amount of
high frequency ripple, it is advisable to bypass both supply pins
to ground with 0.1 µF ceramic capacitors, located as close to the
device as possible.
00504-006
14
13
12
11
10
9
8
1
2
3
4
5
6
7
25kΩ
AD536A
C
AV
V
IN
–V
S
V
OUT
+V
S
ABSOLUTE
VALUE
SQUARER/
DIVIDER
CURRENT
MIRROR
V
IN
NC
–V
S
C
AV
+V
S
NC
NC
NC
dB
COM
BUF OUT
R
L
BUF IN I
OUT
BUF
Figure 13. 14-Lead Standard RMS Connection
AD536A
25kΩ
V
OU
T
I
OUT
+V
S
C
AV
V
IN
–V
S
ABSOLUTE
VALUE
SQUARER/
DIVIDER
CURRENT
MIRROR
00504-020
C
AV
+V
S
dB
COM
BUF IN
BUF OUT
R
L
BUF
Figure 14. 10-Pin Standard RMS Connection
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
AD536A
dB
+V
S
CAV
V
IN
–VS
VOUT
25kΩ
ABSOLUTE
VALUE
SQUARER/
DIVIDER
CURRENT
MIRROR
00504-021
NC
–VS
CAV
NC
NC
NC
COM
BUF OUT
RL
BUF IN
IOUT
NC
NC
NC NC NC
NC
BUF
Figure 15. 20-Terminal Standard RMS Connection
The input and output signal ranges are a function of the supply
voltages; these ranges are shown in Figure 11 and Figure 12.
The AD536A can also be used in an unbuffered voltage output
mode by disconnecting the input to the buffer. The output then
appears unbuffered across the 25 k resistor. The buffer ampli-
fier can then be used for other purposes. Further, the AD536A
can be used in a current output mode by disconnecting the
25 k resistor from ground. The output current is available at
Pin 8 (IOUT, Pin 10 on the H-10 package) with a nominal scale of
40 A per V rms input positive output.
OPTIONAL EXTERNAL TRIMS FOR HIGH
ACCURACY
The accuracy and offset voltage of the AD536A is adjustable
with external trims, as shown in Figure 16. R4 trims the offset.
Note that the offset trim circuit adds 365  in series with the
internal 25 k resistor. This causes a 1.5% increase in scale factor,
which is compensated for by R1. The scale factor adjustment
range is ±1.5%.
The trimming procedure is as follows:
1. Ground the input signal, VIN, and adjust R4 to provide 0 V
output from Pin 6. Alternatively, adjust R4 to provide the
correct output with the lowest expected value of VIN.
2. Connect the desired full-scale input level to VIN, either dc
or a calibrated ac signal (1 kHz is the optimum frequency).
3. Trim R1 to provide the correct output at Pin 6. For example,
1.000 V dc input provides 1.000 V dc output. A ±1.000 V
peak-to-peak sine wave should provide a 0.707 V dc output.
Any residual errors are caused by device nonlinearity.
The major advantage of external trimming is to optimize device
performance for a reduced signal range; the AD536A is
internally trimmed for a 7 V rms full-scale range.
AD536A Data Sheet
Rev. G | Page 12 of 15
CAV
–VS
VIN
VOUT
+VS
14
13
12
11
10
9
8
1
2
3
4
5
6
7
–VS
+VS
AD536A
25kΩ
25kΩ
ABSOLUTE
VALUE
SQUARER/
DIVIDER
CURRENT
MIRROR
R4
50kΩ
OFFSET
ADJUST
R3
750kΩ
R2
365Ω
0
0504-007
BUF
NC
–VS
CAV
+VS
NC
NC
NC
dB COM
BUF OUT
RL
BUF IN
IOUT
SCALE
FACTOR
ADJUST
R1
500Ω
Figure 16. Optional External Gain and Output Offset Trims
SINGLE-SUPPLY OPERATION
Refer to Figure 17 for single supply-rail configurations between
5 V and 36 V. When powered from a single supply, the input
stage (VIN pin) is internally biased at a voltage between ground
and the supply, and the input signal ac coupled. Biasing the
device between the supply and ground is simply a matter of
connecting the COM pin to an external resistor divider and
bypassing to ground. The resistor values are large, minimizing
power consumption, as the COM pin current is only 5 A.
Note that the 10 k and 20 k resistors connected to the COM pin
(Figure 17) are asymmetrical, that is, the voltage at the COM pin is
1/3 of the supply. This ratio of input bias to supply is optimum
for the precision rectifier (aka absolute value circuit) input
circuit employed for rectifying ac input waveforms and ensures
full input symmetry for low signal voltages.
Capacitor C2 is required for AC input coupling, however an
external dc return is unnecessary because biasing occurs
internally. SelectC2 for the desired low frequency breakpoint
using an input resistance of 16.7 k for the 1/ωRC calculation;
C2 = 1 F for a cutoff at 10 Hz. Figure 11 and Figure 12 show
the input and output signal ranges for dual and single supply
configurations, respectively. The load resistor, RL, provides a
path to sink output sink current when an input signal is
disconnected.
C
AV
V
IN
V
OUT
+V
S
14
13
12
11
10
9
8
1
2
3
4
5
6
7
AD536A
25kΩ
ABSOLUTE
VALUE
SQUARER/
DIVIDER
CURRENT
MIRROR
C2
1µF
NONPOLARIZED
R
L
0.1µF
20kΩ
10kΩ
0.1µF
10kΩ
TO
1kΩ
00504-008
V
IN
NC
–V
S
C
AV
+V
S
NC
NC
NC
dB COM
BUF OUT R
L
BUF IN
I
OUT
BUF
Figure 17. Single-Supply Connection
CHOOSING THE AVERAGING TIME CONSTANT
The AD536A computes the rms of both ac and dc signals. If the
input is a slowly varying dc signal, the output of the AD536A
tracks the input exactly.
At higher frequencies, the average output of the AD536A
approaches the rms value of the input signal. The actual output
of the AD536A differs from the ideal output by a dc (or average)
error and some amount of ripple, as shown in Figure 18.
DC ERROR = E
O
– E
O
(IDEAL)
IDEAL E
O
DOUBLE FREQUENCY
RIPPLE
AVERAGE E
O
– E
O
E
O
TIME
00504-009
Figure 18. Typical Output Waveform for Sinusoidal Input
The dc error is dependent on the input signal frequency and
the value of CAV. Use Figure 19 to determine the minimum value
of CAV, which yields a given percentage of dc error above a given
frequency using the standard rms connection.
The ac component of the output signal is the ripple. There are
two ways to reduce the ripple. The first method involves using a
large value of CAV. Because the ripple is inversely proportional
to CAV, a tenfold increase in this capacitance affects a tenfold
reduction in ripple.
When measuring waveforms with high crest factors, such as low
duty cycle pulse trains, the averaging time constant should be at
least 10 times the signal period. For example, a 100 Hz pulse
rate requires a 100 ms time constant, which corresponds to a
4 F capacitor (time constant = 25 ms per F).
Data Sheet AD536A
Rev. G | Page 13 of 15
The primary disadvantage in using a large CAV to remove ripple
is that the settling time for a step change in input level is
increased proportionately. Figure 19 illustrates that the
relationship between CAV and 1% settling time is 115 ms for
each microfarad of CAV. The settling time is twice as great for
decreasing signals as it is for increasing signals. The values in
Figure 19 are for decreasing signals. Settling time also increases
for low signal levels, as shown in Figure 20.
10 100 1k 10k
0.1
1
10
100
0.01
1 100k
INPUT FREQUENCY (Hz)
REQUIRED C
AV
(µF)
0.1
1
10
100
0.01
FOR 1% SETTLING TIME IN SECONDS
MULTIPLY READING BY 0.115
0.01% ERROR
0.1% ERROR
10% ERROR
1% ERROR
1
PERCENT DC ERROR AND PERCENT RIPPLE (PEAK)
VALUES FOR C
AV
AND
1% SETTLING TIME
FOR STATED % OF READING
AVERAGING ERROR
1
ACCURACY ± 20% DUE TO
COMPONENT TOLERANCE
00504-010
Figure 19. Error/Settling Time Graph for Use with the Standard RMS
Connection (See Figure 13 Through Figure 15)
10m 100m 1
7.5
10.0
5.0
1m 10
rms INPUT LEVEL (V)
SETTLING TIME REL
A
TIVE TO 1V rms
INPUT SETTLING TIME
1.0
2.5
00504-011
Figure 20. Settling Time vs. Input Level
A better method to reduce output ripple is the use of a postfilter.
Figure 21 shows a suggested circuit. If a single-pole filter is used
(C3 removed, RX shorted) and C2 is approximately twice the value
of CAV, the ripple is reduced, as shown in Figure 22, and settling
time is increased. For example, with CAV = 1 µF and C2 = 2.2 F,
the ripple for a 60 Hz input is reduced from 10% of reading to
approximately 0.3% of reading.
The settling time, however, is increased by approximately a
factor of 3. Therefore, the values of CAV and C2 can be reduced
to permit faster settling times while still providing substantial
ripple reduction.
The two-pole postfilter uses an active filter stage to provide
even greater ripple reduction without substantially increasing
the settling times over a circuit with a one-pole filter. The values
of CAV, C2, and C3 can then be reduced to allow extremely fast
settling times for a constant amount of ripple. Caution should
be exercised in choosing the value of CAV, because the dc error
is dependent on this value and is independent of the postfilter.
For a more detailed explanation of these topics, refer to the RMS to
DC Conversion Application Guide, 2nd Edition.
C2
VIN
CAV
+VS
14
13
12
11
10
9
8
1
2
3
4
5
6
7
AD536A
25kΩ
ABSOLUTE
VALUE
SQUARER/
DIVIDER
CURRENT
MIRROR
–VS
Rx
24kΩ
+
–
+
–
C31
Vrms OUT
1FOR SINGLE POLE, SHORT Rx, REMOVE C3.
00504-012
VIN
NC
–VS
CAV
+VS
NC
NC
NC
dB COM
BUF OUT RL
BUF IN IOUT
BUF
Figure 21. Two-Pole Postfilter
1
1k100 10k
0.1
10
10
DC ERROR OR RIPPLE (% of Reading)
PEAK-TO-PEAK RIPPLE
C
AV
= 1µF
DC ERROR
C
AV
= 1µF
(ALL FILTERS)
PEAK-TO-PEAK RIPPLE
C
AV
= 1µF
C2 = C3 = 2.2µF (TWO-POLE)
00504-013
Rx = 0Ω
PEAK-TO-PEAK
RIPPLE (ONE POLE)
C
AV
= 1µF, C2 = 2.2µF
FREQUENCY (Hz)
Figure 22. Performance Features of Various Filter Types
(See Figure 13 to Figure 15 for Standard RMS Connection)
AD536A Data Sheet
Rev. G | Page 14 of 15
OUTLINE DIMENSIONS
C
ONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSION
S
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FO
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
.
14
17
8
0.310 (7.87)
0.220 (5.59)
PIN 1
0.080 (2.03) MAX
0.005 (0.13) MIN
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18) 0.070 (1.78)
0.030 (0.76)
0.100 (2.54)
BSC
0.150
(3.81)
MIN
0.765 (19.43) MAX
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
Figure 23. 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]
(D-14)
Dimensions shown in inches and (millimeters)
CONTRO LLING DIM ENSI ONS ARE IN I NCHES; MILLIM ETER DI M E NSI ONS
(IN PAREN T HE SE S) ARE ROUN DED-OF F INCH E QUI VALENTS FOR
REFE RE NCE ONLY AN D ARE N OT APPR OPRIATE F OR US E IN DES IGN.
1
20 4
9
8
13
19
14
3
18
0.02 8 ( 0. 71 )
0.02 2 ( 0. 56 )
45° T YP
0.01 5 (0.38)
MIN
0.055 ( 1 . 40)
0.045 ( 1 . 14)
0.050 (1.27)
BSC
0.075 (1.91)
REF
0.011 (0.28)
0.007 (0. 1 8)
R TYP
0.09 5 (2. 4 1)
0.07 5 (1. 9 0)
0.10 0 (2.5 4) REF
0.20 0 (5. 0 8)
REF
0.15 0 (3.81)
BSC
0.075 (1.91)
REF
0.358 (9. 0 9)
0.342 (8. 6 9)
SQ
0.358
(9.09)
MAX
SQ
0.100 (2. 5 4)
0.064 (1. 6 3)
0.08 8 (2. 2 4)
0.05 4 (1. 3 7)
12-05-2017-B
PKG-000045
BOTTO M VIEW
SIDE VIEW
0.049 (1. 2 4)
0.041 (1. 0 4)
Figure 24. 20-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-20-1)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.310 (7.87)
0.220 (5.59)
0.005 (0.13) MIN 0.098 (2.49) MAX
0.100 (2.54) BSC
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX
0.785 (19.94) MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36) 0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
PIN 1
17
814
Figure 25. 14-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-14)
Dimensions shown in inches and (millimeters)
Data Sheet AD536A
Rev. G | Page 15 of 15
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
DIMENSIONS PER JEDEC STANDARDS MO-006-AF
0.500 (12.70)
MIN
0.185 (4.70)
0.165 (4.19)
REFERENCE PLANE
0.050 (1.27) MAX
0.040 (1.02) MAX
0.021 (0.53)
0.016 (0.40)
1
0.034 (0.86)
0.025 (0.64)
0.045 (1.14)
0.025 (0.65)
0.160 (4.06)
0.110 (2.79)
6
2
8
7
5
4
3
0.115
(2.92)
BSC 9
10
0.230 (5.84)
BSC
BASE & SEATING PLANE
36° BSC
01-19-2015-A
0.370 (9.40)
0.335 (8.51)
0.335 (8.51)
0.305 (7.75)
BOTTOM VIEWSIDE VIEW
PIN 5 IS INTEGRAL
CONNECTION TO
HEADER
Figure 26. 10-Pin Metal Header Package [TO-100]
(H-10)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD536AJD 0°C to +70°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD536AJDZ 0°C to +70°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD536AKDZ 0°C to +70°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD536AJH 0°C to +70°C 10-Pin Metal Header Package [TO-100] H-10
AD536AJHZ 0°C to +70°C 10-Pin Metal Header Package [TO-100] H-10
AD536AKHZ 0°C to +70°C 10-Pin Metal Header Package [TO-100] H-10
AD536AJQ 0°C to +70°C 14-Lead Ceramic Dual In Line Package [CERDIP] Q-14
AD536ASD −55°C to +125°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD536ASD/883B −55°C to +125°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
AD536ASE/883B −55°C to +125°C 20-Terminal Ceramic Leadless Chip Carrier [LCC] E-20-1
AD536ASH −55°C to +125°C 10-Pin Metal Header Package [TO-100] H-10
AD536ASH/883B −55°C to +125°C 10-Pin Metal Header Package [TO-100] H-10
AD536ASCHIPS −55°C to +125°C Die
5962-89805012A −55°C to +125°C 20-Terminal Ceramic Leadless Chip Carrier [LCC] E-20-1
5962-8980501CA −55°C to +125°C 14-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-14
5962-8980501IA −55°C to +125°C 10-Pin Metal Header Package [TO-100] H-10
1 Z = RoHS Compliant Part.
©1976–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00504-0-3/19(G)