24 GHz to 44 GHz, Wideband, Microwave Upconverter ADMV1013 Data Sheet DNC VCC_MIXER VCC_BG BG_RBIAS1 VCC_QUAD LON GND IF_I DVDD I_N SCLK I_P x4 SDI 90 0 GND SDO Q_P BG_RBIAS2 Q_N ADMV1013 VCC_DRV IF_Q GND VCC_BG2 VVA2 VVA1 VENV_P GND VENV_N VCC_AMP1 VCC_ENV SEN2 VCC_AMP2 VCTRL2 VCTRL1 VCC_VVA DNC VCC2_DRV DET 17267-001 RF Point to point microwave radios Radar, electronic warfare systems Instrumentation, automatic test equipment (ATE) LOP RST DNC APPLICATIONS GND FUNCTIONAL BLOCK DIAGRAM Wideband RF input frequency range: 24 GHz to 44 GHz 2 upconversion modes Direct conversion from baseband I/Q to RF Single-sideband upconversion from real IF LO input frequency range: 5.4 GHz to 10.25 GHz LO quadrupler for up to 41 GHz Matched 50 single-ended RF output and IF inputs Option between matched 100 balanced or 50 singleended LO inputs 100 balanced baseband inputs Sideband suppression and carrier feedthrough optimization Variable attenuator for transceiver power control Programmable via 4-wire SPI interface 40-terminal land grid array package (LGA) SEN FEATURES Figure 1. GENERAL DESCRIPTION The ADMV1013 is a wideband, microwave upconverter optimized for point to point microwave radio designs operating in the 24 GHz to 44 GHz radio frequency (RF) range. The upconverter offers two modes of frequency translation. The device is capable of direct conversion to RF from baseband in-phase quadrature (I/Q) input signals, as well as single-sideband (SSB) upconversion from complex intermediate frequency (IF) inputs. The baseband I/Q input path can be disabled and modulated complex IF signals, anywhere from 0.8 GHz to 6.0 GHz, can be inserted in the IF path and upconverted to 24 GHz to 44 GHz Rev. B while suppressing the unwanted sideband by typically better than 26 dBc. The serial port interface (SPI) allows adjustment of the quadrature phase and mixer gate voltage to allow optimum sideband suppression and local oscillator (LO) nulling. In addition, the SPI interface allows powering down the output envelope detector to reduce power consumption. The ADMV1013 upconverter comes in a 40-terminal land grid array package (LGA) package. The ADMV1013 operates over the -40C to +85C case temperature range. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2018-2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADMV1013 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Sideband Suppression Optimization ....................................... 25 Applications ....................................................................................... 1 Carrier Feedthrough Nulling .................................................... 26 Functional Block Diagram .............................................................. 1 Envelope Detector ...................................................................... 26 General Description ......................................................................... 1 Power Down and Reset .............................................................. 26 Revision History ............................................................................... 2 Serial Port Interface (SPI) ......................................................... 26 Specifications..................................................................................... 3 Applications Information .............................................................. 28 Serial Port Register Timing ......................................................... 5 Baseband Quadrature Modulation from Low Frequencies .. 28 Absolute Maximum Ratings............................................................ 6 Performance at Different Quad Filter Settings ....................... 28 Thermal Resistance ...................................................................... 6 VVA Temperature Compensation............................................ 28 ESD Caution .................................................................................. 6 Performance Between Differential vs. Single-Ended LO Input ....................................................................................................... 29 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 9 I/Q Mode ....................................................................................... 9 IF Mode........................................................................................ 14 Envelope Detector Performance............................................... 19 Return Loss and Isolation.......................................................... 21 M x N Spurious Performance ................................................... 24 Theory of Operation ...................................................................... 25 Start-Up Sequence ...................................................................... 25 Baseband Quadrature Modulation (I/Q Mode) ..................... 25 Single-Sideband Upconversion (IF Mode) ............................. 25 Performance Across RF Frequency at Fixed Input Frequencies ................................................................................. 30 Performance Across Common-Mode Voltage in I/Q Mode 31 Operating VCTRL1 and VCTRL2 Independently..................... 31 Recommended Land Pattern .................................................... 33 Evaluation Board Information ................................................. 33 Register Summary .......................................................................... 34 Register Details ............................................................................... 35 Outline Dimensions ....................................................................... 39 Ordering Guide .......................................................................... 39 LO Input Path ............................................................................. 25 REVISION HISTORY 9/2019--Rev. A to Rev. B Changes to Figure 1 .......................................................................... 1 Changes to Figure 3 and Table 5 ..................................................... 7 4/2019--Rev. 0 to Rev. A Changes to Figure 1 .......................................................................... 1 Changes to Frequency Ranges Parameter, Table 1 ....................... 3 Changes to Thermal Resistance Section........................................ 6 Changes to Figure 3 .......................................................................... 7 Changes to Table 5 ............................................................................ 8 Changes to Figure 50 Caption....................................................... 16 Changes to Figure 58 Caption ...................................................... 18 Change to Return Loss and Isolation Section............................. 21 Moved Figure 70; Renumbered Sequentially .............................. 21 Moved Figure 72 ............................................................................. 22 Moved Figure 77 ............................................................................. 22 Moved Figure 80 ............................................................................. 23 Changes to M x N Spurious Performance Section, I/Q Mode Section, and IF Mode Section ....................................................... 24 Changes to Start-Up Sequence Section ....................................... 25 12/2018--Revision 0: Initial Version Rev. B | Page 2 of 39 Data Sheet ADMV1013 SPECIFICATIONS IF and I/Q amplitude = -20 dBm, VCC_DRV = VCC2_DRV = VCC_AMP2 = VCC_ENV = VCC_AMP1 = VCC_BG2 = VCC_MIXER = VCC_BG = VCC_QUAD = 3.3 V, DVDD = VCC_VVA = 1.8 V, TA = 25C, and set Register 0x0A to 0xE700, unless otherwise noted. Measurements in IF mode performed with a 90 hybrid, Register 0x03, Bit 7 = 1, IF input frequency (fIF) = 3.5 GHz. Measurements in I/Q mode are measured as a composite of the I and Q channel performance, common-mode voltage (VCM) = 0 V, Register 0x03, Bit 7 = 0, and Register 0x05, Bits[6:0] = 0x051, unless otherwise noted. I/Q baseband frequency (fBB) = 100 MHz. VCTRL1 = VCTRL2. VCTRL is the attenuation voltage at the VCTRL1 and VCTRL2 pins. VCTRL =1800 mV, unless otherwise specified. Table 1. Parameter FREQUENCY RANGES RF Output LO Input LO Quadrupler IF Input Baseband (BB) I/Q Input LO AMPLITUDE RANGE I/Q MODULATOR PERFORMANCE Conversion Gain 24 GHz to 40 GHz 40 GHz to 44 GHz Voltage Variable Attenuator (VVA) Control Range Single-Sideband (SSB) Noise Figure 24 GHz to 40 GHz 40 GHz to 44 GHz Output Third-Order Intercept (IP3) 24 GHz to 40 GHz 40 GHz to 44 GHz Output 1 dB Compression Point (P1dB) 24 GHz to 40 GHz 40 GHz to 44 GHz Sideband Rejection (SBR) Uncalibrated IF SINGLE-SIDEBAND UPCONVERSION PERFORMANCE Conversion Gain 24 GHz to 40 GHz 40 GHz to 44 GHz VVA Control Range SSB Noise Figure 24 GHz to 40 GHz 40 GHz to 44 GHz Output IP3 24 GHz to 40 GHz 40 GHz to 44 GHz Output P1dB 24 GHz to 40 GHz 40 GHz to 44 GHz SBR Uncalibrated Calibrated Test Conditions/Comments Min 24 5.4 21.6 0.8 DC -6 At maximum gain fBB 3.5 GHz 6 GHz > fBB > 3.5 GHz 18 Typ Max Unit 0 44 10.25 41 6.0 6.0 +6 GHz GHz GHz GHz GHz dBm 23 21 19 35 dB 18 19 dB dB 20 23 22 dBm dBm 10 13 12 dBm dBm 32 dBc 18 12 14 35 dB 25 28 dB dB 20 23 22 dBm dBm 10 13 12 dBm dBm 26 36 dBc dBc dB dB At maximum gain At maximum gain At maximum gain 24 GHz to 44 GHz, at maximum gain At maximum gain fIF 3.5 GHz 6 GHz > fIF > 3.5 GHz 13 dB dB At maximum gain At maximum gain At maximum gain 24 GHz to 44 GHz, at maximum gain Calibrated using LOAMP_PH_ADJ_ Q_FINE and LOAMP_PH_ADJ_I_FINE bits Rev. B | Page 3 of 39 ADMV1013 Parameter ENVELOPE DETECTOR PERFORMANCE Output Level Minimum Maximum Envelope Bandwidth 3 dB 10 dB RETURN LOSS RF Output LO Input IF Input BB Input BB I/Q Input Impedance LEAKAGE Fundamental LO to RF 4 x LO to RF 5.4 GHz to 6.8 GHz LO 6.8 GHz to 10.25 GHz LO 5.4 GHz to 10.25 GHz LO 5 x LO to RF Fundamental LO to IF Fundamental LO to I/Q LOGIC INPUTS Input Voltage Range High, VINH Low, VINL Input Current, IINH/IINL Input Capacitance, CIN LOGIC OUTPUTS Output Voltage Range High, VOH Low, VOL Output High Current, IOH POWER INTERFACE VCC_DRV, VCC2_DRV, VCC_AMP2, VCC_ENV, VCC_AMP1, VCC_BG2, VCC_MIXER, VCC_BG, VCC_QUAD 3.3 V Supply Current DVDD, VCC_VVA 1.8 V Supply Current Data Sheet Test Conditions/Comments Min Typ Max Unit For optimum performance Measured with two tones with total power output (POUT) at RF = 10 dBm RF frequency (fRF) = 28 GHz fRF = 28 GHz 50 single-ended 100 differential 50 single-ended 100 differential -45 -20 dBm dBm 350 1 MHz GHz -8 -12 -12 -10 100 dB dB dB dB -80 dBm -12 -20 -45 dBm dBm dBm -55 -70 -75 dBm dBm dBm At maximum gain Uncalibrated Uncalibrated Calibrated using MXER_OFF_ADJ_I_N, MXER_OFF_ADJ_I_P, MXER_OFF_ ADJ_Q_N, MXER_OFF_ADJ_Q_P bits at VCTRL = 1800 mV, IF mode DVDD - 0.4 0 1.8 0.4 V V A pF 1.8 0.4 500 V V A 3.45 V 100 3 DVDD - 0.4 0 3.15 VCTRL = 1.8 V, no IF and I/Q or LO input signal 550 1.7 VCTRL = 1.8 V, no IF and I/Q or LO input signal Total Power Consumption Power-Down 3.3 1.8 3 1.9 77 Rev. B | Page 4 of 39 mA 1.9 136 V mA W mW Data Sheet ADMV1013 SERIAL PORT REGISTER TIMING Table 2. Parameter tSDI, SETUP tSDI, HOLD tSCLK, HIGH tSCLK, LOW tSCLK, SEN/SEN2_SETUP Description Data to clock setup time Data to clock hold time Clock high duration Clock low duration Clock to SEN/SEN2 setup time Min 10 10 40 to 60 40 to 60 30 tSCLK, DOT tSCLK, DOV tSCLK, SEN/SEN2_INACTIVE Clock to data out transition time Clock to data out valid time Clock to SEN/SEN2 inactive tSEN/SEN2_INACTIVE Inactive SEN/SEN2 (between two operations) Typ Max Unit ns ns % % ns 10 10 20 ns ns ns 80 ns Timing Diagram tSCLK, HIGH tSCLK, LOW SCLK tSCLK, SEN/SEN2_SETU P tSEN/SEN2_INACTIVE SEN/SEN2 tSCLK, DOT tSCLK, SEN/SEN2_INACTIVE tSCLK, DOV tSDI, SETUP SDI Figure 2. Serial Port Register Timing Diagram Rev. B | Page 5 of 39 tSDI, HOLD 17267-106 SDO ADMV1013 Data Sheet ABSOLUTE MAXIMUM RATINGS JA and JC must only be used to compare the thermal performance of the different packages if all test conditions listed are similar to JEDEC specifications. Instead, JT and JB can be used to calculate the junction temperature of the device by using the following equations: Table 3. Parameter Supply Voltage VCC_DRV, VCC2_DRV, VCC_AMP2, VCC_ENV, VCC_AMP1, VCC_BG2, VCC_BG, VCC_MIXER DVDD, VCC_VVA IF Input Power I/Q Input Power LO Input Power Maximum Junction Temperature Maximum Power Dissipation1 Lifetime at Maximum Junction Temperature (TJ) Operating Case Temperature Range Storage Temperature Range Lead Temperature (Soldering 60 sec) Moisture Sensitivity Level (MSL) Rating2 Electrostatic Discharge (ESD) Sensitivity Human Body Model (HBM) Field Induced Charged Device Model (FICDM) Rating 4.3 V TJ = (P x JT) + TTOP 2.3 V 5 dBm 5 dBm 9 dBm 125C 2.9 W 1 x106 hours -40C to +85C -55C to +125C 260C MSL3 1250 V 750 V 1 The maximum power dissipation is a theoretical number calculated by (TJ - 85C)/JC_TOP. 2 Based on IPC/JEDEC J-STD-20 MSL classifications. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. JA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. JC is the junction to case thermal resistance. (1) where: P refers to the total power dissipation in the chip (W). JT refers to the junction to top thermal characterization number. TTOP refers to the package top temperature (C) and is measured at the top center of the package. TJ = (P x JB) + TBOARD (2) where: P refers to the total power dissipation in the chip (W). JB refers to the junction to board thermal characterization number. TBOARD refers to the board temperature measured on the midpoint of the longest side of the package, no more than 1 mm from the edge of the package body (C). As stated in JEDEC51-12, Equation 1 and Equation 2 must be used when no heat sink/heat spreader is present. When a heat sink/heat spreader is added, estimating and calculating junction temperature can be achieved using JC_TOP. Table 4. Thermal Resistance Package Type1 CC-40-5 1 JA2 28 JC_TOP3 13.8 JB4 11.1 JT5 6.4 JB6 13.8 Unit C/W The thermal resistance values specified in Table 4 are simulated based on JEDEC specifications, unless specified otherwise, and must be used in compliance with JESD51-12. 2 JA is the junction to ambient thermal resistance in a natural convection, JEDEC environment. 3 JC_TOP is the junction to case (top) JEDEC thermal resistance. 4 JB is the junction to board JEDEC thermal resistance. 5 JT is the junction to top JEDEC thermal characterization parameter. 6 JB is the junction to board JEDEC thermal characterization parameter. ESD CAUTION Rev. B | Page 6 of 39 Data Sheet ADMV1013 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADMV1013 SEN GND LOP LON GND VCC_QUAD BG_RBIAS1 VCC_BG VCC_MIXER DNC TOP VIEW (Not to Scale) 40 39 38 37 36 35 34 33 32 31 RST DVDD SCLK SDI SDO BG_RBIAS2 VCC_DRV GND RF GND 30 IF_I 29 I_N 1 2 28 I_P 27 GND 3 4 26 Q_P 25 Q_N 5 6 7 8 24 IF_Q 23 VCC_BG2 9 22 VENV_P 10 21 VENV_N NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. EXPOSED PAD. SOLDER THE EXPOSED PAD TO A LOW IMPEDANCE GROUND PLANE. 17267-002 VCC2_DRV DNC DNC VCC_VVA VCTRL1 VCTRL2 VCC_AMP2 SEN2 VCC_ENV VCC_AMP1 11 12 13 14 15 16 17 18 19 20 Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6 Mnemonic RST DVDD SCLK SDI SDO BG_RBIAS2 7 8, 10, 27, 36, 39 9 11 12, 13, 31 14 15 16 17 VCC_DRV GND RF VCC2_DRV DNC VCC_VVA VCTRL1 VCTRL2 VCC_AMP2 18 19 20 SEN2 VCC_ENV VCC_AMP1 21 22 23 VENV_N VENV_P VCC_BG2 24, 30 IF_Q, IF_I 25, 26 28, 29 Q_N, Q_P I_P, I_N Description SPI Reset. Connect this pin to logic high for normal operation. The SPI logic is 1.8 V. 1.8 V SPI Digital Supply. SPI Clock Digital Input. SPI Serial Data Input. SPI Serial Data Output. Voltage Gain Amplifier (VGA) Chip Band Gap Circuit, External High Precision Resistor. Place a 1.1 k, high precision resistor shunt to ground close to this pin. 3.3 V Power Supply for RF Driver. Place a 100 pF, a 0.01 F, and a 10 F capacitor close to this pin. Ground. RF Output. This pin is dc-coupled internally to GND and matched to 50 single ended. 3.3 V Power Supply for RF Predriver. Place a 100 pF, a 0.01 F, and a 10 F capacitor close to this pin. Do Not Connect. Do not connect to this pin. 1.8 V Power Supply for VVA Control Circuit. Place a 100 pF, 0.01 F, and a 10 F capacitor close to this pin. RF Voltage Variable Attenuator 1 (VVA1) Control Voltage. Place a 1 k series resistor with this pin. RF Voltage Variable Attenuator 2 (VVA2) Control Voltage. Place a 1 k series resistor with this pin. 3.3 V Power Supply for RF Amplifier 2 (AMP2). Place a 100 pF, a 0.01 F, and a 10 F capacitor close to this pin. SPI Serial Enable for VGA Chip. Connect this pin with Pin 40 (SEN). 3.3 V Power Supply for Envelope Detector. Place a 100 pF, a 0.01 F, and a 10 F capacitor close to this pin. 3.3 V Power Supply for RF Amplifier 1 (AMP1). Place a 100 pF, a 0.01 F, and a 10 F capacitor close to this pin. Negative Differential Envelope Detector Output. Positive Differential Envelope Detector Output. 3.3 V Power Supply for VGA Chip Band Gap Circuit. Place a 100 pF, a 0.01 F, and a 10 F capacitor close to this pin. IF Single-Ended Complex Inputs. These pins are internally ac-coupled. When in IF mode, Pin 25 (Q_P), Pin 26 (Q_N), Pin 28 (I_P), and Pin 29 (I_N) must be kept floating. Differential Baseband Q Inputs. These pins are dc-coupled. Do not connect these pins in IF mode. Differential Baseband I Inputs. These pins are dc-coupled. Do not connect these pins in IF mode. Rev. B | Page 7 of 39 ADMV1013 Data Sheet Pin No. 32 33 Mnemonic VCC_MIXER VCC_BG 34 BG_RBIAS1 35 37, 38 VCC_QUAD LON, LOP 40 SEN EPAD Description 3.3 V Power Supply for Mixer. Place a 100 pF, a 0.01 F, and a 10 F capacitor close to this pin. 3.3 V Power Supply for Mixer Chip Band Gap Circuit. Place a 100 pF, a 0.01 F, and a 10 F capacitor close to this pin. Mixer Chip Band Gap Circuit, External High Precision Resistor. Place a 1.1 k, high precision resistor shunt to ground close to this pin. 3.3 V Power Supply for Quadruppler. Place a 100 pF, a 0.01 F, and a 10 F capacitor close to this pin. Negative and Positive Differential Local Oscillator Input. This pin is dc-coupled internally to ground and matched to 100 differential or 50 single ended. If using the LO as single ended, terminate the unused LO port with 50 impedance to ground. SPI Serial Enable for Mixer Chip. Connect this pin with Pin 18 (SEN2). Exposed Pad. Solder the exposed pad to a low impedance ground plane. Rev. B | Page 8 of 39 Data Sheet ADMV1013 TYPICAL PERFORMANCE CHARACTERISTICS I/Q MODE 30 25 20 +85C AT 1.8V UPPER SIDEBAND +25C AT 1.8V UPPER SIDEBAND -40C AT 1.8V UPPER SIDEBAND CONVERSION GAIN (dB) +85C AT 0.8V UPPER SIDEBAND +25C AT 0.8V UPPER SIDEBAND -40C AT 0.8V UPPER SIDEBAND +85C AT 0V UPPER SIDEBAND +25C AT 0V UPPER SIDEBAND -40C AT 0V UPPER SIDEBAND 15 10 5 0 -5 +85C AT 39GHz +25C AT 39GHz -40C AT 9GHz +85C AT 28GHz +25C AT 28GHz -40C AT 28GHz -10 -15 -20 -25 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) -30 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VCTRL (V) Figure 4. Conversion Gain vs. RF Frequency (fRF) at Three Different Gain Settings for Various Temperatures, fBB = 100 MHz (Upper Sideband) 17267-006 35 30 25 20 15 10 5 -5 0 -10 -15 -20 -25 -30 -35 -40 -45 -50 23 17267-003 CONVERSION GAIN (dB) I/Q amplitude = -20 dBm, VCC_DRV = VCC2_DRV = VCC_AMP2 = VCC_ENV = VCC_AMP1 = VCC_BG2 = VCC_MIXER = VCC_BG = VCC_QUAD = 3.3 V, DVDD = VCC_VVA = 1.8 V, TA = 25C, and set Register 0x0A to 0xE700, unless otherwise noted. VCTRL1 = VCTRL2. VCTRL is the attenuation voltage at the VCTRL1 and VCTRL2 pins. VCTRL = 1800 mV, unless otherwise specified. Measurements in I/Q mode are measured as a composite of the I and Q channel performance, VCM = 0 V, Register 0x03, Bit 7 = 0, and Register 0x05, Bits[6:0] = 0x051, unless otherwise noted. I/Q fBB = 100 MHz. Figure 7. Conversion Gain vs. VCTRL at Various Temperatures and fRF = 28 GHz and 39 GHz, fBB = 100 MHz 30 28 26 25 24 CONVERSION GAIN (dB) CONVERSION GAIN (dB) 22 20 15 10 5 3.5V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.1V UPPER SIDEBAND 0 20 18 16 14 12 10 8 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 6 4 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) 0 17267-004 25 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 BASEBAND FREQUENCY (GHz) Figure 5. Conversion Gain vs. RF Frequency at for Various Supply Voltages, fBB = 100 MHz (Upper Sideband) 17267-007 2 -5 23 Figure 8. Conversion Gain vs. Baseband Frequency at fRF = 28 GHz and 39 GHz (Upper Sideband) 30 28 26 25 24 CONVERSION GAIN (dB) CONVERSION GAIN (dB) 22 20 15 10 5 +6dBm UPPER SIDEBAND 0dBm UPPER SIDEBAND -6dBm UPPER SIDEBAND 0 20 18 16 14 12 10 8 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND 6 4 27 29 31 33 35 37 RF FREQUENCY (GHz) 39 41 43 45 0 17267-005 25 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 BASEBAND FREQUENCY (GHz) Figure 6. Conversion Gain vs. RF Frequency at for Various LO Inputs, fBB = 100 MHz (Upper Sideband) Rev. B | Page 9 of 39 Figure 9. Conversion Gain vs. Baseband Frequency at fRF = 28 GHz and 39 GHz (Lower Sideband) 17267-008 2 -5 23 ADMV1013 Data Sheet 28 30 26 25 22 20 20 15 OUTPUT IP3 (dBm) 18 16 14 12 10 +85C UPPER SIDEBAND +25C UPPER SIDEBAND -40C UPPER SIDEBAND 8 6 10 5 0 -5 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND -10 4 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) -20 17267-009 0 23 0 26 24 24 22 22 20 20 OUTPUT IP3 (dBm) OUTPUT IP3 (dBm) 28 26 18 16 14 12 10 8 0.8 1.0 1.2 1.4 1.6 1.8 18 16 14 12 10 8 3.5V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.1V UPPER SIDEBAND 4 0.6 Figure 13. Output IP3 vs. VCTRL, RF Amplitude = -20 dBm per Tone at 20 MHz Spacing, fBB = 100 MHz at fRF = 28 GHz and 39 GHz (Upper Sideband) 28 6 0.4 VCTRL (V) Figure 10. Output IP3 vs. RF Frequency at Maximum Gain for Various Temperatures, RF Amplitude = -20 dBm per Tone at 20 MHz Spacing, fBB = 100 MHz (Upper Sideband) 39GHz UPPER BASEBAND 28GHz UPPER BASEBAND 39GHz LOWER BASEBAND 28GHz LOWER BASEBAND 6 4 2 2 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) 0 17267-010 0 23 0.2 17267-012 -15 2 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 BASEBAND FREQUENCY (GHz) Figure 11. Output IP3 vs. RF Frequency at Maximum Gain for Supply Voltages, RF Amplitude = -20 dBm per Tone at 20 MHz Spacing, fBB = 100 MHz (Upper Sideband) 17267-013 OUTPUT IP3 (dBm) 24 Figure 14. Output IP3 vs. Baseband Frequency at fRF = 28 GHz and 39 GHz at Maximum Gain, RF Amplitude = -20 dBm per Tone at 20 MHz Spacing (Upper Sideband and Lower Sideband) 28 24.0 26 23.8 24 22 23.6 OUTPUT IP3 (dBm) OUTPUT IP3 (dBm) 20 18 16 14 12 10 23.4 23.2 23.0 22.8 8 +6dBm UPPER SIDEBAND 0dBm UPPER SIDEBAND -6dBm UPPER SIDEBAND 4 22.6 25 27 29 31 33 35 37 RF FREQUENCY (GHz) 39 41 43 45 22.2 -20 17267-011 0 23 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 22.4 2 -19 -18 -17 -16 -15 -14 -13 -12 -11 -10 TOTAL INPUT POWER (dBm) Figure 12. Output IP3 vs. RF Frequency at Maximum Gain for Various LO Inputs, RF Amplitude = -20 dBm per Tone at 20 MHz Spacing, fBB = 100 MHz (Upper Sideband) Rev. B | Page 10 of 39 Figure 15. Output IP3 vs. Total Input Power at 20 MHz Spacing, fBB = 100 MHz, fRF = 28 GHz and 39 GHz (Upper Sideband) 17267-014 6 Data Sheet ADMV1013 50 45 45 35 30 25 20 15 20 27 29 31 33 35 37 39 41 43 45 0 17267-015 25 RF FREQUENCY (GHz) 0 0.6 0.8 1.0 1.2 1.4 1.6 1.8 50 45 3.5V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.1V UPPER SIDEBAND 35 30 25 20 15 35 30 25 20 15 10 10 5 5 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) 0 17267-016 25 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 40 NOISE FIGURE (dB) 40 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 BASEBAND FREQUENCY (GHz) Figure 17. Noise Figure vs. RF Frequency for Various Supply Voltages, fBB = 100 MHz (Upper Sideband) 17267-019 45 Figure 20. Noise Figure vs. Baseband Frequency at fRF = 28 GHz and 39 GHz (Upper Sideband) 50 50 45 45 NOISE FIGURE (dB) 35 30 25 20 15 35 30 25 20 15 10 10 5 5 27 29 31 33 35 37 RF FREQUENCY (GHz) 39 41 43 45 0 17267-017 25 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND 40 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 BASEBAND FREQUENCY (GHz) Figure 18. Noise Figure vs. RF Frequency for Various LO Inputs, fBB = 100 MHz (Upper Sideband) Rev. B | Page 11 of 39 Figure 21. Noise Figure vs. Baseband Frequency at fRF = 28 GHz and 39 GHz (Lower Sideband) 17267-020 +6dBm UPPER SIDEBAND 0dBm UPPER SIDEBAND -6dBm UPPER SIDEBAND 40 NOISE FIGURE (dB) 0.4 Figure 19. Noise Figure vs. VCTRL for Various Temperatures at fRF = 28 GHz 39 GHz, fBB = 100 MHz 50 0 23 0.2 VCTRL (V) Figure 16. Noise Figure vs. RF Frequency at Maximum Gain for Various Temperatures, fBB = 100 MHz (Upper Sideband) 0 23 +85C AT 39GHz +25C AT 39GHz -40C AT 39GHz +85C AT 28GHz +25C AT 28GHz -40C AT 28GHz 15 5 5 NOISE FIGURE (dB) 25 10 10 0 23 30 17267-018 35 NOISE FIGURE (dB) NOISE FIGURE (dB) 40 +85C UPPER SIDEBAND +25C UPPER SIDEBAND -40C UPPER SIDEBAND 40 Data Sheet 45 45 40 40 35 35 30 25 20 15 +85C UPPER SIDEBAND +25C UPPER SIDEBAND -40C UPPER SIDEBAND 10 5 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) 20 10 0 40 45 30 25 20 15 3.5V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.1V UPPER SIDEBAND 10 5 0.6 0.8 1.0 1.2 1.4 1.6 1.8 40 35 30 25 20 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND 15 10 27 29 31 33 35 37 39 41 43 45 0 17267-023 25 0 BASEBAND FREQUENCY (GHz) Figure 26. Sideband Rejection vs. Baseband Frequency at fRF = 28 GHz and 39 GHz (Upper Sideband and Lower Sideband) Figure 23. Sideband Rejection vs. RF Frequency at for Various Supply Voltages, fBB = 100 MHz (Upper Sideband) 45 40 35 30 25 20 15 10 +6dBm UPPER SIDEBAND 0dBm UPPER SIDEBAND -6dBm UPPER SIDEBAND 5 27 29 31 33 35 37 RF FREQUENCY (GHz) 39 41 43 45 17267-024 0 25 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 Figure 24. Sideband Rejection vs. RF Frequency for Various LO Inputs, fBB = 100 MHz (Upper Sideband) Rev. B | Page 12 of 39 17267-026 5 RF FREQUENCY (GHz) -5 23 0.4 Figure 25. Sideband Rejection vs. VCTRL for Various Temperatures at fRF = 28 GHz and 39 GHz, fBB = 100 MHz 50 35 0.2 VCTRL (V) 45 0 23 +85C AT 39GHz +25C AT 39GHz -40C AT 39GHz +85C AT 28GHz +25C AT 28GHz -40C AT 28GHz 15 0 SIDEBAND REJECTION (dBc) SIDEBAND REJECTION (dBc) Figure 22. Sideband Rejection vs. RF Frequency at Maximum Gain for Various Temperatures, fBB = 100 MHz (Upper Sideband) SIDEBAND REJECTION (dBc) 25 5 17267-021 0 23 30 17267-025 SIDEBAND REJECTION (dBc) SIDEBAND REJECTION (dBc) ADMV1013 Data Sheet ADMV1013 20 20 15 15 0 +85C UPPER SIDEBAND +25C UPPER SIDEBAND -40C UPPER SIDEBAND -5 -10 23 25 27 29 31 33 35 5 0 +85C AT 39GHz +25C AT 39GHz -40C AT 39GHz +85C AT 28GHz +25C AT 28GHz -40C AT 28GHz -5 -10 -15 37 39 41 43 45 RF FREQUENCY (GHz) -20 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VCTRL (V) Figure 27. Output P1dB vs. RF Frequency at Maximum Gain for Various Temperatures, fBB = 100 MHz (Upper Sideband) 17267-030 OUTPUT P1dB (dBm) 5 17267-027 OUTPUT P1dB (dBm) 10 10 Figure 30. Output P1dB vs. VCTRL for Various Temperatures at fRF = 28 GHz and 39 GHz, fBB = 100 MHz 20 20 15 15 OUTPUT P1dB (dBm) 5 0 -5 3.5V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.1V UPPER SIDEBAND -15 -20 23 25 27 29 31 33 10 5 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 0 35 37 39 41 43 45 RF FREQUENCY (GHz) -5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 BASEBAND FREQUENCY (GHz) Figure 28. Output P1dB vs. RF Frequency for Various Supply Voltages, fBB = 100 MHz (Upper Sideband) 17267-031 -10 17267-028 OUTPUT P1dB (dBm) 10 Figure 31. Output P1dB vs. Baseband Frequency at fRF = 28 GHz and 39 GHz (Upper Sideband) 20 20 15 15 OUTPUT P1dB (dBm) 5 0 -5 +6dBm UPPER SIDEBAND 0dBm UPPER SIDEBAND -6dBm UPPER SIDEBAND -15 -20 23 25 27 29 31 33 35 10 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND 5 0 37 39 41 43 45 RF FREQUENCY (GHz) -5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 BASEBAND FREQUENCY (GHz) Figure 32. Output P1dB vs. Baseband Frequency at fRF = 28 GHz and 39 GHz (Lower Sideband) Figure 29. Output P1dB vs. RF Frequency for Various LO Inputs, fBB = 100 MHz (Upper Sideband) Rev. B | Page 13 of 39 17267-032 -10 17267-029 OUTPUT P1dB (dBm) 10 ADMV1013 Data Sheet IF MODE 28 26 26 24 24 22 22 CONVERSION GAIN (dB) 28 20 18 16 14 12 10 +85C UPPER SIDEBAND +25C UPPER SIDEBAND -40C UPPER SIDEBAND +85C LOWER SIDEBAND +25C LOWER SIDEBAND -40C LOWER SIDEBAND 6 4 2 25 27 29 31 33 18 16 14 12 10 8 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND 6 4 2 35 37 39 41 43 45 RF FREQUENCY (GHz) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 Figure 33. Conversion Gain vs. RF Frequency at Maximum Gain for Various Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) IF FREQUENCY (GHz) Figure 36. Conversion Gain vs. IF Frequency at fRF = 28 GHz and 39 GHz at Maximum Gain (Upper Sideband and Lower Sideband) 28 30 26 24 +85C AT 39GHz +25C AT 39GHz -40C AT 39GHz +85C AT 28GHz +25C AT 28GHz -40C AT 28GHz 20 CONVERSION GAIN (dB) 20 18 16 14 12 10 3.5V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.1V UPPER SIDEBAND 3.5V LOWER SIDEBAND 3.3V LOWER SIDEBAND 3.1V LOWER SIDEBAND 6 4 2 0 23 25 27 29 31 33 10 0 -10 -20 -30 35 37 39 41 43 45 RF FREQUENCY (GHz) -40 0 0.6 0.8 1.0 1.2 1.4 1.6 1.8 Figure 37. Conversion Gain vs. VCTRL at Various Temperatures at fRF = 28 GHz and 39 GHz, fIF = 3.5 GHz (Upper Sideband) 30 28 26 +85C AT 39GHz +25C AT 39GHz -40C AT 39GHz +85C AT 28GHz +25C AT 28GHz -40C AT 28GHz 20 24 CONVERSION GAIN (dB) 22 20 18 16 14 12 10 +6dBm UPPER SIDEBAND 0dBm UPPER SIDEBAND -6dBm UPPER SIDEBAND +6dBm LOWER SIDEBAND 0dBm LOWER SIDEBAND -6dBm LOWER SIDEBAND 8 6 4 2 25 27 29 31 33 35 10 0 -10 -20 -30 37 RF FREQUENCY (GHz) 39 41 43 45 17267-037 CONVERSION GAIN (dB) 0.4 VCTRL (V) Figure 34. Conversion Gain vs. RF Frequency at Maximum Gain for Various Supply Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) 0 23 0.2 17267-039 8 17267-036 CONVERSION GAIN (dB) 22 Figure 35. Conversion Gain vs. RF Frequency at Maximum Gain for Various LO Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) Rev. B | Page 14 of 39 -40 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VCTRL (V) Figure 38. Conversion Gain vs. VCTRL at Various Temperatures at fRF = 28 GHz and 39 GHz, fIF = 3.5 GHz (Lower Sideband) 17267-040 0 23 20 17267-038 8 17267-035 CONVERSION GAIN (dB) IF amplitude = -20 dBm, VCC_DRV = VCC2_DRV = VCC_AMP2 = VCC_ENV = VCC_AMP1 = VCC_BG2 = VCC_MIXER = VCC_BG = VCC_QUAD = 3.3 V, DVDD = VCC_VVA = 1.8 V, TA = 25C, and set Register 0x0A to 0xE700, unless otherwise noted. VCTRL1 = VCTRL2. VCTRL is the attenuation voltage at the VCTRL1 and VCTRL2 pins. VCTRL = 1800 mV, unless otherwise specified. Measurements in IF mode performed with a 90 hybrid, Register 0x03, Bit 7 = 1, and fIF = 3.5 GHz. Data Sheet ADMV1013 25 28 26 24 20 22 16 14 12 10 6 4 2 0 23 +85C UPPER SIDEBAND +25C UPPER SIDEBAND -40C UPPER SIDEBAND +85C LOWER SIDEBAND +25C LOWER SIDEBAND -40C LOWER SIDEBAND 25 27 29 31 33 0 35 37 39 41 43 45 -10 0 28 26 24 24 22 22 20 20 OUTPUT IP3 (dBm) 28 18 16 14 12 10 2 0 23 3.5V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.1V UPPER SIDEBAND 3.5V LOWER SIDEBAND 3.3V LOWER SIDEBAND 3.1V LOWER SIDEBAND 25 27 29 31 33 0.6 0.8 1.1 1.2 1.4 1.6 1.8 18 16 14 12 10 8 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND 6 4 2 35 37 39 41 43 45 RF FREQUENCY (GHz) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 17267-042 4 0.4 Figure 42. Output IP3 vs. VCTRL at fRF = 28 GHz and 39 GHz, RF Amplitude = -20 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) 26 6 0.2 VCTRL (V) Figure 39. Output IP3 vs. RF Frequency at Maximum Gain for Various Temperatures, RF Amplitude = -20 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) 8 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND -5 RF FREQUENCY (GHz) OUTPUT IP3 (dBm) 5 Figure 40. Output IP3 vs. RF Frequency at Maximum Gain for Various Supply Voltages, RF Amplitude = -20 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) IF FREQUENCY (GHz) 17267-045 8 10 17267-044 OUTPUT IP3 (dBm) 15 18 17267-041 OUTPUT IP3 (dBm) 20 Figure 43. Output IP3 vs. IF Frequency at fRF = 28 GHz and 39 GHz at Maximum Gain, RF Amplitude = -20 dBm per Tone at 20 MHz Spacing (Upper Sideband and Lower Sideband) 25 28 26 24 23 20 22 18 16 14 12 10 +6dBm UPPER SIDEBAND 0dBm UPPER SIDEBAND -6dBm UPPER SIDEBAND +6dBm LOWER SIDEBAND 0dBm LOWER SIDEBAND -6dBm LOWER SIDEBAND 8 6 4 2 0 23 25 27 29 31 33 35 21 20 19 18 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND 17 16 37 RF FREQUENCY (GHz) 39 41 43 45 17 -20 Figure 41. Output IP3 vs. RF Frequency at Maximum Gain for Various LO Inputs, RF Amplitude = -20 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) -19 -18 -17 -16 -15 -14 -13 TOTAL INPUT POWER (dBm) -12 -11 -10 17267-046 OUTPUT IP3 (dBm) 22 17267-043 OUTPUT IP3 (dBm) 24 Figure 44. Output IP3 vs. Total Input Power at fRF = 28 GHz and 39 GHz at 20 MHz Spacing, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) Rev. B | Page 15 of 39 ADMV1013 Data Sheet 50 40 35 30 25 35 30 25 20 15 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND 20 10 15 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 Figure 45. Noise Figure vs. RF Frequency at Maximum Gain for Various Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) IF FREQUENCY (GHz) Figure 48. Noise Figure vs. IF Frequency at fRF = 28 GHz and 39 GHz at Maximum Gain (Upper Sideband and Lower Sideband) 55 50 35 45 30 25 20 30 27 29 31 33 35 37 39 41 43 45 10 17267-048 25 Figure 46. Noise Figure vs. RF Frequency at Maximum Gain for Various Supply Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VCTRL (V) Figure 49. Noise Figure vs. VCTRL at Various Temperatures, fIF = 3.5 GHz, (Upper Sideband and Lower Sideband) 50 50 +6dBm UPPER SIDEBAND 0dBm UPPER SIDEBAND -6dBm UPPER SIDEBAND +6dBm LOWER SIDEBAND 0dBm LOWER SIDEBAND -6dBm LOWER SIDEBAND 40 45 40 NOISE FIGURE (dB) 45 35 30 25 35 30 25 20 20 15 15 25 27 29 31 33 35 37 RF FREQUENCY (GHz) 39 41 43 45 Figure 47. Noise Figure vs. RF Frequency at Maximum Gain for Various LO Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) +85C AT 39GHz +25C AT 39GHz -40C AT 39GHz +85C AT 28GHz +25C AT 28GHz -40C AT 28GHz 10 17267-049 10 23 +85C UPPER SIDEBAND +25C UPPER SIDEBAND -40C UPPER SIDEBAND +85C LOWER SIDEBAND +25C LOWER SIDEBAND -40C LOWER SIDEBAND 25 15 RF FREQUENCY (GHz) NOISE FIGURE (dB) 35 20 15 10 23 40 17267-051 NOISE FIGURE (dB) 40 50 3.5V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.1V UPPER SIDEBAND 3.5V LOWER SIDEBAND 3.3V LOWER SIDEBAND 3.1V LOWER SIDEBAND NOISE FIGURE (dB) 45 17267-050 25 17267-047 10 23 5 0 0.2 0.4 0.6 0.8 1.0 VCTRL (V) 1.2 1.4 1.6 1.8 17267-052 NOISE FIGURE (dB) 40 45 NOISE FIGURE (dB) 45 50 +85C UPPER SIDEBAND +25C UPPER SIDEBAND -40C UPPER SIDEBAND +85C LOWER SIDEBAND +25C LOWER SIDEBAND -40C LOWER SIDEBAND Figure 50. Noise Figure vs. VCTRL for Various Temperatures at fRF = 28 GHz and 39 GHz, fIF = 3.5 GHz (Lower Sideband) Rev. B | Page 16 of 39 ADMV1013 20 15 15 10 5 0 -5 -10 23 +85C UPPER SIDEBAND +25C UPPER SIDEBAND -40C UPPER SIDEBAND +85C LOWER SIDEBAND +25C LOWER SIDEBAND -40C LOWER SIDEBAND 25 27 29 31 33 10 5 0 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND -5 35 37 39 41 43 45 RF FREQUENCY (GHz) -10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 Figure 51. Output P1dB vs. RF Frequency at Maximum Gain for Various Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) IF FREQUENCY (GHz) 17267-056 OUTPUT P1dB (dBm) 20 17267-053 OUTPUT P1dB (dBm) Data Sheet Figure 54. Output P1dB vs. IF Frequency at fRF = 28 GHz and 39 GHz at Maximum Gain (Upper Sideband and Lower Sideband) 20 20 15 15 OUTPUT P1dB (dBm) 10 5 -5 -10 23 25 27 29 31 33 5 0 -5 +85C AT 39GHz +25C AT 39GHz -40C AT 39GHz +85C AT 28GHz +25C AT 28GHz -40C AT 28GHz -10 -15 -20 35 37 39 41 43 45 RF FREQUENCY (GHz) -25 0 Figure 52. Output P1dB vs. RF Frequency at Maximum Gain for Various Supply Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) 0.2 0.4 0.6 0.8 1.1 VCTRL (V) 1.2 1.4 1.6 1.8 17267-057 0 3.5V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.1V UPPER SIDEBAND 3.5V LOWER SIDEBAND 3.3V LOWER SIDEBAND 3.1V LOWER SIDEBAND 17267-054 OUTPUT P1dB (dBm) 10 Figure 55. Output P1dB vs. VCTRL for Various Temperatures at fRF = 28 GHz and 39 GHz, fIF = 3.5 GHz (Upper Sideband) 15 20 15 OUTPUT P1dB (dBm) 10 5 0 +6dBm UPPER SIDEBAND 0dBm UPPER SIDEBAND -6dBm UPPER SIDEBAND +6dBm LOWER SIDEBAND 0dBm LOWER SIDEBAND -6dBm LOWER SIDEBAND -10 23 25 27 29 31 33 35 5 0 -5 +85C AT 39GHz +25C AT 39GHz -40C AT 39GHz +85C AT 28GHz +25C AT 28GHz -40C AT 28GHz -10 -15 -20 37 RF FREQUENCY (GHz) 39 41 43 45 Figure 53. Output P1dB vs. RF Frequency at Maximum Gain for Various LO Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) Rev. B | Page 17 of 39 -25 0 0.2 0.4 0.6 0.8 1.1 VCTRL (V) 1.2 1.4 1.6 1.8 Figure 56. Output P1dB vs. VCTRL for Various Temperatures at fRF = 28 GHz and 39 GHz, fIF = 3.5 GHz (Lower Sideband) 17267-058 -5 17267-055 OUTPUT P1dB (dBm) 10 ADMV1013 Data Sheet 40 60 55 35 SIDEBAND REJECTION (dBc) 45 40 35 30 25 20 +85C UPPER SIDEBAND +25C UPPER SIDEBAND -40C UPPER SIDEBAND +85C LOWER SIDEBAND +25C LOWER SIDEBAND -40C LOWER SIDEBAND 10 5 25 27 29 31 33 35 20 37 39 41 43 45 Figure 57. Sideband Rejection vs. RF Frequency at Maximum Gain for Various Temperatures, fIF = 3.5 GHz, Uncalibrated (Upper Sideband and Lower Sideband) 10 0 23 55 50 50 SIDEBAND REJECTION (dBc) 60 40 35 30 25 20 +85C UPPER SIDEBAND +25C UPPER SIDEBAND -40C UPPER SIDEBAND 10 29 31 33 35 37 39 41 43 45 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND 45 40 35 30 25 20 15 10 5 5 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 17267-060 0 23 27 Figure 60. Sideband Rejection vs. RF Frequency at Maximum Gain for Various LO Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) 55 45 25 RF FREQUENCY (GHz) 60 15 +6dBm UPPER SIDEBAND 0dBm UPPER SIDEBAND -6dBm UPPER SIDEBAND +6dBm LOWER SIDEBAND 0dBm LOWER SIDEBAND -6dBm LOWER SIDEBAND 15 5 RF FREQUENCY (GHz) SIDEBAND REJECTION (dBc) 25 Figure 58. Sideband Rejection vs. RF Frequency at Maximum Gain for Various Temperatures, fIF = 3.5 GHz, Calibrated at 25C (Upper Sideband). Note: Calibrated Using LOAMP_PH_ADJ_ Q_FINE and LOAMP_PH_ADJ_I_FINE Bits IF FREQUENCY (GHz) 17267-063 0 23 30 17267-062 15 17267-059 SIDEBAND REJECTION (dBc) 50 Figure 61. Sideband Rejection vs. IF Frequency at fRF = 28 GHz and 39 GHz at Maximum Gain (Upper Sideband and Lower Sideband) 40 40 35 SIDEBAND REJECTION (dBc) SIDEBAND REJECTION (dBc) 35 30 25 20 3.5V UPPER SIDEBAND 3.3V UPPER SIDEBAND 3.1V UPPER SIDEBAND 3.5V LOWER SIDEBAND 3.3V LOWER SIDEBAND 3.1V LOWER SIDEBAND 15 10 30 25 20 15 39GHz UPPER SIDEBAND 28GHz UPPER SIDEBAND 39GHz LOWER SIDEBAND 28GHz LOWER SIDEBAND 10 5 23 25 27 29 31 33 35 37 RF FREQUENCY (GHz) 39 41 43 45 17267-061 0 0 Figure 59. Sideband Rejection vs. RF Frequency at Maximum Gain for Various Supply Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) Rev. B | Page 18 of 39 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VCTRL (V) Figure 62. Sideband Rejection vs. VCTRL at fRF = 28 GHz and 39 GHz, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) 17267-064 5 Data Sheet ADMV1013 ENVELOPE DETECTOR PERFORMANCE IF and I/Q amplitude = -20 dBm, VCC_DRV = VCC2_DRV = VCC_AMP2 = VCC_ENV = VCC_AMP1 = VCC_BG2 = VCC_MIXER = VCC_BG = VCC_QUAD = 3.3 V, DVDD = VCC_VVA = 1.8 V, TA = 25C, and set Register 0x0A to 0xE700, unless otherwise noted. Measurements in IF mode performed with a 90 hybrid, Register 0x03, Bit 7 = 1, IF fIF = 3.5 GHz. Measurements in I/Q mode are measured as a composite of the I and Q channel performance, VCM = 0 V, Register 0x03, Bit 7 = 0, and Register 0x05, Bits[6:0] = 0x051, unless otherwise noted. I/Q fBB = 100 MHz. VCTRL1 = VCTRL2. VCTRL is the attenuation voltage at the VCTRL1 and VCTRL2 pins. VCTRL = 1800 mV, unless otherwise specified. Envelope detector measurements made with Register 0x03, Bit 5 = 1. ENVELOPE POUT DELTA (dBm) -20 125 -30 100 -40 75 -50 ENVELOPE POUT, ENVELOPE POUT, ENVELOPE POUT, 50 POUT = 13dBm POUT = 5dBm POUT = 0dBm -70 23 25 27 29 31 33 35 37 39 41 43 -20 -30 -60 25 45 RF FREQUENCY (GHz) Figure 63. VENV_N/VENV_P Delta and Envelope POUT Delta vs. RF Frequency at Various Output Power Levels, Envelope Frequency = 100 MHz, VCTRL = 1800 mV, TA = 25C, LO = 0 dBm, IF = 2 GHz (Upper Sideband) 180 140 -60 120 -70 100 -80 80 -90 60 -100 40 -110 20 -120 -20 -18 0 -16 -14 -12 -10 -8 -6 -4 -2 0 2 POWER IN TOTAL (dBm) Figure 65. POUT and VENV_N/VENV_P Delta vs. Power In Total for POUT RF, POUT Envelope HD1, POUT Envelope HD2, and VENV_N/VENV_P Delta, Measurements Performed with Two Tones with 100 MHz Separation, fRF = 28 GHz, VCTRL = 1800 mV -15 NORMALIZED HD1, 1x NORMALIZED HD2, 2x -25 -30 -35 -40 -45 -50 -55 -60 -65 17267-066 -70 50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 1500 200 160 -10 OUTPUT LEVEL (dBm) 220 -50 0 ENVELOPE FREQUENCY (MHz) 240 POUT RF POUT ENVELOPE AT HD1 POUT ENVELOPE AT HD2 VENV_N/VENV_P DELTA -40 -5 -20 260 -10 POUT (dBm) 150 280 10 0 -10 17267-065 VENV_N/VENV_P DELTA (mV) 175 20 VENV_N/VENV_P DELTA (mV) 0 VENV_N/VENV_P DELTA, POUT = 13dBm VENV_N/VENV_P DELTA, POUT = 5dBm VENV_N/VENV_P DELTA, POUT = 0dBm Figure 64. Output Level vs. Envelope Frequency for Normalized Harmonic Distortion (HD1), 1x and Normalized Harmonic Distortion(HD2), 2x, fRF = 28 GHz, LO = 0 dBm at 25C, HD1 and HD2 Measurement Performed with Two Tones with Delta Equal to Envelope Frequency, HD2 Normalized to HD1 Level at 50 MHz Rev. B | Page 19 of 39 17267-067 200 Data Sheet 130 -10 120 -15 110 -20 100 -25 90 -30 80 -35 70 -40 60 -45 50 POUT ENVELOPE AT PIN = -10dBm POUT ENVELOPE AT PIN = -15dBm VENV_N/VENV_P DELTA, PIN = -10dBm VENV_N/VENV_P DELTA, PIN = -15dBm -50 20 10 Figure 66. HD1 POUT Envelope and VENV_N/VENV_P Delta vs. VCTRL at Various Total Input Power (PIN) Levels, Measurements Performed at 28 GHz with Two Input Tones with Separation of 100 MHz 16 14 12 8 10 17267-069 POUT RF PER TONE (dBm) 6 4 2 0 -2 -4 -6 -8 -60 -20 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 0.1 0 -10 -70 VCTRL (V) -40 -12 -65 30 -30 -14 -60 POUT ENVELOPE AT +25C POUT ENVELOPE AT +85C POUT ENVELOPE AT -40C -20 -16 -55 40 -10 -18 -50 0 POUT ENVELOPE (dBm) 140 VENV_N/VENV_P DELTA (mV) 0 -5 17267-068 HD1 P OUT ENVELOPE (dBm) ADMV1013 Figure 67. POUT Envelope vs. POUT RF per Tone at Various Temperatures at fRF = 33 GHz, Measurement Performed at 3.5 GHz IF with Two Tones at 100 MHz Spacing, VCTRL = 1800 mV Rev. B | Page 20 of 39 Data Sheet ADMV1013 RETURN LOSS AND ISOLATION IF and I/Q amplitude = -20 dBm, VCC_DRV = VCC2_DRV = VCC_AMP2 = VCC_ENV = VCC_AMP1 = VCC_BG2 = VCC_MIXER = VCC_BG = VCC_QUAD = 3.3 V, DVDD = VCC_VVA = 1.8 V, TA = 25C, and set Register 0x0A to 0xE700, unless otherwise noted. Measurements in IF mode performed with a 90 hybrid, Register 0x03, Bit 7 = 1, and fIF = 3.5 GHz. Measurements in I/Q mode are measured as a composite of the I and Q channel performance, VCM = 0 V, Register 0x03, Bit 7 = 0, and Register 0x05, Bits[6:0] = 0x051, unless otherwise noted. I/Q fBB = 100 MHz. VCTRL1 = VCTRL2. VCTRL is the attenuation voltage at the VCTRL1 and VCTRL2 pins. VCTRL = 1800 mV, unless otherwise specified. 0 0 -5 -5 -15 -20 0V 0.9V 1.8V -25 -30 -15 -20 -25 27 29 31 35 33 37 39 41 43 45 RF FREQUENCY (GHz) -35 17267-071 25 0 1 2 3 4 5 6 7 IF FREQUENCY (GHz) Figure 68. RF Return Loss vs. RF Frequency at Various VCTRL Voltages 17267-075 -30 -35 23 Figure 70. IF Return Loss vs. IF Frequency (Taken Without Hybrid) 0 0 -10 -15 -20 -25 -35 4 5 6 7 8 9 10 LO FREQUENCY (GHz) 11 12 17267-072 -30 Figure 69. LO Return Loss vs. LO Frequency -5 I SIDE Q SIDE -10 -15 -20 -25 -30 -35 0 1 2 3 4 5 6 FREQUENCY (GHz) Figure 71. I/Q Differential Return Loss vs. Frequency (Taken Without Hybrids or Baluns) Rev. B | Page 21 of 39 7 17267-074 I/Q DIFFERENTIAL RETURN LOSS (dB) LOP LON LO DIFFERENTIAL -5 LO RETURN LOSS (dB) I SIDE Q SIDE -10 -10 IF RETURN LOSS (dB) RF RETURN LOSS (dBm) Envelope detector measurements made with Register 0x03, Bit 5 = 1. Data Sheet 5x LO AT +85C 5x LO AT +25C 5x LO AT -40C 1x LO AT +85C 1x LO AT +25C 1x LO AT -40C 4 6 8 10 12 LO FREQUENCY (GHz) 1x LO 1x LO 1x LO 1x LO 1x LO 1x LO 1x LO 5 6 7 8 9 10 11 12 LO FREQUENCY (GHz) Figure 73. 1x LO Leakage vs. LO Frequency at Different VCTRL Settings (Uncalibrated) 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 8 9 10 11 12 4x LO LEAKAGE, VCTRL = 0mV 4x LO LEAKAGE, VCTRL = 300mV 4x LO LEAKAGE, VCTRL = 600mV 4x LO 4x LO 4x LO 4x LO 4 5 6 LEAKAGE, VCTRL = 900mV LEAKAGE, VCTRL = 1200mV LEAKAGE, VCTRL = 1500mV LEAKAGE, VCTRL = 1800mV 7 8 9 10 11 12 LO FREQUENCY (GHz) Figure 76. 4x LO Leakage vs. LO Frequency at Different VCTRL Settings (Uncalibrated) 0 VCTRL VCTRL VCTRL VCTRL VCTRL VCTRL -10 -10 -40C +25C +85C -20 4x LO TO RF LEAKAGE (dBm) 4x LO TO RF LEAKAGE (dBm) 7 = 0mV = 300mV = 600mV = 900mV = 1200mV = 1500mV = 1800mV Figure 75. 5x LO Leakage vs. LO Frequency at Different VCTRL Settings (Uncalibrated) 0 -30 -40 -50 -60 -70 -20 -30 = 0V = 0.4V = 0.8V = 1.2V = 1.4V = 1.8V -40 -50 -60 -70 -80 -90 -100 5 6 7 8 9 LO FREQUENCY (GHz) 10 11 12 17267-077 80 4 6 VCTRL VCTRL VCTRL VCTRL VCTRL VCTRL VCTRL 4 5 6 7 8 9 LO FREQUENCY (GHz) Figure 74. 4x LO to RF Leakage vs. LO Frequency at Various Temperatures (Calibrated). Note: Calibrated at Each Frequency Using MXER_OFF_ADJ_I_N, MXER_OFF_ADJ_I_P, MXER_OFF_ADJ_Q_N, and MXER_OFF_ADJ_Q_P Bits at TA = 25C 10 11 12 17267-080 4 LEAKAGE, VCTRL = 0mV LEAKAGE, VCTRL = 300mV LEAKAGE, VCTRL = 600mV LEAKAGE, VCTRL = 900mV LEAKAGE, VCTRL = 1200mV LEAKAGE, VCTRL = 1500mV LEAKAGE, VCTRL = 1800mV 5 LEAKAGE, LEAKAGE, LEAKAGE, LEAKAGE, LEAKAGE, LEAKAGE, LEAKAGE, LO FREQUENCY (GHz) 4x LO LEAKAGE (dBm) 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 5x LO 5x LO 5x LO 5x LO 5x LO 5x LO 5x LO 4 17267-076 1x LO LEAKAGE (dBm) Figure 72. LO to RF Leakage vs. LO Frequency for 4x LO, 5x LO, and 1x LO at Various Temperatures (Uncalibrated) 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 17267-276 5x LO LEAKAGE (dBm) 4x LO AT +85C 4x LO AT +25C 4x LO AT -40C 17267-176 0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 -55 -60 -65 -70 -75 -80 -85 -90 -95 -100 -105 17267-073 LO TO RF LEAKAGE (dBc) ADMV1013 Figure 77. 4x LO to RF Leakage vs. LO Frequency at Various VCTRL (Calibrated) Note: Calibrated at Each Frequency Using MXER_OFF_ADJ_I_N, MXER_OFF_ADJ_I_P, MXER_OFF_ADJ_Q_N, and MXER_OFF_ADJ_Q_P Bits at VCTRL = 1800 mV Rev. B | Page 22 of 39 Data Sheet ADMV1013 0 0 -10 +25C, I_N -40C, I_N +85C, I_N +25C, I_P -40C, I_P +85C, I_P +25C, Q_N -40C, Q_N +85C, Q_N +25C, Q_P -40C, Q_P +85C, Q_P -10 -20 -30 LO LEAKAGE (dBm) -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -100 5 6 8 7 9 10 11 12 LO FREQUENCY (GHz) 17267-079 -90 -100 4 Figure 78. LO Leakage vs. LO Frequency at Various Temperatures at I_N, I_P, Q_N, and Q_P (Taken Without Hybrid(s)) 4 -10 -15 -20 -25 1 2 3 4 5 FREQUENCY (GHz) 17267-082 -30 0 6 7 8 9 10 11 12 Figure 80. LO Leakage vs. LO Frequency at Various Temperatures at IF_I and IF_Q Ports(Taken Without Hybrid) -5 -35 5 LO FREQUENCY (GHz) 0 ENVELOPE DETECTOR DIFFERENTIAL RETURN LOSS (dB) -40C, IF_I +25C, IF_I +85C, IF_I -40C, IF_Q +25C, IF_Q +85C, IF_Q -30 17267-078 LO LEAKAGE (dBm) -20 Figure 79. Envelope Detector Differential Return Loss vs. Frequency Rev. B | Page 23 of 39 ADMV1013 Data Sheet M x N SPURIOUS PERFORMANCE IF Mode Mixer spurious products are measured in dBc from the RF output power level. Spurious frequencies are calculated by fIF = 3.5 GHz at -20 dBm, LO = 6.125 GHz at +6 dBm, and fRF = 28 GHz. |(M x IF) + (N x LO) | (for IF Mode) |(M x IQ) + (N x LO) | (for IQ Mode) N/A means not applicable. Blank cells in the spurious performance tables indicate that the frequency is above 50 GHz and is not measured. REF stands for reference RF output signal. The LO frequencies are referred from the frequencies applied to the ADMV1013. IF and I/Q amplitude = -20 dBm. VCC_DRV = VCC2_DRV = VCC_AMP2 = VCC_ENV = VCC_AMP1 = VCC_BG2 = VCC_MIXER = VCC_BG = VCC_QUAD = 3.3 V, DVDD = VCC_VVA = 1.8 V, TA = 25C, and set Register 0x0A to 0xE700, unless otherwise noted. Measurements in IF mode performed with a 90 hybrid, Register 0x03, Bit 7 = 1, and fIF = 3.5 GHz. Measurements in I/Q mode are measured as a composite of the I and Q channel performance, VCM = 0 V, Register 0x03, Bit 7 = 0, and Register 0x05, Bits[6:0] = 0x051, unless otherwise noted. I/Q fBB = 100 MHz. VCTRL1 = VCTRL2. VCTRL is the attenuation voltage at the VCTRL1 and VCTRL2 pins. VCTRL = 1800 mV, unless otherwise specified. M x IF M x IQ 0 93 93 N/A 93 93 -2 -1 0 +1 +2 1 105 95 80 96 107 2 103 85 72 74 86 N x LO 3 4 122 79 57 26 53 20 32 REF 91 57 5 109 65 61 41 89 6 89 53 35 37 91 M x IF fBB = 100 MHz at -20 dBm, LO = 9.725 GHz at +6 dBm, and fRF = 39 GHz. M x IQ -2 -1 0 +1 +2 0 97 101 N/A 97 101 1 116 100 77 91 118 N x LO 2 3 95 116 37 62 40 63 18 36 80 99 4 89 26 20 REF 64 2 120 80 71 58 75 N x LO 3 4 109 77 77 23 26 9 18 REF 70 58 5 92 46 34 24 80 6 90 56 24 32 82 7 84 53 20 61 75 8 45 44 30 -2 -1 0 83 69 1 132 95 N x LO 2 3 109 96 76 54 0 N/A 69 44 53 16 52 +1 +2 83 69 89 114 24 93 33 98 REF 75 58 4 68 25 5 99 57 6 107 83 fIF = 3.5 GHz at -20 dBm, LO = 7.875 GHz at +6 dBm, and fRF = 28 GHz. M x IF 7 108 110 73 84 83 -2 -1 0 +1 +2 1 117 90 71 92 84 fIF = 3.5 GHz at -20 dBm, LO = 8.875 GHz at +6 dBm, and fRF = 39 GHz. I/Q Mode fBB = 100 MHz at -20 dBm, LO = 6.975 GHz at +6 dBm. 0 76 68 N/A 76 68 -2 -1 0 +1 +2 0 82 65 N/A 82 65 1 140 120 82 94 120 2 115 91 75 60 107 N x LO 3 4 107 69 41 REF 52 23 70 26 111 93 5 99 47 49 75 115 6 97 46 56 7 95 fIF = 3.5 GHz at -20 dBm, LO = 10.5 GHz at +6 dBm, and fRF = 39 GHz. M x IF 5 113 90 77 68 103 Rev. B | Page 24 of 39 -2 -1 0 +1 +2 0 96 80 N/A 97 79 1 122 85 83 95 113 N x LO 2 3 99 91 28 26 34 43 45 49 88 103 4 70 REF 16 41 102 5 94 64 Data Sheet ADMV1013 THEORY OF OPERATION The ADMV1013 is a wideband microwave upconverter optimized for microwave radio designs operating in the 24 GHz to 44 GHz RF frequency range. See Figure 1 for a functional block diagram of the device. The ADMV1013 digital settings are controlled via the SPI. The ADMV1013 has two modes of operation: * * Baseband quadrature modulation (I/Q mode) Single-sideband upconversion (IF mode) START-UP SEQUENCE To use the voltage control RF VVA1 and RF VVA2, the VCC_VVA (1.8 V) supply must be on. The VCTRL1 pin and VCTRL2 pin control the gain of the RF VVA1 and the RF VVA2. Similarly, to use the SPI control, it is necessary to first turn on DVDD and then perform a hard reset by toggling the RST pin to logic low and then to logic high. The ADMV1013 SPI settings require the default settings to be changed during startup for optimum performance. Set Register 0x0A to 0xE700 after each power-up or reset. LO INPUT PATH The LO input path operates from 5.4 GHz to 10.25 GHz with an LO amplitude range of -6 dBm to +6 dBm. The LO has an internal quadrupler (x4) and a programmable band-pass filter. The LO band-pass filter is programmable using the QUAD_ FILTERS bits (Register 0x09, Bits[3:0]). See the Performance at Different Quad Filter Settings section for more information on the QUAD_FILTERS settings. The LO path can operate either differentially or single ended. LOP and LON are the inputs to the LO path. The LO path can switch from differential to single-ended operation by setting the QUAD_SE_MODE bits (Register 0x09, Bits[9:6]). See the Performance Between Differential vs. Single-Ended LO Input section for more information. When using the LO as single ended, the unused LO input pin must be terminated with a 50 load. Figure 81 shows a block diagram of the LO path. BASEBAND QUADRATURE MODULATION (I/Q MODE) To set the ADMV1013 in I/Q mode, set MIXER_IF_EN bit (Register 0x03, Bit 7) to 0. When changing the external VCM, the internal mixer gate voltage also must be changed. To make this change, set the MIXER_VGATE bits (Register 0x05, Bits[6:0]). The MIXER_ VGATE value follows the VCM such as, that for a 0 V to 1.8 V VCM, MIXER_VGATE = 23.89 VCM + 81, and for a >1.8 V to 2.6 V VCM, MIXER_VGATE = 23.75 VCM + 1.25. SINGLE-SIDEBAND UPCONVERSION (IF MODE) The ADMV1013 features the ability to upconvert a real IF input anywhere from 0.8 GHz to 6.0 GHz while suppressing the unwanted sideband by typically better than 26 dBc. The IF inputs are quadrature to each other, 50 single ended, and are internally dc-coupled. IF_I and IF_Q are the quadrature IF inputs. An external 90 hybrid is required to select the appropriate sideband. To configure the ADMV1013 in IF mode, set the MIXER_IF_EN bit (Register 0x03, Bit 7) to 1. The MIXER_IF_EN bit defaults to IF mode on SPI startup and reset. In addition, the baseband pins (I_P, I_N, Q_P, and Q_N) must see an open load for optimum performance in IF mode. LON LOP AMP x4 4 x LON 4 x LOP 17267-105 In I/Q mode, the input impedance of the baseband pins (I_P, I_N, Q_P, and Q_N) are 100 differential. These inputs can be loaded with a dc-coupled 100 differential load. I_P and I_N are the differential baseband I inputs, and Q_P and Q_N are the differential baseband Q inputs. These inputs can operate from a VCM of 0 V to 2.6 V. The baseband I/Q ports can operate from dc to 6.0 GHz at each I and Q channel. Figure 81. LO Path Block Diagram Enable the quadrupler by setting the QUAD_PD bits (Register 0x03, Bits[13:11]) to 0x0. To power down the quadrupler, set these bits to 0x7. SIDEBAND SUPPRESSION OPTIMIZATION Unwanted sideband can be upconverted from the quadrature error by generating the quadrature LO signals and the external quadrature inputs. Deviation from ideal quadrature (that is, total sideband rejection and no sideband tone upconverts) on these signals limits the amount of achievable sideband rejection. The ADMV1013 offers approximately 25 of quadrature phase adjustment in the LO path quadrature signals to suppress the sideband. Make these adjustments through the LOAMP_PH_ ADJ_I_FINE bits (Register 0x05, Bits[13:7]) and the LOAMP_ PH_ADJ_Q_FINE bits (Register 0x06, Bits[13:7]). These bits reject the unwanted sideband signal. To achieve the required sideband suppression, it may be necessary to adjust the amplitude difference between the quadrature inputs, as well externally. In I/Q mode, the recommendation is to adjust the sideband suppression through the external transceiver digital-to-analog converter (DAC). Rev. B | Page 25 of 39 ADMV1013 Data Sheet CARRIER FEEDTHROUGH NULLING POWER DOWN AND RESET Carrier feedthrough results from minute dc offsets that occur on the internal mixer. In an I/Q modulator, nonzero differential offsets mix with the LO and result in carrier feedthrough to the RF output. In addition to this effect, some of the signal power at the LO input couples directly to the RF output (this may be because of the bond wire to bond wire coupling or coupling through the silicon substrate). The net carrier feedthrough at the RF output is the vector combination of the signals that appear at the output because of these two effects. The SPI of the ADMV1013 allows the user to power down the device circuits and reduce power consumption to typically 77 mW. To turn off the entire chip, set the BG_PD bit (Register 0x03, Bit 10) to 1. In addition, individual blocks of the circuit can be powered down individually. To power down the quadrupler, set the QUAD_PD bits (Register 0x03, Bits[13:11]) to 0x7. To power down the VGA, set the VGA_PD bit (Register 0x03, Bit 15) to 1. To power down the mixer, set the MIXER_PD bit (Register 0x03, Bit 14) to 1. To power down the detector, set the DET_EN bit (Register 0x03, Bit 5) to 0. The ADMV1013 offers, in IF mode, LO feedthrough offset calibration adjustment in the LO path. Make these adjustments through the MXER_OFF_ADJ_I_N bits (Register 0x07, Bits[8:2], the MXER_OFF_ADJ_I_P bits (Register 0x07, Bits[15:9]), the MXER_OFF_ADJ_Q_N bits (Register 0x08, Bits[8:2]), and the MXER_OFF_ADJ_Q_P bits (Register 0x08, Bits[15:9] in order to reject the unwanted LO signal. SERIAL PORT INTERFACE (SPI) The SPI of the ADMV1013 allows the user to configure the device for specific functions or operations via a 4-wire SPI port. This interface provides users with added flexibility and customization. The SPI consists of four control lines: SCLK, SDI, SDO, and active low chip select lines, SEN/SEN2. SEN and SEN2 must be connected together. For I/Q mode, the LO feedthrough offset amplitude and phase calibration optimization can be adjusted externally through a transceiver DAC. The ADMV1013 protocol consists of a write/read bit followed by six register address bits, 16 data bits, and a parity bit. Both the address and data fields are organized MSB first and end with the LSB. For a write, set the first bit to 0. For a read, set the first bit to 1. ENVELOPE DETECTOR The ADMV1013 features an envelope detector with a pseudo differential voltage output. The envelope detector output pins are VENV_P and VENV_N. The ADMV1013 turns on with the envelope detector turned off. To turn on the envelope detector, set the DET_EN bit (Bit 5, Register 0x03). The differential voltage output of the envelope detector rises linearly to the square of the input envelope voltage to the detector. The detector output ranges from -45 dBm to -20 dBm when the input two tone power ranges from -20 dBm to 0 dBm. The envelope detector has 350 MHz, 3 dB envelope bandwidth and 1 GHz, 10 dB envelope bandwidth. The envelope detector precedes the VVA and the output driver of the ADMV1013. The write cycle sampling must be performed on the rising edge. The 16 bits of the serial write data are shifted in, MSB to lower sideband. The ADMV1013 input logic level for the write cycle supports a 1.8 V interface. For a read cycle, up to 16 bits of serial read data are shifted out, MSB first. After the 16 bits of data shift out, the parity bit shifts out. The output logic level for a read cycle is 1.8 V. The parity bit always follows the direction of the data. If parity is not used, the transmitting end transmits zero instead of parity. The parity is odd, which means that the total number of ones transmitted during a command, including the read/write bit, the address bit, the data bit, and the parity bit, must be odd. Figure 82 and Figure 83 show the SPI write and read protocol, respectively. SEN/SEN2 1 2 3 4 5 6 7 8 9 D15 D14 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SDI R/W A5 A4 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 Figure 82. SPI Write Timing Diagram Rev. B | Page 26 of 39 D7 D6 D5 D4 D3 D2 D1 D0 P 17267-107 SCLK Data Sheet ADMV1013 SEN/SEN2 1 2 3 4 5 6 7 8 9 D15 D14 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCLK SDO R/W A5 A4 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 Figure 83. SPI Read Timing Diagram Rev. B | Page 27 of 39 D7 D6 D5 D4 D3 D2 D1 D0 P 17267-108 SDI ADMV1013 Data Sheet APPLICATIONS INFORMATION Figure 84 shows the I/Q mode performance at low baseband input frequencies. The measurements were performed at 28 GHz, -10 dBm input power, VCM = 0 V, Register 0x03, Bit 7 = 0, 0 dBm LO input power, and TA = 25C. 45 35 SIDEBAND REJECTION CONVERSION GAIN 30 25 -10 -15 -20 -25 -30 -35 QUAD FILTERS = 0 QUAD FILTERS = 5 QUAD FILTERS = 10 QUAD FILTERS = 15 -40 -45 -50 -60 15 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 4x LO FREQUENCY (GHz) 10 17267-089 -55 20 Figure 86. 4x LO to RF Leakage vs. 4x LO Frequency for Four Different QUAD_FILTERS Settings 0 1 10 100 1k 10k 100k 1M BASEBAND FREQUENCY (Hz) 10M 100M 17267-087 5 Figure 84. Conversion Gain and Sideband Rejection vs. Baseband Frequency PERFORMANCE AT DIFFERENT QUAD FILTER SETTINGS Figure 85 shows the conversion gain vs. RF frequency in IF mode at TA = 25C and LO input power = 0 dBm for different QUAD_FILTERS settings. 24 22 20 18 16 14 12 10 8 6 4 2 0 -2 -4 -6 -8 -10 VVA TEMPERATURE COMPENSATION Figure 87 shows the conversion gain vs. RF frequency at two different Register 0x0A settings, the recommended setting (0xE700) and a setting for higher gain, and three different temperatures for IF mode. The recommended value suggested in the Start-Up Sequence section provides the least variation in conversion gain over temperature. If the priority is to increase the conversion gain, Register 0x0A can be set to 0xFA00. However, at this value, the conversion gain variation over temperature can increase by 2 dB. 26 24 CONVERSION GAIN (dB) 22 QUAD FILTERS = 0 QUAD FILTERS = 5 QUAD FILTERS = 10 QUAD FILTERS = 15 20 18 16 14 12 -40C, 0xFA00 +25C, 0xFA00 +85C, 0xFA00 -40C, 0xE700 +25C, 0xE700 +85C, 0xE700 10 8 6 4 23 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) 17267-088 CONVERSION GAIN (dB) 0 -5 2 0 23 Figure 85. Conversion Gain vs. RF Frequency for Four Different QUAD_FILTERS Settings, fIF = 3.5 GHz (Upper Sideband) 25 27 29 31 33 35 37 RF FREQUENCY (GHz) 39 41 43 45 17267-090 CONVERSION GAIN (dB) AND SIDEBAND REJECTION (dBc) 40 Figure 86 shows the 4x LO to RF leakage vs. 4x LO frequency at different quad filter settings. 4x LO TO RF LEAKAGE (dBm) BASEBAND QUADRATURE MODULATION FROM LOW FREQUENCIES Figure 87. Conversion Gain vs. RF Frequency at Maximum Gain for Various Temperatures and Register 0x0A Settings (Recommended and Higher Gain Setting), fIF = 3.5 GHz Rev. B | Page 28 of 39 Data Sheet ADMV1013 28 26 24 24 22 20 SINGLE-ENDED POSITIVE SIDE DISABLE SINGLE-ENDED NEGATIVE SIDE DISABLE DIFFERENTIAL 18 16 14 12 10 8 6 20 4 18 2 16 0 14 23 12 -40C, 0xE700 +25C, 0xE700 +85C, 0xE700 -40C, 0x0000 +25C, 0x0000 +85C, 0x0000 10 8 6 25 27 29 31 33 35 37 39 RF FREQUENCY (GHz) 41 43 45 17267-093 CONVERSION GAIN (dB) 22 28 26 OUTPUT IP3 (dBm) Figure 88 shows the conversion gain vs. RF frequency at two different Register 0x0A settings, the recommended setting and the default setting, and three different temperatures for IF mode. The default values provides slightly less gain and a larger gain variation across temperature compared to the recommended setting. Figure 90. Output IP3 vs. RF Frequency for Three Different LO Mode Settings, RF Amplitude = -20 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz (Upper Sideband) 4 40 2 0 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) Figure 88. Conversion Gain vs. RF Frequency at Maximum Gain for Various Temperatures and Register 0x0A Settings (Default and Recommended Register 0x0A Settings), fIF = 2 GHz PERFORMANCE BETWEEN DIFFERENTIAL vs. SINGLE-ENDED LO INPUT Figure 89 to Figure 91 show the conversion gain, output IP3, and sideband rejection performance for operating the ADMV1013 LO input as differential vs. single ended. The measurements were performed with 0 dBm LO input power, IF mode, with an IF frequency of 3.5 GHz, upper sideband, and TA = 25C. 28 SINGLE-ENDED POSITIVE SIDE DISABLE SINGLE-ENDED NEGATIVE SIDE DISABLE DIFFERENTIAL 26 24 CONVERSION GAIN (dB) 14 12 10 8 6 4 31 33 35 37 39 RF FREQUENCY (GHz) 41 43 45 17267-092 2 29 10 25 27 29 31 33 35 37 39 RF FREQUENCY (GHz) 41 43 45 Figure 91. Sideband Rejection vs. RF Frequency for Three Different LO Mode Settings, RF Amplitude = -30 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz (Upper Sideband) 18 27 15 23 16 25 20 0 20 23 25 5 22 0 SINGLE-ENDED POSITIVE SIDE DISABLE SINGLE-ENDED NEGATIVE SIDE DISABLE DIFFERENTIAL 30 17267-094 27 SIDEBAND REJECTION (dBc) 25 17267-091 35 23 Figure 89. Conversion Gain vs. RF Frequency for Three Different LO Mode Settings, fIF = 3.5 GHz (Upper Sideband) Rev. B | Page 29 of 39 ADMV1013 Data Sheet The ADMV1013 quadrupler operates from 21.6 GHz to 41 GHz. When using the lower sideband, the conversion gain starts rolling off gradually after the quadrupler frequency reaches 41 GHz. When using the upper sideband, the conversion gain starts rolling off when the quadrupler frequency is 21.6 GHz. Figure 92 and Figure 93 show the conversion gain vs. RF frequency in IF mode for fixed IF frequencies (TA = 25C, LO = 0 dBm) for the upper sideband and lower sideband, respectively. 0.8GHz UPPER SIDEBAND 1GHz UPPER SIDEBAND 2GHz UPPER SIDEBAND 3GHz UPPER SIDEBAND 4GHz UPPER SIDEBAND 26 24 26 24 22 18 I/Q, I/Q, I/Q, I/Q, I/Q, I/Q, I/Q, 16 14 12 10 8 0.8GHz 1GHz 2GHz 3GHz 4GHz 5GHz 6GHz 6 20 4 18 2 16 0 23 14 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) 12 Figure 94. Conversion Gain vs. RF Frequency for Multiple Baseband Frequency Settings (Upper Sideband) 10 8 28 6 5GHz UPPER SIDEBAND 6GHz UPPER SIDEBAND 7GHz UPPER SIDEBAND 26 24 0 23 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) Figure 92. Conversion Gain vs. RF Frequency for Multiple IF Frequency Settings (Upper Sideband) 28 0.8GHz LOWER SIDEBAND 1GHz LOWER SIDEBAND 2GHz LOWER SIDEBAND 3GHz LOWER SIDEBAND 4GHz LOWER SIDEBAND 26 24 22 22 CONVERSION GAIN (dB) 2 17267-095 4 CONVERSION GAIN (dB) 20 20 18 I/Q, I/Q, I/Q, I/Q, I/Q, I/Q, I/Q, 16 14 12 10 8 0.8GHz 1GHz 2GHz 3GHz 4GHz 5GHz 6GHz 6 20 4 18 2 16 0 23 14 25 27 29 31 33 35 37 RF FREQUENCY (GHz) 12 39 41 43 45 17267-098 CONVERSION GAIN (dB) 22 28 17267-097 28 Figure 94 and Figure 95 show the conversion gain vs. RF frequency in I/Q mode for multiple baseband (BB) frequencies (TA = 25C, LO = 0 dBm) for upper sideband and lower sideband, respectively. CONVERSION GAIN (dB) PERFORMANCE ACROSS RF FREQUENCY AT FIXED INPUT FREQUENCIES Figure 95. Conversion Gain vs. RF Frequency at Multiple Baseband Frequency Settings (Lower Sideband) 10 8 6 2 0 23 25 27 29 31 33 35 37 RF FREQUENCY (GHz) 39 41 43 45 17267-096 5GHz LOWER SIDEBAND 6GHz LOWER SIDEBAND 7GHz LOWER SIDEBAND 4 Figure 93. Conversion Gain vs. RF Frequency at Multiple IF Frequency Settings (Lower Sideband) Rev. B | Page 30 of 39 Data Sheet ADMV1013 PERFORMANCE ACROSS COMMON-MODE VOLTAGE IN I/Q MODE OPERATING VCTRL1 AND VCTRL2 INDEPENDENTLY Figure 96, Figure 97, and Figure 98 show the performance at various common-mode voltages in I/Q mode. For each common-mode voltage, the mixer gate voltage was changed based on the equation described in the Baseband Quadrature Modulation (I/Q Mode) section. 30 Figure 99, Figure 102, and Figure 105 show the conversion gain, input IP3, and noise figure vs. the RF frequency, respectively (IF = 2 GHz, upper sideband, LO = 0 dBm at TA = 25C), when VCTRL1 is equal to VCTRL2. 25 CONVERSION GAIN (dB) The data shown in the Specifications section and the Typical Performance Characteristics section is based on the VCTRL1 and VCTRL2 voltages being equal. Finer gain regulation can be obtained if VCTRL1 and VCTRL2 are used separately. Operating VCTRL1 and VCTRL2 also allows either maintaining IP3 or noise figure performance while attenuating the RF output. 20 Figure 100, Figure 103, and Figure 106 show the conversion gain, input IP3, and noise figure vs. the RF frequency, respectively (IF = 2 GHz, upper sideband, LO = 0 dBm at TA = 25C), when VCTRL2 is held at a minimum attenuation and VCTRL1 is changed. 0V 0.4V 1.0V 1.2V 1.4V 1.8V 2.0V 2.4V 2.6V 15 10 0 23 25 27 29 31 33 35 37 39 RF FREQUENCY (GHz) 41 43 45 17267-099 5 Figure 96. Conversion Gain vs. RF Frequency at Multiple Common-Mode Voltages in I/Q Mode (fBB = 100 MHz, LO = 0 dBm, TA = 25C) Figure 101, Figure 104, and Figure 107 show the conversion gain, input IP3, and noise figure vs. the RF frequency, respectively (IF = 2 GHz, upper sideband, LO = 0 dBm at TA = 25C), when VCTRL1 is held at minimum attenuation and VCTRL2 is changed. 30 28 20 26 24 CONVERSION GAIN (dB) 10 20 0V 0.4V 1.0V 1.2V 1.4V 1.8V 2.0V 2.4V 2.6V 18 16 14 12 10 0 -10 -20 VCTRL1 = 0V, VCTRL2 = 0V VCTRL1 = 0.1V, VCTRL2 = 0.1V VCTRL1 = 0.2V, VCTRL2 = 0.2V VCTRL1 = 0.3V, VCTRL2 = 0.3V VCTRL1 = 0.4V, VCTRL2 = 0.4V VCTRL1 = 0.5V, VCTRL2 = 0.5V VCTRL1 = 0.6V, VCTRL2 = 0.6V VCTRL1 = 0.7V, VCTRL2 = 0.7V VCTRL1 = 0.8V, VCTRL2 = 0.8V VCTRL1 = 0.9V, VCTRL2 = 0.9V VCTRL1 = 1.0V, VCTRL2 = 1.0V VCTRL1 = 1.1V, VCTRL2 = 1.1V -30 -40 8 6 -50 4 2 VCTRL1 = 1.2V, VCTRL2 = 1.2V VCTRL1 = 1.3V, VCTRL2 = 1.3V VCTRL1 = 1.4V, VCTRL2 = 1.4V VCTRL1 = 1.5V, VCTRL2 = 1.5V VCTRL1 = 1.6V, VCTRL2 = 1.6V VCTRL1 = 1.7V, VCTRL2 = 1.7V VCTRL1 = 1.8V, VCTRL2 = 1.8V -60 23 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) 23 17267-100 0 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) Figure 97. Output IP3 vs. RF Frequency at Multiple Common-Mode Voltages in I/Q Mode (fBB = 100 MHz, LO = 0 dBm, TA = 25C) 17267-102 OUTPUT IP3 (dBm) 22 Figure 99. Conversion Gain vs. RF Frequency at Various VCTRL Voltages (VCTRL1 = VCTRL2), IF Mode, IF Frequency = 2 GHz, Upper Sideband 30 20 18 20 14 12 10 0V 0.2V 0.4V 0.6V 0.8V 1.0V 1.2V 8 6 4 1.4V 1.6V 1.8V 2.0V 2.2V 2.4V 2.6V 10 0 VCTRL1 = 0V VCTRL1 = 0.1V VCTRL1 = 0.2V VCTRL1 = 0.3V VCTRL1 = 0.4V VCTRL1 = 0.5V VCTRL1 = 0.6V VCTRL1 = 0.7V VCTRL1 = 0.8V VCTRL1 = 0.9V VCTRL1 = 1.0V VCTRL1 = 1.1V -10 -20 -30 2 VCTRL1 = 1.2V VCTRL1 = 1.3V VCTRL1 = 1.4V VCTRL1 = 1.5V VCTRL1 = 1.6V VCTRL1 = 1.7V VCTRL1 = 1.8V 23 25 27 29 31 33 35 37 RF FREQUENCY (GHz) 39 41 43 45 17267-101 -40 0 23 25 27 29 31 33 35 37 RF FREQUENCY (GHz) Figure 98. Output P1dB vs. RF Frequency at Multiple Common-Mode Voltages in I/Q Mode (fBB = 100 MHz, LO = 0 dBm, TA = 25C) 39 41 43 45 17267-103 CONVERSION GAIN (dB) OUTPUT P1dB (dBm) 16 Figure 100. Conversion Gain vs. RF Frequency at Various VCTRL1 Voltages (VCTRL2 = 1.8 V), IF Mode, IF Frequency = 2 GHz, Upper Sideband Rev. B | Page 31 of 39 ADMV1013 Data Sheet 30 20 15 0 VCTRL2 = 0V VCTRL2 = 0.1V VCTRL2 = 0.2V VCTRL2 = 0.3V VCTRL2 = 0.4V VCTRL2 = 0.5V VCTRL2 = 0.6V VCTRL2 = 0.7V VCTRL2 = 0.8V VCTRL2 = 0.9V VCTRL2 = 1.0V VCTRL2 = 1.1V -10 -20 -30 VCTRL2 = 1.2V VCTRL2 = 1.3V VCTRL2 = 1.4V VCTRL2 = 1.5V VCTRL2 = 1.6V VCTRL2 = 1.7V VCTRL2 = 1.8V 25 27 29 31 33 5 VCTRL2 = 0V VCTRL2 = 0.1V VCTRL2 = 0.2V VCTRL2 = 0.3V VCTRL2 = 0.4V VCTRL2 = 0.5V VCTRL2 = 0.6V VCTRL2 = 0.7V VCTRL2 = 0.8V 0 -5 -40 23 10 35 37 39 41 43 45 RF FREQUENCY (GHz) Figure 101. Conversion Gain vs. RF Frequency at Various VCTRL2 Voltages (VCTRL1 = 1.8 V), IF Mode, IF Frequency = 2 GHz, Upper Sideband VCTRL2 = 0.9V VCTRL2 = 1.0V VCTRL2 = 1.1V VCTRL2 = 1.2V VCTRL2 = 1.3V VCTRL2 = 1.4V VCTRL2 = 1.5V VCTRL2 = 1.6V VCTRL2 = 1.7V VCTRL2 = 1.8V -10 23 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz) 17267-117 INPUT IP3 (dBm) 10 17267-104 CONVERSION GAIN (dB) 20 Figure 104. Input IP3 vs. RF Frequency at Various VCTRL2 Voltages (VCTRL1 = 1.8 V), IF Mode, IF Frequency = 2 GHz, Upper Sideband 60 20 55 50 15 VCTRL1 = 0V, VCTRL2 = 0V VCTRL1 = 0.1V, VCTRL2 = 0.1V VCTRL1 = 0.2V, VCTRL2 = 0.2V VCTRL1 = 0.3V, VCTRL2 = 0.3V VCTRL1 = 0.4V, VCTRL2 = 0.4V VCTRL1 = 0.5V, VCTRL2 = 0.5V VCTRL1 = 0.6V, VCTRL2 = 0.6V VCTRL1 = 0.7V, VCTRL2 = 0.7V VCTRL1 = 0.8V, VCTRL2 = 0.8V -5 VCTRL1 = 0.9V, VCTRL2 = 0.9V VCTRL1 = 1.0V, VCTRL2 = 1.0V VCTRL1 = 1.1V, VCTRL2 = 1.1V VCTRL1 = 1.2V, VCTRL2 = 1.2V VCTRL1 = 1.3V, VCTRL2 = 1.3V VCTRL1 = 1.4V, VCTRL2 = 1.4V VCTRL1 = 1.5V, VCTRL2 = 1.5V VCTRL1 = 1.6V, VCTRL2 = 1.6V VCTRL1 = 1.7V, VCTRL2 = 1.7V VCTRL1 = 1.8V, VCTRL2 = 1.8V 25 27 29 31 33 35 37 39 41 30 25 20 VCTRL1 = 0V, VCTRL2 = 0V VCTRL1 = 0.1V, VCTRL2 = 0.1V VCTRL1 = 0.2V, VCTRL2 = 0.2V VCTRL1 = 0.3V, VCTRL2 = 0.3V VCTRL1 = 0.4V, VCTRL2 = 0.4V VCTRL1 = 0.5V, VCTRL2 = 0.5V VCTRL1 = 0.6V, VCTRL2 = 0.6V VCTRL1 = 0.7V, VCTRL2 = 0.7V VCTRL1 = 0.8V, VCTRL2 = 0.8V 15 10 5 -10 23 35 43 45 RF FREQUENCY (GHz) Figure 102. Input IP3 vs. RF Frequency at Various VCTRL Voltages (VCTRL1 = VCTRL2), I IF Mode, IF Frequency = 2 GHz, Upper Sideband 0 23 25 27 29 60 VCTRL1 = 0V VCTRL1 = 0.1V VCTRL1 = 0.2V VCTRL1 = 0.3V VCTRL1 = 0.4V VCTRL1 = 0.5V VCTRL1 = 0.6V VCTRL1 = 0.7V VCTRL1 = 0.8V 55 50 15 NOISE FIGURE (dB) 0 VCTRL1 = 0V, VCTRL1 = 0.1V VCTRL1 = 0.2V VCTRL1 = 0.3V VCTRL1 = 0.4V VCTRL1 = 0.5V VCTRL1 = 0.6V VCTRL1 = 0.7V VCTRL1 = 0.8V -5 VCTRL1 = 0.9V VCTRL1 = 1.0V VCTRL1 = 1.1V VCTRL1 = 1.2V VCTRL1 = 1.3V VCTRL1 = 1.4V VCTRL1 = 1.5V VCTRL1 = 1.6V VCTRL1 = 1.7V VCTRL1 = 1.8V 25 27 29 31 33 43 45 40 VCTRL1 = 0.9V VCTRL1 = 1.0V VCTRL1 = 1.1V VCTRL1 = 1.2V VCTRL1 = 1.3V VCTRL1 = 1.4V VCTRL1 = 1.5V VCTRL1 = 1.6V VCTRL1 = 1.7V VCTRL1 = 1.8V 35 30 25 20 10 5 0 -10 23 41 15 35 37 RF FREQUENCY (GHz) 39 41 43 45 17267-116 INPUT IP3 (dBm) 45 5 31 33 35 37 39 RF FREQUENCY (GHz) Figure 105. Noise Figure vs. RF Frequency at Various VCTRL Voltages (VCTRL1 = VCTRL2), IF Mode, IF Frequency = 2 GHz, Upper Sideband 20 10 VCTRL1 = 0.9V, VCTRL2 = 0.9V VCTRL1 = 1.0V, VCTRL2 = 1.0V VCTRL1 = 1.1V, VCTRL2 = 1.1V VCTRL1 = 1.2V, VCTRL2 = 1.2V VCTRL1 = 1.3V, VCTRL2 = 1.3V VCTRL1 = 1.4V, VCTRL2 = 1.4V VCTRL1 = 1.5V, VCTRL2 = 1.5V VCTRL1 = 1.6V, VCTRL2 = 1.6V VCTRL1 = 1.7V, VCTRL2 = 1.7V VCTRL1 = 1.8V, VCTRL2 = 1.8V Figure 103. Input IP3 vs. RF Frequency at Various VCTRL1 Voltages (VCTRL2 = 1.8 V), IF Mode, IF Frequency = 2 GHz, Upper Sideband 23 25 27 29 31 33 35 37 39 RF FREQUENCY (GHz) 41 43 45 17267-119 0 40 17267-118 NOISE FIGURE (dB) 5 17267-115 INPUT IP3 (dBm) 45 10 Figure 106. Noise Figure vs. RF Frequency at Various VCTRL1 Voltages (VCTRL2 = 1.8 V), IF Mode, IF Frequency = 2 GHz, Upper Sideband Rev. B | Page 32 of 39 Data Sheet ADMV1013 60 55 VCTRL2 = 0V VCTRL2 = 0.1V VCTRL2 = 0.2V VCTRL2 = 0.3V VCTRL2 = 0.4V VCTRL2 = 0.5V VCTRL2 = 0.6V VCTRL2 = 0.7V VCTRL2 = 0.8V 50 NOISE FIGURE (dB) 45 40 35 VCTRL2 = 0.9V VCTRL2 = 1.0V VCTRL2 = 1.1V VCTRL2 = 1.2V VCTRL2 = 1.3V VCTRL2 = 1.4V VCTRL2 = 1.5V VCTRL2 = 1.6V VCTRL2 = 1.7V VCTRL2 = 1.8V 30 25 20 15 10 0 23 25 27 29 31 33 35 37 RF FREQUENCY (GHz) 39 41 43 45 17267-120 5 Figure 107. Noise Figure vs. RF Frequency at Various VCTRL2 Voltages (VCTRL1 = 1.8 V), IF Mode, IF Frequency = 2 GHz, Upper Sideband Solder the exposed pad on the underside of the ADMV1013 to a low thermal and electrical impedance ground plane. This pad is typically soldered to an exposed opening in the solder mask on the evaluation board. Connect these ground vias to all other ground layers on the evaluation board to maximize heat dissipation from the device package. 17267-126 RECOMMENDED LAND PATTERN Figure 108. Evaluation Board Layout for the LGA Package EVALUATION BOARD INFORMATION For more information about the ADMV1013 evaluation board, refer to the ADMV1013-EVALZ user guide. Rev. B | Page 33 of 39 ADMV1013 Data Sheet REGISTER SUMMARY Table 6. Bit 15 Bit 7 PARITY_EN Bit 14 Bit 6 SPI_SOFT_ RESET Bit 13 Bit 5 Bit 12 Bit 4 RESERVED Reg. (Hex) 00 Register Name SPI_CONTROL Bits [15:8] 01 ALARM [7:0] [15:8] 02 ALARM_MASKS [7:0] [15:8] 03 ENABLE 05 LO_AMP_I 06 LO_AMP_Q [15:8] [7:0] 07 OFFSET_ADJUST_I [15:8] MXER_OFF_ADJ_I_P 08 OFFSET_ADJUST_Q [7:0] [15:8] MXER_OFF_ADJ_I_N MXER_OFF_ADJ_Q_P 09 QUAD 0A VVA_TEMPERATURE_ COMPENSATION [7:0] [15:8] [7:0] [15:8] [7:0] [7:0] [15:8] [7:0] [15:8] [7:0] PARITY_ ERROR CHIP_ID TOO_FEW_ TOO_MANY_ ERRORS ERRORS PARITY_ ERROR_ MASK TOO_FEW_ ERRORS_ MASK VGA_PD MIXER_PD MIXER_IF_EN RESERVED RESERVED LOAMP_ PH_ADJ_ I_FINE RESERVED LOAMP_ PH_ADJ_ Q_FINE QUAD_SE_MODE Bit 11 Bit 3 Bit 10 Bit 2 Bit 9 Bit 1 CHIP_ID Bit 8 Bit 0 REVISION ADDRESS_ RESERVED RANGE_ ERROR RESERVED TOO_MANY_ ADDRESS_ RESERVED ERRORS_ RANGE_ MASK ERROR_MASK RESERVED QUAD_PD BG_PD RESERVED DET_EN RESERVED LOAMP_PH_ADJ_I_FINE MIXER_VGATE LOAMP_PH_ADJ_Q_FINE RESERVED MXER_OFF_ADJ_Q_N[5:0] RESERVED RESERVED VVA_TEMPERATURE_COMPENSATION VVA_TEMPERATURE_COMPENSATION Rev. B | Page 34 of 39 MXER_OFF_ ADJ_I_N RESERVED MXER_OFF_ ADJ_Q_N RESERVED QUAD_SE_MODE QUAD_FILTERS Reset 0x00A4 R/W R/W 0x0000 R 0xFFFF R/W 0x01D7 R/W 0x5051 R/W 0x5000 R/W 0xFFFC R/W 0xFFFC R/W 0x5700 R/W 0x0000 R/W Data Sheet ADMV1013 REGISTER DETAILS Address: 0x00, Reset: 0x00A4, Name: SPI_CONTROL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 [15] PARITY_EN (R/W) Enable the Parity for Write Execution [3:0] REVISION (R) Revision ID [14] SPI_SOFT_RESET (R/W) SPI Soft Reset [11:4] CHIP_ID (R) Chip ID [13:12] RESERVED Table 7. Bit Descriptions for SPI_CONTROL Bits 15 14 [13:12] [11:4] [3:0] Bit Name PARITY_EN SPI_SOFT_RESET RESERVED CHIP_ID REVISION Settings Description Enable the Parity for Write Execution SPI Soft Reset Reserved Chip ID Revision ID Reset 0x0 0x0 0x0 0xA 0x4 Access R/W R/W R R R Address: 0x01, Reset: 0x0000, Name: ALARM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [15] PARITY_ERROR (R) Parity Error [11:0] RESERVED [12] ADDRESS_RANGE_ERROR (R) Address Range Error [14] TOO_FEW_ERRORS (R) Too Few Errors [13] TOO_MANY_ERRORS (R) Too Many Errors Table 8. Bit Descriptions for ALARM Bits 15 14 13 12 [11:0] Bit Name PARITY_ERROR TOO_FEW_ERRORS TOO_MANY_ERRORS ADDRESS_RANGE_ERRO R RESERVED Settings Description Parity Error Too Few Errors Too Many Errors Address Range Error Reset 0x0 0x0 0x0 0x0 Access R R R R Reserved 0x0 R Reset 0x1 0x1 0x1 0x1 0xFFF Access R/W R/W R/W R/W R Address: 0x02, Reset: 0xFFFF, Name: ALARM_MASKS 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 [15] PARITY_ERROR_MASK (R/W) Parity Error Mask [11:0] RESERVED [12] ADDRESS_RANGE_ERROR_MASK (R/W) Address Range Error Mask [14] TOO_FEW_ERRORS_MASK (R/W) Too Few Errors Mask [13] TOO_MANY_ERRORS_MASK (R/W) Too Many Errors Mask Table 9. Bit Descriptions for ALARM_MASKS Bits 15 14 13 12 [11:0] Bit Name PARITY_ERROR_MASK TOO_FEW_ERRORS_MASK TOO_MANY_ERRORS_MASK ADDRESS_RANGE_ERROR_MASK RESERVED Settings Description Parity Error Mask Too Few Errors Mask Too Many Errors Mask Address Range Error Mask Reserved Rev. B | Page 35 of 39 ADMV1013 Data Sheet Address: 0x03, Reset: 0x01D7, Name: ENABLE 15 14 13 12 11 10 6 7 8 9 3 4 5 2 1 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 1 [15] VGA_PD (R/W) Power Down the VGA Circuit [4:0] RESERVED [5] DET_EN (R/W) Enable the Envelope Detector [14] MIXER_PD (R/W) Power Down the Mixer Circuit [6] RESERVED [13:11] QUAD_PD (R/W) Power Down the Quad 0: Enable LO Quad Circuit. 111: Disable LO Quad Circuit. [7] MIXER_IF_EN (R/W) Enable the IF Mode [10] BG_PD (R/W) Power Down the Transmitter Band Gap [9:8] RESERVED Table 10. Bit Descriptions for ENABLE Bits 15 14 [13:11] Bit Name VGA_PD MIXER_PD QUAD_PD Settings Description Power Down the VGA Circuit Power Down the Mixer Circuit Power Down the Quad Enable LO Quad Circuit Disable LO Quad Circuit Power Down the Transmitter Band Gap Reserved Enable the IF Mode Reserved Enable the Envelope Detector Reserved 000 111 10 [9:8] 7 6 5 [4:0] BG_PD RESERVED MIXER_IF_EN RESERVED DET_EN RESERVED Reset 0x0 0x0 0x0 Access R/W R/W R/W 0x0 0x0 0x1 0x1 0x0 0x17 R/W R R/W R R/W R Address: 0x05, Reset: 0x5051, Name: LO_AMP_I 15 14 13 12 11 10 9 8 5 6 7 4 3 2 1 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 0 1 [15:14] RESERVED [6:0] MIXER_VGATE (R/W) Control Mixer Gate Voltage. For 0 V to 1.8 V, MIXER_VGATE = 23.89 x Common-Mode Voltage +81, and for 1.8 V to 2.6 V, MIXER_VGATE = 23.75 x Common-Mode Voltage +1.25. [13:7] LOAMP_PH_ADJ_I_FINE (R/W) Mixer Image Rejection Calibration Table 11. Bit Descriptions for LO_AMP_I Bits [15:14] [13:7] [6:0] Bit Name RESERVED LOAMP_PH_ADJ_I_FINE MIXER_VGATE Settings Description Reserved. Mixer Image Rejection Calibration. Control Mixer Gate Voltage. For 0 V to 1.8 V, MIXER_VGATE = 23.89 x Common-Mode Voltage + 81, and for 1.8 V to 2.6 V, MIXER_VGATE = 23.75 x Common-Mode Voltage + 1.25. Reset 0x1 0x20 0x51 Access R R/W R/W Address: 0x06, Reset: 0x5000, Name: LO_AMP_Q 15 14 13 12 0 1 0 1 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 [15:14] RESERVED [6:0] RESERVED [13:7] LOAMP_PH_ADJ_Q_FINE (R/W) Mixer Im age Rejection Calibration Table 12. Bit Descriptions for LO_AMP_Q Bits [15:14] [13:7] [6:0] Bit Name RESERVED LOAMP_PH_ADJ_Q_FINE RESERVED Settings Description Reserved Mixer Image Rejection Calibration Reserved Rev. B | Page 36 of 39 Reset 0x1 0x20 0x0 Access R R/W R Data Sheet ADMV1013 Address: 0x07, Reset: 0xFFFC, Name: OFFSET_ADJUST_I 11 10 15 14 13 12 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 [15:9] MXER_OFF_ADJ_I_P (R/W) LO Feedthrough Offset Calibration I Positive for IF Mode [1:0] RESERVED [8:2] MXER_OFF_ADJ_I_N (R/W) LO Feedthrough Offset Calibration I Negative for IF Mode Table 13. Bit Descriptions for OFFSET_ADJUST_I Bits [15:9] [8:2] [1:0] Bit Name MXER_OFF_ADJ_I_P MXER_OFF_ADJ_I_N RESERVED Settings Description LO Feedthrough Offset Calibration I Positive for IF Mode LO Feedthrough Offset Calibration I Negative for IF Mode Reserved Reset 0x7F 0x7F 0x0 Access R/W R/W R Address: 0x08, Reset: 0xFFFC, Name: OFFSET_ADJUST_Q 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 [15:9] MXER_OFF_ADJ_Q_P (R/W) LO Feedthrough Offset Calibration Q Positive for IF Mode [1:0] RESERVED [8:2] MXER_OFF_ADJ_Q_N (R/W) LO Feedthrough Offset Calibration Q Negative for IF Mode Table 14. Bit Descriptions for OFFSET_ADJUST_Q Bits [15:9] [8:2] [1:0] Bit Name MXER_OFF_ADJ_Q_P MXER_OFF_ADJ_Q_N RESERVED Settings Description LO Feedthrough Offset Calibration Q Positive for IF Mode LO Feedthrough Offset Calibration Q Negative for IF Mode Reserved Reset 0x7F 0x7F 0x0 Access R/W R/W R Address: 0x09, Reset: 0x5700, Name: QUAD 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 [15:10] RESERVED [9:6] QUAD_SE_MODE (R/W) Switch Differential/Single-Ended Modes 0110: Single Ended Mode, N Side Disable. 1001: Single Ended Mode, P Side Disable. 1100: Differential Mode. [3:0] QUAD_FILTERS (R/W) LO Filters Bandwidth Selection 0000: LO Frequency Bandwidth: 8.62 GHz to 10.25 GHz. 0101: LO Frequency Bandwidth: 6.6 GHz to 9.2 GHz. 1010: LO Frequency Bandwidth: 5.4 GHz to 8 GHz. 1111: LO Frequency Bandwidth: 5.4 GHz to 7 GHz. [5:4] RESERVED Table 15. Bit Descriptions for QUAD Bits [15:10] [9:6] Bit Name RESERVED QUAD_SE_MODE Settings 0110 1001 1100 [5:4] [3:0] RESERVED QUAD_FILTERS 0000 0101 1010 1111 Description Reserved. Switch Differential/Single-Ended Modes. Single-Ended Mode, Negative Side Disable. Single-Ended Mode, Positive Side Disable. Differential Mode. Reserved. LO Filters Bandwidth Selection. LO Frequency Bandwidth: 8.62 GHz to 10.25 GHz. LO Frequency Bandwidth: 6.6 GHz to 9.2 GHz. LO Frequency Bandwidth: 5.4 GHz to 8 GHz. LO Frequency Bandwidth: 5.4 GHz to 7 GHz. Rev. B | Page 37 of 39 Reset 0x15 0xC Access R R/W 0x0 0x0 R R/W ADMV1013 Data Sheet Address: 0x0A, Reset: 0x0000, Name: VVA_TEMPERATURE_COMPENSATION 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [15:0] VVA_TEMPERATURE_COMPENSATION (R/W) VVA Temperature Compensation. PARITY_EN must be disabled when updating the VVA temperature compensation Table 16. Bit Descriptions for VVA_TEMPERATURE_COMPENSATION Bits [15:0] Bit Name VVA_TEMPERATURE_COMPENSATION Settings Description VVA Temperature Compensation. PARITY_EN must be disabled when updating the VVA temperature compensation. Set to 0xE700 on startup. Rev. B | Page 38 of 39 Reset 0x0 Access R/W Data Sheet ADMV1013 OUTLINE DIMENSIONS 6.10 6.00 5.90 PIN 1 CORNER AREA 0.40 0.35 0.30 0.32 0.27 0.22 1.06 BSC SQ PIN 1 INDICATOR 40 31 1 30 4.50 REF SQ 4.77 BSC 2.22 BSC SQ 0.50 BSC 21 10 20 PKG-005728 0.75 MAX 0.67 NOM SIDE VIEW 0.52 0.45 0.38 0.25 0.22 0.19 SEATING PLANE 11 BOTTOM VIEW 0.275 BSC 0.165 BSC FOR PROPER CONNECTION OF THE EXPOSED PADS, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 02-12-2018-A 0.750 BSC TOP VIEW Figure 109. 40-Terminal Land Grid Array Package [LGA] 6 mm x 6 mm Body and 0.67 mm Package Height (CC-40-5) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADMV1013ACCZ ADMV1013ACCZ-R7 ADMV1013-EVALZ 1 Temperature Range -40C to +85C -40C to +85C Package Description 40-Terminal Land Grid Array Package [LGA] 40-Terminal Land Grid Array Package [LGA] Evaluation Board Z = RoHS Compliant Part. (c)2018-2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D17267-0-9/19(B) Rev. B | Page 39 of 39 Package Option CC-40-5 CC-40-5