24 GHz to 44 GHz,
Wideband, Microwave Upconverter
Data Sheet
ADMV1013
Rev. B Document Feedback
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FEATURES
Wideband RF input frequency range: 24 GHz to 44 GHz
2 upconversion modes
Direct conversion from baseband I/Q to RF
Single-sideband upconversion from real IF
LO input frequency range: 5.4 GHz to 10.25 GHz
LO quadrupler for up to 41 GHz
Matched 50 Ω single-ended RF output and IF inputs
Option between matched 100 Ω balanced or 50 Ω single-
ended LO inputs
100 Ω balanced baseband inputs
Sideband suppression and carrier feedthrough optimization
Variable attenuator for transceiver power control
Programmable via 4-wire SPI interface
40-terminal land grid array package (LGA)
APPLICATIONS
Point to point microwave radios
Radar, electronic warfare systems
Instrumentation, automatic test equipment (ATE)
FUNCTIONAL BLOCK DIAGRAM
90°
DVDD
GND
VCC_MIXER
VCC_BG
BG_RBIAS1
VCC_QUAD
GND
LON
LOP
DNC
SENVCC2_DRV
VCC_ENV
DNCVCC_AMP1
SEN2
VCC_AMP2
VCTRL2
VCTRL1
VCC_VVA
DNC
RF
GND
VCC_DRV
BG_RBIAS2
SDO
SDI
SCLK
I_N
VENV_P
VCC_BG2
IF_Q
Q_N
Q_P
GND
I_P
0°
GND VENV_N
×4
ADMV1013
RST IF_I
17267-001
VVA2 VVA1
DET
Figure 1.
GENERAL DESCRIPTION
The ADMV1013 is a wideband, microwave upconverter optimized
for point to point microwave radio designs operating in the
24 GHz to 44 GHz radio frequency (RF) range.
The upconverter offers two modes of frequency translation. The
device is capable of direct conversion to RF from baseband in-phase
quadrature (I/Q) input signals, as well as single-sideband (SSB)
upconversion from complex intermediate frequency (IF) inputs.
The baseband I/Q input path can be disabled and modulated
complex IF signals, anywhere from 0.8 GHz to 6.0 GHz, can be
inserted in the IF path and upconverted to 24 GHz to 44 GHz
while suppressing the unwanted sideband by typically better than
26 dBc. The serial port interface (SPI) allows adjustment of the
quadrature phase and mixer gate voltage to allow optimum
sideband suppression and local oscillator (LO) nulling. In
addition, the SPI interface allows powering down the output
envelope detector to reduce power consumption.
The ADMV1013 upconverter comes in a 40-terminal land grid
array package (LGA) package. The ADMV1013 operates over
the −40°C to +85°C case temperature range.
ADMV1013 Data Sheet
Rev. B | Page 2 of 39
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Serial Port Register Timing ......................................................... 5
Absolute Maximum Ratings ............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 9
I/Q Mode ....................................................................................... 9
IF Mode ........................................................................................ 14
Envelope Detector Performance ............................................... 19
Return Loss and Isolation .......................................................... 21
M × N Spurious Performance ................................................... 24
Theory of Operation ...................................................................... 25
Start-Up Sequence ...................................................................... 25
Baseband Quadrature Modulation (I/Q Mode) ..................... 25
Single-Sideband Upconversion (IF Mode) ............................. 25
LO Input Path ............................................................................. 25
Sideband Suppression Optimization ....................................... 25
Carrier Feedthrough Nulling .................................................... 26
Envelope Detector ...................................................................... 26
Power Down and Reset .............................................................. 26
Serial Port Interface (SPI) ......................................................... 26
Applications Information .............................................................. 28
Baseband Quadrature Modulation from Low Frequencies .. 28
Performance at Different Quad Filter Settings ....................... 28
VVA Temperature Compensation............................................ 28
Performance Between Differential vs. Single-Ended LO Input
....................................................................................................... 29
Performance Across RF Frequency at Fixed Input
Frequencies ................................................................................. 30
Performance Across Common-Mode Voltage in I/Q Mode 31
Operating VCTRL1 and VCTRL2 Independently ..................... 31
Recommended Land Pattern .................................................... 33
Evaluation Board Information ................................................. 33
Register Summary .......................................................................... 34
Register Details ............................................................................... 35
Outline Dimensions ....................................................................... 39
Ordering Guide .......................................................................... 39
REVISION HISTORY
9/2019—Rev. A to Rev. B
Changes to Figure 1 .......................................................................... 1
Changes to Figure 3 and Table 5 ..................................................... 7
4/2019—Rev. 0 to Rev. A
Changes to Figure 1 .......................................................................... 1
Changes to Frequency Ranges Parameter, Table 1 ....................... 3
Changes to Thermal Resistance Section ........................................ 6
Changes to Figure 3 .......................................................................... 7
Changes to Table 5 ............................................................................ 8
Changes to Figure 50 Caption ....................................................... 16
Changes to Figure 58 Caption ...................................................... 18
Change to Return Loss and Isolation Section............................. 21
Moved Figure 70; Renumbered Sequentially .............................. 21
Moved Figure 72 ............................................................................. 22
Moved Figure 77 ............................................................................. 22
Moved Figure 80 ............................................................................. 23
Changes to M × N Spurious Performance Section, I/Q Mode
Section, and IF Mode Section ....................................................... 24
Changes to Start-Up Sequence Section ....................................... 25
12/2018—Revision 0: Initial Version
Data Sheet ADMV1013
Rev. B | Page 3 of 39
SPECIFICATIONS
IF and I/Q amplitude = −20 dBm, VCC_DRV = VCC2_DRV = VCC_AMP2 = VCC_ENV = VCC_AMP1 = VCC_BG2 = VCC_MIXER =
VCC_BG = VCC_QUAD = 3.3 V, DVDD = VCC_VVA = 1.8 V, TA = 25°C, and set Register 0x0A to 0xE700, unless otherwise noted.
Measurements in IF mode performed with a 90° hybrid, Register 0x03, Bit 7 = 1, IF input frequency (fIF) = 3.5 GHz.
Measurements in I/Q mode are measured as a composite of the I and Q channel performance, common-mode voltage (VCM) = 0 V,
Register 0x03, Bit 7 = 0, and Register 0x05, Bits[6:0] = 0x051, unless otherwise noted. I/Q baseband frequency (fBB) = 100 MHz.
VCTRL1 = VCTRL2. VCTRL is the attenuation voltage at the VCTRL1 and VCTRL2 pins. VCTRL =1800 mV, unless otherwise specified.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGES
RF Output 24 44 GHz
LO Input 5.4 10.25 GHz
LO Quadrupler 21.6 41 GHz
IF Input 0.8 6.0 GHz
Baseband (BB) I/Q Input DC 6.0 GHz
LO AMPLITUDE RANGE −6 0 +6 dBm
I/Q MODULATOR PERFORMANCE
Conversion Gain At maximum gain
24 GHz to 40 GHz fBB ≤ 3.5 GHz 18 23 dB
6 GHz > fBB > 3.5 GHz 21
40 GHz to 44 GHz 19 dB
Voltage Variable Attenuator (VVA) Control Range 35 dB
Single-Sideband (SSB) Noise Figure At maximum gain
24 GHz to 40 GHz
18
dB
40 GHz to 44 GHz 19 dB
Output Third-Order Intercept (IP3) At maximum gain
24 GHz to 40 GHz 20 23 dBm
40 GHz to 44 GHz 22 dBm
Output 1 dB Compression Point (P1dB)
At maximum gain
24 GHz to 40 GHz 10 13 dBm
40 GHz to 44 GHz 12 dBm
Sideband Rejection (SBR) 24 GHz to 44 GHz, at maximum gain
Uncalibrated 32 dBc
IF SINGLE-SIDEBAND UPCONVERSION PERFORMANCE
Conversion Gain At maximum gain
24 GHz to 40 GHz fIF ≤ 3.5 GHz 13 18 dB
6 GHz > fIF > 3.5 GHz 12
40 GHz to 44 GHz 14 dB
VVA Control Range 35 dB
SSB Noise Figure At maximum gain
24 GHz to 40 GHz 25 dB
40 GHz to 44 GHz 28 dB
Output IP3
At maximum gain
24 GHz to 40 GHz 20 23 dBm
40 GHz to 44 GHz 22 dBm
Output P1dB At maximum gain
24 GHz to 40 GHz 10 13 dBm
40 GHz to 44 GHz 12 dBm
SBR 24 GHz to 44 GHz, at maximum gain
Uncalibrated 26 dBc
Calibrated Calibrated using LOAMP_PH_ADJ_
Q_FINE and LOAMP_PH_ADJ_I_FINE bits
36 dBc
ADMV1013 Data Sheet
Rev. B | Page 4 of 39
Parameter Test Conditions/Comments Min Typ Max Unit
ENVELOPE DETECTOR PERFORMANCE
Output Level For optimum performance
Minimum −45 dBm
Maximum −20 dBm
Envelope Bandwidth
Measured with two tones with total
power output (POUT) at RF = 10 dBm
3 dB RF frequency (fRF) = 28 GHz 350 MHz
10 dB fRF = 28 GHz 1 GHz
RETURN LOSS
RF Output 50 Ω single-ended −8 dB
LO Input 100 Ω differential −12 dB
IF Input 50 Ω single-ended −12 dB
BB Input 100 Ω differential −10 dB
BB I/Q Input Impedance 100 Ω
LEAKAGE At maximum gain
Fundamental LO to RF −80 dBm
4 × LO to RF
5.4 GHz to 6.8 GHz LO Uncalibrated −12 dBm
6.8 GHz to 10.25 GHz LO Uncalibrated −20 dBm
5.4 GHz to 10.25 GHz LO Calibrated using MXER_OFF_ADJ_I_N,
MXER_OFF_ADJ_I_P, MXER_OFF_
ADJ_Q_N, MXER_OFF_ADJ_Q_P bits at
VCTRL = 1800 mV, IF mode
−45 dBm
5 × LO to RF −55 dBm
Fundamental LO to IF −70 dBm
Fundamental LO to I/Q −75 dBm
LOGIC INPUTS
Input Voltage Range
High, VINH DVDD − 0.4 1.8 V
Low, VINL 0 0.4 V
Input Current, IINH/IINL 100 µA
Input Capacitance, CIN 3 pF
LOGIC OUTPUTS
Output Voltage Range
High, VOH DVDD − 0.4 1.8 V
Low, VOL 0 0.4 V
Output High Current, IOH 500 µA
POWER INTERFACE
VCC_DRV, VCC2_DRV, VCC_AMP2, VCC_ENV,
VCC_AMP1, VCC_BG2, VCC_MIXER, VCC_BG,
VCC_QUAD
3.15 3.3 3.45 V
3.3 V Supply Current VCTRL = 1.8 V, no IF and I/Q or LO input
signal
550 mA
DVDD, VCC_VVA 1.7 1.8 1.9 V
1.8 V Supply Current VCTRL = 1.8 V, no IF and I/Q or LO input
signal
3 mA
Total Power Consumption
1.9
W
Power-Down 77 136 mW
Data Sheet ADMV1013
Rev. B | Page 5 of 39
SERIAL PORT REGISTER TIMING
Table 2.
Parameter Description Min Typ Max Unit
t
SDI, SETUP
Data to clock setup time
10
ns
tSDI, HOLD Data to clock hold time 10 ns
tSCLK, HIGH Clock high duration 40 to 60 %
tSCLK, LOW Clock low duration 40 to 60 %
tSCLK, SEN/SEN2_SETUP
Clock to SEN/SEN2 setup time 30 ns
tSCLK, DOT Clock to data out transition time 10 ns
tSCLK, DOV Clock to data out valid time 10 ns
tSCLK, SEN/SEN2_INACTIVE
Clock to SEN/SEN2 inactive 20 ns
tSEN/SEN2_INACTIVE Inactive SEN/SEN2 (between two operations) 80 ns
Timing Diagram
t
SCLK, LOW
t
SCLK, DOT
SDO
t
SCLK, DOV
SDI
t
SDI, SETUP
t
SDI, HOLD
SCLK
t
SCLK, HIGH
t
SCLK, SEN/ SEN2 _SETU P
t
SCLK, SEN/SEN2 _ INACTIVE
t
SEN/SEN2_INACTIVE
17267-106
SEN/SEN2
Figure 2. Serial Port Register Timing Diagram
ADMV1013 Data Sheet
Rev. B | Page 6 of 39
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Supply Voltage
VCC_DRV, VCC2_DRV, VCC_AMP2,
VCC_ENV, VCC_AMP1, VCC_BG2,
VCC_BG, VCC_MIXER
4.3 V
DVDD, VCC_VVA 2.3 V
IF Input Power 5 dBm
I/Q Input Power 5 dBm
LO Input Power 9 dBm
Maximum Junction Temperature 125°C
Maximum Power Dissipation1 2.9 W
Lifetime at Maximum Junction Temperature (TJ) 1 ×106 hours
Operating Case Temperature Range −40°C to +85°C
Storage Temperature Range −55°C to +125°C
Lead Temperature (Soldering 60 sec) 260°C
Moisture Sensitivity Level (MSL) Rating2 MSL3
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM) 1250 V
Field Induced Charged Device Model
(FICDM)
750 V
1 The maximum power dissipation is a theoretical number calculated by
(TJ − 85°C)/θJC_TOP.
2 Based on IPC/JEDEC J-STD-20 MSL classifications.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC
is the junction to case thermal resistance.
θJA and θJC must only be used to compare the thermal
performance of the different packages if all test conditions
listed are similar to JEDEC specifications. Instead, ѰJT and ѰJB
can be used to calculate the junction temperature of the device
by using the following equations:
TJ = (P × ѰJT) + TTOP (1)
where:
P refers to the total power dissipation in the chip (W).
ѰJT refers to the junction to top thermal characterization
number.
TTOP refers to the package top temperature (°C) and is measured
at the top center of the package.
TJ = (P × ѰJB) + TBOARD (2)
where:
P refers to the total power dissipation in the chip (W).
ѰJB refers to the junction to board thermal characterization
number.
TBOARD refers to the board temperature measured on the
midpoint of the longest side of the package, no more than
1 mm from the edge of the package body (°C).
As stated in JEDEC51-12, Equation 1 and Equation 2 must be
used when no heat sink/heat spreader is present. When a heat
sink/heat spreader is added, estimating and calculating junction
temperature can be achieved using θJC_TOP.
Table 4. Thermal Resistance
Package Type1 θ
JA2 θJC_TOP3 θ
JB4 Ψ
JT5 ΨJB6 Unit
CC-40-5 28 13.8 11.1 6.4 13.8 °C/W
1 The thermal resistance values specified in Table 4 are simulated based on
JEDEC specifications, unless specified otherwise, and must be used in
compliance with JESD51-12.
2 θJA is the junction to ambient thermal resistance in a natural convection,
JEDEC environment.
3 θJC_TOP is the junction to case (top) JEDEC thermal resistance.
4 θJB is the junction to board JEDEC thermal resistance.
5 ΨJT is the junction to top JEDEC thermal characterization parameter.
6 ΨJB is the junction to board JEDEC thermal characterization parameter.
ESD CAUTION
Data Sheet ADMV1013
Rev. B | Page 7 of 39
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADMV1013
TOP VIEW
(No t t o Scal e)
17267-002
RST
1
DVDD
2
SCLK
3
SDI
4
SDO
5
BG_RBIAS2
6
VCC_DRV
7
GND
8
RF
9
GND
10
VENV_N
21
VENV_P
22
VCC_BG2
23
IF_Q
24
Q_N
25
Q_P
26
GND
27
I_P
28
I_N
29
IF_I
30
VCC2_DRV
11
DNC
12
DNC
13
VCC_VVA
14
VCTRL1
15
VCTRL2
16
VCC_AMP2
17
SEN2
18
VCC_ENV
19
VCC_AMP1
20
DNC
31
VCC_MIXER
32
VCC_BG
33
BG_RBIAS1
34
VCC_QUAD
35
GND
36
LON
37
LOP
38
GND
39
SEN
40
NOTES
1. DNC = DO NO T CO NNE CT. DO NO T CO NNE CT T O T HIS PIN.
2. EX P OSE D P AD. SOL DE R THE E X P OSE D P AD TO A LOW I M P E DANCE GRO UND P LANE.
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 RST SPI Reset. Connect this pin to logic high for normal operation. The SPI logic is 1.8 V.
2
DVDD
1.8 V SPI Digital Supply.
3 SCLK SPI Clock Digital Input.
4 SDI SPI Serial Data Input.
5 SDO SPI Serial Data Output.
6 BG_RBIAS2 Voltage Gain Amplifier (VGA) Chip Band Gap Circuit, External High Precision Resistor. Place a 1.1 kΩ,
high precision resistor shunt to ground close to this pin.
7 VCC_DRV 3.3 V Power Supply for RF Driver. Place a 100 pF, a 0.01 µF, and a 10 µF capacitor close to this pin.
8, 10, 27, 36, 39 GND Ground.
9 RF RF Output. This pin is dc-coupled internally to GND and matched to 50 Ω single ended.
11 VCC2_DRV 3.3 V Power Supply for RF Predriver. Place a 100 pF, a 0.01 µF, and a 10 µF capacitor close to this pin.
12, 13, 31 DNC Do Not Connect. Do not connect to this pin.
14
VCC_VVA
1.8 V Power Supply for VVA Control Circuit. Place a 100 pF, 0.01 µF, and a 10 µF capacitor close to this pin.
15 VCTRL1 RF Voltage Variable Attenuator 1 (VVA1) Control Voltage. Place a 1 kΩ series resistor with this pin.
16 VCTRL2 RF Voltage Variable Attenuator 2 (VVA2) Control Voltage. Place a 1 kΩ series resistor with this pin.
17 VCC_AMP2 3.3 V Power Supply for RF Amplifier 2 (AMP2). Place a 100 pF, a 0.01 µF, and a 10 µF capacitor close to
this pin.
18 SEN2 SPI Serial Enable for VGA Chip. Connect this pin with Pin 40 (SEN).
19
VCC_ENV
3.3 V Power Supply for Envelope Detector. Place a 100 pF, a 0.01 µF, and a 10 µF capacitor close to this pin.
20 VCC_AMP1 3.3 V Power Supply for RF Amplifier 1 (AMP1). Place a 100 pF, a 0.01 µF, and a 10 µF capacitor close to
this pin.
21 VENV_N Negative Differential Envelope Detector Output.
22 VENV_P Positive Differential Envelope Detector Output.
23 VCC_BG2 3.3 V Power Supply for VGA Chip Band Gap Circuit. Place a 100 pF, a 0.01 µF, and a 10 µF capacitor
close to this pin.
24, 30 IF_Q, IF_I IF Single-Ended Complex Inputs. These pins are internally ac-coupled. When in IF mode, Pin 25 (Q_P),
Pin 26 (Q_N), Pin 28 (I_P), and Pin 29 (I_N) must be kept floating.
25, 26 Q_N, Q_P Differential Baseband Q Inputs. These pins are dc-coupled. Do not connect these pins in IF mode.
28, 29 I_P, I_N Differential Baseband I Inputs. These pins are dc-coupled. Do not connect these pins in IF mode.
ADMV1013 Data Sheet
Rev. B | Page 8 of 39
Pin No. Mnemonic Description
32 VCC_MIXER 3.3 V Power Supply for Mixer. Place a 100 pF, a 0.01 µF, and a 10 µF capacitor close to this pin.
33 VCC_BG 3.3 V Power Supply for Mixer Chip Band Gap Circuit. Place a 100 pF, a 0.01 µF, and a 10 µF capacitor
close to this pin.
34 BG_RBIAS1 Mixer Chip Band Gap Circuit, External High Precision Resistor. Place a 1.1 kΩ, high precision resistor
shunt to ground close to this pin.
35 VCC_QUAD 3.3 V Power Supply for Quadruppler. Place a 100 pF, a 0.01 µF, and a 10 µF capacitor close to this pin.
37, 38 LON, LOP Negative and Positive Differential Local Oscillator Input. This pin is dc-coupled internally to ground
and matched to 100 Ω differential or 50 Ω single ended. If using the LO as single ended, terminate
the unused LO port with 50 Ω impedance to ground.
40 SEN SPI Serial Enable for Mixer Chip. Connect this pin with Pin 18 (SEN2).
EPAD Exposed Pad. Solder the exposed pad to a low impedance ground plane.
Data Sheet ADMV1013
Rev. B | Page 9 of 39
TYPICAL PERFORMANCE CHARACTERISTICS
I/Q MODE
I/Q amplitude = −20 dBm, VCC_DRV = VCC2_DRV = VCC_AMP2 = VCC_ENV = VCC_AMP1 = VCC_BG2 = VCC_MIXER =
VCC_BG = VCC_QUAD = 3.3 V, DVDD = VCC_VVA = 1.8 V, TA = 25°C, and set Register 0x0A to 0xE700, unless otherwise noted.
VCTRL1 = VCTRL2. VCTRL is the attenuation voltage at the VCTRL1 and VCTRL2 pins. VCTRL = 1800 mV, unless otherwise specified.
Measurements in I/Q mode are measured as a composite of the I and Q channel performance, VCM = 0 V, Register 0x03, Bit 7 = 0, and
Register 0x05, Bits[6:0] = 0x051, unless otherwise noted. I/Q fBB = 100 MHz.
23 25 27 31 35 3929 33 37 41 43 45
RF FREQ UE NCY ( GHz)
35
–50
–20
–30
–10
–5
0
10
30
–25
–35
–40
–45
–15
5
25
20
15
CONVE RS IO N GAI N ( dB)
+8 5° C AT 1 .8V UPP ER SIDEBAND
+2 5° C AT 1 .8V UPP ER SIDEBAND
–40° C AT 1 .8V UPP ER SIDEBAND
+8 5° C AT 0 .8V UPP ER SIDEBAND
+2 5° C AT 0 .8V UPP ER SIDEBAND
–40° C AT 0 .8V UPP ER SIDEBAND
+8 5° C AT 0 V UPPE R SIDEBAND
+2 5° C AT 0 V UPPE R SIDEBAND
–40° C AT 0 V UPPE R SIDEBAND
17267-003
Figure 4. Conversion Gain vs. RF Frequency (fRF) at Three Different Gain
Settings for Various Temperatures, f
BB
= 100 MHz (Upper Sideband)
30
–5
0
5
20
25
15
10
23 25 27 31 35 39
29 33 37 41 43 45
CONVE RS IO N GAI N ( dB)
RF FREQ UE NCY ( GHz)
3.5V UP P E R S IDEBAND
3.3V UP P E R S IDEBAND
3.1V UP P E R S IDEBAND
17267-004
Figure 5. Conversion Gain vs. RF Frequency at for Various Supply
Voltages, f
BB
= 100 MHz (Upper Sideband)
30
–5
0
5
20
25
15
10
23 25 27 31 35 3929 33 37 41 43 45
CONVE RS IO N GAI N ( dB)
RF FREQ UE NCY ( GHz)
+6dBm UP P E R S IDEBAND
0dBm UPP E R S IDEBAND
–6dBm UP PE R S IDEBAND
17267-005
Figure 6. Conversion Gain vs. RF Frequency at for Various LO Inputs,
f
BB
= 100 MHz (Upper Sideband)
30
–30
–15
–25
–5
5
–10
–20
0
10
15
20
25
00.2 0.4 0.8 1.2 1.60.6 1.0 1.4 1.8
CONVE RS IO N GAI N ( dB)
V
CTRL
(V)
+85° C AT 39G Hz
+25° C AT 39G Hz
–40°C AT 9G Hz
+85° C AT 28G Hz
+25° C AT 28G Hz
–40°C AT 28G Hz
17267-006
Figure 7. Conversion Gain vs. VCTRL at Various Temperatures and
f
RF
= 28 GHz and 39 GHz, f
BB
= 100 MHz
28
0
10
2
14
18
12
6
4
8
16
20
22
24
26
00.5 1.0 2.5 4.5 6.51.5 3.5 5.5
2.0 4.0 6.03.0 5.0 7.0
CONVE RS IO N GAI N ( dB)
BASEBAND F RE QUENCY ( GHz)
39GHz UPP E R S IDEBAND
28GHz UPP E R S IDEBAND
17267-007
Figure 8. Conversion Gain vs. Baseband Frequency at
fRF = 28 GHz and 39 GHz (Upper Sideband)
28
0
10
2
14
18
12
6
4
8
16
20
22
24
26
00.5 1.0 2.5 4.5 6.51.5 3.5 5.52.0 4.0 6.03.0 5.0 7.0
CONVE RS IO N GAI N ( dB)
BASEBAND F RE QUENCY ( GHz)
39GHz LOWER S IDEBAND
28GHz LOWER S IDEBAND
17267-008
Figure 9. Conversion Gain vs. Baseband Frequency at
fRF = 28 GHz and 39 GHz (Lower Sideband)
ADMV1013 Data Sheet
Rev. B | Page 10 of 39
23 25 27 31 35 3929 33 37 41 43 45
OUTPUT IP3 ( dBm)
RF FREQ UE NCY ( GHz)
+85° C UP P E R S IDEBAND
+25° C UP P E R S IDEBAND
–40°C UP P E R S IDEBAND
28
0
10
2
14
18
12
6
4
8
16
20
22
24
26
17267-009
Figure 10. Output IP3 vs. RF Frequency at Maximum Gain for
Various Temperatures, RF Amplitude = −20 dBm per Tone at 20 MHz
Spacing, fBB = 100 MHz (Upper Sideband)
23 25 27 31 35 39
29 33 37 41 43 45
OUTPUT IP3 ( dBm)
RF FREQ UE NCY ( GHz)
28
0
10
2
14
18
12
6
4
8
16
20
22
24
26
3.5V UP P E R S IDEBAND
3.3V UP P E R S IDEBAND
3.1V UP P E R S IDEBAND
17267-010
Figure 11. Output IP3 vs. RF Frequency at Maximum Gain for
Supply Voltages, RF Amplitude = −20 dBm per Tone at 20 MHz Spacing,
fBB = 100 MHz (Upper Sideband)
23 25 27 31 35 3929 33 37 41 43 45
OUTPUT IP3 ( dBm)
RF FREQ UE NCY ( GHz)
28
0
10
2
14
18
12
6
4
8
16
20
22
24
26
17267-011
+6dBm UP P E R S IDEBAND
0dBm UPP E R S IDEBAND
–6dBm UP PE R S IDEBAND
Figure 12. Output IP3 vs. RF Frequency at Maximum Gain for
Various LO Inputs, RF Amplitude = −20 dBm per Tone at 20 MHz Spacing,
fBB = 100 MHz (Upper Sideband)
30
–20
0
–10
–5
–15
5
10
15
20
25
00.2 0.4 0.8 1.2 1.60.6 1.0 1.4 1.8
OUTPUT IP3 ( dBm)
V
CTRL
(V)
39GHz UP P E R S IDEBAND
28GHz UP P E R S IDEBAND
17267-012
Figure 13. Output IP3 vs. VCTRL, RF Amplitude = −20 dBm per Tone at
20 MHz Spacing, fBB = 100 MHz at fRF = 28 GHz and 39 GHz (Upper Sideband)
28
0
10
2
14
18
12
6
4
8
16
20
22
24
26
00.5 1.0 2.5 4.5 6.51.5 3.5 5.52.0 4.0 6.0
3.0 5.0 7.0
OUTPUT IP3 ( dBm)
BASEBAND F RE QUENCY ( GHz)
39GHz UPP E R BAS E BAND
28GHz UPP E R BAS E BAND
39GHz LOWER BAS E BAND
28GHz LOWER BAS E BAND
17267-013
Figure 14. Output IP3 vs. Baseband Frequency at fRF = 28 GHz and 39 GHz
at Maximum Gain, RF Amplitude = −20 dBm per Tone at 20 MHz Spacing
(Upper Sideband and Lower Sideband)
24.0
22.2
22.6
23.0
22.4
22.8
23.2
23.4
23.6
23.8
–20 –19 –18 –15 –11–17 –13–16 –12
–14 –10
OUTPUT IP3 ( dBm)
TOTAL INPUT POWER (dBm)
39GHz UPP E R S IDEBAND
28GHz UPP E R S IDEBAND
17267-014
Figure 15. Output IP3 vs. Total Input Power at 20 MHz Spacing,
fBB = 100 MHz, fRF = 28 GHz and 39 GHz (Upper Sideband)
Data Sheet ADMV1013
Rev. B | Page 11 of 39
50
0
5
15
25
10
20
30
35
40
45
NOISE FIGURE (dB)
23 25 27 31 35 3929 33 37 41 43 45
RF FREQ UE NCY ( GHz)
+85° C UP P E R S IDEBAND
+25° C UP P E R S IDEBAND
–40°C UP P E R S IDEBAND
17267-015
Figure 16. Noise Figure vs. RF Frequency at Maximum Gain for
Various Temperatures, fBB = 100 MHz (Upper Sideband)
50
0
5
15
25
10
20
30
35
40
45
NOISE FIGURE (dB)
23 25 27 31 35 3929 33 37 41 43 45
RF FREQ UE NCY ( GHz)
3.5V UP P E R S IDEBAND
3.3V UP P E R S IDEBAND
3.1V UP P E R S IDEBAND
17267-016
Figure 17. Noise Figure vs. RF Frequency for Various Supply Voltages,
fBB = 100 MHz (Upper Sideband)
50
0
5
15
25
10
20
30
35
40
45
NOISE FIGURE (dB)
23 25 27 31 35 39
29 33 37 41 43 45
RF FREQ UE NCY ( GHz)
+6dBm UP P E R S IDEBAND
0dBm UPP E R S IDEBAND
–6dBm UP PE R S IDEBAND
17267-017
Figure 18. Noise Figure vs. RF Frequency for Various LO Inputs, fBB = 100 MHz
(Upper Sideband)
45
0
15
10
5
20
25
30
35
40
00.2 0.4 0.8 1.2 1.60.6 1.0 1.4 1.8
NOISE FIGURE (dB)
V
CTRL
(V)
+85° C AT 39G Hz
+25° C AT 39G Hz
–40°C AT 39G Hz
+85° C AT 28G Hz
+25° C AT 28G Hz
–40°C AT 28G Hz
17267-018
Figure 19. Noise Figure vs. VCTRL for Various Temperatures at
fRF = 28 GHz 39 GHz, fBB = 100 MHz
50
0
5
15
25
10
20
30
35
40
45
00.5 1.0 2.5 4.5 6.51.5 3.5 5.52.0 4.0 6.03.0 5.0 7.0
NOISE FIGURE (dB)
BASEBAND F RE QUENCY ( GHz)
39GHz UPP E R S IDEBAND
28GHz UPP E R S IDEBAND
17267-019
Figure 20. Noise Figure vs. Baseband Frequency at
fRF = 28 GHz and 39 GHz (Upper Sideband)
50
0
5
15
25
10
20
30
35
40
45
00.5 1.0 2.5 4.5 6.51.5 3.5 5.52.0 4.0 6.03.0 5.0 7.0
NOISE FIGURE (dB)
BASEBAND F RE QUENCY ( GHz)
39GHz LOWER S IDEBAND
28GHz LOWER S IDEBAND
17267-020
Figure 21. Noise Figure vs. Baseband Frequency at
fRF = 28 GHz and 39 GHz (Lower Sideband)
ADMV1013 Data Sheet
Rev. B | Page 12 of 39
45
0
15
10
5
20
25
30
35
40
SIDE BAND RE JE CTI ON (dBc)
23 25 27 31 35 3929 33 37 41 43 45
RF FREQ UE NCY ( GHz)
+85° C UP P E R S IDEBAND
+25° C UP P E R S IDEBAND
–40°C UP P E R S IDEBAND
17267-021
Figure 22. Sideband Rejection vs. RF Frequency at Maximum Gain for
Various Temperatures, fBB = 100 MHz (Upper Sideband)
45
0
15
10
5
20
25
30
35
40
SIDE BAND RE JE CTI ON (dBc)
23 25 27 31 35 3929 33 37 41 43 45
RF FREQ UE NCY ( GHz)
3.5V UP P E R S IDEBAND
3.3V UP P E R S IDEBAND
3.1V UP P E R S IDEBAND
17267-023
Figure 23. Sideband Rejection vs. RF Frequency at for Various Supply
Voltages, fBB = 100 MHz (Upper Sideband)
45
–5
0
15
10
5
20
25
30
35
40
SIDE BAND RE JE CTI ON (dBc)
23 25 27 31 35 3929 33 37 41 43 45
RF FREQ UE NCY ( GHz)
+6dBm UP P E R S IDEBAND
0dBm UPP E R S IDEBAND
–6dBm UP PE R S IDEBAND
17267-024
Figure 24. Sideband Rejection vs. RF Frequency for Various LO Inputs,
fBB = 100 MHz (Upper Sideband)
45
0
15
10
5
20
25
30
35
40
SIDE BAND RE JE CTI ON (dBc)
00.2 0.4 0.8 1.2 1.60.6 1.0 1.4 1.8
V
CTRL
(V)
+85° C AT 39G Hz
+25° C AT 39G Hz
–40°C AT 39G Hz
+85° C AT 28G Hz
+25° C AT 28G Hz
–40°C AT 28G Hz
17267-025
Figure 25. Sideband Rejection vs. VCTRL for Various Temperatures at
fRF = 28 GHz and 39 GHz, fBB = 100 MHz
50
0
5
15
25
10
20
30
35
40
45
00.5 1.0 2.5 4.5 6.51.5 3.5 5.52.0 4.0 6.03.0 5.0 7.0
SIDE BAND RE JE CTI ON (dBc)
BASEBAND F RE QUENCY ( GHz)
39GHz UPP E R S IDEBAND
28GHz UPP E R S IDEBAND
39GHz LOWER S IDEBAND
28GHz LOWER S IDEBAND
17267-026
Figure 26. Sideband Rejection vs. Baseband Frequency at
fRF = 28 GHz and 39 GHz (Upper Sideband and Lower Sideband)
Data Sheet ADMV1013
Rev. B | Page 13 of 39
20
–10
–5
0
5
10
15
23 25 27 31 35 3929 33 37 41 43 45
OUTPUT P 1dB (dBm)
RF FREQ UE NCY ( GHz)
+85° C UP P E R S IDEBAND
+25° C UP P E R S IDEBAND
–40°C UP P E R S IDEBAND
17267-027
Figure 27. Output P1dB vs. RF Frequency at Maximum Gain for Various
Temperatures, fBB = 100 MHz (Upper Sideband)
20
–20
–10
–15
–5
0
5
10
15
23 25 27 31 35 3929 33 37 41 43 45
OUTPUT P 1dB (dBm)
RF FREQ UE NCY ( GHz)
3.5V UP P E R S IDEBAND
3.3V UP P E R S IDEBAND
3.1V UP P E R S IDEBAND
17267-028
Figure 28. Output P1dB vs. RF Frequency for Various Supply Voltages,
fBB = 100 MHz (Upper Sideband)
20
–20
–10
–15
–5
0
5
10
15
23 25 27 31 35 3929 33 37 41 43 45
OUTPUT P 1dB (dBm)
RF FREQ UE NCY ( GHz)
+6dBm UP P E R S IDEBAND
0dBm UPP E R S IDEBAND
–6dBm UP PE R S IDEBAND
17267-029
Figure 29. Output P1dB vs. RF Frequency for Various LO Inputs,
fBB = 100 MHz (Upper Sideband)
20
–20
–10
–15
–5
0
5
10
15
00.2 0.4 0.8 1.2 1.60.6 1.0 1.4 1.8
OUTPUT P 1dB (dBm)
V
CTRL
(V)
+85° C AT 39G Hz
+25° C AT 39G Hz
–40°C AT 39G Hz
+85° C AT 28G Hz
+25° C AT 28G Hz
–40°C AT 28G Hz
17267-030
Figure 30. Output P1dB vs. VCTRL for Various Temperatures at
fRF = 28 GHz and 39 GHz, fBB = 100 MHz
20
–5
0
5
10
15
00.5 1.0 2.5 4.5 6.51.5 3.5 5.52.0 4.0 6.03.0 5.0 7.0
OUTPUT P 1dB (dBm)
BASEBAND F RE QUENCY ( GHz)
39GHz UPP E R S IDEBAND
28GHz UPP E R S IDEBAND
17267-031
Figure 31. Output P1dB vs. Baseband Frequency at
fRF = 28 GHz and 39 GHz (Upper Sideband)
20
–5
0
5
10
15
00.5 1.0 2.5 4.5 6.51.5 3.5 5.52.0 4.0 6.03.0 5.0 7.0
OUTPUT P 1dB (dBm)
BASEBAND F RE QUENCY ( GHz)
39GHz LOWER S IDEBAND
28GHz LOWER S IDEBAND
17267-032
Figure 32. Output P1dB vs. Baseband Frequency at
fRF = 28 GHz and 39 GHz (Lower Sideband)
ADMV1013 Data Sheet
Rev. B | Page 14 of 39
IF MODE
IF amplitude = −20 dBm, VCC_DRV = VCC2_DRV = VCC_AMP2 = VCC_ENV = VCC_AMP1 = VCC_BG2 = VCC_MIXER =
VCC_BG = VCC_QUAD = 3.3 V, DVDD = VCC_VVA = 1.8 V, TA = 25°C, and set Register 0x0A to 0xE700, unless otherwise noted.
VCTRL1 = VCTRL2. VCTRL is the attenuation voltage at the VCTRL1 and VCTRL2 pins. VCTRL = 1800 mV, unless otherwise specified.
Measurements in IF mode performed with a 90° hybrid, Register 0x03, Bit 7 = 1, and fIF = 3.5 GHz.
+85° C UP P E R S IDEBAND
+25° C UP P E R S IDEBAND
–40°C UP P E R S IDEBAND
+85° C LO WER SIDEBAND
+25° C LO WER SIDEBAND
–40°C LO WER S I DE BAND
23 25 27 31 35 39
29 33 37 41 43 45
RF FREQ UE NCY ( GHz)
28
0
10
2
14
18
12
6
4
8
16
20
22
24
26
CONVE RS IO N GAI N ( dB)
17267-035
Figure 33. Conversion Gain vs. RF Frequency at Maximum Gain for Various
Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
3.5V UP P E R S IDEBAND
3.3V UP P E R S IDEBAND
3.1V UP P E R S IDEBAND
3.5V LO WER S IDEBAND
3.3V LO WER S IDEBAND
3.1V LO WER S IDEBAND
23 25 27 31 35 3929 33 37 41 43 45
RF FREQ UE NCY ( GHz)
28
0
10
2
14
18
12
6
4
8
16
20
22
24
26
CONVE RS IO N GAI N ( dB)
17267-036
Figure 34. Conversion Gain vs. RF Frequency at Maximum Gain for Various
Supply Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
+6dBm UP P E R S IDEBAND
0dBm UPP E R S IDEBAND
–6dBm UP PE R S IDEBAND
+6dBm LO WER S IDEBAND
0dBm LOWER S IDEBAND
–6dBm LOWER S IDEBAND
23 25 27 31 35 3929 33 37 41 43 45
RF FREQ UE NCY ( GHz)
28
0
10
2
14
18
12
6
4
8
16
20
22
24
26
CONVE RS IO N GAI N ( dB)
17267-037
Figure 35. Conversion Gain vs. RF Frequency at Maximum Gain for Various
LO Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
28
0
10
2
14
18
12
6
4
8
16
20
22
24
26
CONVE RS IO N GAI N ( dB)
0.5 1.0 2.5 4.5 6.5
1.5 3.5 5.5
2.0 4.0 6.0
3.0 5.0 7.0
IF FRE QUENCY ( GHz)
39GHz UPP E R S IDEBAND
28GHz UPP E R S IDEBAND
39GHz LOWER S IDEBAND
28GHz LOWER S IDEBAND
17267-038
Figure 36. Conversion Gain vs. IF Frequency at fRF = 28 GHz and 39 GHz at
Maximum Gain (Upper Sideband and Lower Sideband)
+85° C AT 39G Hz
+25° C AT 39G Hz
–40°C AT 39G Hz
+85° C AT 28G Hz
+25° C AT 28G Hz
–40°C AT 28G Hz
00.2 0.4 0.8 1.2 1.60.6 1.0 1.4 1.8
V
CTRL
(V)
30
–40
–20
–30
–10
0
10
20
CONVE RS IO N GAI N ( dB)
17267-039
Figure 37. Conversion Gain vs. VCTRL at Various Temperatures at
fRF = 28 GHz and 39 GHz, fIF = 3.5 GHz (Upper Sideband)
+85° C AT 39G Hz
+25° C AT 39G Hz
–40°C AT 39G Hz
+85° C AT 28G Hz
+25° C AT 28G Hz
–40°C AT 28G Hz
00.2 0.4 0.8 1.2 1.60.6 1.0 1.4 1.8
V
CTRL
(V)
30
–40
–20
–30
–10
0
10
20
CONVE RS IO N GAI N ( dB)
17267-040
Figure 38. Conversion Gain vs. VCTRL at Various Temperatures at
fRF = 28 GHz and 39 GHz, fIF = 3.5 GHz (Lower Sideband)
Data Sheet ADMV1013
Rev. B | Page 15 of 39
+85° C UP P E R S IDEBAND
+25° C UP P E R S IDEBAND
–40°C UP P E R S IDEBAND
+85° C LO WER SIDEBAND
+25° C LO WER SIDEBAND
–40°C LO WER SIDEBAND
23 25 27 31 35 3929 33 37 41 43 45
RF FREQ UE NCY ( GHz)
28
0
10
2
14
18
12
6
4
8
16
20
22
24
26
OUTPUT IP3 ( dBm)
17267-041
Figure 39. Output IP3 vs. RF Frequency at Maximum Gain for Various
Temperatures, RF Amplitude = −20 dBm per Tone at 20 MHz Spacing,
fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
23 25 27 31 35 3929 33 37 41 43 45
RF FREQ UE NCY ( GHz)
28
0
10
2
14
18
12
6
4
8
16
20
22
24
26
OUTPUT IP3 ( dBm)
3.5V UP P E R S IDEBAND
3.3V UP P E R S IDEBAND
3.1V UP P E R S IDEBAND
3.5V LO WER S IDEBAND
3.3V LO WER S IDEBAND
3.1V LO WER S IDEBAND
17267-042
Figure 40. Output IP3 vs. RF Frequency at Maximum Gain for Various Supply
Voltages, RF Amplitude = −20 dBm per Tone at 20 MHz Spacing,
fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
23 25 27 31 35 3929 33 37 41 43 45
RF FREQ UE NCY ( GHz)
28
0
10
2
14
18
12
6
4
8
16
20
22
24
26
OUTPUT IP3 ( dBm)
+6dBm UP P E R S IDEBAND
0dBm UPP E R S IDEBAND
–6dBm UP PE R S IDEBAND
+6dBm LO WER S IDEBAND
0dBm LOWER S IDEBAND
–6dBm LOWER S IDEBAND
17267-043
Figure 41. Output IP3 vs. RF Frequency at Maximum Gain for Various
LO Inputs, RF Amplitude = −20 dBm per Tone at 20 MHz Spacing,
fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
0.200.4 0.6 0.8 1.2 1.61.1 1.4 1.8
V
CTRL
(V)
OUTPUT IP3 ( dBm)
39GHz UPP E R S IDEBAND
28GHz UPP E R S IDEBAND
39GHz LOWER S IDEBAND
28GHz LOWER S IDEBAND
–5
5
–10
0
10
15
20
25
17267-044
Figure 42. Output IP3 vs. VCTRL at fRF = 28 GHz and 39 GHz,
RF Amplitude = −20 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz
(Upper Sideband and Lower Sideband)
28
0
10
2
14
18
12
6
4
8
16
20
22
24
26
OUTPUT IP3 ( dBm)
0.5 1.0 2.5 4.5 6.51.5 3.5 5.5
2.0 4.0 6.03.0 5.0 7.0
IF FRE QUENCY ( GHz)
39GHz UPP E R S IDEBAND
28GHz UPP E R S IDEBAND
39GHz LOWER S IDEBAND
28GHz LOWER S IDEBAND
17267-045
Figure 43. Output IP3 vs. IF Frequency at fRF = 28 GHz and 39 GHz at
Maximum Gain, RF Amplitude = −20 dBm per Tone at 20 MHz Spacing
(Upper Sideband and Lower Sideband)
25
17
16
18
20
17
19
21
22
23
24
OUTPUT IP3 ( dBm)
–20 –19 –16 –12–18 –14–17 –13–15 –11 –10
TOTAL INPUT POWER (dBm)
39GHz UPP E R S IDEBAND
28GHz UPP E R S IDEBAND
39GHz LOWER S IDEBAND
28GHz LOWER S IDEBAND
17267-046
Figure 44. Output IP3 vs. Total Input Power at fRF = 28 GHz and 39 GHz at
20 MHz Spacing, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
ADMV1013 Data Sheet
Rev. B | Page 16 of 39
50
10
15
25
20
30
35
40
45
NOISE FIGURE (dB)
23 25 27 31 35 3929 33 37 41 43 45
RF FREQ UE NCY ( GHz)
+85° C UP P E R S IDEBAND
+25° C UP P E R S IDEBAND
–40°C UP P E R S IDEBAND
+85° C LO WER SIDEBAND
+25° C LO WER SIDEBAND
–40°C LO WER SIDEBAND
17267-047
Figure 45. Noise Figure vs. RF Frequency at Maximum Gain for Various
Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
50
10
15
25
20
30
35
40
45
NOISE FIGURE (dB)
23 25 27 31 35 3929 33 37 41 43 45
RF FREQ UE NCY ( GHz)
3.5V UP P E R S IDEBAND
3.3V UP P E R S IDEBAND
3.1V UP P E R S IDEBAND
3.5V LO WER S IDEBAND
3.3V LO WER S IDEBAND
3.1V LO WER S IDEBAND
17267-048
Figure 46. Noise Figure vs. RF Frequency at Maximum Gain for Various
Supply Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
50
10
15
25
20
30
35
40
45
NOISE FIGURE (dB)
23 25 27 31 35 3929 33 37 41 43 45
RF FREQ UE NCY ( GHz)
+6dBm UP P E R S IDEBAND
0dBm UPP E R S IDEBAND
–6dBm UP PE R S IDEBAND
+6dBm LO WER S IDEBAND
0dBm LOWER S IDEBAND
–6dBm LOWER S IDEBAND
17267-049
Figure 47. Noise Figure vs. RF Frequency at Maximum Gain for Various
LO Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
NOISE FIGURE (dB)
0.5 1.0 2.5 4.5 6.51.5 3.5 5.52.0 4.0 6.0
3.0 5.0 7.0
IF FRE QUENCY ( GHz)
39GHz UPP E R S IDEBAND
28GHz UPP E R S IDEBAND
39GHz LOWER S IDEBAND
28GHz LOWER S IDEBAND
50
0
5
15
25
10
20
30
35
40
45
17267-050
Figure 48. Noise Figure vs. IF Frequency at fRF = 28 GHz and 39 GHz at
Maximum Gain (Upper Sideband and Lower Sideband)
55
50
10
15
25
20
30
35
40
45
NOISE FIGURE (dB)
00.2 0.4 0.8 1.2 1.6
0.6 1.0 1.4 1.8
V
CTRL
(V)
+85° C UP P E R S IDEBAND
+25° C UP P E R S IDEBAND
–40°C UP P E R S IDEBAND
+85° C LO WER SIDEBAND
+25° C LO WER SIDEBAND
–40°C LO WER S I DE BAND
17267-051
Figure 49. Noise Figure vs. VCTRL at Various Temperatures, fIF = 3.5 GHz,
(Upper Sideband and Lower Sideband)
00.2 0.4 0.8 1.2 1.60.6 1.0 1.4 1.8
V
CTRL
(V)
+85° C AT 39G Hz
+25° C AT 39G Hz
–40°C AT 39G Hz
+85° C AT 28G Hz
+25° C AT 28G Hz
–40°C AT 28G Hz
50
10
15
25
20
30
35
40
45
NOISE FIGURE (dB)
17267-052
Figure 50. Noise Figure vs. VCTRL for Various Temperatures at fRF = 28 GHz and
39 GHz, fIF = 3.5 GHz (Lower Sideband)
Data Sheet ADMV1013
Rev. B | Page 17 of 39
+85° C UP P E R S IDEBAND
+25° C UP P E R S IDEBAND
–40°C UP P E R S IDEBAND
+85° C LO WER SIDEBAND
+25° C LO WER SIDEBAND
–40°C LO WER SIDEBAND
23 25 27 31 35 3929 33 37 41 43 45
RF FREQ UE NCY ( GHz)
20
–10
–5
0
5
10
15
OUTPUT P 1dB (dBm)
17267-053
Figure 51. Output P1dB vs. RF Frequency at Maximum Gain for Various
Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
23 25 27 31 35 3929 33 37 41 43 45
RF FREQ UE NCY ( GHz)
20
–10
–5
0
5
10
15
OUTPUT P 1dB (dBm)
3.5V UP P E R S IDEBAND
3.3V UP P E R S IDEBAND
3.1V UP P E R S IDEBAND
3.5V LO WER S IDEBAND
3.3V LO WER S IDEBAND
3.1V LO WER S IDEBAND
17267-054
Figure 52. Output P1dB vs. RF Frequency at Maximum Gain for Various
Supply Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
23 25 27 31 35 3929 33 37 41 43 45
RF FREQ UE NCY ( GHz)
–10
–5
0
5
10
15
OUTPUT P 1dB (dBm)
+6dBm UP P E R S IDEBAND
0dBm UPP E R S IDEBAND
–6dBm UP PE R S IDEBAND
+6dBm LO WER S IDEBAND
0dBm LOWER S IDEBAND
–6dBm LOWER S IDEBAND
17267-055
Figure 53. Output P1dB vs. RF Frequency at Maximum Gain for Various
LO Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
20
–10
–5
0
5
10
15
OUTPUT P 1dB (dBm)
0.5 1.0 2.5 4.5 6.5
1.5 3.5 5.5
2.0 4.0 6.0
3.0 5.0 7.0
IF FRE QUENCY ( GHz)
0
39GHz UPP E R S IDEBAND
28GHz UPP E R S IDEBAND
39GHz LOWER S IDEBAND
28GHz LOWER S IDEBAND
17267-056
Figure 54. Output P1dB vs. IF Frequency at fRF = 28 GHz and 39 GHz at
Maximum Gain (Upper Sideband and Lower Sideband)
+85° C AT 39G Hz
+25° C AT 39G Hz
–40°C AT 39G Hz
+85° C AT 28G Hz
+25° C AT 28G Hz
–40°C AT 28G Hz
VCTRL (V)
20
–25
–15
–5
–10
–20
0
5
10
15
OUTPUT P 1dB (dBm)
17267-057
0.200.4 0.6 0.8 1.2 1.61.1 1.4 1.8
Figure 55. Output P1dB vs. VCTRL for Various Temperatures at
fRF = 28 GHz and 39 GHz, fIF = 3.5 GHz (Upper Sideband)
+85° C AT 39G Hz
+25° C AT 39G Hz
–40°C AT 39G Hz
+85° C AT 28G Hz
+25° C AT 28G Hz
–40°C AT 28G Hz
VCTRL (V)
20
–25
–15
–5
–10
–20
0
5
10
15
OUTPUT P 1dB (dBm)
17267-058
0.200.4 0.6 0.8 1.2 1.61.1 1.4 1.8
Figure 56. Output P1dB vs. VCTRL for Various Temperatures at
fRF = 28 GHz and 39 GHz, fIF = 3.5 GHz (Lower Sideband)
ADMV1013 Data Sheet
Rev. B | Page 18 of 39
+85° C UP P E R S IDEBAND
+25° C UP P E R S IDEBAND
–40°C UP P E R S IDEBAND
+85° C LO WER SIDEBAND
+25° C LO WER SIDEBAND
–40°C LO WER SIDEBAND
23 25 27 31 35 3929 33 37 41 43 45
RF FREQ UE NCY ( GHz)
60
0
15
25
35
20
5
10
30
40
45
50
55
SIDE BAND RE JE CTI ON (dBc)
17267-059
Figure 57. Sideband Rejection vs. RF Frequency at Maximum Gain for
Various Temperatures, fIF = 3.5 GHz, Uncalibrated
(Upper Sideband and Lower Sideband)
+85° C UP P E R S IDEBAND
+25° C UP P E R S IDEBAND
–40°C UP P E R S IDEBAND
23 25 27 31 35 3929 33 37 41 43 45
RF FREQ UE NCY ( GHz)
60
0
15
25
35
20
5
10
30
40
45
50
55
SIDE BAND RE JE CTI ON (dBc)
17267-060
Figure 58. Sideband Rejection vs. RF Frequency at Maximum Gain for Various
Temperatures, fIF = 3.5 GHz, Calibrated at 25°C (Upper Sideband). Note:
Calibrated Using LOAMP_PH_ADJ_ Q_FINE and LOAMP_PH_ADJ_I_FINE Bits
23 25 27 31 35 3929 33 37 41 43 45
RF FREQ UE NCY ( GHz)
0
15
25
35
20
5
10
30
40
SIDE BAND RE JE CTI ON (dBc)
3.5V UP P E R S IDEBAND
3.3V UP P E R S IDEBAND
3.1V UP P E R S IDEBAND
3.5V LO WER S IDEBAND
3.3V LO WER S IDEBAND
3.1V LO WER S IDEBAND
17267-061
Figure 59. Sideband Rejection vs. RF Frequency at Maximum Gain for Various
Supply Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
+6dBm UP P E R S IDEBAND
0dBm UPP E R S IDEBAND
–6dBm UP PE R S IDEBAND
+6dBm LO WER S IDEBAND
0dBm LOWER S IDEBAND
–6dBm LOWER S IDEBAND
17267-062
23 25 27 31 35 3929 33 37 41 43 45
RF FREQ UE NCY ( GHz)
0
15
25
35
20
5
10
30
40
SIDE BAND RE JE CTI ON (dBc)
Figure 60. Sideband Rejection vs. RF Frequency at Maximum Gain for
Various LO Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
60
0
15
25
35
20
5
10
30
40
45
50
55
SIDE BAND RE JE CTI ON (dBc)
0.5 1.0 2.5 4.5 6.51.5 3.5 5.52.0 4.0 6.03.0 5.0 7.0
IF FRE QUENCY ( GHz)
39GHz UPP E R S IDEBAND
28GHz UPP E R S IDEBAND
39GHz LOWER S IDEBAND
28GHz LOWER S IDEBAND
17267-063
Figure 61. Sideband Rejection vs. IF Frequency at fRF = 28 GHz and 39 GHz at
Maximum Gain (Upper Sideband and Lower Sideband)
SIDE BAND RE JE CTI ON (dBc)
0.2 0.8 1.60.4 1.20.6 1.41.0 1.8
V
CTRL
(V)
39GHz UPP E R S IDEBAND
28GHz UPP E R S IDEBAND
39GHz LOWER S IDEBAND
28GHz LOWER S IDEBAND
17267-064
0
5
10
15
20
25
30
35
40
Figure 62. Sideband Rejection vs. VCTRL at fRF = 28 GHz and 39 GHz,
fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
Data Sheet ADMV1013
Rev. B | Page 19 of 39
ENVELOPE DETECTOR PERFORMANCE
IF and I/Q amplitude = −20 dBm, VCC_DRV = VCC2_DRV = VCC_AMP2 = VCC_ENV = VCC_AMP1 = VCC_BG2 = VCC_MIXER =
VCC_BG = VCC_QUAD = 3.3 V, DVDD = VCC_VVA = 1.8 V, TA = 25°C, and set Register 0x0A to 0xE700, unless otherwise noted.
Measurements in IF mode performed with a 90° hybrid, Register 0x03, Bit 7 = 1, IF fIF = 3.5 GHz.
Measurements in I/Q mode are measured as a composite of the I and Q channel performance, VCM = 0 V, Register 0x03, Bit 7 = 0, and
Register 0x05, Bits[6:0] = 0x051, unless otherwise noted. I/Q fBB = 100 MHz.
VCTRL1 = VCTRL2. VCTRL is the attenuation voltage at the VCTRL1 and VCTRL2 pins. VCTRL = 1800 mV, unless otherwise specified.
Envelope detector measurements made with Register 0x03, Bit 5 = 1.
–70
–60
–50
–40
–30
–20
–10
0
25
50
75
100
125
150
175
200
23 25 27 29 31 33 35 37 39 41 43 45
ENVELOPE P
OUT
DELTA (dBm)
VENV_N/VENV_P DELTA (mV)
RF FREQUENCY (GHz)
VENV_N/VENV_P DELTA, P
OUT
= 13dBm
VENV_N/VENV_P DELTA, P
OUT
= 5dBm
VENV_N/VENV_P DELTA, P
OUT
= 0dBm
ENVELOPE P
OUT
, P
OUT
= 13dBm
ENVELOPE P
OUT
, P
OUT
= 5dBm
ENVELOPE P
OUT
, P
OUT
= 0dBm
17267-065
Figure 63. VENV_N/VENV_P Delta and Envelope POUT Delta vs. RF Frequency
at Various Output Power Levels, Envelope Frequency = 100 MHz, VCTRL = 1800 mV,
TA = 25°C, LO = 0 dBm, IF = 2 GHz (Upper Sideband)
–70
–65
–60
–55
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
50
100
150
200
250
300
350
400
450
500
550
600
650
700
750
800
850
900
950
1000
1050
1100
1150
1200
1250
1300
1350
1400
1450
1500
OUTPUT LEVEL (dBm)
ENVELOPE FREQUENCY (MHz)
NORMALIZED HD1, 1×
NORMALIZED HD2, 2×
17267-066
Figure 64. Output Level vs. Envelope Frequency for Normalized Harmonic
Distortion (HD1), 1× and Normalized Harmonic Distortion(HD2), 2×,
fRF = 28 GHz, LO = 0 dBm at 25°C, HD1 and HD2 Measurement Performed
with Two Tones with Delta Equal to Envelope Frequency,
HD2 Normalized to HD1 Level at 50 MHz
0
20
40
60
80
100
120
140
160
180
200
220
240
260
280
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10
20
–20 –18 –16 –14 –12 –10 –8 –6 –4 –2 0 2
VENV_N/VENV_P DELTA (mV)
P
OUT
(dBm)
POWER IN TOTAL (dBm)
P
OUT
RF
P
OUT
ENVELOPE AT HD1
P
OUT
ENVELOPE ATHD2
VENV_N/VENV _P DE LT A
17267-067
Figure 65. POUT and VENV_N/VENV_P Delta vs. Power In Total for POUT RF,
POUT Envelope HD1, POUT Envelope HD2, and VENV_N/VENV_P Delta,
Measurements Performed with Two Tones with 100 MHz Separation,
fRF = 28 GHz, VCTRL = 1800 mV
ADMV1013 Data Sheet
Rev. B | Page 20 of 39
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
–70
–65
–60
–55
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
VENV_N/ V E NV _P DE LT A ( mV )
HD1 P OUT ENVELOPE (dBm)
VCTRL (V)
17267-068
POUT ENVELO PE AT PIN = –10dBm
POUT ENVELO PE AT PIN = –15dBm
VENV_N/VE NV _P DE LT A, PIN = –10dBm
VENV_N/VE NV _P DE LT A, PIN = –15dBm
Figure 66. HD1 POUT Envelope and VENV_N/VENV_P Delta vs. VCTRL at
Various Total Input Power (PIN) Levels, Measurements Performed at 28 GHz
with Two Input Tones with Separation of 100 MHz
–60
–50
–40
–30
–20
–10
0
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
0
2
4
6
8
10
12
14
16
P
OUT
ENVELOPE (dBm)
P
OUT
RF PER TONE (dBm)
P
OUT
ENVELOPE AT +25°C
P
OUT
ENVELOPE AT +85°C
P
OUT
ENVELOPE AT –40°C
17267-069
Figure 67. POUT Envelope vs. POUT RF per Tone at Various Temperatures at
fRF = 33 GHz, Measurement Performed at 3.5 GHz IF with Two Tones at
100 MHz Spacing, VCTRL = 1800 mV
Data Sheet ADMV1013
Rev. B | Page 21 of 39
RETURN LOSS AND ISOLATION
IF and I/Q amplitude = −20 dBm, VCC_DRV = VCC2_DRV = VCC_AMP2 = VCC_ENV = VCC_AMP1 = VCC_BG2 = VCC_MIXER =
VCC_BG = VCC_QUAD = 3.3 V, DVDD = VCC_VVA = 1.8 V, TA = 25°C, and set Register 0x0A to 0xE700, unless otherwise noted.
Measurements in IF mode performed with a 90° hybrid, Register 0x03, Bit 7 = 1, and fIF = 3.5 GHz.
Measurements in I/Q mode are measured as a composite of the I and Q channel performance, VCM = 0 V, Register 0x03, Bit 7 = 0, and
Register 0x05, Bits[6:0] = 0x051, unless otherwise noted. I/Q fBB = 100 MHz.
VCTRL1 = VCTRL2. VCTRL is the attenuation voltage at the VCTRL1 and VCTRL2 pins. VCTRL = 1800 mV, unless otherwise specified.
Envelope detector measurements made with Register 0x03, Bit 5 = 1.
0
–35
–30
–25
–20
–15
–10
–5
23 25 27 31 35 3929 33 37 41 43 45
RF RETURN L OSS ( dBm)
RF FREQ UE NCY ( GHz)
17267-071
0V
0.9V
1.8V
Figure 68. RF Return Loss vs. RF Frequency at Various VCTRL Voltages
–35
–30
–25
–20
–15
–10
–5
0
4 5 6 7 8 9 10 11 12
LO RETURN LOSS (dB)
LO FREQUENCY (GHz)
LO DIFFERENTIAL
LOP
LON
17267-072
Figure 69. LO Return Loss vs. LO Frequency
–35
–30
–25
–20
–15
–10
–5
0
0 1 2 3 4 5 6 7
IF RETURN LOSS (dB)
IF FREQUENCY (GHz)
17267-075
I SIDE
Q SIDE
Figure 70. IF Return Loss vs. IF Frequency (Taken Without Hybrid)
–35
–30
–25
–20
–15
–10
–5
0
0 1 2 3 4 5 6 7
I/Q DIFFERENTIAL RETURN LOSS (dB)
FREQUENCY (GHz)
17267-074
I SIDE
Q SIDE
Figure 71. I/Q Differential Return Loss vs. Frequency
(Taken Without Hybrids or Baluns)
ADMV1013 Data Sheet
Rev. B | Page 22 of 39
0
–105
–80
–100
–60
–70
–90
–50
–40
–20
–30
–10
–75
–95
–55
–65
–85
–45
–35
–15
–25
–5
4 6 8 10 12
LO TO RF LEAKAGE (dBc)
LO FRE QUENCY ( GHz)
1× LO AT + 85°C
1× LO AT + 25°C
1× LO AT –40°C
4× LO AT + 85°C
4× LO AT + 25°C
4× LO AT –40°C
17267-073
5× LO AT + 85°C
5× LO AT + 25°C
5× LO AT –40°C
Figure 72. LO to RF Leakage vs. LO Frequency for 4× LO, 5× LO, and 1× LO at
Various Temperatures (Uncalibrated)
–85
–80
–75
–70
–65
–60
–55
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
4 5 6 7 8 9 10 11 12
1× LO L E AKAGE ( dBm)
LO FRE QUENCY ( GHz)
1× LO LEAKAGE, VCTRL = 0mV
1× LO LEAKAGE, VCTRL = 300mV
1× LO LEAKAGE, VCTRL = 600mV
1× LO LEAKAGE, VCTRL = 900mV
1× LO LEAKAGE, VCTRL = 1200mV
1× LO LEAKAGE, VCTRL = 1500mV
1× LO LEAKAGE, VCTRL = 1800mV
17267-076
Figure 73. 1× LO Leakage vs. LO Frequency at Different VCTRL Settings
(Uncalibrated)
80
–70
–60
–50
–40
–30
–20
–10
0
4 5 6 7 8 9 10 11 12
4x LO TO RF LEAKAGE (dBm)
LO FREQUENCY (GHz)
–40°C
+25°C
+85°C
17267-077
Figure 74. 4× LO to RF Leakage vs. LO Frequency at Various Temperatures
(Calibrated). Note: Calibrated at Each Frequency Using MXER_OFF_ADJ_I_N,
MXER_OFF_ADJ_I_P, MXER_OFF_ADJ_Q_N, and MXER_OFF_ADJ_Q_P Bits
at TA = 25°C
–85
–80
–75
–70
–65
–60
–55
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
4 5 6 7 8 9 10 11 12
5× LO L E AKAGE ( dBm)
LO FRE QUENCY ( GHz)
17267-276
5× LO LEAKAGE, V
CTRL
= 0mV
5× LO LEAKAGE, V
CTRL
= 300mV
5× LO LEAKAGE, V
CTRL
= 600mV
5× LO LEAKAGE, V
CTRL
= 900mV
5× LO LEAKAGE, V
CTRL
= 1200mV
5× LO LEAKAGE, V
CTRL
= 1500mV
5× LO LEAKAGE, V
CTRL
= 1800mV
Figure 75. 5× LO Leakage vs. LO Frequency at Different VCTRL Settings
(Uncalibrated)
–85
–80
–75
–70
–65
–60
–55
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
4 5 6 7 8 9 10 11 12
4× LO L E AKAGE ( dBm)
LO FRE QUENCY ( GHz)
17267-176
4× LO LEAKAGE, VCTRL = 0mV
4× LO LEAKAGE, VCTRL = 300mV
4× LO LEAKAGE, VCTRL = 600mV
4× LO LEAKAGE, VCTRL = 900mV
4× LO LEAKAGE, VCTRL = 1200mV
4× LO LEAKAGE, VCTRL = 1500mV
4× LO LEAKAGE, VCTRL = 1800mV
Figure 76. 4× LO Leakage vs. LO Frequency at Different VCTRL Settings
(Uncalibrated)
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
4 5 6 7 8 9 10 11 12
4× LO TO RF LEAKAGE (dBm)
LO FRE QUENCY ( GHz)
V
CTRL
= 0V
V
CTRL
= 0.4V
V
CTRL
= 0.8V
V
CTRL
= 1.2V
V
CTRL
= 1.4V
V
CTRL
= 1.8V
17267-080
Figure 77. 4× LO to RF Leakage vs. LO Frequency at Various VCTRL (Calibrated)
Note: Calibrated at Each Frequency Using MXER_OFF_ADJ_I_N,
MXER_OFF_ADJ_I_P, MXER_OFF_ADJ_Q_N, and MXER_OFF_ADJ_Q_P Bits
at VCTRL = 1800 mV
Data Sheet ADMV1013
Rev. B | Page 23 of 39
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
45 6 78910 11 12
LO LE AKAGE ( dBm)
LO FRE QUENCY ( GHz)
+25° C, I _N
–40°C, I _N
+85° C, I _N
+25° C, I _P
–40°C, I _P
+85° C, I _P
+25° C, Q _N
–40°C, Q _N
+85° C, Q _N
+25° C, Q _P
–40°C, Q _P
+85° C, Q _P
17267-079
Figure 78. LO Leakage vs. LO Frequency at Various Temperatures at I_N, I_P,
Q_N, and Q_P (Taken Without Hybrid(s))
–35
–30
–25
–20
–15
–10
–5
0
0 1 2 3 4 5
ENVELOPE DETECTOR
DIFFERENTIAL RETURN LOSS (dB)
FRE Q UE NCY ( GHz)
17267-082
Figure 79. Envelope Detector Differential Return Loss vs. Frequency
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
4 5 6 7 8 9 10 11 12
LO LE AKAGE ( dBm)
LO FRE QUENCY ( GHz)
+25° C, I F_I
–40°C, I F_I
+85° C, I F_I
+25° C, I F_Q
–40°C, I F_Q
+85° C, I F_Q
17267-078
Figure 80. LO Leakage vs. LO Frequency at Various Temperatures at IF_I and
IF_Q Ports(Taken Without Hybrid)
ADMV1013 Data Sheet
Rev. B | Page 24 of 39
M × N SPURIOUS PERFORMANCE
Mixer spurious products are measured in dBc from the RF
output power level. Spurious frequencies are calculated by
|(M × IF) + (N × LO) | (for IF Mode)
|(M × IQ) + (N × LO) | (for IQ Mode)
N/A means not applicable. Blank cells in the spurious
performance tables indicate that the frequency is above 50 GHz
and is not measured. REF stands for reference RF output signal.
The LO frequencies are referred from the frequencies applied to
the ADMV1013. IF and I/Q amplitude = −20 dBm.
VCC_DRV = VCC2_DRV = VCC_AMP2 = VCC_ENV =
VCC_AMP1 = VCC_BG2 = VCC_MIXER = VCC_BG =
VCC_QUAD = 3.3 V, DVDD = VC C _ V VA = 1 . 8 V, T A = 25°C,
and set Register 0x0A to 0xE700, unless otherwise noted.
Measurements in IF mode performed with a 90° hybrid,
Register 0x03, Bit 7 = 1, and fIF = 3.5 GHz.
Measurements in I/Q mode are measured as a composite of the
I and Q channel performance, VCM = 0 V, Register 0x03, Bit 7 = 0,
and Register 0x05, Bits[6:0] = 0x051, unless otherwise noted. I/Q
fBB = 100 MHz.
VCTRL1 = VCTRL2. VCTRL is the attenuation voltage at the
VCTRL1 and VCTRL2 pins. VCTRL = 1800 mV, unless otherwise
specified.
I/Q Mode
fBB = 100 MHz at −20 dBm, LO = 6.975 GHz at +6 dBm.
N × LO
0 1 2 3 4 5 6 7
M × IQ
−2 93 105 103 122 79 109 89 108
−1 93 95 85 57 26 65 53 110
0 N/A 80 72 53 20 61 35 73
+1
93 96 74 32 REF 41 37 84
+2 93 107 86 91 57 89 91 83
fBB = 100 MHz at −20 dBm, LO = 9.725 GHz at +6 dBm, and
fRF = 39 GHz.
N × LO
0 1 2 3 4 5
M × IQ
−2 97 116 95 116 89 113
−1 101 100 37 62 26 90
0 N/A 77 40 63 20 77
+1 97 91 18 36 REF 68
+2 101 118 80 99 64 103
IF Mode
fIF = 3.5 GHz at −20 dBm, LO = 6.125 GHz at +6 dBm, and
fRF = 28 GHz.
N × LO
0 1 2 3 4 5 6 7 8
M × IF
−2 76 117 120 109 77 92 90 84 45
−1 68 90 80 77 23 46 56 53 44
0 N/A 71 71 26 9 34 24 20 30
+1 76 92 58 18 REF 24 32 61
+2 68 84 75 70 58 80 82 75
fIF = 3.5 GHz at −20 dBm, LO = 8.875 GHz at +6 dBm, and
fRF = 39 GHz.
N × LO
0 1 2 3 4 5 6
M × IF
−2 83 132 109 96 68 99 107
−1 69 95 76 54 25 57 83
0 N/A 69 44 53 16 52
+1 83 89 24 33 REF 58
+2 69 114 93 98 75
fIF = 3.5 GHz at −20 dBm, LO = 7.875 GHz at +6 dBm, and
fRF = 28 GHz.
N × LO
0 1 2 3 4 5 6 7
M × IF
−2 82 140 115 107 69 99 97 95
−1 65 120 91 41 REF 47 46
0 N/A 82 75 52 23 49 56
+1 82 94 60 70 26 75
+2 65 120 107 111 93 115
fIF = 3.5 GHz at −20 dBm, LO = 10.5 GHz at +6 dBm, and
fRF = 39 GHz.
N × LO
0 1 2 3 4 5
M × IF
−2 96 122 99 91 70 94
−1 80 85 28 26 REF 64
0 N/A 83 34 43 16
+1 97 95 45 49 41
+2 79 113 88 103 102
Data Sheet ADMV1013
Rev. B | Page 25 of 39
THEORY OF OPERATION
The ADMV1013 is a wideband microwave upconverter optimized
for microwave radio designs operating in the 24 GHz to 44 GHz
RF frequency range. See Figure 1 for a functional block diagram
of the device. The ADMV1013 digital settings are controlled via the
SPI. The ADMV1013 has two modes of operation:
• Baseband quadrature modulation (I/Q mode)
• Single-sideband upconversion (IF mode)
START-UP SEQUENCE
To use the voltage control RF VVA1 and RF VVA2, the
VCC_VVA (1.8 V) supply must be on. The VCTRL1 pin and
VCTRL2 pin control the gain of the RF VVA1 and the RF
V VA 2 . Similarly, to use the SPI control, it is necessary to first
turn on DVDD and then perform a hard reset by toggling the
RST pin to logic low and then to logic high.
The ADMV1013 SPI settings require the default settings to be
changed during startup for optimum performance.
Set Register 0x0A to 0xE700 after each power-up or reset.
BASEBAND QUADRATURE MODULATION
(I/Q MODE)
In I/Q mode, the input impedance of the baseband pins (I_P,
I_N, Q_P, and Q_N) are 100 Ω differential. These inputs can be
loaded with a dc-coupled 100 Ω differential load. I_P and I_N
are the differential baseband I inputs, and Q_P and Q_N are the
differential baseband Q inputs. These inputs can operate from a
VCM of 0 V to 2.6 V. T h e b aseband I/Q ports can operate from
dc to 6.0 GHz at each I and Q channel.
To set the ADMV1013 in I/Q mode, set MIXER_IF_EN bit
(Register 0x03, Bit 7) to 0.
When changing the external VCM, the internal mixer gate
voltage also must be changed. To make this change, set the
MIXER_VGATE bits (Register 0x05, Bits[6:0]). The MIXER_
VGATE value follows the VCM such as, that for a 0 V to 1.8 V
VCM, MIXER_VGATE = 23.89 VCM + 81, and for a >1.8 V to
2.6 V VCM, MIXER_VGATE = 23.75 VCM + 1.25.
SINGLE-SIDEBAND UPCONVERSION (IF MODE)
The ADMV1013 features the ability to upconvert a real IF input
anywhere from 0.8 GHz to 6.0 GHz while suppressing the
unwanted sideband by typically better than 26 dBc. The IF
inputs are quadrature to each other, 50 Ω single ended, and are
internally dc-coupled. IF_I and IF_Q are the quadrature IF inputs.
An external 90° hybrid is required to select the appropriate
sideband. To configure the ADMV1013 in IF mode, set the
MIXER_IF_EN bit (Register 0x03, Bit 7) to 1. The MIXER_IF_EN
bit defaults to IF mode on SPI startup and reset.
In addition, the baseband pins (I_P, I_N, Q_P, and Q_N) must
see an open load for optimum performance in IF mode.
LO INPUT PATH
The LO input path operates from 5.4 GHz to 10.25 GHz with
an LO amplitude range of −6 dBm to +6 dBm. The LO has an
internal quadrupler (×4) and a programmable band-pass filter.
The LO band-pass filter is programmable using the QUAD_
FILTERS bits (Register 0x09, Bits[3:0]). See the Performance at
Different Quad Filter Settings section for more information on
the QUAD_FILTERS settings.
The LO path can operate either differentially or single ended.
LOP and LON are the inputs to the LO path. The LO path can
switch from differential to single-ended operation by setting the
QUAD_SE_MODE bits (Register 0x09, Bits[9:6]). See the
Performance Between Differential vs. Single-Ended LO Input
section for more information. When using the LO as single
ended, the unused LO input pin must be terminated with a
50 Ω load.
Figure 81 shows a block diagram of the LO path.
AMP 4 × LON
4 × LOP
LON
LOP ×4
17267-105
Figure 81. LO Path Block Diagram
Enable the quadrupler by setting the QUAD_PD bits
(Register 0x03, Bits[13:11]) to 0x0. To power down the
quadrupler, set these bits to 0x7.
SIDEBAND SUPPRESSION OPTIMIZATION
Unwanted sideband can be upconverted from the quadrature
error by generating the quadrature LO signals and the external
quadrature inputs. Deviation from ideal quadrature (that is,
total sideband rejection and no sideband tone upconverts) on
these signals limits the amount of achievable sideband rejection.
The ADMV1013 offers approximately 25° of quadrature phase
adjustment in the LO path quadrature signals to suppress the
sideband. Make these adjustments through the LOAMP_PH_
ADJ_I_FINE bits (Register 0x05, Bits[13:7]) and the LOAMP_
PH_ADJ_Q_FINE bits (Register 0x06, Bits[13:7]). These bits
reject the unwanted sideband signal. To achieve the required
sideband suppression, it may be necessary to adjust the
amplitude difference between the quadrature inputs, as well
externally.
In I/Q mode, the recommendation is to adjust the sideband
suppression through the external transceiver digital-to-analog
converter (DAC).
ADMV1013 Data Sheet
Rev. B | Page 26 of 39
CARRIER FEEDTHROUGH NULLING
Carrier feedthrough results from minute dc offsets that occur
on the internal mixer. In an I/Q modulator, nonzero differential
offsets mix with the LO and result in carrier feedthrough to the
RF output. In addition to this effect, some of the signal power at
the LO input couples directly to the RF output (this may be
because of the bond wire to bond wire coupling or coupling
through the silicon substrate). The net carrier feedthrough at
the RF output is the vector combination of the signals that appear
at the output because of these two effects.
The ADMV1013 offers, in IF mode, LO feedthrough offset
calibration adjustment in the LO path. Make these adjustments
through the MXER_OFF_ADJ_I_N bits (Register 0x07,
Bits[8:2], the MXER_OFF_ADJ_I_P bits (Register 0x07,
Bits[15:9]), the MXER_OFF_ADJ_Q_N bits (Register 0x08,
Bits[8:2]), and the MXER_OFF_ADJ_Q_P bits (Register 0x08,
Bits[15:9] in order to reject the unwanted LO signal.
For I/Q mode, the LO feedthrough offset amplitude and phase
calibration optimization can be adjusted externally through a
transceiver DAC.
ENVELOPE DETECTOR
The ADMV1013 features an envelope detector with a pseudo
differential voltage output. The envelope detector output pins
are VENV_P and VENV_N. The ADMV1013 turns on with the
envelope detector turned off. To turn on the envelope detector,
set the DET_EN bit (Bit 5, Register 0x03). The differential voltage
output of the envelope detector rises linearly to the square of
the input envelope voltage to the detector. The detector output
ranges from −45 dBm to −20 dBm when the input two tone
power ranges from −20 dBm to 0 dBm. The envelope detector
has 350 MHz, 3 dB envelope bandwidth and 1 GHz, 10 dB
envelope bandwidth. The envelope detector precedes the VVA
and the output driver of the ADMV1013.
POWER DOWN AND RESET
The SPI of the ADMV1013 allows the user to power down the
device circuits and reduce power consumption to typically 77 mW.
To turn off the entire chip, set the BG_PD bit (Register 0x03,
Bit 10) to 1. In addition, individual blocks of the circuit can be
powered down individually. To power down the quadrupler,
set the QUAD_PD bits (Register 0x03, Bits[13:11]) to 0x7. To
power down the VGA, set the VGA_PD bit (Register 0x03,
Bit 15) to 1. To power down the mixer, set the MIXER_PD bit
(Register 0x03, Bit 14) to 1. To power down the detector, set the
DET_EN bit (Register 0x03, Bit 5) to 0.
SERIAL PORT INTERFACE (SPI)
The SPI of the ADMV1013 allows the user to configure the device
for specific functions or operations via a 4-wire SPI port. This
interface provides users with added flexibility and customization.
The SPI consists of four control lines: SCLK, SDI, SDO, and
active low chip select lines, SEN/SEN2. SEN and SEN2 must be
connected together.
The ADMV1013 protocol consists of a write/read bit followed
by six register address bits, 16 data bits, and a parity bit. Both
the address and data fields are organized MSB first and end with
the LSB. For a write, set the first bit to 0. For a read, set the first
bit to 1.
The write cycle sampling must be performed on the rising edge.
The 16 bits of the serial write data are shifted in, MSB to lower
sideband. The ADMV1013 input logic level for the write cycle
supports a 1.8 V interface.
For a read cycle, up to 16 bits of serial read data are shifted out,
MSB first. After the 16 bits of data shift out, the parity bit shifts
out. The output logic level for a read cycle is 1.8 V.
The parity bit always follows the direction of the data. If parity
is not used, the transmitting end transmits zero instead of parity.
The parity is odd, which means that the total number of ones
transmitted during a command, including the read/write bit,
the address bit, the data bit, and the parity bit, must be odd.
Figure 82 and Figure 83 show the SPI write and read protocol,
respectively.
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCLK
SDI D11R/W A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 PD10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
17267-107
SEN/SEN2
Figure 82. SPI Write Timing Diagram
ADMV1013 Data Sheet
Rev. B | Page 28 of 39
APPLICATIONS INFORMATION
BASEBAND QUADRATURE MODULATION FROM
LOW FREQUENCIES
Figure 84 shows the I/Q mode performance at low baseband
input frequencies. The measurements were performed at 28
GHz, −10 dBm input power, VCM = 0 V, Register 0x03, Bit 7 = 0,
0 dBm LO input power, and TA = 25°C.
0
5
10
15
20
25
30
35
40
45
1 10 100 1k 10k 100k 1M 10M 100M
CONVERSION GAIN (dB) AND
SIDEBAND REJECTION (dBc)
17267-087
BASEBAND FREQUENCY (Hz)
SIDEBAND REJECTION
CONVERSION GAIN
Figure 84. Conversion Gain and Sideband Rejection vs. Baseband Frequency
PERFORMANCE AT DIFFERENT QUAD FILTER
SETTINGS
Figure 85 shows the conversion gain vs. RF frequency in
IF mode at TA = 25°C and LO input power = 0 dBm for
different QUAD_FILTERS settings.
–10
–8
–6
–4
–2
0
2
4
6
8
10
12
14
16
18
20
22
24
23 25 27 29 31 33 35 37 39 41 43 45
CONVERSION GAIN (dB)
RF FREQUENCY (GHz)
QUAD FILTERS = 0
QUAD FILTERS = 5
QUAD FILTERS = 10
QUAD FILTERS = 15
17267-088
Figure 85. Conversion Gain vs. RF Frequency for Four Different
QUAD_FILTERS Settings, fIF = 3.5 GHz (Upper Sideband)
Figure 86 shows the 4× LO to RF leakage vs. 4× LO frequency at
different quad filter settings.
–60
–55
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48
4× LO TO RF LEAKAGE (dB
m
)
4× LO FREQUENCY (GHz)
QUAD FILTERS = 0
QUAD FILTERS = 5
QUAD FILTERS = 10
QUAD FILTERS = 15
17267-089
Figure 86. 4× LO to RF Leakage vs. 4× LO Frequency for Four Different
QUAD_FILTERS Settings
VVA TEMPERATURE COMPENSATION
Figure 87 shows the conversion gain vs. RF frequency at two
different Register 0x0A settings, the recommended setting
(0xE700) and a setting for higher gain, and three different
temperatures for IF mode. The recommended value suggested
in the Start-Up Sequence section provides the least variation in
conversion gain over temperature. If the priority is to increase
the conversion gain, Register 0x0A can be set to 0xFA00.
However, at this value, the conversion gain variation over
temperature can increase by 2 dB.
0
2
4
6
8
10
12
14
16
18
20
22
24
26
23 25 27 29 31 33 35 37 39 41 43 45
CONVERSION GAIN (dB)
RF FREQUENCY (GHz)
–40°C, 0xFA00
+25°C, 0xFA00
+85°C, 0xFA00
–40°C, 0xE700
+25°C, 0xE700
+85°C, 0xE700
17267-090
Figure 87. Conversion Gain vs. RF Frequency at Maximum Gain for
Various Temperatures and Register 0x0A Settings (Recommended and
Higher Gain Setting), fIF = 3.5 GHz
Data Sheet ADMV1013
Rev. B | Page 29 of 39
Figure 88 shows the conversion gain vs. RF frequency at two
different Register 0x0A settings, the recommended setting and
the default setting, and three different temperatures for IF mode.
The default values provides slightly less gain and a larger gain
variation across temperature compared to the recommended
setting.
0
2
4
6
8
10
12
14
16
18
20
22
24
28
26
23 25 27 29 31 33 35 37 39 41 43 45
CONVERSION GAIN (dB)
RF FREQUENCY (GHz)
–40°C, 0xE700
+25° C, 0xE700
+85° C, 0xE700
–40°C, 0x0000
+25° C, 0x0000
+85° C, 0x0000
17267-091
Figure 88. Conversion Gain vs. RF Frequency at Maximum Gain for
Various Temperatures and Register 0x0A Settings (Default and
Recommended Register 0x0A Settings), fIF = 2 GHz
PERFORMANCE BETWEEN DIFFERENTIAL vs.
SINGLE-ENDED LO INPUT
Figure 89 to Figure 91 show the conversion gain, output IP3, and
sideband rejection performance for operating the ADMV1013 LO
input as differential vs. single ended. The measurements were
performed with 0 dBm LO input power, IF mode, with an IF
frequency of 3.5 GHz, upper sideband, and TA = 25°C.
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
23 25 27 29 31 33 35 37 39 41 43 45
CONVERSION GAIN (dB)
RF FREQUENCY (GHz)
17267-092
SINGLE-ENDE
D POSITIVE SI DE DISABLE
SINGLE-ENDED NEGATIVE SI DE DISABLE
DIFFERENTIAL
Figure 89. Conversion Gain vs. RF Frequency for Three Different LO Mode
Settings, fIF = 3.5 GHz (Upper Sideband)
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
23 25 27 29 31 33 35 37 39 41 43 45
OUTPUT IP3(dBm)
RF FREQUENCY (GHz)
17267-093
SINGLE-ENDED POSIT I VE SI DE DISABLE
SINGLE-ENDED NEGATIVE SIDE DISABLE
DIFFERENTIAL
Figure 90. Output IP3 vs. RF Frequency for Three Different LO Mode Settings,
RF Amplitude = −20 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz
(Upper Sideband)
0
5
10
15
20
25
30
35
40
23 25 27 29 31 33 35 37 39 41 43 45
SIDE BAND RE JE CTI ON (dBc)
RF FREQUENCY (GHz)
SINGLE-ENDED POSIT I VE SI DE DISABLE
SINGLE-ENDED NEGATIVE SI DE DISABLE
DIFFERENTIAL
17267-094
Figure 91. Sideband Rejection vs. RF Frequency for Three Different LO Mode
Settings, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing,
fIF = 3.5 GHz (Upper Sideband)
ADMV1013 Data Sheet
Rev. B | Page 30 of 39
PERFORMANCE ACROSS RF FREQUENCY AT FIXED
INPUT FREQUENCIES
The ADMV1013 quadrupler operates from 21.6 GHz to 41 GHz.
When using the lower sideband, the conversion gain starts
rolling off gradually after the quadrupler frequency reaches
41 GHz. When using the upper sideband, the conversion gain
starts rolling off when the quadrupler frequency is 21.6 GHz.
Figure 92 and Figure 93 show the conversion gain vs. RF frequency
in IF mode for fixed IF frequencies (TA = 25°C, LO = 0 dBm) for
the upper sideband and lower sideband, respectively.
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
23 25 27 29 31 33 35 37 39 41 43 45
CONVERSION GAIN (dB)
RF FREQUENCY (GHz)
0.8GHz UPPE R S IDEBAND
1GHz UP PE R S IDEBAND
2GHz UPPE R S IDEBAND
3GHz UPPE R S IDEBAND
4GHz UP PE R S IDEBAND
5GHz UPPE R S IDEBAND
6GHz UPPE R S IDEBAND
7GHz UPP E R S IDEBAND
17267-095
Figure 92. Conversion Gain vs. RF Frequency for Multiple IF Frequency
Settings (Upper Sideband)
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
23 25 27 29 31 33 35 37 39 41 43 45
CONVERSION GAIN (dB)
RF FREQUENCY (GHz)
0.8GHz LOW E R S IDEBAND
1GHz LOWER S IDEBAND
2GHz LOW E R S IDEBAND
3GHz LOW E R S IDEBAND
4GHz LOW E R S IDEBAND
5GHz LOW E R S IDEBAND
6GHz LOW E R S IDEBAND
7GHz LOW E R S IDEBAND
17267-096
Figure 93. Conversion Gain vs. RF Frequency at Multiple IF Frequency
Settings (Lower Sideband)
Figure 94 and Figure 95 show the conversion gain vs. RF
frequency in I/Q mode for multiple baseband (BB) frequencies
(TA = 25°C, LO = 0 dBm) for upper sideband and lower
sideband, respectively.
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
23 25 27 29 31 33 35 37 39 41 43 45
CONVERSION GAIN (dB)
RF FREQUENCY (GHz)
17267-097
I/Q, 0.8GHz
I/Q, 1GHz
I/Q, 2GHz
I/Q, 3GHz
I/Q, 4GHz
I/Q, 5GHz
I/Q, 6GHz
Figure 94. Conversion Gain vs. RF Frequency for Multiple Baseband
Frequency Settings (Upper Sideband)
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
23 25 27 29 31 33 35 37 39 41 43 45
CONVERSION GAIN (dB)
RF FREQUENCY (GHz)
I/Q, 0.8GHz
I/Q, 1GHz
I/Q, 2GHz
I/Q, 3GHz
I/Q, 4GHz
I/Q, 5GHz
I/Q, 6GHz
17267-098
Figure 95. Conversion Gain vs. RF Frequency at Multiple Baseband Frequency
Settings (Lower Sideband)
Data Sheet ADMV1013
Rev. B | Page 31 of 39
PERFORMANCE ACROSS COMMON-MODE
VOLTAGE IN I/Q MODE
Figure 96, Figure 97, and Figure 98 show the performance at
various common-mode voltages in I/Q mode. For each
common-mode voltage, the mixer gate voltage was changed
based on the equation described in the Baseband Quadrature
Modulation (I/Q Mode) section.
0
5
10
15
20
25
30
23 25 27 29 31 33 35 37 39 41 43 45
CONVE RS IO N GAI N ( dB)
RF FREQ UE NCY ( GHz)
0V
0.4V
1.0V
1.2V
1.4V
1.8V
2.0V
2.4V
2.6V
17267-099
Figure 96. Conversion Gain vs. RF Frequency at Multiple Common-Mode
Voltages in I/Q Mode (fBB = 100 MHz, LO = 0 dBm, TA = 25°C)
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
23 25 27 29 31 33 35 37 39 41 43 45
RF FREQ UE NCY ( GHz)
OUTPUT IP3 ( dBm)
0V
0.4V
1.0V
1.2V
1.4V
1.8V
2.0V
2.4V
2.6V
17267-100
Figure 97. Output IP3 vs. RF Frequency at Multiple Common-Mode Voltages
in I/Q Mode (fBB = 100 MHz, LO = 0 dBm, TA = 25°C)
23 25 27 29 31 33 35 37 39 41 43 45
RF FREQ UE NCY ( GHz)
17267-101
0
2
4
6
8
10
12
14
16
18
20
0V
0.2V
0.4V
0.6V
0.8V
1.0V
1.2V
1.4V
1.6V
1.8V
2.0V
2.2V
2.4V
2.6V
OUTPUT P 1dB (dBm)
Figure 98. Output P1dB vs. RF Frequency at Multiple Common-Mode
Voltages in I/Q Mode (fBB = 100 MHz, LO = 0 dBm, TA = 25°C)
OPERATING VCTRL1 AND VCTRL2 INDEPENDENTLY
The data shown in the Specifications section and the Typical
Performance Characteristics section is based on the VCTRL1
and VCTRL2 voltages being equal. Finer gain regulation can be
obtained if VCTRL1 and VCTRL2 are used separately. Operating
VCTRL1 and VCTRL2 also allows either maintaining IP3 or
noise figure performance while attenuating the RF output.
Figure 99, Figure 102, and Figure 105 show the conversion gain,
input IP3, and noise figure vs. the RF frequency, respectively (IF =
2 GHz, upper sideband, LO = 0 dBm at TA = 25°C), when
VCTRL1 is equal to VCTRL2.
Figure 100, Figure 103, and Figure 106 show the conversion
gain, input IP3, and noise figure vs. the RF frequency, respectively
(IF = 2 GHz, upper sideband, LO = 0 dBm at TA = 25°C), when
VCTRL2 is held at a minimum attenuation and VCTRL1 is
changed.
Figure 101, Figure 104, and Figure 107 show the conversion
gain, input IP3, and noise figure vs. the RF frequency, respectively
(IF = 2 GHz, upper sideband, LO = 0 dBm at TA = 25°C), when
VCTRL1 is held at minimum attenuation and VCTRL2
is changed.
–40
–50
–60
–30
–20
–10
0
10
20
30
VCTRL1 = 0V, VCTRL2 = 0V
VCTRL1 = 0.1V, VCTRL2 = 0.1V
VCTRL1 = 0.2V, VCTRL2 = 0.2V
VCTRL1 = 0.3V, VCTRL2 = 0.3V
VCTRL1 = 0.4V, VCTRL2 = 0.4V
VCTRL1 = 0.5V, VCTRL2 = 0.5V
VCTRL1 = 0.6V, VCTRL2 = 0.6V
VCTRL1 = 0.7V, VCTRL2 = 0.7V
VCTRL1 = 0.8V, VCTRL2 = 0.8V
VCTRL1 = 0.9V, VCTRL2 = 0.9V
VCTRL1 = 1.0V, VCTRL2 = 1.0V
VCTRL1 = 1.1V, VCTRL2 = 1.1V
VCTRL1 = 1.2V, VCTRL2 = 1.2V
VCTRL1 = 1.3V, VCTRL2 = 1.3V
VCTRL1 = 1.4V, VCTRL2 = 1.4V
VCTRL1 = 1.5V, VCTRL2 = 1.5V
VCTRL1 = 1.6V, VCTRL2 = 1.6V
VCTRL1 = 1.7V, VCTRL2 = 1.7V
VCTRL1 = 1.8V, VCTRL2 = 1.8V
23 25 27 29 31 33 35 37 39 41 43 45
CONVE RS IO N GAI N ( dB)
RF FREQ UE NCY ( GHz)
17267-102
Figure 99. Conversion Gain vs. RF Frequency at Various VCTRL Voltages
(VCTRL1 = VCTRL2), IF Mode, IF Frequency = 2 GHz, Upper Sideband
–40
–30
–20
–10
0
10
20
30
23 25 27 29 31 33 35 37 39 41 43 45
CONVERSION GAIN (dB)
RF FREQUENCY (GHz)
VCTRL1 = 0V
VCTRL1 = 0.1V
VCTRL1 = 0.2V
VCTRL1 = 0.3V
VCTRL1 = 0.4V
VCTRL1 = 0.5V
VCTRL1 = 0.6V
VCTRL1 = 0.7V
VCTRL1 = 0.8V
VCTRL1 = 0.9V
VCTRL1 = 1.0V
VCTRL1 = 1.1V
VCTRL1 = 1.2V
VCTRL1 = 1.3V
VCTRL1 = 1.4V
VCTRL1 = 1.5V
VCTRL1 = 1.6V
VCTRL1 = 1.7V
VCTRL1 = 1.8V
17267-103
Figure 100. Conversion Gain vs. RF Frequency at Various VCTRL1 Voltages
(VCTRL2 = 1.8 V), IF Mode, IF Frequency = 2 GHz, Upper Sideband
ADMV1013 Data Sheet
Rev. B | Page 32 of 39
–40
–30
–20
–10
0
10
20
30
23 25 27 29 31 33 35 37 39 41 43 45
CONVERSION GAIN (dB)
RF FREQUENCY (GHz)
VCTRL2 = 0V
VCTRL2 = 0.1V
VCTRL2 = 0.2V
VCTRL2 = 0.3V
VCTRL2 = 0.4V
VCTRL2 = 0.5V
VCTRL2 = 0.6V
VCTRL2 = 0.7V
VCTRL2 = 0.8V
VCTRL2 = 0.9V
VCTRL2 = 1.0V
VCTRL2 = 1.1V
VCTRL2 = 1.2V
VCTRL2 = 1.3V
VCTRL2 = 1.4V
VCTRL2 = 1.5V
VCTRL2 = 1.6V
VCTRL2 = 1.7V
VCTRL2 = 1.8V
17267-104
Figure 101. Conversion Gain vs. RF Frequency at Various VCTRL2 Voltages
(VCTRL1 = 1.8 V), IF Mode, IF Frequency = 2 GHz, Upper Sideband
–10
–5
0
5
10
15
20
23 25 27 29 31 33 35 37 39 41 43 45
INPUT IP3 (dBm)
RF FREQUENCY (GHz)
17267-115
VCTRL1 = 0V, VCTRL2 = 0V
VCTRL1 = 0.1V, VCTRL2 = 0.1V
VCTRL1 = 0.2V, VCTRL2 = 0.2V
VCTRL1 = 0.3V, VCTRL2 = 0.3V
VCTRL1 = 0.4V, VCTRL2 = 0.4V
VCTRL1 = 0.5V, VCTRL2 = 0.5V
VCTRL1 = 0.6V, VCTRL2 = 0.6V
VCTRL1 = 0.7V, VCTRL2 = 0.7V
VCTRL1 = 0.8V, VCTRL2 = 0.8V
VCTRL1 = 0.9V, VCTRL2 = 0.9V
VCTRL1 = 1.0V, VCTRL2 = 1.0V
VCTRL1 = 1.1V, VCTRL2 = 1.1V
VCTRL1 = 1.2V, VCTRL2 = 1.2V
VCTRL1 = 1.3V, VCTRL2 = 1.3V
VCTRL1 = 1.4V, VCTRL2 = 1.4V
VCTRL1 = 1.5V, VCTRL2 = 1.5V
VCTRL1 = 1.6V, VCTRL2 = 1.6V
VCTRL1 = 1.7V, VCTRL2 = 1.7V
VCTRL1 = 1.8V, VCTRL2 = 1.8V
Figure 102. Input IP3 vs. RF Frequency at Various VCTRL Voltages (VCTRL1 =
VCTRL2), I IF Mode, IF Frequency = 2 GHz, Upper Sideband
–10
–5
0
5
10
15
20
23 25 27 29 31 33 35 37 39 41 43 45
INPUT IP3 (dBm)
RF FREQUENCY (GHz)
17267-116
VCTRL1 = 0V,
VCTRL1 = 0.1V
VCTRL1 = 0.2V
VCTRL1 = 0.3V
VCTRL1 = 0.4V
VCTRL1 = 0.5V
VCTRL1 = 0.6V
VCTRL1 = 0.7V
VCTRL1 = 0.8V
VCTRL1 = 0.9V
VCTRL1 = 1.0V
VCTRL1 = 1.1V
VCTRL1 = 1.2V
VCTRL1 = 1.3V
VCTRL1 = 1.4V
VCTRL1 = 1.5V
VCTRL1 = 1.6V
VCTRL1 = 1.7V
VCTRL1 = 1.8V
Figure 103. Input IP3 vs. RF Frequency at Various VCTRL1 Voltages (VCTRL2 =
1.8 V), IF Mode, IF Frequency = 2 GHz, Upper Sideband
–10
–5
0
5
10
15
20
23 25 27 29 31 33 35 37 39 41 43 45
INPUT IP3 (dBm)
RF FREQUENCY (GHz)
17267-117
VCTRL2 = 0V
VCTRL2 = 0.1V
VCTRL2 = 0.2V
VCTRL2 = 0.3V
VCTRL2 = 0.4V
VCTRL2 = 0.5V
VCTRL2 = 0.6V
VCTRL2 = 0.7V
VCTRL2 = 0.8V
VCTRL2 = 0.9V
VCTRL2 = 1.0V
VCTRL2 = 1.1V
VCTRL2 = 1.2V
VCTRL2 = 1.3V
VCTRL2 = 1.4V
VCTRL2 = 1.5V
VCTRL2 = 1.6V
VCTRL2 = 1.7V
VCTRL2 = 1.8V
Figure 104. Input IP3 vs. RF Frequency at Various VCTRL2 Voltages (VCTRL1 =
1.8 V), IF Mode, IF Frequency = 2 GHz, Upper Sideband
0
5
10
15
20
25
30
35
40
45
50
55
60
23 25 27 29 31 33 35 37 39 41 43 45
NOISE FIGURE (dB)
RF FREQUENCY (GHz)
17267-118
VCTRL1 = 0V, VCTRL2 = 0V
VCTRL1 = 0.1V, VCTRL2 = 0.1V
VCTRL1 = 0.2V, VCTRL2 = 0.2V
VCTRL1 = 0.3V, VCTRL2 = 0.3V
VCTRL1 = 0.4V, VCTRL2 = 0.4V
VCTRL1 = 0.5V, VCTRL2 = 0.5V
VCTRL1 = 0.6V, VCTRL2 = 0.6V
VCTRL1 = 0.7V, VCTRL2 = 0.7V
VCTRL1 = 0.8V, VCTRL2 = 0.8V
VCTRL1 = 0.9V, VCTRL2 = 0.9V
VCTRL1 = 1.0V, VCTRL2 = 1.0V
VCTRL1 = 1.1V, VCTRL2 = 1.1V
VCTRL1 = 1.2V, VCTRL2 = 1.2V
VCTRL1 = 1.3V, VCTRL2 = 1.3V
VCTRL1 = 1.4V, VCTRL2 = 1.4V
VCTRL1 = 1.5V, VCTRL2 = 1.5V
VCTRL1 = 1.6V, VCTRL2 = 1.6V
VCTRL1 = 1.7V, VCTRL2 = 1.7V
VCTRL1 = 1.8V, VCTRL2 = 1.8V
Figure 105. Noise Figure vs. RF Frequency at Various VCTRL Voltages (VCTRL1 =
VCTRL2), IF Mode, IF Frequency = 2 GHz, Upper Sideband
0
5
10
15
20
25
30
35
40
45
50
55
60
23 25 27 29 31 33 35 37 39 41 43 45
NOISE FIGURE (dB)
RF FREQUENCY (GHz)
17267-119
VCTRL1 = 0V
VCTRL1 = 0.1V
VCTRL1 = 0.2V
VCTRL1 = 0.3V
VCTRL1 = 0.4V
VCTRL1 = 0.5V
VCTRL1 = 0.6V
VCTRL1 = 0.7V
VCTRL1 = 0.8V
VCTRL1 = 0.9V
VCTRL1 = 1.0V
VCTRL1 = 1.1V
VCTRL1 = 1.2V
VCTRL1 = 1.3V
VCTRL1 = 1.4V
VCTRL1 = 1.5V
VCTRL1 = 1.6V
VCTRL1 = 1.7V
VCTRL1 = 1.8V
Figure 106. Noise Figure vs. RF Frequency at Various VCTRL1 Voltages
(VCTRL2 = 1.8 V), IF Mode, IF Frequency = 2 GHz, Upper Sideband
Data Sheet ADMV1013
Rev. B | Page 33 of 39
0
5
10
15
20
25
30
35
40
45
50
55
60
23 25 27 29 31 33 35 37 39 41 43 45
NOISE FIGURE (dB)
RF FREQUENCY (GHz)
17267-120
VCTRL2 = 0V
VCTRL2 = 0.1V
VCTRL2 = 0.2V
VCTRL2 = 0.3V
VCTRL2 = 0.4V
VCTRL2 = 0.5V
VCTRL2 = 0.6V
VCTRL2 = 0.7V
VCTRL2 = 0.8V
VCTRL2 = 0.9V
VCTRL2 = 1.0V
VCTRL2 = 1.1V
VCTRL2 = 1.2V
VCTRL2 = 1.3V
VCTRL2 = 1.4V
VCTRL2 = 1.5V
VCTRL2 = 1.6V
VCTRL2 = 1.7V
VCTRL2 = 1.8V
Figure 107. Noise Figure vs. RF Frequency at Various VCTRL2 Voltages
(VCTRL1 = 1.8 V), IF Mode, IF Frequency = 2 GHz, Upper Sideband
RECOMMENDED LAND PATTERN
Solder the exposed pad on the underside of the ADMV1013 to a
low thermal and electrical impedance ground plane. This pad is
typically soldered to an exposed opening in the solder mask on
the evaluation board. Connect these ground vias to all other
ground layers on the evaluation board to maximize heat
dissipation from the device package.
17267-126
Figure 108. Evaluation Board Layout for the LGA Package
EVALUATION BOARD INFORMATION
For more information about the ADMV1013 evaluation board,
refer to the ADMV1013-EVALZ user guide.
ADMV1013 Data Sheet
Rev. B | Page 34 of 39
REGISTER SUMMARY
Table 6.
Reg.
(Hex) Register Name Bits
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reset R/W
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
00 SPI_CONTROL [15:8] PARITY_EN SPI_SOFT_
RESET
RESERVED CHIP_ID 0x00A4 R/W
[7:0] CHIP_ID REVISION
01 ALARM [15:8] PARITY_
ERROR
TOO_FEW_
ERRORS
TOO_MANY_
ERRORS
ADDRESS_
RANGE_
ERROR
RESERVED 0x0000 R
[7:0] RESERVED
02 ALARM_MASKS [15:8] PARITY_
ERROR_
MASK
TOO_FEW_
ERRORS_
MASK
TOO_MANY_
ERRORS_
MASK
ADDRESS_
RANGE_
ERROR_MASK
RESERVED 0xFFFF R/W
[7:0] RESERVED
03 ENABLE [15:8] VGA_PD MIXER_PD QUAD_PD BG_PD RESERVED 0x01D7 R/W
[7:0] MIXER_IF_EN RESERVED DET_EN RESERVED
05
LO_AMP_I
[15:8]
RESERVED
LOAMP_PH_ADJ_I_FINE
0x5051
R/W
[7:0] LOAMP_
PH_ADJ_
I_FINE
MIXER_VGATE
06 LO_AMP_Q [15:8] RESERVED LOAMP_PH_ADJ_Q_FINE 0x5000 R/W
[7:0]
LOAMP_
PH_ADJ_
Q_FINE
RESERVED
07 OFFSET_ADJUST_I [15:8] MXER_OFF_ADJ_I_P MXER_OFF_
ADJ_I_N
0xFFFC R/W
[7:0]
MXER_OFF_ADJ_I_N
RESERVED
08 OFFSET_ADJUST_Q [15:8] MXER_OFF_ADJ_Q_P MXER_OFF_
ADJ_Q_N
0xFFFC R/W
[7:0]
MXER_OFF_ADJ_Q_N[5:0]
RESERVED
09 QUAD [15:8] RESERVED QUAD_SE_MODE 0x5700 R/W
[7:0] QUAD_SE_MODE RESERVED QUAD_FILTERS
0A VVA_TEMPERATURE_
COMPENSATION
[15:8] VVA_TEMPERATURE_COMPENSATION 0x0000 R/W
[7:0] VVA_TEMPERATURE_COMPENSATION
Data Sheet ADMV1013
Rev. B | Page 35 of 39
REGISTER DETAILS
Address: 0x00, Reset: 0x00A4, Name: SPI_CONTROL
Enable the P arity for Write E xecution Revi sion I D
SPI Soft Reset Chip ID
0
0
1
0
2
1
3
0
4
0
5
1
6
0
7
1
8
0
9
0
10
0
11
0
12
0
13
0
14
0
15
0
[15] PARITY_EN (R/W) [3: 0] REVISION (R)
[14] SPI_SOFT_R ESET (R /W) [11: 4] CHIP_ID (R)
[13:12] RESER V ED
Table 7. Bit Descriptions for SPI_CONTROL
Bits Bit Name Settings Description Reset Access
15 PARITY_EN Enable the Parity for Write Execution 0x0 R/W
14 SPI_SOFT_RESET SPI Soft Reset 0x0 R/W
[13:12] RESERVED Reserved 0x0 R
[11:4] CHIP_ID Chip ID 0xA R
[3:0] REVISION Revision ID 0x4 R
Address: 0x01, Reset: 0x0000, Name: ALARM
Parity Error
T oo Few Error s Address Range Er ror
T oo Many E rror s
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
0
9
0
10
0
11
0
12
0
13
0
14
0
15
0
[15] PARITY_ERROR (R) [11:0] RESERVED
[14] TOO_F EW_ERRORS (R) [12] ADDRESS_RANG E_ERROR (R)
[13] TOO_MANY_ERRORS (R)
Table 8. Bit Descriptions for ALARM
Bits Bit Name Settings Description Reset Access
15 PARITY_ERROR Parity Error 0x0 R
14 TOO_FEW_ERRORS Too Few Errors 0x0 R
13 TOO_MANY_ERRORS Too Many Errors 0x0 R
12 ADDRESS_RANGE_ERRO
R
Address Range Error 0x0 R
[11:0] RESERVED Reserved 0x0 R
Address: 0x02, Reset: 0xFFFF, Name: ALARM_MASKS
Parity Error M ask
T oo Few Error s Mask Address Range Er ror Mask
T oo Many E rror s Mask
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
1
10
1
11
1
12
1
13
1
14
1
15
1
[15] PARITY_ERROR_MASK (R/W) [11:0] RESERVED
[14] TOO_F EW_ERRORS_MASK (R/W) [12] ADDRESS_RANG E _ERROR_MASK (R/W)
[13] TOO_MANY_ERRORS_MASK (R/W)
Table 9. Bit Descriptions for ALARM_MASKS
Bits Bit Name Settings Description Reset Access
15 PARITY_ERROR_MASK Parity Error Mask 0x1 R/W
14 TOO_FEW_ERRORS_MASK Too Few Errors Mask 0x1 R/W
13 TOO_MANY_ERRORS_MASK Too Many Errors Mask 0x1 R/W
12 ADDRESS_RANGE_ERROR_MASK Address Range Error Mask 0x1 R/W
[11:0] RESERVED Reserved 0xFFF R
ADMV1013 Data Sheet
Rev. B | Page 36 of 39
Address: 0x03, Reset: 0x01D7, Name: ENABLE
Power Down the VGA Circuit
Power Down the Mixer Circuit Enable the Envelope Detector
Power Down the Quad
111: Disable LO Quad Circuit.
0: Enable LO Quad Circuit.
Power Down the Transmitter Band Gap
Enable the IF Mode
0
1
1
1
2
1
3
0
4
1
5
0
6
1
7
1
8
1
9
0
10
0
11
0
12
0
13
0
14
0
15
0
[15] VGA_PD (R /W) [4:0] RESERVED
[14] M IX E R_PD (R/W) [5] DE T _ E N (R/W)
[13:11] QUAD_PD (R/W) [6] RESERVED
[10] BG_PD (R/W)
[7] M IX ER_ IF _ EN (R/W)
[9:8] RESERVED
Table 10. Bit Descriptions for ENABLE
Bits Bit Name Settings Description Reset Access
15 VGA_PD Power Down the VGA Circuit 0x0 R/W
14
MIXER_PD
Power Down the Mixer Circuit
0x0
R/W
[13:11] QUAD_PD Power Down the Quad 0x0 R/W
000 Enable LO Quad Circuit
111 Disable LO Quad Circuit
10 BG_PD Power Down the Transmitter Band Gap 0x0 R/W
[9:8] RESERVED Reserved 0x0 R
7
MIXER_IF_EN
Enable the IF Mode
0x1
R/W
6 RESERVED Reserved 0x1 R
5 DET_EN Enable the Envelope Detector 0x0 R/W
[4:0] RESERVED Reserved 0x17 R
Address: 0x05, Reset: 0x5051, Name: LO_AMP_I
Control Mixer G ate Voltage. For 0 V to 1.8
V, MIXER_VGATE = 23.89 x Common-Mode
Voltage +81, and for 1.8 V to 2.6 V, MIXER_VGATE
= 23.75 x Common-Mode Voltage +1.25.
Mixer Image Rejection Calibration
0
1
1
0
2
0
3
0
4
1
5
0
6
1
7
0
8
0
9
0
10
0
11
0
12
1
13
0
14
1
15
0
[15:14] RESERVED [6:0] M IX E R_VGAT E (R/W)
[13:7] LOAMP_PH_ADJ_I_FINE (R/W)
Table 11. Bit Descriptions for LO_AMP_I
Bits Bit Name Settings Description Reset Access
[15:14] RESERVED Reserved. 0x1 R
[13:7] LOAMP_PH_ADJ_I_FINE Mixer Image Rejection Calibration. 0x20 R/W
[6:0] MIXER_VGATE Control Mixer Gate Voltage. For 0 V to 1.8 V, MIXER_VGATE = 23.89 ×
Common-Mode Voltage + 81, and for 1.8 V to 2.6 V, MIXER_VGATE =
23.75 × Common-Mode Voltage + 1.25.
0x51 R/W
Address: 0x06, Reset: 0x5000, Name: LO_AMP_Q
Mixer Image Rejection Calibration
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
0
9
0
10
0
11
0
12
1
13
0
14
1
15
0
[15:14] RESER V ED [6:0] RESERVED
[13:7] LOA M P_PH_ADJ_Q _FINE ( R/W)
Table 12. Bit Descriptions for LO_AMP_Q
Bits
Bit Name
Settings
Description
Reset
Access
[15:14] RESERVED Reserved 0x1 R
[13:7] LOAMP_PH_ADJ_Q_FINE Mixer Image Rejection Calibration 0x20 R/W
[6:0]
RESERVED
Reserved
0x0
R
Data Sheet ADMV1013
Rev. B | Page 37 of 39
Address: 0x07, Reset: 0xFFFC, Name: OFFSET_ADJUST_I
LO Feedthrough Off set Cali brat i on
I Positive for I F Mode
LO Feedthrough Off set Cali brat i on
I Negat i ve f or I F Mode
0
0
1
0
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
1
10
1
11
1
12
1
13
1
14
1
15
1
[15:9] M XER_O FF_ADJ_I_P ( R/W) [1:0] RESERVED
[8:2] M XER_O FF_ADJ_I_N (R/W)
Table 13. Bit Descriptions for OFFSET_ADJUST_I
Bits Bit Name Settings Description Reset Access
[15:9] MXER_OFF_ADJ_I_P LO Feedthrough Offset Calibration I Positive for IF Mode 0x7F R/W
[8:2] MXER_OFF_ADJ_I_N LO Feedthrough Offset Calibration I Negative for IF Mode 0x7F R/W
[1:0] RESERVED Reserved 0x0 R
Address: 0x08, Reset: 0xFFFC, Name: OFFSET_ADJUST_Q
LO Feedthrough Off set Cali brat i on
Q P ositive for IF Mode
LO Feedthrough Off set Cali brat i on
Q Negative f or I F Mode
0
0
1
0
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
1
10
1
11
1
12
1
13
1
14
1
15
1
[15:9] M XER_O FF_ADJ_Q _P (R/ W) [1:0] RESERVED
[8:2] M XER_O FF_ADJ_Q _N (R/ W)
Table 14. Bit Descriptions for OFFSET_ADJUST_Q
Bits
Bit Name
Settings
Description
Reset
Access
[15:9] MXER_OFF_ADJ_Q_P LO Feedthrough Offset Calibration Q Positive for IF Mode 0x7F R/W
[8:2] MXER_OFF_ADJ_Q_N LO Feedthrough Offset Calibration Q Negative for IF Mode 0x7F R/W
[1:0]
RESERVED
Reserved
0x0
R
Address: 0x09, Reset: 0x5700, Name: QUAD
LO Filters Bandwidth Selection
1111: LO Frequency Bandwidth: 5.4 G H z to 7 GHz.
1010: LO Frequency Bandwidth: 5.4 G H z to 8 GHz.
0101: GHz.
LO Frequency Bandwidth: 6.6 G H z to 9.2
0000: GHz.
LO Frequency Bandwidth: 8.62 G H z to 10.25
Switch Differential/Single-Ended Modes
1100: Differential Mode.
1001: Single Ended Mode, P Side Disable.
0110: Single Ended Mode, N Side Disable.
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
1
9
1
10
1
11
0
12
1
13
0
14
1
15
0
[15:10] RESERVED [3:0] QUAD_FILTERS (R/W)
[9:6] QUAD_SE_MODE (R/W)
[5:4] RESERVED
Table 15. Bit Descriptions for QUAD
Bits Bit Name Settings Description Reset Access
[15:10] RESERVED Reserved. 0x15 R
[9:6] QUAD_SE_MODE Switch Differential/Single-Ended Modes. 0xC R/W
0110 Single-Ended Mode, Negative Side Disable.
1001 Single-Ended Mode, Positive Side Disable.
1100 Differential Mode.
[5:4] RESERVED Reserved. 0x0 R
[3:0] QUAD_FILTERS LO Filters Bandwidth Selection. 0x0 R/W
0000
LO Frequency Bandwidth: 8.62 GHz to 10.25 GHz.
0101 LO Frequency Bandwidth: 6.6 GHz to 9.2 GHz.
1010 LO Frequency Bandwidth: 5.4 GHz to 8 GHz.
1111 LO Frequency Bandwidth: 5.4 GHz to 7 GHz.
ADMV1013 Data Sheet
Rev. B | Page 38 of 39
Address: 0x0A, Reset: 0x0000, Name: VVA_TEMPERATURE_COMPENSATION
VVA Temperature Compensation. PARITY_EN
must be disabled when updating the VVA
temperature compensation
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
0
9
0
10
0
11
0
12
0
13
0
14
0
15
0
[15:0] VVA_TEMPERATURE_COMPENSATIO N (R/W)
Table 16. Bit Descriptions for VVA_TEMPERATURE_COMPENSATION
Bits Bit Name Settings Description Reset Access
[15:0] VVA_TEMPERATURE_COMPENSATION VVA Temperature Compensation. PARITY_EN must be
disabled when updating the VVA temperature
compensation. Set to 0xE700 on startup.
0x0 R/W
Data Sheet ADMV1013
Rev. B | Page 39 of 39
OUTLINE DIMENSIONS
02-12-2018-A
PKG-005728
6.10
6.00
5.90
TOP VIEW
SIDE VIEW
BOTTOM VIEW
1
10
11
20
21
30
31 40
0.50
BSC
0.275
BSC 0.165
BSC
0.750
BSC
4.50 REF
SQ 4.77 BSC
0.40
0.35
0.30
0.32
0.27
0.22
0.25
0.22
0.19
0.52
0.45
0.38
0.75 M AX
0.67 NO M
2.22 BSC
SQ
FOR PRO P E R CONNECTI ON O F
THE EXPOSED PADS, REFER TO
THE PIN CO NFI GURAT IO N AND
FUNCTION DES CRIPTI ONS
SECTION OF THIS DATA SHEET.
1.06 BSC
SQ
PIN 1
INDIC
ATOR
PIN 1
CORNE R AREA
SEATING
PLANE
Figure 109. 40-Terminal Land Grid Array Package [LGA]
6 mm × 6 mm Body and 0.67 mm Package Height
(CC-40-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADMV1013ACCZ
−40°C to +85°C 40-Terminal Land Grid Array Package [LGA] CC-40-5
ADMV1013ACCZ-R7 −40°C to +85°C 40-Terminal Land Grid Array Package [LGA] CC-40-5
ADMV1013-EVALZ Evaluation Board
1 Z = RoHS Compliant Part.
©2018–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D17267-0-9/19(B)
