FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI 3.3 Volt Synchronous x18 First-In/First-Out Queue Memory Configuration Device 4,096 x 18 2,048 x 18 1,024 x 18 512 x 18 256 x 18 FQV245 FQV235 FQV225 FQV215 FQV205 Key Features: * * * * * * * * * * * * * Industry leading First-In/First-Out Queues (up to 133MHz) Independent Write and Read cycle time 3.3V power supply 5V input tolerant on all control and data input pins 5V output tolerant on all flags and data output pins Reset clears all previously programmed configurations including Write and Read pointers. Preset for Almost Full ( PRAF ) and Almost Empty ( PRAE ) offsets values Parallel programming of PRAF and PRAE offset values Full, Empty, Almost Full, Almost Empty, and Half Full indicators Asynchronous output enable tri-state data output drivers Available package: 64 - pin Plastic Thin Quad Flat Package (TQFP), 64 - pin Slim Thin Quad Flat Package (STQFP) (0C to 70C) Commercial operating temperature available for cycle time of 7.5ns and above (-40C to 85C) Industrial operating temperature available for cycle time of 10ns and above Product Description: HBA's FlexQTM I offers industry leading FIFO queuing bandwidth (up to 2.4 Gbps), with a wide range of memory configurations (from 256 x 18 to 4,096 x 18). System designer has full flexibility of implementing deeper and wider queues with Write ( WEXI and WEXO ) and Read ( REXI and REXO ) expansion features using daisy chain technique. Full, Empty, and Half Full indicators allow easy handshaking between transmitters and receivers. User programmable Almost Full and Almost Empty (Parallel) indicators allow implementation of virtual queue depths. 5V tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. Asynchronous Output Enable pin configures the tri-state data output drivers. Independent Write and Read controls provide rate-matching capability. Data is written into the queue at the low to high transition of WCLK if WEN is asserted. Data is read from the queue at the low to high transition of RCLK if REN is asserted. Reset clears all previously programmed configurations by providing a low pulse on RST pin. In addition, Write and Read pointers to the queue are initialized to zero. These FlexQTM I devices have low power consumption, hence minimizing system power requirements. In addition, industry standard 64 - pin Plastic TQFP and 64 - pin STQFP are offered to save system board space. These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test equipment, network switching, etc. 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 1 of 1 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI Block Diagram of Single Synchronous Queue 4,096 x 18 / 2 ,048 x 18 / 1,024 x 18 / 512 x 18 / 256 x 18 RESET (RST ) READ CLOCK (RCLK) WRITE CLOCK (WCLK) READ ENABLE ( REN ) WRITE ENABLE ( WEN ) OUTPUT ENABLE (OE ) LOAD ( LOAD ) FQV245 FQV235 FQV225 FQV215 FQV205 DATA IN (D17 - 0) FULL FLAG ( FULL ) DATA OUT (Q17 - 0) EMPTY FLAG ( EMPTY ) PROGRAMMABLE ( PRAF) PROGRAMMABLE ( PRAE) WEXO HALF - FULL FLAG ( HALF ) REXO FIRST LOAD (FIRST ) READ EXPANSION IN (REXI) WRITE EXPANSION IN ( WEXI ) Figure 1. Single Device Configuration Signal Flow Diagram 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 2 of 2 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI WCLK WEN LOAD Write Control Logic FULL / DRDY PRAF Offset Register EMPTY/ QRDY Flag Logic PRAE ( WEXO) / HALF Write Pointer Input Register D17-0 x18 SRAM Output Register Output Buffer Q 17-0 x18 OE Read Pointer FIRST WEXI WEXO /( HALF) Expansion Logic Read Control Logic Reset REXI REXO RCLK REN RST Figure 2. Device Architecture 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 3 of 3 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 OE RST Vcc GND EMPTY Q17 Q16 GND Q15 Vcc 58 57 56 55 54 53 52 51 50 49 RCLK 61 LOAD GND 62 59 D17 63 REN D16 64 FlexQTMI 16 Q14 47 Q13 46 GND 45 Q12 44 Q11 43 Vcc 42 Q10 41 Q9 40 GND 39 Q8 38 Q7 37 Q6 36 Q5 35 GND 34 Q4 33 Vcc 32 D0 48 Q3 15 31 D1 Q2 14 60 30 D2 GND 13 29 D3 Q1 12 28 D4 Q0 11 27 D5 REXO 10 26 D6 WEXO/HALF 9 25 D7 FULL 8 24 D8 REXI 7 23 D9 PRAF 6 22 D10 Vcc 5 21 D11 WEXI 4 20 D12 WEN 3 19 D13 WCLK 2 18 D14 FIRST 1 17 D15 PRAE PIN 1 TQFP - 64 (Drw No: PF-01A; Order Code: PF) STQFP - 64 (Drw No: TF-01A; Order Code: TF) Top View Figure 3. Device Pin Out 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 4 of 4 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI Pin # Pin Name Pin Symbol Input/Output Description 57 Reset RST Input Reset is required to initialize Write and Read pointers to the first position of the queue by setting RST low. FULL and PRAF will go high; EMPTY and PRAE will go low. All data outputs will go low. Previous programmed configurations will not be maintained. 19 Write Clock WCLK Input Writes data into queue during low to high transitions of WCLK if WEN is set low. 20 Write Enable WEN Input Controls write operation into queue or offset registers during low to high transition of WCLK. 59 Load Enable LOAD Input LOAD controls write/read, to/from offset registers during low to high transition of WCLK/RCLK respectively. Use in conjunction with WEN / REN . Input In single device configuration, FIRST is set low. In depth expansion configuration, FIRST is set low for the first device and set high for other devices in the daisy chain. 18 First Load 21 Write Expansion In WEXI Input In single device configuration, WEXI is set low. In depth expansion configuration, WEXI is connected to WEXO of previous device in the daisy chain. 63, 64, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 Data Inputs D17-0 Input 18 - bit wide input data bus. 61 Read Clock RCLK Input Reads data from queue during low to high transitions of RCLK if REN is set low. 60 Read Enable REN Input Controls read operation from queue or offset registers during low to high transition of RCLK. 24 Read Expansion In REXI Input In single device configuration, REXI is set low. In depth expansion configuration, REXI is connected to REXO of previous device in the daisy chain. 58 Output Enable OE Input Setting OE low activates the data output drivers. Setting OE high deactivates the data output drivers (High-Z). 53, 52, 50, 48, 47, 45, 44, 42, 41, 39, 38, 37, 36, 34, 32, 31, 29, 28 Data Outputs Q17-0 Output 18 - bit wide output data bus. 27 Read Expansion Out REXO Output In depth expansion configuration, REXO is connected to REXI of next device in the daisy chain. 25 Full Flag FULL Output Queue is full when FULL goes low during the low to high transition of WCLK. This prohibits further writes into the queue. FIRST Table 1. Pin Descriptions 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 5 of 5 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI Description Pin # Pin Name Pin Symbol Input/Output 54 Empty Flag EMPTY Output Queue is empty when EMPTY goes low during the low to high transition of RCLK. This prohibits further reads from the queue. Output Queue is almost full when PRAF goes low during the low to high transition of WCLK. Default (Full-offset) or programmed offset values determine the status of PRAF . Output Queue is almost empty when PRAE goes low during the low to high transition of RCLK. Default (Empty+offset) or programmed offset values determine the status of PRAE . In single device configuration, queue is more than half full when WEXO / HALF goes low. In depth expansion configuration, WEXO / HALF is connected to WEXI of next device in the daisy chain. 23 17 Almost Full Almost Empty PRAF PRAE 26 Write Expansion Out/Half Full WEXO / HALF Output 22, 33, 43, 49, 56 Power Vcc N/A 3.3V power supply. 30, 35, 40, 46, 51, 55, 62 Ground GND N/A 0V Ground. Table 1. Pin Descriptions (Continued) 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 6 of 6 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI Symbol Rating Com'l & Ind'l Unit VTERM Terminal Voltage with respect to GND -0.5 to + 5.0 V TSTG Storage Temperature -55 to +125 IOUT DC Output Current -50 to +50 C NOTES: Absolute Max Ratings are for reference only. Permanent damage to the device may occur if extended period of operation is outside this range. Standard operation should fall within the Recommended Operating Conditions. mA Table 2. Absolute Maximum Ratings FQV245 FQV235 FQV225 FQV215 FQV205 Commercial Clock = 7.5ns, 10ns, 15ns, 20ns Symbol Parameter Industrial Clock = 10ns, 15ns, 20ns Min. Typ. Max. Min. Typ. Max. Unit 3.0 3.3 3.6 3.0 3.3 3.6 V 0 0 0 0 0 0 V Recommended Operating Conditions VCC Supply Voltage Com'l/Ind'l GND Supply Voltage VIH Input High Voltage Com'l/Ind'l 2.0 - 5.5 2.0 - 5.5 V VIL Input Low Voltage Com'l/Ind'l - - 0.8 - - 0.8 V TA Operating Temperature Commercial 0 - 70 0 - 70 C TA Operating Temperature Industrial -40 - 85 -40 - 85 C DC Electrical Characteristics ILI(1) Input Leakage Current (any input) -10 - 10 -10 - 10 A ILO Output Leakage Current -10 - 10 -10 - 10 A VOH Output Logic "1" Voltage, IOH=-2mA 2.4 - - 2.4 - - V VOL Output Logic "0" Voltage, IOL = 8mA - - 0.4 - - 0.4 V ICC1(2,3) Active Power Supply Current - - 30 - - 30 mA ICC2(4) Standby Current - - 5 - - 5 mA Power Consumption Table 3. DC Specifications 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 7 of 7 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI Capacitance at 1.0 MHz Ambient Temperature (25C) Symbol Parameter CIN(2) Input Capacitance COUT(2,4) Output Capacitance Conditions Max. Unit VIN= 0V 10 pF VOUT= 0V 10 pF NOTES: 1. 2. 3. 4. Measurement with 0.4<=VIN<=Vcc With output tri-stated ( OE = High) Icc(1,2) is measured with WCLK and RCLK at 20 MHz Design simulated, not tested. Table 3. DC Specifications (Continued) 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 8 of 8 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI Commercial & Industrial Commercial Symbol Parameter FQV245-7.5 FQV235-7.5 FQV225-7.5 FQV215-7.5 FQV205-7.5 FQV245-10 FQV235-10 FQV225-10 FQV215-10 FQV205-10 FQV245-15 FQV235-15 FQV225-15 FQV215-15 FQV205-15 FQV245-20 FQV235-20 FQV225-20 FQV215-20 FQV205-20 Min. Max. Min. Max. Min. Max. Min. Max. Unit - 133 - 100 - 66 - 50 MHz fs Clock Cycle Frequency tA Data Access Time 1 5 2 6.5 2 10 2 12 ns tWCLK Write Clock Cycle Time 7.5 - 10 - 15 - 20 - ns tWCLKH Write Clock High Time 3.5 - 4.5 - 6 - 8 - ns tWCLKL Write Clock Low Time 3.5 - 4.5 - 6 - 8 - ns tRCLK Read Clock Cycle Time 7.5 - 10 - 15 - 20 - ns tRCLKH Read Clock High Time 3.5 - 4.5 - 6 - 8 - ns tRCLKL Read Clock Low Time 3.5 - 4.5 - 6 - 8 - ns tDS Data Set-up Time 2.5 - 3 - 4 - 5 - ns tDH Data Hold Time 0.5 - 0.5 - 1 0 1 - ns tENS Enable Set-up Time 2.5 - 3 - 4 - 5 - ns tENH Enable Hold Time 0.5 - 0.5 - 1 - 1 - ns - 10 - 15 - 20 - ns 8 - 10 - 12 - ns (1) tRST Reset Pulse Width 10 tRSTS Reset Set-up Time 8 tRSTR Reset Recovery Time 8 - 8 - 10 - 12 - ns tRSTF Reset to Flag and Output Time - 12 - 15 - 15 - 20 ns 0 - 0 - 0 - 0 - ns 2 5 3 6 3 8 3 10 ns (2) tOLZ Output Enable to Output in Low-Z tOE Output Enable to Output Valid (2) tOHZ Output Enable to Output in High-Z 2 5 3 6 3 8 3 10 ns tFULL Write Clock to Full Flag - 5 - 6.5 - 10 - 12 ns tEMPTY Read Clock to Empty Flag - 5 - 6.5 - 10 - 12 ns tPRAF Clock to Programmable Almost-Full Flag - 13 - 17 - 20 - 22 ns tPRAE Clock to Programmable Almost-Empty Flag - 13 - 17 - 20 - 22 ns tHALF Clock to Half-Full Flag - 13 - 17 - 20 - 22 ns tXO Clock to Expansion Out - 5 - 6.5 - 10 - 12 ns tXI Expansion in Pulse Width 3 - 3 - 6.5 - 8 - ns tXIS Expansion in Set-Up Time 3.5 - 5 - 5 - 8 - ns tSKEW1 Skew time between Read Clock & Write Clock for Full Flag 4 - 5 - 6 - 8 - ns tSKEW2 Skew time between Read Clock & Write Clock for Empty Flag 4 - 5 - 6 - 8 - ns NOTES: 1. 2. Pulse widths less than minimum values are not allowed. Design simulated, not tested. Table 4. AC Electrical Characteristics 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 9 of 9 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns(1) Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load*, clock = 10ns, 15ns, 20ns See Figure 5 Output Load, clock = 7.5ns See Figure 4 *Include jig and scope capacitances Notes: 1. For 133MHz, operation input rise/fall times are 1.5ns. Table 5. AC Test Condition 3.3V Vcc/2 330 50 D.U.T. 30pF* I/O Z0 = 50 Figure 4. AC Test Load for clock = 7.5ns 510 Figure 5. Output Load for clock = 10ns, 15ns, 20ns *Includes jig and scope capacitances. 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 10 of 10 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI Pin Functions RST Reset is required to initialize Write and Read pointers to the first position of the queue by setting RST low. FULL and PRAF will go high; EMPTY and PRAE will go low. All data outputs will go low. Previous programmed configurations will not be maintained. WCLK Writes data into queue during low to high transitions of WCLK if WEN is set low. Synchronizes FULL and PRAF flags. WCLK and RCLK are independent of each other. WEN Controls write operation into queue or offset registers during low to high transition of WCLK. LOAD LOAD controls write/read, to/from offset registers during low to high transition of WCLK/RCLK respectively for parallel programming. Use in conjunction with WEN / REN . FIRST In single device configuration, FIRST is set low. In depth expansion configuration, FIRST is set low for the first device and set high for other devices in the daisy chain. WEXI In single device configuration, WEXI is set low. In depth expansion configuration, WEXI is connected to WEXO of previous device in the daisy chain. D17-0 18 - bit wide input data bus. RCLK Reads data from queue during low to high transitions of RCLK if REN is set low. Synchronizes the EMPTY and PRAE flags. RCLK and WCLK are independent of each other. REN Reads data from queue during low to high transitions of RCLK if REN is set to low. This also advances the Read pointer of the queue. OE Setting OE low activates the data output drivers. Setting OE high deactivates the data output drivers (High-Z). OE does not control advancement of Read pointer. Q17-0 18 - bit wide output data bus. REXO In depth expansion configuration, REXO is connected to REXI of next device in the daisy chain. FULL Queue is full when FULL goes low during the low to high transition of WCLK. This prohibits further writes into the queue and prevents advancement of Write pointer. Refer to Table 8 for behavior of FULL . EMPTY Queue is empty when EMPTY goes low during the low to high transition of RCLK. This prohibits further reads from the queue and prevents advancement of Read pointer. Refer to Table 8 for behavior of EMPTY . PRAF Queue is almost full when PRAF goes low during the low to high transition of WCLK. PRAF goes high during the low to high transition of RCLK. Default (Full-offset) or programmed offset values determine the status of PRAF . Refer to Table 8 for behavior of PRAF . PRAE Queue is almost empty when PRAE goes low during the low to high transition of RCLK. PRAE goes high during the low to high transition of WCLK. Default (Empty+offset) or programmed offset values determine the status of PRAE . Refer to Table 8 for behavior of PRAE . WEXO / HALF In single device configuration, queue is more than half full when HALF goes low during the low to high transition of WCLK. Queue is less than half full when HALF goes high during the low to high transition of RCLK. Refer to Table 8 for details. In depth expansion configuration, WEXO is connected to WEXI of next device in the daisy chain REXI In single device configuration, REXI is set low. In depth expansion configuration, REXI is connected to REXO of previous device in the daisy chain. 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 11 of 11 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI LOAD 0 WEN REN 0 WCLK 1 RCLK X 0 1 0 X X 1 1 X 1 0 X 1 X 0 FQV245 FQV235 FQV225 FQV215 FQV205 Selection / Sequence Parallel write to offset registers: Empty Offset Full Offset Parallel write to registers: 1. PRAE 2. PRAF Parallel read from offset registers: Empty Offset Full Offset Parallel read from registers: 1. PRAE 2. PRAF X No Operation X Write Memory X Read Memory Figure 6. Programmable Flag Offset Programming Sequence Device PRAF Programming (bits) PRAE Programming (bits) FQV245 D/Q11-0 D/Q11-0 FQV235 D/Q10-0 D/Q10-0 FQV225 D/Q9-0 D/Q9-0 FQV215 D/Q8-0 D/Q8-0 FQV205 D/Q7-0 D/Q7-0 Table 6. Parallel Offset Register Data Mapping Table Device Default FQV245 007FH FQV235 007FH FQV225 007FH FQV215 003FH FQV205 001FH Table 7. Default Values of Offset Registers 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 12 of 12 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI FQV245 4,096 x 18 Data Width D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 1st Cycle PRAE 11 10 9 8 7 6 5 4 3 2 1 0 2nd Cycle PRAF 11 10 9 8 7 6 5 4 3 2 1 0 FQV235 2,048 x 18 Data Width D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 1st Cycle PRAE 10 9 8 7 6 5 4 3 2 1 0 2nd Cycle PRAF 10 9 8 7 6 5 4 3 2 1 0 FQV225 1,024 x 18 Data Width D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 1st Cycle PRAE 9 8 7 6 5 4 3 2 1 0 2nd Cycle PRAF 9 8 7 6 5 4 3 2 1 0 FQV215 512 x 18 Data Width D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 1st Cycle PRAE 8 7 6 5 4 3 2 1 0 2nd Cycle PRAF 8 7 6 5 4 3 2 1 0 FQV205 256 x 18 Data Width D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 1st Cycle PRAE 7 6 5 4 3 2 1 0 2nd Cycle PRAF 7 6 5 4 3 2 1 0 # of Bits for Offset Registers 12 bits for FQV245 11 bits for FQV235 10 bits for FQV225 9 bits for FQV215 8 bits for FQV205 Note: Don't Care applies to all unused bits Figure 7. Parallel Offset Write/Read Cycles Diagram 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 13 of 13 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI FQV245 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 2,048 2,049 to [4,096-(x+1)] (4,096 -x(2)) to 4,095 4,096 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H FQV235 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 1,024 1,025 to [2,048-(x+1)] (2,048 -x(2)) to 2,047 2,048 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H FQV225 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 512 513 to [1,024-(x+1)] (1,024 -x(2)) to 1,023 1,024 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H FQV215 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 256 257 to [512-(x+1)] (512 -x(2)) to 511 512 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H FQV205 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 128 129 to [256-(x+1)] (256 -x(2)) to 255 256 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H NOTES: 1. y = PRAE offset. Default Values: FQV205 y = 31, FQV215 y = 63, FQV245/FQV235/FQV225 y = 127. 2. x = PRAF offset. Default Values: FQV205 x = 31, FQV215 x = 63, FQV245/FQV235/FQV225 x = 127. Table 8. Status Flags 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 14 of 14 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI Timing Diagrams tRST RST tRSTS tRSTR REN , WEN , LOAD tRSTF EMPTY , PRAE tRSTF FULL , PRAF , HALF tRSTF OE = 1 Q17 - 0 OE = 0 NOTES: 1. 2. After reset, the outputs will be low if OE = 0 and tri-state if OE =1. The clocks (RCLK, WCLK) can be free-running during reset. Diagram 1. Reset Timing 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 15 of 15 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI tWCLK tWCLKL tWCLKH WCLK tDS tDH D17 - 0 tENH Data Valid tENS No Operation WEN tFULL tFULL FULL tSKEW1 RCLK REN NOTES: 1. tSKEW1 is the minimum time between a rising RCLK edge and rising WCLK edge to guarantee that FULL will go high during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is equal to or less than tSKEW1, then FULL may not change state until the next WCLK edge. Diagram 2. Write Cycle Timing 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 16 of 16 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI tRCLK tRCLKH tRCLKL RCLK tENS tENH REN tEMPTY tEMPTY EMPTY tA Valid Data Q17 - 0 tOLZ tOHZ tOE OE tSKEW1 WCLK WEN NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EMPTY will go high during the current clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EMPTY may not change state until the next RCLK edge. Diagram 3. Read Cycle Timing 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 17 of 17 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI WCLK tDS DW1 D17 - 0 DW3 DW2 DW4 DW5 tENS WEN tSKEW2 tFRL(1) RCLK tEMPTY EMPTY tENS REN tA Q17 - 0 tA DW1 tOLZ DW2 tOE OE NOTES: 1. tFRL is the latency from first write to first Read. When tSKEW2 is greater than or equal to minimum specification, tFRL (maximum) = tRCLK + tSKEW2. When tSKEW2 is less than minimum specification, tFRL (maximum) equals either 2* tRCLK + tSKEW2 or tRCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary ( EMPTY = low). Diagram 4. First Data Word Latency after Reset with Simultaneous Read and Write 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 18 of 18 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI No Write No Write WCLK tDS tSKEW 1(1) tDS tSKEW 1(1) Data Write D17 - 0 tFULL Data Write tFULL tFULL FULL WEN RCLK tENS tENH tENS tENH REN OE LOW tA Q17 - 0 tA Output Register Data Data Read Next Data Read NOTES: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FULL will go high during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FULL may not change state until the next WCLK edge. Diagram 5. Full Flag Timing 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 19 of 19 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI WCLK tDS tDS DW2 DW1 D17 - 0 tENS tENS tENH tENH WEN tSKEW2 RCLK tFRL(1) tSKEW2 tEMPTY tFRL(1) tEMPTY tEMPTY EMPTY REN OE LOW tA Output Register Data Q17 - 0 DW1 NOTES: 1. tFRL is the latency from first write to first Read. When tSKEW2 is greater than or equal to minimum specification, tFRL (maximum) = tRCLK + t SKEW2. When tSKEW2 less than minimum specification, tFRL (maximum) equals either 2 * tRCLK + tSKEW2, or tRCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary ( EMPTY = low). Diagram 6. Empty Flag Timing 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 20 of 20 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI tWCLKH tWCLK tWCLKL WCLK tENS tENH LOAD tENS WEN tDS tDH PRAE offset D11 - 0 PRAE offset PRAF offset PRAF offset Diagram 7. Write Programmable Registers tRCLKH tRCLK tRCLKL RCLK tENS tENH LOAD tENS REN tA Q11 - 0 PRAF offset PRAE offset PRAE offset PRAF offset Diagram 8. Read Programmable Registers tWCLKH tWCLKL WCLK tENS tENH WEN tPRAE PRAE y + 1 words in Queue y words in Queue y words in Queue tPRAE RCLK tENS tENH REN NOTES: 1. y = PRAE offset. Diagram 9. Programmable Almost-Empty Flag Timing 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 21 of 21 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI tWCLKH tWCLKL WCLK tENH tENS WEN tPRAF PRAF D - x words in Queue memory(2) D - (x+1) words in Queue memory(1) D - (x+1) words in Queue memory(1) tPRAF RCLK tENH tENS REN NOTES: 1. 2. x = PRAF offset. D = maximum queue depth = 256 words for FQV205; 512 words for FQV215; 1,024 words for FQV225; 2,048 words for FQV235; and 4,096 words for FQV245. Diagram 10. Programmable Almost-Full Flag Timing tWCLKH tWCLKL WCLK tENS tENH WEN tHALF D/2 + 1 words in Queue memory(2) D/2 words in Queue memory(1) HALF D/2 words in Queue memory(1) tHALF RCLK tENS tENH REN NOTES: 1. D = maximum queue depth = 256 words for FQV205; 512 words for FQV215; 1,024 words for FQV225; 2,048 words for FQV235; and 4,096 words for FQV245. Diagram 11. Half-Full Flag Timing 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 22 of 22 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI WCLK Note 1 tXO tXO WEXO tENS WEN NOTES: 1. Write to Last Physical Location. Diagram 12. Write Expansion Out Timing RCLK Note 1 tXO tXO REXO tENS REN NOTES: 1. Read from Last Physical Location. Diagram 13. Read Expansion Out Timing tXI WEXI tXIS WCLK Diagram 14. Write Expansion in Timing tXI REXI tXIS RCLK Diagram 15. Read Expansion in Timing 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 23 of 23 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI Width Expansion Configuration Simply connecting together the control signals of multiple devices may increase word width. Status flags can be detected from any one device. The exceptions are the Empty Flag and Full Flag. Because of variations in skew between RCLK and WCLK, it is possible for flag assertion and de-assertion to vary by one cycle between FIFOs. To avoid problems the user must create composite flags by ANDing the Empty Flags of every FIFO, and separately ANDing all Full Flags. Figure 8 demonstrates a 36-bit width by using two FQV245 / 235 / 225 / 215 / 205s. Any word width can be attained by adding additional FQV245 / 235 / 225 / 215 / 205s. Block Diagram of Synchronous Queue 4,096 x 36 / 2,048 x 36 / 1,024 x 36 / 512 x 36 / 256 x 36 RESET (RST ) DATA IN (D) 36 RESET (RST ) 18 18 READ CLOCK (RCLK) WRITE CLOCK (WCLK) READ ENABLE (REN ) WRITE ENABLE (WEN ) OUTPUT ENABLE (OE ) LOAD ( LOAD ) PROGRAMMABLE (PRAE ) HALF- FULL (HALF) FULL FULL ( FULL ) PROGRAMMABLE (PRAF) FQV245 FQV235 FQV225 FQV215 FQV205 FQV245 FQV235 FQV225 FQV215 FQV205 EMPTY FULL EMPTY FLAG ( EMPTY) EMPTY 18 DATA OUT (Q) 36 18 FIRST LOAD ( FIRST ) WRITE EXPANSION IN (WEXI ) READ EXPANSION IN ( REXI ) NOTES: 1. Do not connect any output control signals directly together. Figure 8. Width Expansion Configuration 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 24 of 24 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI Depth Expansion Configuration (with Programmable Flags) These devices can easily be adapted to applications requiring more than 4,096 / 2,048 / 1,024 / 512 / 256 words of buffering. Figure 8 shows Depth Expansion using three FQV245 / 235 / 225 / 215 / 205s. Maximum depth is limited only by signal loading. Follow these steps: * The first device must be designated by grounding the First Load ( FIRST ) control input. * All other devices must have FIRST in the high state. * The Write Expansion Out ( WEXO ) pin of each device must be tied to the Write Expansion In ( WEXI ) pin of the next device. * The Read Expansion Out ( REXO ) pin of each device must be tied to the Read Expansion In ( REXI ) pin of the next device. * All Load ( LOAD ) pins are tied together. * The Half-Full Flag ( HALF ) is not available in this Depth Expansion Configuration. * EMPTY , FULL , PRAF , and PRAE are created with composite flags by ORing together every respective flags for monitoring. The composite PRAF and PRAE flags are not precise. Block Diagram of Synchronous Queue 12,288 x 18 / 6,144 x 18 / 3,072 x 18 / 1,536 x 18 / 768 x 18 WEXO REXO WCLK WEN RCLK REN RST FQV245 FQV235 FQV225 FQV215 FQV205 LOAD D OE Q Vcc FIRST FULL EMPTY PRAE PRAF WEXI REXI WEXO WCLK WEN REXO RCLK RST REN FQV245 FQV235 FQV225 FQV215 FQV205 LOAD DATA IN D Vcc OE Q DATA OUT FIRST FULL EMPTY PRAF WEXI PRAE REXI WEXO WRITE CLOCK WRITE ENABLE RESET WEN RCLK RST REN D LOAD FULL PRAF REXO WCLK LOAD FULL PRAF FQV245 FQV235 FQV225 FQV215 FQV205 READ CLOCK READ ENABLE OUTPUT ENABLE OE Q EMPTY PRAE EMPTY PRAE WEXI REXI FIRST LOAD (FIRST ) Figure 9. Block Diagram of Multiple Devices with Programmable Flags used in Depth Expansion Configuration 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. FEBRUARY 2003 Page 25 of 25 FQV245 * FQV235 * FQV225 * FQV215 * FQV205 FlexQTMI Order Information: HBA Device Family Device Type Power Speed (ns)* Package** Temperature Range XX FQ XXXX V245 (4,096 x 18) X LB XX 7-5 - 133 MHz XX PF X Blank - Commercial (0C to 70C) V235 (2,048 x 18 10 - 100 MHz TF I - Industrial (-40 to 85C) V225 (1,024 x 18) 15 - 66 MHz V215 (512 x 18) 20 - 50 MHz V205 (256 x 18) Power - Low (LB) *Speed - 7.5ns available only in Commercial temp (0C to 70C). Slower speeds available upon request. **Package - 64 pin Plastic Thin Quad Flat Pack (TQFP), 64 pin Slim Thin Quad Flat Pack (STQFP) Example: FQV235LB7-5TF FQV225LB10PFI (32k x 18, 7.5ns, Commercial temp) (16k x 18, 10ns, Industrial temp) Document Revision History: 02/06/03 pg. 5, 7, 8, 9, 10, 12, 14 USA 2107 North First Street, Suite 415 San Jose, CA 95131, USA www.hba.com Tel: 408.453.8885 Fax: 408.453.8886 3F118C (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Taiwan No. 81, Suite 8F-9, Shui-Lee Rd. Hsinchu, Taiwan, R.O.C. www.hba.com Tel: 886.3.516.9118 Fax: 886.3.516.9181 FEBRUARY 2003 Page 26 of 26