FQV24
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FEBRUARY 2003
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© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 1 of 1
3.3 Volt Synchronous x18 First-In/First-Out Queue
Memory Configuration Device
4,096 x 18 FQV245
2,048 x 18 FQV235
1,024 x 18 FQV225
512 x 18 FQV215
256 x 18 FQV205
Key Features:
• Industry leading First-In/First-Out Queues (up to 133MHz)
• Independent Write and Read cycle time
• 3.3V power supply
• 5V input tolerant on all control and data input pins
• 5V output tolerant on all flags and data output pins
• Reset clears all previously programmed configurations including Write and Read pointers.
• Preset for Almost Full ( PRAF ) and Almost Empty ( PRAE ) offsets values
• Parallel programming of PRAF and PRAE offset values
• Full, Empty, Almost Full, Almost Empty, and Half Full indicators
• Asynchronous output enable tri-state data output drivers
• Available package: 64 - pin Plastic Thin Quad Flat Package (TQFP), 64 - pin Slim Thin Quad Flat Package
(STQFP)
• (0°C to 70°C) Commercial operating temperature available for cycle time of 7.5ns and above
• (-40°C to 85°C) Industrial operating temperature available for cycle time of 10ns and above
Product Description:
HBA’s FlexQ™ I offers industry leading FIFO queuing bandwidth (up to 2.4 Gbps), with a wide range of memory configurations
(from 256 x 18 to 4,096 x 18). System designer has full flexibility of implementing deeper and wider queues with Write ( WEXI
and WEXO ) and Read ( REXI and REXO ) expansion features using daisy chain technique. Full, Empty, and Half Full
indicators allow easy handshaking between transmitters and receivers. User programmable Almost Full and Almost Empty
(Parallel) indicators allow implementation of virtual queue depths.
5V tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. Asynchronous
Output Enable pin configures the tri-state data output drivers. Independent Write and Read controls provide rate-matching
capability.
Data is written into the queue at the low to high transition of WCLK if WEN is asserted. Data is read from the queue at the low
to high transition of RCLK if REN is asserted.
Reset clears all previously programmed configurations by providing a low pulse on RST pin. In addition, Write and Read
pointers to the queue are initialized to zero.
These FlexQ™ I devices have low power consumption, hence minimizing system power requirements. In addition, industry
standard 64 - pin Plastic TQFP and 64 - pin STQFP are offered to save system board space.
These queues are ideal for applications such as data communication, telecommunication, graphics, multiprocessing, test
equipment, network switching, etc.
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© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 2 of 2
FQV245
FQV235
FQV225
FQV215
FQV205
DATA IN (D17 - 0)
READ CLOCK (RCLK)
DATA OUT (Q17 - 0)
LOAD ( )
HALF - FULL FLAG ( )
PROGRAMMABLE ( )
FULL FLAG ( )
WRITE CLOCK (WCLK)
WRITE ENABLE ( )
PROGRAMMABLE ( )
EMPTY FLAG ( )
OUTPUT ENABLE ( )
READ ENABLE ( )
WRITE EXPANSION IN ( )
WEXI
READ EXPANSION IN ( )
REXI
Block Diagram of Single Synchronous Queue
4,096 x 18 / 2 ,048 x 18 / 1,024 x 18 / 512 x 18 / 256 x 18
RESET ( )
RST
WEN
LOAD
FULL
HALF
PRAE
REN
OE
EMPTY
PRAF
FIRST LOAD ( )
FIRST
WEXO
REXO
Figure 1. Single Device Configuration Signal Flow Diagram
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© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Page 3 of 3
Offset Register
Write Control
Logic
Write Pointer
SRAM
Input Register Output Register
Flag Logic
Output
Buffer Q17-0 x18
x18
D
17-0
Read Pointer
Read Control
Logic Reset
WCLK
OE
RCLK REN
WEN
PRAF
/
FULL DRDY
PRAE
EMPTY QRDY
/
LOAD
Expansion Logic
FIRST
WEXI
)HALF/(WEXO
REXI
REXO
HALF/)WEXO(
RST
Figure 2. Device Architecture
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1
7
8
9
10
11
12
13
14
15
16
3
4
5
6
2
17
19
18
28
26
25
24
23
22
21
20
32
31
30
29
60
33
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
49
59
58
57
56
54
55
53
52
51
50
64
63
62
61
27
PIN 1
D14
D12
D13
D4
D5
D6
D7
D8
D9
D10
D11
Q4
D1
D2
D3
Q14
Q13
GND
Q12
Q11
Vcc
Q10
Q9
GND
Q8
Q7
GND
Q6
Q5
Vcc
FIRST
PRAE
Q0
REXO
FULL
REXI
PRAF
Vcc
WEXI
WEN
WCLK
Q16
GND
Q15
Q3
Q2
GND
Q1
RCLK
LOAD
OE
RST
Vcc
GND
EMPTY
Q17
D16
D17
GND
D15
D0
REN
Vcc
WEXO/HALF
TQFP – 64 (Drw No: PF-01A; Order Code: PF)
STQFP – 64 (Drw No: TF-01A; Order Code: TF)
Top View
Figure 3. Device Pin Out
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Pin # Pin Name Pin Symbol Input/Output Description
57 Reset RST Input
Reset is required to initialize Write and Read pointers
to the first position of the queue by setting RST low.
FULL and PRAF will go high; EMPTY and
PRAE will go low. All data outputs will go low.
Previous programmed configurations will not be
maintained.
19 Write Clock WCLK Input
Writes data into queue during low to high transitions
of WCLK if WEN is set low.
20 Write Enable
WEN Input Controls write operation into queue or offset registers
during low to high transition of WCLK.
59 Load Enable LOAD Input
LOAD controls write/read, to/from offset registers
during low to high transition of WCLK/RCLK
respectively. Use in conjunction with WEN /REN .
18 First Load
FIRST Input
In single device configuration, FIRST is set low.
In depth expansion configuration, FIRST is set low
for the first device and set high for other devices in
the daisy chain.
21 Write Expansion
In WEXI Input
In single device configuration, WEXI is set low.
In depth expansion configuration, WEXI is
connected to WEXO of previous device in the daisy
chain.
63, 64, 1, 2, 3, 4,
5, 6, 7, 8, 9, 10,
11, 12, 13, 14, 15,
16
Data Inputs D17-0 Input
18 - bit wide input data bus.
61 Read Clock RCLK Input Reads data from queue during low to high transitions
of RCLK if REN is set low.
60 Read Enable
REN Input Controls read operation from queue or offset registers
during low to high transition of RCLK.
24 Read Expansion
In REXI Input
In single device configuration, REXI is set low.
In depth expansion configuration, REXI is connected
to REXO of previous device in the daisy chain.
58 Output Enable
OE Input
Setting OE low activates the data output drivers.
Setting OE high deactivates the data output drivers
(High-Z).
53, 52, 50, 48, 47,
45, 44, 42, 41, 39,
38, 37, 36, 34, 32,
31, 29, 28
Data Outputs Q17-0 Output
18 - bit wide output data bus.
27 Read Expansion
Out REXO Output In depth expansion configuration, REXO is
connected to REXI of next device in the daisy chain.
25 Full Flag
FULL Output
Queue is full when FULL goes low during the low to
high transition of WCLK. This prohibits further
writes into the queue.
Table 1. Pin Descriptions
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Pin # Pin Name Pin Symbol Input/Output Description
54 Empty Flag
EMPTY Output
Queue is empty when EMPTY goes low during the
low to high transition of RCLK. This prohibits
further reads from the queue.
23 Almost Full
PRAF Output
Queue is almost full when PRAF goes low during the
low to high transition of WCLK. Default (Full-offset)
or programmed offset values determine the status of
PRAF .
17 Almost Empty
PRAE Output
Queue is almost empty when PRAE goes low during
the low to high transition of RCLK. Default
(Empty+offset) or programmed offset values
determine the status of PRAE .
26 Write Expansion
Out/Half Full WEXO / HALF Output
In single device configuration, queue is more than
half full when WEXO / HALF goes low.
In depth expansion configuration, WEXO / HALF is
connected to WEXI of next device in the daisy
chain.
22, 33, 43, 49, 56 Power Vcc N/A 3.3V power supply.
30, 35, 40, 46, 51,
55, 62 Ground GND N/A
0V Ground.
Table 1. Pin Descriptions (Continued)
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Symbol Rating Com’l & Ind’l Unit
VTERM Terminal Voltage with
respect to GND -0.5 to + 5.0 V
TSTG Storage Temperature -55 to +125 °C
IOUT DC Output Current -50 to +50 mA
NOTES:
Absolute Max Ratings are for reference only. Permanent damage to the device
may occur if extended period of operation is outside this range. Standard operation
should fall within the Recommended Operating Conditions.
Table 2. Absolute Maximum Ratings
FQV245
FQV235
FQV225
FQV215
FQV205
Commercial
Clock = 7.5ns, 10ns, 15ns, 20ns
Industrial
Clock = 10ns, 15ns, 20ns
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit
Recommended Operating Conditions
VCC Supply Voltage Com’l/Ind’l 3.0 3.3 3.6 3.0 3.3 3.6 V
GND Supply Voltage 0 0 0 0 0 0 V
VIH Input High Voltage
Com’l/Ind’l 2.0 - 5.5 2.0 - 5.5 V
VIL Input Low Voltage
Com’l/Ind’l - - 0.8 - - 0.8 V
TA Operating Temperature
Commercial 0 - 70 0 - 70
°C
TA Operating Temperature
Industrial -40 - 85 -40 - 85
°C
DC Electrical Characteristics
ILI(1) Input Leakage Current (any
input) -10 - 10 -10 - 10
µA
ILO Output Leakage Current -10 - 10 -10 - 10 µA
VOH Output Logic “1” Voltage,
IOH=-2mA 2.4 - - 2.4 - - V
VOL Output Logic “0” Voltage,
IOL = 8mA - - 0.4 - - 0.4 V
Power Consumption
ICC1(2,3) Active Power Supply
Current - - 30 - - 30 mA
ICC2(4) Standby Current - - 5 - - 5 mA
Table 3. DC Specifications
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Capacitance at 1.0 MHz Ambient Temperature (25°C)
Symbol Parameter Conditions Max. Unit
CIN(2) Input Capacitance VIN= 0V 10 pF
COUT(2,4) Output Capacitance VOUT= 0V 10 pF
NOTES:
1. Measurement with 0.4<=VIN<=Vcc
2. With output tri-stated ( OE = High)
3. Icc(1,2) is measured with WCLK and RCLK at 20 MHz
4. Design simulated, not tested.
Table 3. DC Specifications (Continued)
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Commercial Commercial & Industrial
FQV245-7.5
FQV235-7.5
FQV225-7.5
FQV215-7.5
FQV205-7.5
FQV245-10
FQV235-10
FQV225-10
FQV215-10
FQV205-10
FQV245-15
FQV235-15
FQV225-15
FQV215-15
FQV205-15
FQV245-20
FQV235-20
FQV225-20
FQV215-20
FQV205-20
S
y
mbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
fs Clock Cycle Frequency - 133 - 100 - 66 - 50 MHz
tA Data Access Time 1 5 2 6.5 2 10 2 12 ns
tWCLK Write Clock Cycle Time 7.5 - 10 - 15 - 20 - ns
tWCLKH Write Clock High Time 3.5 - 4.5 - 6 - 8 - ns
tWCLKL Write Clock Low Time 3.5 - 4.5 - 6 - 8 - ns
tRCLK Read Clock Cycle Time 7.5 - 10 - 15 - 20 - ns
tRCLKH Read Clock High Time 3.5 - 4.5 - 6 - 8 - ns
tRCLKL Read Clock Low Time 3.5 - 4.5 - 6 - 8 - ns
tDS Data Set-up Time 2.5 - 3 - 4 - 5 - ns
tDH Data Hold Time 0.5 - 0.5 - 1 0 1 - ns
tENS Enable Set-up Time 2.5 - 3 - 4 - 5 - ns
tENH Enable Hold Time 0.5 - 0.5 - 1 - 1 - ns
tRST Reset Pulse Width(1) 10 - 10 - 15 - 20 - ns
tRSTS Reset Set-up Time 8 8 - 10 - 12 - ns
tRSTR Reset Recovery Time 8 - 8 - 10 - 12 - ns
tRSTF Reset to Flag and Output Time - 12 - 15 - 15 - 20 ns
tOLZ Output Enable to Output in Low-Z(2) 0 - 0 - 0 - 0 - ns
tOE Output Enable to Output Valid 2 5 3 6 3 8 3 10 ns
tOHZ Output Enable to Output in High-Z(2) 2 5 3 6 3 8 3 10 ns
tFULL Write Clock to Full Flag - 5 - 6.5 - 10 - 12 ns
tEMPTY Read Clock to Empty Flag - 5 - 6.5 - 10 - 12 ns
tPRAF Clock to Programmable Almost-Full Flag - 13 - 17 - 20 - 22 ns
tPRAE Clock to Programmable Almost-Empty Flag - 13 - 17 - 20 - 22 ns
tHALF Clock to Half-Full Flag - 13 - 17 - 20 - 22 ns
tXO Clock to Expansion Out - 5 - 6.5 - 10 - 12 ns
tXI Expansion in Pulse Width 3 - 3 - 6.5 - 8 - ns
tXIS Expansion in Set-Up Time 3.5 - 5 - 5 - 8 - ns
tSKEW1 Skew time between Read Clock & Write
Clock for Full Flag 4 - 5 - 6 - 8 - ns
tSKEW2 Skew time between Read Clock & Write
Clock for Empty Flag 4 - 5 - 6 - 8 - ns
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Design simulated, not tested.
Table 4. AC Electrical Characteristics
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Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns(1)
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load*, clock = 10ns, 15ns, 20ns See Figure 5
Output Load, clock = 7.5ns See Figure 4
*Include jig and scope capacitances
Notes:
1. For 133MHz, operation input rise/fall times are 1.5ns.
Table 5. AC Test Condition
D.U.T.
510Ω
30pF*
330Ω
3.3V
Figure 5. Output Load
*Includes jig and scope capacitances.
for clock = 10ns, 15ns, 20ns
Vcc/2
50 Ω
Z0 = 50 Ω
I/O
Figure 4. AC Test Load
for clock = 7.5ns
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Pin Functions
RST Reset is required to initialize Write and Read pointers to the first position of the queue by setting RST
low. FULL and PRAF will go high; EMPTY and PRAE will go low. All data outputs will go low.
Previous programmed configurations will not be maintained.
WCLK Writes data into queue during low to high transitions of WCLK if WEN is set low. Synchronizes
FULL and PRAF flags. WCLK and RCLK are independent of each other.
WEN Controls write operation into queue or offset registers during low to high transition of WCLK.
LOAD LOAD controls write/read, to/from offset registers during low to high transition of WCLK/RCLK
respectively for parallel programming. Use in conjunction with WEN /REN .
FIRST In single device configuration, FIRST is set low. In depth expansion configuration, FIRST is set low for
the first device and set high for other devices in the daisy chain.
WEXI In single device configuration, WEXI is set low. In depth expansion configuration, WEXI is connected to
WEXO of previous device in the daisy chain.
D17-0 18 - bit wide input data bus.
RCLK Reads data from queue during low to high transitions of RCLK if REN is set low. Synchronizes the
EMPTY and PRAE flags. RCLK and WCLK are independent of each other.
REN Reads data from queue during low to high transitions of RCLK if REN is set to low. This also advances
the Read pointer of the queue.
OE Setting OE low activates the data output drivers. Setting OE high deactivates the data output drivers
(High-Z). OE does not control advancement of Read pointer.
Q17-0 18 - bit wide output data bus.
REXO In depth expansion configuration, REXO is connected to REXI of next device in the daisy chain.
FULL Queue is full when FULL goes low during the low to high transition of WCLK. This prohibits further
writes into the queue and prevents advancement of Write pointer. Refer to Table 8 for behavior of FULL .
EMPTY Queue is empty when EMPTY goes low during the low to high transition of RCLK. This prohibits further
reads from the queue and prevents advancement of Read pointer. Refer to Table 8 for behavior of
EMPTY .
PRAF Queue is almost full when PRAF goes low during the low to high transition of WCLK. PRAF goes high
during the low to high transition of RCLK. Default (Full-offset) or programmed offset values determine
the status of PRAF . Refer to Table 8 for behavior of PRAF .
PRAE Queue is almost empty when PRAE goes low during the low to high transition of RCLK. PRAE goes
high during the low to high transition of WCLK. Default (Empty+offset) or programmed offset values
determine the status of PRAE . Refer to Table 8 for behavior of PRAE .
WEXO /HALF In single device configuration, queue is more than half full when HALF goes low during the low to high
transition of WCLK. Queue is less than half full when HALF goes high during the low to high transition
of RCLK. Refer to Table 8 for details. In depth expansion configuration, WEXO is connected to
WEXI of next device in the daisy chain
REXI In single device configuration, REXI is set low. In depth expansion configuration, REXI is connected to
REXO of previous device in the daisy chain.
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LOAD WEN REN WCLK RCLK
FQV245
FQV235
FQV225
FQV215
FQV205
Selection / Sequence
0 0 1
X
Parallel write to offset
registers:
Empty Offset
Full Offset
Parallel write to
registers:
1. PRAE
2. PRAF
0 1 0 X
Parallel read from offset
registers:
Empty Offset
Full Offset
Parallel read
from registers:
1. PRAE
2. PRAF
X 1 1 X X
No Operation
1 0 X
X Write Memory
1 X 0 X
Read Memory
Figure 6. Programmable Flag Offset Programming Sequence
Device PRAF Programming (bits) PRAE Programming (bits)
FQV245 D/Q11-0 D/Q11-0
FQV235 D/Q10-0 D/Q10-0
FQV225 D/Q9-0 D/Q9-0
FQV215 D/Q8-0 D/Q8-0
FQV205 D/Q7-0 D/Q7-0
Table 6. Parallel Offset Register Data Mapping Table
Device Default
FQV245 007FH
FQV235 007FH
FQV225 007FH
FQV215 003FH
FQV205 001FH
Table 7. Default Values of Offset Registers
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# of Bits for Offset Registers
12 bits for FQV245
11 bits for FQV235
10 bits for FQV225
9 bits for FQV215
8 bits for FQV205
Note: Don’t Care applies to all unused bits
Figure 7. Parallel Offset Write/Read Cycles Diagram
Data Width
Data Width
Data Width
Data Width
FQV245 4,096 x 18
FQV235 2,048 x 18
FQV225 1,024 x 18
FQV215 512 x 18
D/Q8 D/Q6 D/Q4 D/Q2 D/Q0D/Q7 D/Q5 D/Q3 D/Q1
D/Q9D/Q10D/Q11D/Q12D/Q13D/Q14D/Q15D/Q16D/Q17
D/Q8 D/Q6 D/Q4 D/Q2 D/Q0D/Q7 D/Q5 D/Q3 D/Q1
D/Q9D/Q10D/Q11D/Q12D/Q13D/Q14D/Q15D/Q16D/Q17
D/Q8 D/Q6 D/Q4 D/Q2 D/Q0D/Q7 D/Q5 D/Q3 D/Q1
D/Q9D/Q10D/Q11D/Q12D/Q13D/Q14D/Q15D/Q16D/Q17
D/Q8 D/Q6 D/Q4 D/Q2 D/Q0D/Q7 D/Q5 D/Q3 D/Q1
D/Q9D/Q10D/Q11D/Q12D/Q13D/Q14D/Q15D/Q16D/Q17
PRAE
PRAF
1st Cycle
2nd Cycle
PRAE
PRAF
1st Cycle
2nd Cycle
PRAE
PRAF
1st Cycle
2nd Cycle
Data Width
FQV205 256 x 18
D/Q8 D/Q6 D/Q4 D/Q2 D/Q0D/Q7 D/Q5 D/Q3 D/Q1
D/Q9D/Q10D/Q11D/Q12D/Q13D/Q14D/Q15D/Q16D/Q17
PRAE
PRAF
1st Cycle
2nd Cycle
PRAE
PRAF
1st Cycle
2nd Cycle
42031
31420756
756
42031
31420756
756
8
8
42031
31420
95
6
756
78
8
9
10
10
11
11
42031
31420
95
6
756
78
8
9
10
10
42031
31420
95
6
756
78
8
9
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FQV245 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 2,048 H H H H H
2,049 to [4,096-(x+1)] H H L H H
(4,096 -x(2)) to 4,095 H L L H H
4,096 L L L H H
FQV235 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 1,024 H H H H H
1,025 to [2,048-(x+1)] H H L H H
(2,048 -x(2)) to 2,047 H L L H H
2,048 L L L H H
FQV225 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 512 H H H H H
513 to [1,024-(x+1)] H H L H H
(1,024 –x(2)) to 1,023 H L L H H
1,024 L L L H H
FQV215 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 256 H H H H H
257 to [512-(x+1)] H H L H H
(512 -x(2)) to 511 H L L H H
512 L L L H H
FQV205 FULL PRAF HALF PRAE EMPTY
0 H H H L L
1 to y(1) H H H L H
(y+1) to 128 H H H H H
129 to [256-(x+1)] H H L H H
(256 –x(2)) to 255 H L L H H
256 L L L H H
NOTES:
1. y = PRAE offset. Default Values: FQV205 y = 31, FQV215 y = 63, FQV245/FQV235/FQV225 y = 127.
2. x =
PRAF offset. Default Values: FQV205 x = 31, FQV215 x = 63, FQV245/FQV235/FQV225 x = 127.
Table 8. Status Flags
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Timing Diagrams
tRSTS tRSTR
tRST
tRSTF
tRSTF
tRSTF
= 1
= 0
Q17 - 0
RST
LOADWENREN ,,
PRAEEMP TY ,
HALFPRAFFULL ,,
OE
OE
NOTES:
1. After reset, the outputs will be low if OE = 0 and tri-state if OE =1.
2. The clocks (RCLK, WCLK) can be free-running during reset.
Diagram 1. Reset Timing
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tWCLK
tENS
tFULL
tSKEW1
tENH
tDHtDS
Data Valid
No Operation
WCLK
D17 - 0
RCLK
WEN
FULL
REN
tWCLKLtWCLKH
tFULL
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and rising WCLK edge to guarantee that FULL will go high
during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is equal to or less than
tSKEW1, then FULL may not change state until the next WCLK edge.
Diagram 2. Write Cycle Timing
FQV24
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· FQV235 · FQV225 · FQV215 · FQV205
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tRCLK
tRCLKLtRCLKH
tEMPTY
tA
tOE
tSKEW1
tOHZ
tEMPTY
Valid Data
tOLZ
tENS tENH
Q17 - 0
RCLK
REN
EMPTY
OE
WCLK
WEN
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EMPTY will go
high during the current clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is
less than tSKEW1, then EMPTY may not change state until the next RCLK edge.
Diagram 3. Read Cycle Timing
FQV24
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· FQV235 · FQV225 · FQV215 · FQV205
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DW1
DW1
tENS
tFRL(1)
tOE
tOLZ
tAtA
tENS
tEMPTY
tSKEW2
tDS
WCLK
D17 - 0
RCLK
Q17 - 0
WEN
EMPTY
REN
OE
DW2DW3DW4DW5
DW2
NOTES:
1. tFRL is the latency from first write to first Read. When tSKEW2 is greater than or equal to minimum specification, tFRL (maximum) = tRCLK +
tSKEW2. When tSKEW2 is less than minimum specification, tFRL (maximum) equals either 2* tRCLK + tSKEW2 or tRCLK + tSKEW2.
The Latency Timing applies only at the Empty Boundary ( EMPTY = low).
Diagram 4. First Data Word Latency after Reset with Simultaneous Read and Write
FQV24
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Output Register Data Data Read Next Data Read
LOW
Data Write Data Write
No Write
No Write
tSKEW 1(1) tDS tDS
tFULLtFULLtFULL
tENS tENH tENS tENH
tAtA
WCLK
D17 - 0
RCLK
Q17 - 0
tSKEW 1(1)
OE
REN
WEN
FULL
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FULL will go
high during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less
than tSKEW1, then FULL may not change state until the next WCLK edge.
Diagram 5. Full Flag Timing
FQV24
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· FQV235 · FQV225 · FQV215 · FQV205
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Output Register Data DW1
DW1 DW2
tFRL(1)
tSKEW2
tA
tSKEW2
tFRL(1)
tEMPTY
tENH
tENS
tDS tDS
tENS tENH
WCLK
D17 - 0
RCLK
Q17 - 0
LOW
OE
EMPTY
WEN
tEMPTY tEMPTY
REN
NOTES:
1. tFRL is the latency from first write to first Read. When tSKEW2 is greater than or equal to minimum specification, tFRL (maximum) = tRCLK + t SKEW2.
When tSKEW2 less than minimum specification, tFRL (maximum) equals either 2 * tRCLK + tSKEW2, or tRCLK + tSKEW2. The Latency Timing
applies only at the Empty Boundary ( EMPTY = low).
Diagram 6. Empty Flag Timing
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tWCLKLtWCLKH
tWCLK
tENHtENS
tENS
tDH
tDS
offset offset
offset
D11 - 0
WCLK
offset
WEN
LOAD
PRAE
PRAE
PRAF PRAF
Diagram 7. Write Programmable Registers
tRCLKLtRCLKH
tRCLK
tENHtENS
tENS
Q11 - 0
RCLK
tA
offset offset
LOAD
REN
PRAE PRAF offset
PRAE offset
PRAF
Diagram 8. Read Programmable Registers
tWCLKLtWCLKH
tPRAE
y + 1 words in Queue
tPRAE
y words in Queue
WCLK
RCLK
tENH
tENS
tENS
y words in Queue
WEN
PRAE
REN
tENH
NOTES:
1. y = PRAE offset.
Diagram 9. Programmable Almost-Empty Flag Timing
FQV24
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tWCLKLtWCLKH
tPRAF D - x words in Queue
memory(2)
tPRAF
D - (x+1) words in Queue
memory(1)
WCLK
RCLK
tENH
tENS
tENS
D - (x+1) words in Queue memory(1)
WEN
PRAF
REN
tENH
NOTES:
1. x = PRAF offset.
2. D = maximum queue depth = 256 words for FQV205; 512 words for FQV215; 1,024 words for FQV225; 2,048 words for FQV235; and 4,096 words for
FQV245.
Diagram 10. Programmable Almost-Full Flag Timing
tWCLKLtWCLKH
tHALF
D/2 + 1 words in
Queue memory(2)
tHALF
D/2 words in Queue
memory(1)
WCLK
RCLK
tENH
tENS
tENS
D/2 words in Queue memory(1)
WEN
HALF
REN
tENH
NOTES:
1. D = maximum queue depth = 256 words for FQV205; 512 words for FQV215; 1,024 words for FQV225; 2,048 words for FQV235; and 4,096 words for
FQV245.
Diagram 11. Half-Full Flag Timing
FQV24
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· FQV235 · FQV225 · FQV215 · FQV205
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WCLK
tXO
tXO
tENS
WEN
WEXO
Note 1
NOTES:
1. Write to Last Physical Location.
Diagram 12. Write Expansion Out Timing
RCLK
tXO
tXO
Note 1
tENS
REXO
REN
NOTES:
1. Read from Last Physical Location.
Diagram 13. Read Expansion Out Timing
WCLK
tXIS
tXI
WEXI
Diagram 14. Write Expansion in Timing
RCLK
tXIS
tXI
REXI
Diagram 15. Read Expansion in Timing
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Width Expansion Configuration
Simply connecting together the control signals of multiple devices may increase word width. Status flags can be detected
from any one device. The exceptions are the Empty Flag and Full Flag. Because of variations in skew between RCLK and
WCLK, it is possible for flag assertion and de-assertion to vary by one cycle between FIFOs. To avoid problems the user
must create composite flags by ANDing the Empty Flags of every FIFO, and separately ANDing all Full Flags. Figure 8
demonstrates a 36-bit width by using two FQV245 / 235 / 225 / 215 / 205s. Any word width can be attained by adding
additional FQV245 / 235 / 225 / 215 / 205s.
RESET ( )
DATA IN (D)
WRITE CLOCK (WCLK)
LOAD ( )
PROGRAMMABLE ( )
HALF- FULL ( )
RESET ( )
36 18
18
18
18 36DATA OUT (Q)
READ CLOCK (RCLK)
FULL ( )
PROGRAMMABLE ( )
FIRST LOAD ( )
WRITE EXPANSION IN ( )
READ EXPANSION IN ( )
FQV245
FQV235
FQV225
FQV215
FQV205
Block Diagram of Synchronous Queue
4,096 x 36 / 2,048 x 36 / 1,024 x 36 / 512 x 36 / 256 x 36
RST RST
OUTPUT ENABLE ( )
OE
READ ENABLE ( )
REN
PRAF
EMPTY FLAG ( )
EMPTY
FIRST
WEXI
REXI
EMPTY
EMPTY FULLFULL
FQV245
FQV235
FQV225
FQV215
FQV205
FULL
HALF
WRITE ENABLE ( )
WEN
LOAD
PRAE
NOTES:
1. Do not connect any output control signals directly together.
Figure 8. Width Expansion Configuration
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Depth Expansion Configuration (with Programmable Flags)
These devices can easily be adapted to applications requiring more than 4,096 / 2,048 / 1,024 / 512 / 256 words of buffering.
Figure 8 shows Depth Expansion using three FQV245 / 235 / 225 / 215 / 205s. Maximum depth is limited only by signal
loading. Follow these steps:
• The first device must be designated by grounding the First Load ( FIRST ) control input.
• All other devices must have FIRST in the high state.
• The Write Expansion Out ( WEXO ) pin of each device must be tied to the Write Expansion In ( WEXI ) pin of the next device.
• The Read Expansion Out ( REXO ) pin of each device must be tied to the Read Expansion In ( REXI ) pin of the next device.
• All Load ( LOAD ) pins are tied together.
• The Half-Full Flag ( HALF ) is not available in this Depth Expansion Configuration.
• EMPTY , FULL , PRAF , and PRAE are created with composite flags by ORing together every respective flags for
monitoring. The composite PRAF and PRAE flags are not precise.
DATA OUT
READ CLOCK
READ ENABLE
LOAD
RESET
WRITE ENABLE
WRITE CLOCK
DATA IN
Vcc
QD
Vcc
FIRST LOAD ( )
OUTPUT ENABLE
Block Diagram of Synchronous Queue
12,288 x 18 / 6,144 x 18 / 3,072 x 18 / 1,536 x 18 / 768 x 18
WEXI REXI
FIRST
PRAF
FULL
PRAE
EMPTY
WCLK
DQ
RCLK
FQV245
FQV235
FQV225
FQV215
FQV205
WEXO REXO
WEN
REN
RST
OE
LOAD
FULL
PRAF WEXI REXI
PRAE
EMPTY
WCLK
RCLK
FQV245
FQV235
FQV225
FQV215
FQV205
WEXO REXO
WEN
REN
RST
OE
LOAD
FULL
PRAF PRAE
EMPTY
FIRST
Q
D
WEXI REXI
WCLK
RCLK
FQV245
FQV235
FQV225
FQV215
FQV205
WEXO REXO
WEN
REN
RST
OE
LOAD
FULL
PRAF PRAE
EMPTY
FIRST
Figure 9. Block Diagram of Multiple Devices with Programmable Flags used in Depth Expansion Configuration
FQV24
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Order Information:
†Power – Low (LB)
*Speed – 7.5ns available only in Commercial temp (0°C to 70°C). Slower speeds available upon request.
**Package – 64 pin Plastic Thin Quad Flat Pack (TQFP), 64 pin Slim Thin Quad Flat Pack (STQFP)
Example:
FQV235LB7-5TF (32k x 18, 7.5ns, Commercial temp)
FQV225LB10PFI (16k x 18, 10ns, Industrial temp)
Document Revision History:
02/06/03 pg. 5, 7, 8, 9, 10, 12, 14
USA
Taiwan
2107 North First Street, Suite 415
San Jose, CA 95131, USA
www.hba.com
Tel: 408.453.8885
Fax: 408.453.8886
No. 81, Suite 8F-9, Shui-Lee Rd.
Hsinchu, Taiwan, R.O.C.
www.hba.com
Tel: 886.3.516.9118
Fax: 886.3.516.9181
HBA
Device Family
Device Type
Power†
Speed (ns)*
Package**
Temperature Range
XX XXXX X XX XX X
FQ V245 (4,096 x 18) LB 7-5 – 133 MHz PF Blank – Commercial (0°C to 70°C)
V235 (2,048 x 18 10 – 100 MHz TF I – Industrial (-40° to 85°C)
V225 (1,024 x 18) 15 – 66 MHz
V215 (512 x 18) 20 – 50 MHz
V205 (256 x 18)
