5962-8973501SA - e2v Aerospace & Defense

REVISIONS

LTR DESCRIPTION DATE (YR-MO-DA) APPROVED

A

Technical and editorial changes throughout. 92-04-17

M. L. Poelking

B

Change boilerplate to add QML class V criteria. Add ground bounce immunity

characterization. Editorial changes throughout.

97-05-15

T.M. Hess

C

Add RHA limits - jak.

98-05-29

Monica L. Poelking

D

Make corrections to figure 5. Update boilerplate. - jak

00-08-16

Monica L. Poelking

E

Update the boilerplate to current MIL-PRF - 38535 requirements.

Update radiation hardness assurance requirements. - jak

08-03-17

Thomas M. Hess

REV

SHEET

REV E E E E E E

SHEET 15 16 17 18 19 20

REV STATUS

REV E E E E E E E E E E E E E E

OF SHEETS

SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14

PMIC N/A

PREPARED BY

James E. Nicklaus

STANDARD

MICROCIRCUIT

DRAWING

CHECKED BY

Thomas J. Ricciuti

DEFENSE SUPPLY CENTER COLUMBUS

COLUMBUS, OHIO 4321 8-3990

http://www.dscc.dla.mil

THIS DRAWING IS AVAILABLE

FOR USE BY ALL

DEPARTMENTS

AND AGENCIES OF THE

DEPARTMENT OF DEFENSE

APPROVED BY

Michael A. Frye

DRAWING APPROVAL DATE

90-10-02

MICROCIRCUIT, DIGITAL, ADVANCED

CMOS, OCTAL D-TYPE FLIP-FLOP WITH

RESET, TTL COMPATIBLE INPUTS,

MONOLITHIC SILICON

AMSC N/A

REVISION LEVEL

E SIZE

A CAGE CODE

67268

5962-89735

SHEET

1 OF

20

DSCC FORM 2233

APR 97 5962-E074-08

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A

5962-89735

DEFENSE SUPPLY CENTER COLUMBUS

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REVISION LEVEL

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1. SCOPE

1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)

and space application (devic e class V). A choice of case outlines and lead finishes are available an d are reflected in the Part or

Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.

1.2 PIN. The PIN is as shown in the following examples:

For device classes M and Q:

5962 - 89735 01 R A

Federal RHA Device Case Lead

stock class designator type outline finish

designator (see 1.2.1) (see 1.2.2) (see 1.2.4) (see 1.2.5)

\ /

\/

Drawing number

For device clas s V:

5962 R 89735 01 V R A

Federal RHA Device Device Case Lead

stock class designator type class outline finish

designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5)

\ / (see 1.2.3)

\/

Drawing number

1.2.1 RHA designator. Device classes Q and V RHA marked dev ices meet the MIL-PRF-38535 specified RHA levels and are

marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF - 38535, appendix A

specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a n on-RHA device.

1.2.2 Device type(s). The device type(s) identify the circuit function as follows:

Device type Generic number Circuit function

01 54ACTQ273 Octal D type flip-flop with reset,

TTL compatible inputs

1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance l evel as listed

below. Since the device class designator has been added after the original issuance of this drawing, device classes M and Q

designators will not be included in the PIN and will not be marked on the device.

Device class Device requirements docum entation

M Vendor self-certification to the requireme nts for MIL-STD-883 compliant, non-JAN

class level B microcircuits in accordance with MIL-PRF-38535, appendix A

Q or V Certification and qualification to MIL-PRF-38535

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REVISION LEVEL

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1.2.4 Case outline(s). The case outline(s) are as desi gnated in MIL-STD-1835 and as follows:

Outline letter Descriptive designator Terminals Package style

R GDIP1-T20 or CDIP2-T20 20 Dual-in-line

S GDFP2-F20 or CDFP3-F20 20 Flat pack

2 CQCC1-N20 20 Square leadles s chip carrier

1.2.5 Lead finish. The lead finish is as speci fied in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A

for device class M.

1.3 Absolute maximum ratings. 1/ 2/ 3/

Supply voltage range (VCC).................................................................................. -0.5 V dc to +6.0 V dc

DC input voltage range (VIN)................................................................................ -0.5 V dc to VCC + 0.5 V dc

DC output voltage range (VOUT)........................................................................... -0.5 V dc to VCC + 0.5 V dc

DC input diode current......................................................................................... ±20 mA

DC output diode current (per output pin) ............................................................. ±50 mA

DC output source or sink current (per output pin).............................................. ±50 mA

DC VCC or GND current ....................................................................................... ±100 mA

Storage temperature range.................................................................................. -65°C to +150°C

Maximum power dissipation (PD)........................................................................ 500 mW

Lead temperature (soldering, 10 seconds) .......................................................... +300°C

Thermal resistance, junction-to-case (ΘJC).......................................................... See MIL-STD-1835

Junction temperature (TJ) .................................................................................... +175°C 4/

1.4 Recommended operating conditions. 2/ 3/

Supply voltage range (VCC).................................................................................. +4.5 V dc to +5.5 V dc

Input voltage range (VIN)...................................................................................... +0.0 V dc to VCC

Output voltage range (VOUT) ................................................................................ +0.0 V dc to VCC

Case operating temperature rang e (TC)............................................................... -55°C to +125°C

Maximum Input rise or fall rate (Δt/Δv) ................................................................ 8 ns/V

Minimum high level input voltage (IOH)................................................................. -24 mA

Maximum low level output current (IOL) ............................................................... +24 mA

Maximum frequency, (fmax):

T

C = +25°C:

VCC = 4.5 V to 5.5 V .................................................................................. 95 MHz

T

C = -55°C, +125°C:

VCC = 4.5 V to 5.5 V .................................................................................. 85 MHz

Minimum setup time, Dn to CP (ts):

T

C = +25°C:

VCC = 4.5 V to 5.5 V .................................................................................. 5.0 ns

T

C = -55°C, +125°C:

VCC = 4.5 V to 5.5 V .................................................................................. 5.0 ns

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Maximum hold time, Dn to CP (th):

T

C = +25°:

VCC = 4.5 V to 5.5 V .................................................................................. 2.0 ns

T

C = -55°C, +125°C:

VCC = 4.5 V to 5.5 V .................................................................................. 2.0 ns

Maximum clock high, low pulse width (tw1):

T

C = +25°C:

VCC = 4.5 V to 5.5 V .................................................................................. 5.0 ns

T

C = -55°C, +125°C:

VCC = 4.5 V to 5.5 V .................................................................................. 5.0 ns

Maximum pulse width, MR low (tw2):

T

C = +25°:

VCC = 4.5 V to 5.5 V .................................................................................. 5.0 ns

T

C = -55°C, +125°C:

VCC = 4.5 V to 5.5 V .................................................................................. 5.0 ns

Maximum removal time, MR to clock (trem):

T

C = +25°:

VCC = 4.5 V to 5.5 V .................................................................................. 4.0 ns

T

C = -55°C, +125°C:

VCC = 4.5 V to 5.5 V .................................................................................. 4.0 ns

1.5 Radiation features.

Maximum total dose available (dose rate = 50 – 300 rads (Si)/s) ....................... 100 krads (Si)

1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended oper ation at the

maximum levels may degrade performance and affect reliability.

2/ Unless other wise noted, a ll voltages are referenced to GND.

3/ The limits for the parameters specified herein shall ap ply over the full specified VCC range and case temperatur e range

of -55°C to +125°C.

4/ Maximum junction temperature shall not be exceeded exc ep t for allowable short duration burn-in scree ning conditions in

accordance with method 5004 of MIL-STD-883.

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APR 97

2. APPLICABLE DOCUMENTS

2.1 Government specification, standards, and han dbooks. The following specification, standards, and handbooks form a part

of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the

solicitation or contract.

DEPARTMENT OF DEFENSE SPECIFICATION

MIL-PRF-385 35 - Integrated Circuits, Manufacturing, General Specification for.

DEPARTMENT OF DEFENSE STANDARDS

MIL-STD-883 - Test Method Standard Microcircuits.

MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.

DEPARTMENT OF DEFENSE HANDBOOKS

MIL-HDBK-103 - List of Standard Microcircuit Drawings.

MIL-HDBK-780 - Standard Microcircuit Drawings.

(Copies of these documents ar e available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from

the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)

2.2 Non-Government publications. The following document (s) form a part of this document to the extent specifie d herein.

Unless otherwise specified, th e issues of these documents are those cited in the solicitation or contract.

ELECTRONIC INDUSTRIES ALLIANCE (EIA)

JESD 78 - IC Latch-Up T est

JEDEC Standard No. 20 - Standard for Descripti on of 54/74ACXXXX and 54/74ACTXXXX Advanced High-Speed

CMOS Devices.

(Copies of this document is available online at www.eia.org/ or from the Electronics Industries Alliance, 2500 Wilson

Boulevard, Arlington, VA 22201-3834).

AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM)

ASTM F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion

Irradiation of semiconductor Devices.

(Copies of these documents ar e available online at http://www.astm.org or from ASTM International, 100 Barr Harbor Drive,

P.O. Box C700, West Conshohocken, PA, 19428-2959).

2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of

this drawing takes precedence. Nothing in this doc ument, however, supersedes applicable laws and regulations unless a specific

exemption has been obtaine d.

3. REQUIREMENTS

3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accor da nce with

MIL-PRF-38535 and as specif ied herein or as modified in the device manufacturer's Qualit y Management (QM) plan. The

modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for

device class M shall be in acc ordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specif ied

herein.

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REVISION LEVEL

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3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in

MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.

3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.

3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.

3.2.3 Truth table. The truth table shall be as specified on figure 2.

3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3.

3.2.5 Ground bounce load circ uit and waveforms. The ground bounce lo ad circuit and waveforms shall be as specifi ed on

figure 4.

3.2.6 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 5.

3.2.7 Radiation exposure circ uit. The radiation exposure circuit shall be as specified when available.

3.3 Electrical performance characterist ics and postirradiation parameter limits. Unless otherwise specified herein, the electrical

performance characteristics and postirradiation parameter li mits are as specified in table I and shall apply over the full case

operating temperature range.

3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. T he electrical

tests for each subgroup are defined in table I.

3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be

marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer

has the option of not marking the "5962-" on the devic e. For RHA product using this option, the RHA designator shall still be

marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in

accordance with MIL-PRF-38535, appendix A.

3.5.1 Certification/compliance mark. The certification mark for devic e classes Q and V shall be a "QML" or "Q" as required in

MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.

3.6 Certificate of compliance. For device classes Q and V, a certificate of complianc e shall be required from a QML-38535

listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of

compliance shall be required from a manufacturer in order to be listed as an approved source of supp ly in MIL-HDBK-103 (see

6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this

drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and

herein or for device class M, the requirement s of MIL-PRF-38535, appendi x A and herein.

3.7 Certificate of conformance. A certificate of conformance as require d for device classes Q and V in MIL-PRF-38535 or

for device class M in MIL-PRF-38535, appendix A shall be provi ded with each lot of microcircuits delivered to this drawing.

3.8 Notification of change for device class M. For device class M, notification to DSCC- VA of change of product (see 6.2

herein) involving devic es acquired to this drawing is required for any change that affect this drawing.

3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acqu iring activity retain the

option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made

available onshore at the optio n of the reviewer.

3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in

microcircuit group number 38 (see MIL-PRF-38535, appendix A).

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REVISION LEVEL

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DSCC FORM 2233

APR 97

TABLE I. Electrical performance characteristi c s.

Test and

MIL-STD-883

test method 1/

Symbol Test conditions 2/ 3/

-55°C ≤ TC ≤ +125°C

+4.5 V ≤ VCC ≤ +5.5 V

Device

type

and

VCC Group A

subgroups Limits 4/ Unit

unless otherwise specified Device

class Min Max

High level output

voltage VOH

For all inputs affecting output under

test, VIN = 2.0 V or 0.8 V All

All 4.5 V 1, 2, 3 4.4 V

3006 5/ 6/ For all other inputs,

VIN = VCC or GND All

All 5.5 V 1, 2, 3 5.4

IOH = -50 μA M, D, P, L, R

All

All 5.5 V 1 5.4

For all inputs affecting output under

test, VIN = 2.0 V or 0.8 V All

All 4.5 V 1 3.86

For all other inputs,

VIN = VCC or GND M, D, P, L, R

All

All 4.5 V 1 3.86

I

OH = -24 mA All

All 4.5 V 2, 3 3.7

All

All 5.5 V 1 4.86

All

All 5.5 V 2, 3 4.7

For all inputs affecting output under

test, VIN = 2.0 V or 0.8 V All

All 5.5 V 1, 2, 3 3.85

For all other inputs,

VIN = VCC or GND

IOH = -50 mA 7/

M, D, P, L, R

All

All 5.5 V 1 3.85

Low level output

voltage VOL

For all inputs affecting output under

test, VIN = 2.0 V or 0.8 V All

All 4.5 V 1, 2, 3 0.1 V

3007 5/ 6/ For all other inputs,

VIN = VCC or GND All

All 5.5 V 1, 2, 3 0.1

IOL = 50 μA M, D, P, L, R

All

All 5.5 V 1 0.1

For all inputs affecting output under

test, VIN = 2.0 V or 0.8 V All

All 4.5 V 1 0.36

For all other inputs,

VIN = VCC or GND M, D, P, L, R

All

All 4.5 V 1 0.36

I

OL = 24 mA All

All 4.5 V 2, 3 0.5

All

All 5.5 V 1 0.36

All

All 5.5 V 2, 3 0.5

For all inputs affecting output under

test, VIN = 2.0 V or 0.8 V All

All 5.5 V 1, 2, 3 1.65

For all other inputs,

VIN = VCC or GND

IOL = 50 mA 7/

M, D, P, L, R

All

All 5.5 V 1 1.65

See footnotes at end of table.

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TABLE I. Electrical performance characteristi c s - Continued.

Test and

MIL-STD-883

test method 1/

Symbol Test conditions 2/ 3/

-55°C ≤ TC ≤ +125°C

+4.5 V ≤ VCC ≤ +5.5 V

Device

type

and

VCC Group A

subgroups Limits 4/ Unit

unless otherwise specified Device

class Min Max

Positive input

clamp voltage VIC+ For input under test, IIN = 18 mA All

V 4.5 V 1, 2, 3 5.7 V

3022 5/ 6/ M, D, P, L, R

All

V 4.5 V 1 5.7

Negative input

clamp voltage VIC- For input under test, IIN = -18 mA All

V 4.5 V 1, 2, 3 -1.2 V

3022 5/ 6/ M, D, P, L, R

All

V 4.5 V 1 -1.2

Input leakage

current high IIH For input under test, VIN = VCC

For all other inputs, VIN = VCC or All

All 5.5 V 1 0.1 μA

3010 5/ 6 GND M, D, P, L, R

All

All 5.5 V 1 0.1

All

All 5.5 V 2, 3 1.0

Input leakage

current low IIL For input under test, VIN = GND

For all other inputs, VIN = VCC or All

All 5.5 V 1 -0.1 μA

3009 5/ 6/ GND M, D, P, L, R

All

All 5.5 V 1 -0.1

All

All 5.5 V 2, 3 1.0

Input capacitance

3012 CIN See 4.4.1c

TC = +25°C All

All GND 4 10 pF

Power dissipation

capacitance CPD

8/ See 4.4.1c

TC = +25°C All

All 5.0 V 4 55 pF

Quiescent supply

current delta, ΔICC

For input under test,

VIN = VCC - 2.1 V All

All 5.5 V 1 1.0 mA

TTL input level

3005 5/ 6/

9/ For all other inputs, VIN = VCC or

GND 2, 3

1.6

M, D All 5.5 V 1 1.6

P, L, R All 3.5

Quiescent supply

current, output ICCH V

IN = VCC or GND

IOUT = 0.0 A All

All 5.5 V 1 4.0 μA

high

3005 5/ 6/ 2, 3

80.0

M All 5.5 V 1 100

D All 1.0 mA

P, L, R 3.5

Quiescent supply

current, output ICCL V

IN = VCC or GND

IOUT = 0.0 A All

All 5.5 V 1 4.0 μA

low

3005 5/ 6/ 2, 3

80.0

M All 5.5 V 1 100.0

D All 1.0 mA

P, L, R 3.5

See footnotes at end of table.

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TABLE I. Electrical performance characteristi c s - Continued.

Limits 4/

Test and

MIL-STD-883

test method 1/

Symbol

Test conditions 2/ 3/

-55°C ≤ TC ≤ +125°C

+4.5 V ≤ VCC ≤ +5.5 V

unless otherwise specified

Device

type

and

Device

class

VCC

Group A

subgroups

Min Max

Unit

Low level ground

bounce noise VOLP

10/ VIH = 3.0 V, VIL = 0.0 V

TA = +25°C All

All 5.0 V 4 1500 mV

V

OLV

10/ See 4.4.1d

See figure 4 4 -1200

High level VCC

bounce noise VOHP

10/ 5.0 V 4 VOH

+1200 mV

V

OHV

10/ 4 VOH

-2200

Functional tests

3014 5/ 6/

11/ VIH = 2.0 V, VIL = 0.8 V

See 4.4.1b All

All 4.5 V

7, 8 L H

Verify output

VOUT M, D, P, L, R All

All 7 L H

All

All 5.5 V

7, 8 L H

Latch-up

input/output

over-voltage

ICC

(O/V1)

12/

tw ≥ 100 μs, tcool ≥ tw

5 μs ≤ tr ≤ 5 ms

5 μs ≤ tf ≤ 5 ms

Vtest = 6.0 V, VCCQ = 5.5 V

Vover = 10.5 V

See 4.4.1e

All

V 5.5 V 2 200 mA

Latch-up

input/output

positive over-

current

ICC

(O/I1+)

12/

tw ≥ 100 μs, tcool ≥ tw

5 μs ≤ tr ≤ 5 ms

5 μs ≤ tf ≤ 5 ms

Vtest = 6.0 V, VCCQ = 5.5 V

Itrigger = +120 mA

See 4.4.1e

All

V 5.5 V 2 200 mA

Latch-up

input/output

negative over-

current

ICC

(O/I1-)

12/

tw ≥ 100 μs, tcool ≥ tw

5 μs ≤ tr ≤ 5 ms

5 μs ≤ tf ≤ 5 ms

Vtest = 6.0 V, VCCQ = 5.5 V

Itrigger = -120 mA

See 4.4.1e

All

V 5.5 V 2 200 mA

Latch-up supply

over-voltage ICC

(O/V2)

12/

tw ≥ 100 μs, tcool ≥ tw

5 μs ≤ tr ≤ 5 ms

5 μs ≤ tf ≤ 5 ms

Vtest = 6.0 V, VCCQ = 5.5 V

Vover = 9.0 V

See 4.4.1e

All

V 5.5 V 2 100 mA

Propagation delay

time, CP to Qn tPHL1 C

L = 50 pF minimum

RL = 500Ω All

All 4.5 V 9 1.0 9.0 ns

3003 5/ 6/

13/ See figure 5 M, D, P, L, R All

All 9 1.0 9.0

All

All 10, 11 1.0 10.0

See footnotes at end of table.

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TABLE I. Electrical performance characteristi c s - Continued.

Test and

MIL-STD-883

test method 1/

Symbol

VCC

Group A

subgroups

Limits 4/

Unit

Test conditions 2/ 3/

-55°C ≤ TC ≤ +125°C

+4.5 V ≤ VCC ≤ +5.5 V

unless otherwise specified

Device

type

and

Device

class Min Max

Propagation delay

time, CP to Qn tPLH1 C

L = 50 pF minimum

RL = 500Ω All

All 4.5 V 9 1.0 9.0 ns

3003 5/ 6/

13/ See figure 5 M, D, P, L, R All

All 9 1.0 9.0

All

All 10, 11 1.0 10.0

Propagation delay

time, MR to Qn tPHL2 C

L = 50 pF minimum

RL = 500Ω All

All 4.5 V 9 1.0 9.5 ns

3003 5/ 6/

13/ See figure 5 M, D, P, L, R All

All 9 1.0 9.5

All

All 10, 11 1.0 11.0

1/ For tests not listed in the referenced MIL-STD-883, (e.g. ΔICC), utilize the general test procedure under the conditions listed

herein. All inputs and outputs shall be tested, as applicabl e, to the tests in table I herein.

2/ Each input/output, as applicable, shall be tested at the specified temperature, for the specified limits. Output terminals not

designated shall be high level logic, low level logic, or o pen, except for the ICC and ΔICC tests, the output terminal shall be

open. When performing the ICC and ΔICC tests, the current meter shal l be placed in the circuit such that all current flows

through the meter.

Additional detailed information on qualified devices (i.e. pin for pin conditions and testing sequ ence) is available from the

qualifying activity (DCSS-VQC) upon request.

3/ RHA parts supplied to this drawing are tested through all levels M, D, P, L, and R of irradiation. Pre and Post irradiation

values are identical unless otherwise specified in table I. When performing post irradiation electrical measurements for any

RHA level, TA = +25°C.

4/ For negative and positive voltage and current values, the sign designates the potential differenc e in reference to GND and

the direction of current flow, respectively; and the absolute value of the magnitude, not the sign, is relative to the minimum

and maximum limits, as applicabl e, listed herein. All devices shall meet or exceed the limits specified in table I, as

applicable, at +4.5 V ≤ VCC ≤ +5.5 V.

5/ RHA samples do not have to be tested at -55°C and +125°C prior to irradiation.

6/ When performing post irradiation electrical measurements for RHA level, TA = +25°C. Limits shown are guaranteed at

T

A = +25°C ±5°C.

7/ Transmission driving tests are performe d at VCC = 5.5 V with a 2 ms duration maximum. This test may be performed using

VIN = VCC or GND. When VIN = VCC or GND is used, the test is guaranteed for VIN = 2.0 V or 0.8 V.

8/ Power dissipation capacitance (CPD) determines the no load power consumption, PD = (CPD + CL) (VCC x VCC) f

+ (ICC x VCC) + (n x d x ΔICC x VCC). The dynamic current consumption, IS = (CPD + CL) VCCf + ICC

+ (n x d x ΔICC). For both PD and IS, n is the number of device inputs at TTL levels, f is the frequency of the input signal, d

is the duty cycle of the input signal, and CL is the output load capacita nce.

9/ This test may be performed either one input at a time (preferred method) or with all input pins simultaneously at

V

IN = VCC - 2.1 V (alternate method). When the test is performed using the alternate test method, the maximum limit is

equal to the number of inputs at a high TTL input level times 1.6 mA; and the preferred method and limits are guaranteed.

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TABLE I. Electrical performance characteristi c s - Continued.

10/ This test is for qualification only. Ground and VCC bounce tests are performed on a non- switching (quiescent) output

and are used to measure the magnitude of induced noise caused by other simultaneously switching outputs. The test is

performed on a low noise bench test fixture. For the device under test, all outputs shall be loaded with 500Ω of load

resistance and a minimum of 50 pF of loa d capacitance (see figure 4). Only chip capacitors and resistors shall be used.

The output load components shall be located as close as possible to the device outputs. It is suggested that, whenever

possible, this distance be kept to less than 0.25 inches. Decoupling capacitors shall be placed in parall el from VCC to

ground. The values of these decoupling capacitors shall be determined by the device manufacturer. The low and high

level ground and VCC bo unce noise is measured at the q uiet output using a 1 GHz minimum bandwidth oscilloscope

with a 50Ω input impedance.

The device inputs shall be co nditioned such that all outputs are at a high nominal VOH level. The device inputs shall

then be conditioned such that they switch simultaneous ly and the output under test remains at VOH as all other outputs

possible are switched from VOH to VOL. VOHV and VOHP are then measured from the nominal VOH level to the largest

negative and positive peaks, respectivel y (see figure 4). T his is then repe ated with the same outputs not under test

switching from VOL to VOH.

The device inputs shall be co nditioned such that all outputs are at a lo w nominal VOL level. The device inputs shall then

be conditioned such that they s witch simult aneously and the output under test remains at VOL as all other outputs

possible are switched from VOL to VOH. VOLP and VOLV are then measured from the nominal VOL level to the largest

positive and negative peaks, respectively (see figure 4). This is then repeated with the same outputs not under test

switching from VOH to VOL.

11/ Tests shall be performed in s equence, attributes data only. Functional tests shall inclu de the truth table and other logic

patterns used for fault detection. The test vectors used to verify the truth table shall, at a minimum, test all functions of

each input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth

table in figure 2 herein. Func tional tests shall be performed in sequence as approved b y the qualifying a c tivity on qualified

devices. After incorporating allowable tolerances per MIL-STD-883, VIL = 0.4 V and VIH = 2.4 V. For outputs, L ≤ 0.8 V, H

≥ 2.0 V.

12/ See JESD 17 for electrically induced latch-up test methods and procedures. The values listed for Vtrigger, Itrigger and Vover,

are to be accurate within ±5 percent.

13/ AC limits at VCC = 5.5 V are equal to limits at VCC = 4.5 V and guaranteed by testing at VCC = 4.5 V. Minimum AC limits for

VCC = 5.5 V are 1.0 ns and guaranteed b y guardbanding the VCC = 4.5 V minimum limits to 1.5 ns. F or propagati on delay

tests, all paths must be tested.

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Device type

01

Case outlines

R, S, and 2

Terminal number

Terminal symbol

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

MR

Q0

D0

D1

Q1

Q2

D2

D3

Q3

GND

CP

Q4

D4

D5

Q5

Q6

D6

D7

Q7

VCC

Pin description

Terminal symbol

Description

Dn (n = 0 to 7)

Data inputs

Qn (n = 0 to 7)

Data outputs

MR

Master reset input (active low)

CP

Clock pulse input

FIGURE 1. Terminal connections.

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Device type 01

Inputs

Outputs

__

MR

CP

Dn

Qn

L

H

X

↑

L

X

H

L

X

L

H

L

Q0

H = High voltage level

L = Low voltage level

X = Irrelevant

↑ = Transition from low to high level

Q0 = The level of Q before the indicated steady-state input

conditions were established

FIGURE 2. Truth table.

FIGURE 3. Logic diagram.

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NOTES:

1. CL= includes a 47 pF chip capacitor (-0 percent, +20 percent) and at least 3 pF of equivalent capacitance from the test jig

and probe.

2. RL= 450Ω ± 1 percent, chip resistor in series with a 50Ω termination. For monitored outputs, the 50Ω termination shall

be the 50Ω characteristic impeda nce of the coaxial connector to the oscilloscop e.

3. Input signal to the device under test:

a. VIN = 0.0 V to 3.0 V; duty cycle = 50 percent; fIN > 1 MHz.

b. tr, tf = 3 ns ±1.0 ns. For input signal generators incapable of maintaining these values of tr and tf, the 3.0 ns limit

c. may be increased up to 10 ns, as needed, maintaining the ±1.0 ns tolerance and guaranteeing the results at 3.0 ns

±1.0 ns; skew between any two switching input signals (tsk): < 250ps.

FIGURE 4. Ground bounce load circuit and waveforms.

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FIGURE 5. Switching waveforms and test circuit.

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NOTES:

1. CL = 50 pF minimum or equivalent (includes test jig and probe capacita nce).

2. RT = 50Ω or equivalent, RL = 500Ω or equivalent.

3. Input signal from pulse g en erator: VIN = 0.0 V to 3.0 V; PRR < 10 MHz; tr < 3.0 ns; tf < 3.0ns; tr and tf shall be

measured from 0.3 V to 2.7 V and from 2.7 V to 0.3 V, respectively; duty cycle = 50 percent.

4. Timing parameters shall be tested at a minimum input frequency of 1 MHz.

5. The outputs are measured one at a time with one transition per measurement.

FIGURE 5. Switching waveforms and test circuit - Continued.

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4. VERIFICATION

4.1 Sampling and inspection. For device classes Q and V, sampling and i nspection procedur es shall be in accordance with

MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan

shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in

accordance with MIL-PRF-38535, appendix A.

4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted

on all devices prior to qualific ation and technology conformance inspection. For device class M, screenin g shall be in

accordance with method 5004 of MIL-STD-883, and shal l be conducted on all devices prior to qua lity conformance inspection.

4.2.1 Additional criteria for device class M.

a. Burn-in test, method 1015 of MIL-STD-883.

(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document re vision

level control and shall be ma de available to the preparing or acquiring activit y upon requ est. The test circuit shall

specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in

method 1015.

(2) TA = +125°C, minimum.

b. Interim and final electrical test parameters shall be as specified in table II herein.

4.2.2 Additional criteria for device classes Q and V.

a. The burn-in test duration, test condition and test temperature, or approved alternatives sh all be as specified in the

device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under

document revision level contro l of the device manufacturer's Technolog y Review Board (TRB) in accordance with

MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall

specify the inputs, outputs, biases, and power dissipation, as applica ble, in accordance with the intent specified in

method 1015 of MIL-STD-883.

b. Interim and final electrical test parameters shall be as specified in table II herein.

c. Additional screening for device class V beyond the requirements of devic e class Q shall be as specified in

MIL-PRF-38535, appendix B.

4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in

accordance with MIL-PRF-38535. Inspectio ns to be performed shall be those specified in MIL-PRF-38 535 and herein for groups

A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).

4.4 Conformance inspection. T echnolo gy conformance inspection for classes Q and V shall be in accordance with

MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein except where option 2 of

MIL-PRF-38535 permits alternate in- line control testing. Quality conformanc e inspection for device class M shall be i n

accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be

those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).

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TABLE II. Electrical test requirements.

Test requirements Subgrou ps

(in accordance with

MIL-STD-883,

method 5005, table I)

Subgroups

(in accordance with

MIL-PRF-38535, table III)

Device

class M

Device

class Q

Device

class V

Interim electrical

parameters (see 4.2)

- - - 1 1

Final electrical

parameters (see 4.2)

1/ 1, 2, 3, 7,

8, 9

1/ 1, 2, 3, 7,

8, 9, 10, 11

2/ 1, 2, 3, 7,

8, 9, 10, 11

Group A test

requirements (see 4.4)

1, 2, 3, 4, 7,

8, 9, 10, 11

1, 2, 3, 4, 7,

8, 9, 10, 11

1, 2, 3, 4, 7,

8, 9, 10, 11

Group C end-point electrical

parameters (see 4.4)

1, 2, 3 1, 2, 3, 7, 8 1, 2, 3, 7, 8

Group D end-point electrical

parameters (see 4.4)

1, 2, 3 1, 2, 3, 7, 8 1, 2, 3, 7, 8

Group E end-point electrical

parameters (see 4.4)

1, 7, 9 1, 7, 9 1, 7, 9

1/ PDA applies to subgroup 1.

2/ PDA applies to subgroups 1 and 7.

4.4.1 Group A inspection.

a. Tests shall be as specified in table II herein.

b. The test vectors used to verify the truth table shall, at a minimum, test all functions of each input and output. All

possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2, herein.

c. CIN and CPD shall be measured only for initial qualification and after process or design changes which may affect

capacitance. CIN shall be measured between the designated terminal and GND at a frequenc y of 1 MHz. For CIN and

CPD, test all applicable pins on five devices with zero failures.

d. Ground and VCC bounce tests are required fo r all device classes. These tests shall be performed only for initial

qualification, after process or design changes which may affect the performance of the device, and any chan ges to the

test fixture. VOLP, VOLV, VOHP, and VOHV shall be meas ured for the worst case outputs of the device. All other outputs

shall be guaranteed, if not tested, to the limits established f or the worst case outputs. The worst case outputs tested are

to be determined by the manufacturer. Test 5 devices assembl ed in the worst case package type supplied to this

document. All other package t ypes shall be guaranteed, if not tested, to the limits established for the worst case

package. The 5 devices to be tested shall be the worst case device type supplied to this drawing. All other device

types shall be guarante ed, if not tested, to the limits established for the worst case device type. The pa ckage type and

device type to be tested shall be determined by the manufacturer. The device manufacturer will submit to DSCC-VA

data that shall include all measured peak values for each device tested and detailed oscilloscope plots for each VOLP,

VOLV, VOHP, and VOHV from one sample part per function. The plot shall contain the waveforms of both a switching output

and the output under test.

Each device m anufacturer shall test product on the fixtures the y currently use. When a new fixture is us ed, the device

manufacturer shall inform DSCC-VA of this change and test the 5 devices on both the new and old test fixtures. The

device manufacturer shal l then submit to DSCC-VA data from testing on both fixtures, that shall include all measured

peak values for each device tested and detailed oscilloscope plots for each VOLP, VOLV, VOHP, and VOHV from one sample

part per function. The plot shall contain the waveforms of both a switching output and the output under test.

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For V

OLP, VOLV, VOHP, and VOHV a device manufacturer may qualify devices by functional groups. A specific functiona l

group shall be composed of function types, that by design, will yield the same test values when tested in accordance

with table I, herein. The device manufacturer shall set a fun ctional group limit for the VOLP, VOLV, VOHP, and VOHV tests.

The device manufacturer may then test one device function from a functional group, to the limits and conditions

specified herein. All other device functions in that particular functional gro up shall be guaranteed, if not tested, to the

limits and conditions specified in table I, here in. T he device manufacturers shall submit to DSCC-VA the device

functions listed in each functional group and test results, along with the oscilloscope plots, for each device tested.

e. Latch-up tests are required for device class V. These tests shall be performed only for init ial qualification and after

process or design changes which may affect the performanc e of the device. Latch-up tests shall be considered

destructive. Test all applicable pins on five devices with zero failures.

4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein.

4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:

a. Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level

control and shall be made available to the preparing or acquiring activit y upon request. The test circuit shall specify the

inputs, outputs, biases, and power dissipation, as applicable, in accordance with the inte nt specified in test method 1005

of MIL-STD-883.

b. TA = +125°C, minimum.

c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.

4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,

or approved alternativ es shall be as specified in the device manufacturer's QM plan in accordance with

MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB in

accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit

shall specify the inp uts, outpu ts, biases, and power dissipation, as applicable, in accordance with the intent specified in test

method 1005 of MIL-STD-883.

4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table II herein.

4.4.4 Group E inspection. Group E inspection is required onl y for parts intended to be marked as radiation hardness assured

(see 3.5 herein).

a. End-point e lectrical parameters shall be as specified in table II herein.

b. For device classes Q, and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as

specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to

radiation hardness assured tests as specified in MIL-PRF - 38535, appendix A for the RHA level being tested. All device

classes must meet the postirradiation end-point electrical parameter limits as defined in table I at TA = +25°C ±5°C, after

exposure, to the subgroups specified in table II herein.

4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883

method 1019, condition A and as specified herein. Prior to and during total dose irrad iation characterization and testing, the

devices for characterization shall b e biased so that 50 percent are at inputs high and 50 p ercent are at inputs low, and the

devices for testing shall be biased to the worst case condition established during characterizatio n. Device s shall be biased as

follows:

1. Inputs tested high, VCC = 5.5 V dc + 5%, RCC = 10Ω ±20%, VIN = 5.0 V dc +5%, RIN = 1 kΩ ±20%, and all outputs are

open.

2. Inputs tested low, VCC = 5.5 V dc +5%, RCC = 10Ω ±20%, VIN = 0.0 V dc, RIN = 1 kΩ ±20%, and all outputs are open.

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4.4.4.1.1 Accelerated annealing test . Accelerated annealing tests shall b e performed on all devices requiring a RHA l evel

greater than 5k rads (Si). The post-anneal e nd-point electrical parameter limits shall be as specified in table I herein and shall be

the pre-irradiation end-point electrical parameter limit at 25°C ±5°C. Testing shall be performed at initial qualification and after

any design or process chan ges which may affect the RHA response of the device.

4.5 Methods of inspection. Methods of inspection shall be specified as follows:

4.5.1 Voltage and current. Unless otherwise specified, all voltages giv en are referenced to the microcircuit GND terminal.

Currents given are convention al current and positive when flowing into the referenced terminal.

5. PACKAGING

5.1 Packaging requirements. The requir eme nts for packaging shall be in accordance with MIL-PRF-38535 for device classes

Q and V or MIL-PRF-38535, appendix A for device class M.

6. NOTES

6.1 Intended use. Microcircuits conforming t o this drawing are intended for use for Government microcircuit applicati on s

(original equipment), desig n applications, and lo gistics purposes.

6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-

prepared specification or drawing.

6.1.2 Substitutability. Device class Q devices will replace device class M devices.

6.2 Configuration control of SMD's. All proposed chan ges to existing SMD's will be coordinated with the users of record for

the individual documents. This coordination will be accomplished in accordance with MIL-STD-973 using DD F orm 1692,

Engineering Change Proposal.

6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system

application requires configuration control an d which SMD's are applicable to that system. DSCC will maintain a record of users

and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic

devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.

6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43218-3990, or telepho ne

(614) 692-0547.

6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herei n are defined in

MIL-PRF-38535 and MIL-HDBK-1331.

6.6 Sources of supply.

6.6.1 Sources of supply for device classes Q and V. Sources of suppl y for device classes Q and V are listed in QML-38535.

The vendors listed in QML-38535 h ave submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have a gree d to

this drawing.

6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.

The vendors listed in MIL-HDBK-103 h ave agreed to this drawing and a certificate of compliance (see 3.6 herein) has been

submitted to and accepted by DSCC-VA.

STANDARD MICROCIRCUIT DRAWING SOURCE APPROVAL BULLETIN

DATE: 08-03-17

Approved sources of suppl y for SMD 5962-89735 are listed belo w for immediate acquisition information only and

shall be added to MIL-HDBK-103 an d QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be

revised to include the addition or deletion of sources. The vendors listed bel ow have agreed to this drawing and a

certificate of compliance has been subm itted to and accepted by DSCC-VA. This information bulletin is superseded

by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current

sources of supply at http://www.dscc.dla.mil/Programs/Smcr/.

Standard

microcircuit drawing

PIN 1/

Vendor

CAGE

number

Vendor

similar

PIN 2/

5962-89735012A 0C7V7 54ACTQ273LMQB

5962-8973501RA 0C7V7 54ACTQ273DMQB

5962-8973501SA 0C7V7 54ACTQ273FMQB

5962R8973501RA 3/ 54ACTQ273DMQB-R

5962R8973501SA 3/ 54ACTQ273FMQB-R

5962R89735012A 3/ 54ACTQ273LMQB-R

5962-8973501VRA 3/

5962-8973501VSA 3/

5962-8973501V2A 3/

5962R8973501V2A 27014 54ACTQ273ERQMLV

5962R8973501VRA 27014 54ACTQ273JRQMLV

5962R8973501VSA 27014 54ACTQ273WRQMLV

1/ T he lead finish shown for each PIN representing a hermetic

package is the most readily available from the manufacturer

listed for that part. If the desired lead finish is not listed

contact the Vendor to determine its availability.

2/ Caution. Do not use this number for item

acquisition. Items acquired to this number m ay not

satisfy the performance requir ements of this drawing.

3/ No longer available from an approved source of supply.

Vendor CAGE Vendor name

number and address

27014 National Semiconductor

2900 Semiconductor Drive

P.O. Box 58090

Santa Clara, CA 95052-8090

Point of contact: 5 Foden Road

South Portland, ME 04106

0C7V7 QP Semiconductor

2945 Oakmead Village Court

Santa Clara, CA 95051

The information contained herein is disseminated for conv enience only and the

Government assumes no liability whatsoeve r for any inaccuracies in the

information bulletin.