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TYPICAL APPLICATION
FIGURE 1. VOLTAGE-TO-CURRENT CONVERSION
DC and low distortion AC current waveforms are delivered
to a grounded load by using matched resistors (A and B
sections) and taking advantage of the high common mode
rejection of the PA10.
Foldover current limit is used to modify current limits based
on output voltage. When load resistance drops to 0, the current
is limited based on output voltage. When load resistance drops
to 0, the current limit is 0.79A resulting in an internal dissipa-
tion of 33.3 W. When output voltage increases to 36V, the
current limit is 1.69A. Refer to Application Note 9 on foldover
limiting for details.
EXTERNAL CONNECTIONS
FEATURES
• GAIN BANDWIDTH PRODUCT — 4MHz
• TEMPERATURE RANGE — –55 to +125°C (PA10A)
• EXCELLENT LINEARITY — Class A/B Output
• WIDE SUPPLY RANGE — ±10V to ±50V
• HIGH OUTPUT CURRENT — ±5A Peak
APPLICATIONS
• MOTOR, VALVE AND ACTUATOR CONTROL
• MAGNETIC DEFLECTION CIRCUITS UP TO 4A
• POWER TRANSDUCERS UP TO 100kHz
• TEMPERATURE CONTROL UP TO 180W
• PROGRAMMABLE POWER SUPPLIES UP TO 90V
• AUDIO AMPLIFIERS UP TO 60W RMS
DESCRIPTION
The PA10 and PA10A are high voltage, high output current
operational amplifiers designed to drive resistive, inductive
and capacitive loads. For optimum linearity, the output stage
is biased for class A/B operation. The safe operating area
(SOA) can be observed for all operating conditions by selec-
tion of user programmable current limiting resistors. Both
amplifiers are internally compensated for all gain settings. For
continuous operation under load, a heatsink of proper rating
is recommended.
This hybrid integrated circuit utilizes thick film (cermet)
resistors, ceramic capacitors and semiconductor chips to
maximize reliability, minimize size and give top performance.
Ultrasonically bonded aluminum wires provide reliable inter-
connections at all operating temperatures. The 8-pin TO-3
package is hermetically sealed and electrically isolated. The
use of compressible isolation washers voids the warranty.
EQUIVALENT SCHEMATIC
8-PIN TO-3
PACKAGE STYLE CE
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ABSOLUTE MAXIMUM RATINGS
SPECIFICATIONS
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS SUPPLY VOLTAGE, +VS to –VS 100V
OUTPUT CURRENT, within SOA 5A
POWER DISSIPATION, internal 67W
INPUT VOLTAGE, differential ±VS –3V
INPUT VOLTAGE, common mode ±VS
TEMPERATURE, pin solder - 10s 300°C
TEMPERATURE, junction1 200°C
TEMPERATURE RANGE, storage –65 to +150°C
OPERATING TEMPERATURE RANGE, case –55 to +125°C
PA10 PA10A
PARAMETER TEST CONDITIONS 2, 5 MIN TYP MAX MIN TYP MAX UNITS
INPUT
OFFSET VOLTAGE, initial TC = 25°C ±2 ±6 ±1 ±4 mV
OFFSET VOLTAGE, vs. temperature Full temperature range ±10 ±65 * ±40 µV/°C
OFFSET VOLTAGE, vs. supply TC = 25°C ±30 ±200 * * µV/V
OFFSET VOLTAGE, vs. power TC = 25°C ±20 * µVW
BIAS CURRENT, initial TC = 25°C 12 30 10 20 nA
BIAS CURRENT, vs. temperature Full temperature range ±50 ±500 * * pA/°C
BIAS CURRENT, vs. supply TC = 25°C .±10 * pA/V
OFFSET CURRENT, initial TC = 25°C ±12 ±30 ±5 ±10 nA
OFFSET CURRENT, vs. temperature Full temperature range ±50 * pA/°C
INPUT IMPEDANCE, DC TC = 25°C 200 * MΩ
INPUT CAPACITANCE TC = 25°C 3 * pF
COMMON MODE VOLTAGE RANGE3 Full temperature range ±VS–5 ±VS–3 * * V
COMMON MODE REJECTION, DC3 Full temp. range, VCM = ±VS –6V 74 100 * * dB
GAIN
OPEN LOOP GAIN at 10Hz TC = 25°C, 1KΩ load 110 * dB
OPEN LOOP GAIN at 10Hz Full temp. range, 15Ω load 96 108 * * dB
GAIN BANDWIDTH PRODUCT @ 1MHz TC = 25°C, 15Ω load 4 * MHz
POWER BANDWIDTH TC = 25°C, 15Ω load 10 15 * * kHz
PHASE MARGIN Full temp. range, 15Ω load 35 * °
OUTPUT
VOLTAGE SWING3 TC = 25°C, IO = 5A ±VS–8 ±VS–5 ±VS–6 * V
VOLTAGE SWING3 Full temp. range, IO = 2A ±VS–6 * V
VOLTAGE SWING3 Full temp. range, IO = 80mA ±VS–5 * V
CURRENT, peak TC = 25°C 5 * A
SETTLING TIME to .1% TC = 25°C, 2V step 2 * µs
SLEW RATE TC = 25°C 2 3 * * V/µs
CAPACITIVE LOAD Full temperature range, AV = 1 .68 * nF
CAPACITIVE LOAD Full temperature range, AV = 2.5 10 * nF
CAPACITIVE LOAD Full temperature range, AV > 10 SOA * nF
POWER SUPPLY
VOLTAGE Full temperature range ±10 ±40 ±45 * * ±50 V
CURRENT, quiescent TC = 25°C 8 15 30 * * * mA
THERMAL
RESISTANCE, AC, junction to case4 TC = –55 to +125°C, F > 60Hz 1.9 2.1 * * °C/W
RESISTANCE, DC, junction to case TC = –55 to +125°C 2.4 2.6 * * °C/W
RESISTANCE, junction to air TC = –55 to +125°C 30 * °C/W
TEMPERATURE RANGE, case Meets full range specifications –25 +85 –55 +125 °C
PA10 • PA10A
The internal substrate contains beryllia (BeO). Do not break the seal. If accidentally broken, do not crush, machine, or
subject to temperatures in excess of 850°C to avoid generating toxic fumes.
CAUTION
NOTES: * The specification of PA10A is identical to the specification for PA10 in applicable column to the left.
1. Long term operation at the maximum junction temperature will result in reduced product life. Derate internal power dissipation
to achieve high MTTF.
2. The power supply voltage for all tests is ±40, unless otherwise noted as a test condition.
3. +VS and –VS denote the positive and negative supply rail respectively. Total VS is measured from +VS to –VS.
4. Rating applies if the output current alternates between both output transistors at a rate faster than 60Hz.
5. Full temperature range specifications are guaranteed but not tested.
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TYPICAL PERFORMANCE
GRAPHS PA10 • PA10A
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OPERATING
CONSIDERATIONS
PA10 • PA10A
GENERAL
Please read Application Note 1 "General Operating Consider-
ations" which covers stability, supplies, heat sinking, mounting,
current limit, SOA interpretation, and specification interpretation.
Visit www.apexmicrotech.com for design tools that help automate
tasks such as calculations for stability, internal power dissipation,
current limit; heat sink selection; Apex’s complete Application Notes
library; Technical Seminar Workbook; and Evaluation Kits.
SAFE OPERATING AREA (SOA)
The output stage of most power amplifiers has three distinct
limitations:
1. The current handling capability of the transistor geometry and
the wire bonds.
2. The second breakdown effect which occurs whenever the
simultaneous collector current and collector-emitter voltage
exceeds specified limits.
3. The junction temperature of the output transistors.
The SOA curves combine the effect of these limits. For a given
application, the direction and magnitude of the output current
should be calculated or measured and checked against the SOA
curves. This is simple for resistive loads but more complex for
reactive and EMF generating loads.
1. For DC outputs, especially those resulting from fault condi-
tions, check worst case stress levels against the new SOA
graph.
For sine wave outputs, use Power Design1 to plot a load
line. Make sure the load line does not cross the 0.5ms limit
and that excursions beyond any other second breakdown
line do not exceed the time label, and have a duty cycle of
no more than 10%.
For other waveform outputs, manual load line plotting is
recommended. Applications Note 22, SOA AND LOAD LINES,
will be helpful. A Spice type analysis can be very useful in that
a hardware setup often calls for instruments or amplifiers with
wide common mode rejection ranges.
2. The amplifier can handle any EMF generating or reactive load
and short circuits to the supply rail or shorts to common if the
current limits are set as follows at TC = 85°C:
SHORT TO ±VS SHORT TO
±VS C, L, OR EMF LOAD COMMON
50V .21A .61A
40V .3A .87A
35V .36A 1.0A
30V .46A 1.4A
25V .61A 1.7A
20V .87A 2.2A
15V 1.4A 2.9A
CURRENT LIMITING
Refer to Application Note 9, "Current Limiting", for details of
both fixed and foldover current limit operation. Visit the Apex
web site at www.apexmicrotech.com for a copy of the Power
Design spreadsheet (Excel) which plots current limits vs. steady
state SOA. Beware that current limit should be thought of as a
+/–20% function initially and varies about 2:1 over the range
of –55°C to 125°C.
For fixed current limit, leave pin 7 open and use equations
1 and 2.
RCL = 0.65/LCL (1)
ICL = 0.65/RCL (2)
Where:
ICL is the current limit in amperes.
RCL is the current limit resistor in ohms.
For certain applications, foldover current limit adds a slope
to the current limit which allows more power to be delivered
to the load without violating the SOA. For maximum foldover
slope, ground pin 7 and use equations 3 and 4.
0.65 + (Vo * 0.014)
ICL = (3)
RCL
0.65 + (Vo * 0.014)
RCL = (4)
ICL
Where:
Vo is the output voltage in volts.
Most designers start with either equation 1 to set RCL for the
desired current at 0v out, or with equation 4 to set RCL at the
maximum output voltage. Equation 3 should then be used to
plot the resulting foldover limits on the SOA graph. If equa-
tion 3 results in a negative current limit, foldover slope must
be reduced. This can happen when the output voltage is the
opposite polarity of the supply conducting the current.
In applications where a reduced foldover slope is desired, this can
be achieved by adding a resistor (RFO) between pin 7 and ground.
Use equations 4 and 5 with this new resistor in the circuit.
0.65 + Vo * 0.14
10.14 + RFO
ICL = (5)
RCL
0.65 + Vo * 0.14
10.14 + RFO
RCL = (6)
ICL
Where:
RFO is in K ohms.
1 Note 1. Power Design is a self-extracting Excel spreadsheet avail-
able free from www.apexmicrotech.com
This data sheet has been carefully checked and is believed to be reliable, however, no responsibility is assumed for possible inaccuracies or omissions. All specifications are subject to change without notice.
PA10U REV O OCTOBER 2004 © 2004 Apex Microtechnology Corp.
