CCD Area Image Sensor MN3711CFP 4.5mm (1/4 inch) 510H CCD Area Image Sensor Overview Pin Assignments The MN3711CFP is a 4.5mm (1/4 inch) Interline Transfer CCD (ITCCD) solid state image sensor device. This device uses photodiodes in the optoelectric conversion section and CCDs for signal read out. The electronic shutter function has made possible an exposure time of 1/10000 seconds. Further, this device has the features of high sensitivity, low noise, broad dynamic range, and low smear. This device has a total of 270K pixels (542 horizontal x 494 vertical) and provides stable and clear images with a resolution of 330 horizontal TV-lines and 350 vertical TV-lines. Type No. MN3711CFP Size System Color or B/W 4.5mm (1/4 inch) NTSC Color OD 1 14 PW oR 2 13 o V4 RD 3 12 o V3 VO 4 11 o V2 LG 5 10 o V1 o H2 6 9 PT o H1 7 8 Sub MN3711CFP (Top View) C14 WDIP014-P-0400 Features * Total number of pixels: 542 (horizontal) x 494 (vertical) * High sensitivity * Low noise * Broad dynamic range * Low smear * Low image lag * Electronic shutter function present * No image distortion * Small size enables design of compact equipment * High reliability * 14 Pin DIL ceramic package Applications * Compact lightweight camcoders * Cameras for surveillance, measurement, and medical use MN3711CFP CCD Area Image Sensor Block Diagram (2 columns OB+512 columns valid area+28 columns OB) (Internal connection) VO 4 OD 1 Output section GND 14 (Internal bias) LG 5 RD 3 12 o V3 Photodiode Vertical shift register PW 14 (2 dummies+1 OB+492+1 OB+1 dummy) 13 o V4 11 o V2 10 o V1 8 Sub 9 PT Horizontal shift register 2 oR 6 7 o H2 o H1 Pin Descriptions Pin No. Symbol 1 2 3 4 5 6 7 OD oR RD VO LG oH2 o H1 Descriptions Output drain Reset pulse Reset drain Video output Output load transistor gate Horizontal register clock pulse (2) Horizontal register clock pulse (1) Pin No. Symbol 8 9 10 11 12 13 14 Sub PT oV1 oV2 oV3 oV4 PW Descriptions Substrate P-well for protection circuit Vertical shift register clock pulse (1) Vertical shift register clock pulse (2) Vertical shift register clock pulse (3) Vertical shift register clock pulse (4) P-well MN3711CFP CCD Area Image Sensor Absolute Maximum Ratings and Operating Conditions Rating Note 2) Symbol Parameter min Reset drain voltage Output drain voltage Output load transistor gate voltage Note 3) VRD VOD VLG Protection P well voltage VPT P well voltage Reset pulse voltage Horizontal register clock pulse voltage 1 Horizontal register clock pulse voltage 2 Vertical shift register clock pulse voltage 1 Vertical shift register clock pulse voltage 2 Vertical shift register clock pulse voltage 3 Vertical shift register clock pulse voltage 4 Substrate voltage Operating temperature Storage temperature Topr Tstg max min typ Unit max 15.0 14.5 15.0 14.5 (Supplied internally) o V (L) oV (L) -10.0 0.2 -1.0 -1.2 0 -- Reference voltage -- 5.0 18 4.7 Adjust - 0.2 -- 0 5.0 -- 18 4.7 -- 0 - 0.2 0 -- 18 5.0 4.7 - 0.2 -- 0 0 -- 18 15.0 14.5 -- -- 0 - 0.2 -9 -- -7.0 -7.3 -- 15 1.0 0.8 -9 -- -7.0 -7.3 -- 18 15.0 14.5 -- -- 0 - 0.2 -9 -- -7.0 -7.3 -- 15 1.0 0.8 -9 -- -7.0 -7.3 Adjust 3.0 - 0.2 45 25.0 24.5 -10 70 25.0 -- -30 80 -- -- - 0.2 - 0.2 VPW Vo R (H-L)*1 Vo R (Bias) *1 Vo H1 (H) Vo H1 (L) Vo H2 (H) Vo H2 (L) Vo V1 (H) Vo V1 (M) Vo V1 (L) Vo V2 (M) Vo V2 (L) Vo V3 (H) Vo V3 (M) Vo V3 (L) Vo V4 (M) Vo V4 (L) VSub *2 o VSub *2 H-L Bias Operating condition Note 1) 18 18 15.5 15.5 oV (L) - 0.7 -- 5.3 5.0 5.3 0 5.3 0 15.5 0.2 -6.7 1.2 -6.7 15.5 0.2 -6.7 1.2 -6.7 14.5 25.5 -- -- V V V V V V V V V V V V V V V V V V V V V V V C C Note 1) The initial setting of VSub shall be 8.0V and shall be adjusted to the minimum voltage at which no blooming is caused at a light input of 100 times the standard value. The standard light input is the one when the exposure is done at an aperture of F/8 using a light source of 2856K and 1050nt, and placing a color temperature conversion filter LB-40 (Hoya) and an IR cutting filter CAW-500 (t=2.5mm) in the light path. (F/1.4 20.5nt) If any FPN picture is present at the minimum operating condition of VSub, it should be adjusted to the minimum voltage at which there is no FPN picture. When any overflow charge is present, it should be adjusted to the minimum voltage at which the overflow charge is eliminated in the range under 13.5V. Note 2) Absolute maximum ratings: - 0.2 <VSub-VPT < + 55 (V) - 0.2 <VoV-VPT < + 24.5 (V) Note 3) The LG pins should each be grounded via a capacitor of 0.047F or more. *1 *2 VSub when using electronic shutter function o VSub H o VSub(V) Vo RH H-L Vo RL o VSub L Bias (0 to 5.0V DC) E VSub(V) E Optical Characteristics Type No. MN3711CFP Color or B/W Valid pixels H V Color 512 492 S/N typ. (dB) Saturation output typ. (mV) Sensitivity F8 typ. (mV) Vertical smear Sm typ. (%) 58 650 200 0.01 Image lag Horizontal Vertical resolution resolution typ. typ. typ. (%) (TV-lines) (TV-lines) 0 330 350 MN3711CFP CCD Area Image Sensor Graphs of Characteristics CCD Spectral Characteristics Relative responsivity (%) 100 80 60 40 20 Without color filter 0 400 500 600 700 Wavelength (nm) Color Filter Spectral Characteristics 100 CY 80 Ye Mg Transmittance (%) 60 Gr 40 20 0 400 500 600 Wavelength (nm) 700 MN3711CFP CCD Area Image Sensor Example of Recommended Driving Pulses * V Rate timing < Field A > CBLK HD VD o V1 o V2 o V3 o V4 a b a b o Sub o H1 o H2 < Field B > CBLK HD VD o V1 o V2 o V3 o V4 o Sub o H1 o H2 MN3711CFP CCD Area Image Sensor * H Rate timing (232.2T) 206.5T 0T 10.83s (12.03s) CBLK 0T 6.36s (6.58s) HD Margin Dummy Video output OB 1.21s Margin (2 bits) Dummy (1 bit) Blank feed (4 bits) CCD output Margin (7 bits) OB (28 bits) 512 valid bits Dummies (6 bits) OB (2 bits) 45T 154T(178T) 45T 154T(178T) o H1 o H2 70T 100T o V1 90T 120T o V2 o V3 o V4 60T 110T 80T 130T 94T o Sub 134T * High speed pulse timing o H1 o H2 oR CCD output D D D D D : Dummy DS1 DS2 D D OB OB 1 2 3 CY + G Ye + M g CY + G or or or CY + M g Ye + G CY + M g