LTC2751
1
2751f
C2
150pF
–
+
1/2 LT®1469
–
+
1/2 LT1469
16-BIT DAC WITH SPAN SELECT
LTC2751-16
RVOS
RCOM
1
RIN
2
R2
R1
38
ROFS
37
REF
5V
5V
REF RFB
IOUT1
VOUT
36
35
IOUT2
GND
WR
UPD
READ
D/S
CLR
MSPAN
4
16
31
30
29
28
17
18
3, 32, 33
SPAN I/O
S2-S0
C1
15pF
VDD
15
2751 TA01
WR
UPD
READ
D/S
CLR
C3
0.1μF
3
6-14, 19-25 34
DATA I/O
D15-D0
16
TYPICAL APPLICATION
FEATURES
APPLICATIONS
DESCRIPTION
Current Output
12-/14-/16-Bit SoftSpan
TM
DACs with Parallel I/O
The LTC
®
2751 is a family of 12-, 14-, and 16-bit multi-
plying parallel-input, current-output DACs. They operate
from a single 2.7V to 5.5V supply. All parts are guaranteed
monotonic over temperature. The LTC2751A-16 provides
16-bit performance (±1LSB INL and DNL) over temperature
without any adjustments. These SoftSpan™ DACs offer six
output ranges—two unipolar and four bipolar—that can be
programmed through the parallel interface, or pinstrapped
for operation in a single range.
These parts use a bidirectional input/output parallel
interface that allows readback of any on-chip register. A
power-on circuit resets the DAC output to 0V when power is
initially applied. A logic low on the
⎯
C
⎯
L
⎯
R pin asynchronously
clears the DAC to 0V in any output range.
The parts are specifi ed over commercial and industrial
temperature ranges.
16-Bit DAC with Software Selectable Ranges
■ Six Programmable Output Ranges
Unipolar: 0V to 5V, 0V to 10V
Bipolar: ±5V, ±10V, ±2.5V, –2.5V to 7.5V
■ Maximum 16-Bit INL Error: ±1 LSB over Temperature
■ Low 1µA (Maximum) Supply Current
■ Guaranteed Monotonic over Temperature
■ Low Glitch Impulse 1nV • s
■ 2.7V to 5.5V Single Supply Operation
■ 2µs Settling Time to ±1 LSB
■ Reference Input: ±15V
■ Parallel Interface with Readback of All Registers
■ Asynchronous
⎯
C
⎯
L
⎯
R Pin Clears DAC Output to 0V in
Any Output Range
■ Power-On Reset to 0V
■ 38-Pin 5mm × 7mm QFN Package
■ High Resolution Offset and Gain Adjustment
■ Process Control and Industrial Automation
■ Automatic Test Equipment
■ Data Acquisition Systems
LTC2751-16 Integral Nonlinearity
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
CODE
0
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0.0
1.0
0.4
16384 32768
–0.6
0.6
0.8
0.2
49152 65535
2751 TA01b
25°C
90°C
–45°C
VDD = 5V
VREF = 5V
±10V RANGE
LTC2751
2
2751f
13 14 15 16
TOP VIEW
39
LTC2751-12 UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
17 18 19
38 37 36 35 34 33 32
24
25
26
27
28
29
30
31
8
7
6
5
4
3
2
1RCOM
RIN
S2
IOUT2
NC
D11
D10
D9
D8
D7
D6
D5
WR
UPD
READ
D/S
NC
NC
NC
NC
NC
NC
D0
D1
REF
ROFS
RFB
IOUT1
RVOS
S1
S0
D4
D3
VDD
GND
CLR
MSPAN
D2
23
22
21
20
9
10
11
12
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
13 14 15 16
TOP VIEW
39
LTC2751-14 UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
17 18 19
38 37 36 35 34 33 32
24
25
26
27
28
29
30
31
8
7
6
5
4
3
2
1RCOM
RIN
S2
IOUT2
NC
D13
D12
D11
D10
D9
D8
D7
WR
UPD
READ
D/S
NC
NC
NC
NC
D0
D1
D2
D3
REF
ROFS
RFB
IOUT1
RVOS
S1
S0
D6
D5
VDD
GND
CLR
MSPAN
D4
23
22
21
20
9
10
11
12
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
13 14 15 16
TOP VIEW
39
LTC2751-16 UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
17 18 19
38 37 36 35 34 33 32
24
25
26
27
28
29
30
31
8
7
6
5
4
3
2
1RCOM
RIN
S2
IOUT2
NC
D15
D14
D13
D12
D11
D10
D9
WR
UPD
READ
D/S
NC
NC
D0
D1
D2
D3
D4
D5
REF
ROFS
RFB
IOUT1
RVOS
S1
S0
D8
D7
VDD
GND
CLR
MSPAN
D6
23
22
21
20
9
10
11
12
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 39) IS GND, MUST BE SOLDERED TO PCB
ABSOLUTE MAXIMUM RATINGS
IOUT1, IOUT2, RCOM to GND .....................................±0.3V
RFB, ROFS, RIN, REF, RVOS to GND ...........................±15V
VDD to GND .................................................. –0.3V to 7V
S2, S1, S0, D15-D0, MSPAN, READ,
⎯
D/S,
⎯
W
⎯
R,
UPD,
⎯
C
⎯
L
⎯
R to GND ........–0.3V to VDD + 0.3V (7V Max)
(Notes 1, 2)
PIN CONFIGURATION
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2751CUHF-12#PBF LTC2751CUHF-12#TRPBF 275112 38-Lead (5mm × 7mm) Plastic QFN 0°C to 70°C
LTC2751IUHF-12#PBF LTC2751IUHF-12#TRPBF 275112 38-Lead (5mm × 7mm) Plastic QFN –40°C to 85°C
LTC2751CUHF-14#PBF LTC2751CUHF-14#TRPBF 275114 38-Lead (5mm × 7mm) Plastic QFN 0°C to 70°C
LTC2751IUHF-14#PBF LTC2751IUHF-14#TRPBF 275114 38-Lead (5mm × 7mm) Plastic QFN –40°C to 85°C
LTC2751BCUHF-16#PBF LTC2751BCUHF-16#TRPBF 275116 38-Lead (5mm × 7mm) Plastic QFN 0°C to 70°C
LTC2751BIUHF-16#PBF LTC2751BIUHF-16#TRPBF 275116 38-Lead (5mm × 7mm) Plastic QFN –40°C to 85°C
LTC2751ACUHF-16#PBF LTC2751ACUHF-16#TRPBF 275116 38-Lead (5mm × 7mm) Plastic QFN 0°C to 70°C
LTC2751AIUHF-16#PBF LTC2751AIUHF-16#TRPBF 275116 38-Lead (5mm × 7mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
Operating Temperature Range
LTC2751C .................................................... 0°C to 70°C
LTC2751I ................................................. –40°C to 85°C
Maximum Junction Temperature .......................... 125°C
Storage Temperature Range ................... –65°C to 150°C
LTC2751
3
2751f
ELECTRICAL CHARACTERISTICS
V
DD = 5V, VREF = 5V unless otherwise specifi ed. The ● denotes the
specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C.
SYMBOL PARAMETER CONDITIONS
LTC2751-12 LTC2751-14 LTC2751B-16 LTC2751A-16
UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
Static Performance
Resolution ●12 14 16 16 Bits
Monotonicity ●12 14 16 16 Bits
DNL Differential
Nonlinearity
●±1 ±1 ±1 ±0.2 ±1 LSB
INL Integral
Nonlinearity
●±1 ±1 ±2 ±0.4 ±1 LSB
GE Gain Error All Output
Ranges
●±0.5 ±2 ±1.5 ±5 ±20 ±4 ±14 LSB
GETC Gain Error Temp-
erature Coeffi cient
ΔGain/ΔTemp ±0.6 ±0.6 ±0.6 ±0.6 ppm/°C
BZE Bipolar Zero Error All Bipolar
Ranges
●±0.2 ±1 ±0.6 ±3 ±12 ±2 ±8 LSB
BZSTC Bipolar Zero Temp-
erature Coeffi cient
±0.5 ±0.5 ±0.5 ±0.5 ppm/°C
PSR Power Supply
Rejection
VDD = 5V, ±10%
VDD = 3V, ±10%
●
●
±0.025
±0.06
±0.1
±0.25
±0.4
±1
±0.03
±0.1
±0.2
±0.5
LSB/V
ILKG IOUT1 Leakage
Current
TA = 25°C
TMIN to TMAX ●
±0.05
±2
±5
±0.05 ±2
±5
±0.05 ±2
±5
±0.05 ±2
±5
nA
CIOUT1 Output
Capacitance
Full-Scale
Zero Scale
75
45
75
45
75
45
75
45
pF
pF
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Resistances (Note 3)
R1/R2 Reference Inverting Resistors (Note 4) ●16 20 kΩ
RREF DAC Input Resistance ●810 kΩ
RFB Feedback Resistor (Note 3) ●810 kΩ
ROFS Bipolar Offset Resistor (Note 3) ●16 20 kΩ
RVOS Offset Adjust Resistor ●800 1000 kΩ
Dynamic Performance
Output Settling Time 0V to 10V Range, 10V Step. To ±0.0015% FS
(Note 5)
2μs
Glitch Impulse (Note 6) 1 nV•s
Digital-to-Analog Glitch Impulse (Note 7) 1 nV•s
Multiplying Feedthrough Error 0V to 10V Range, VREF = ±10V, 10kHz
Sine Wave
0.5 mV
THD Total Harmonic Distortion (Note 8) Multiplying –110 dB
Output Noise Voltage Density (Note 9) at IOUT1 13 nV/√
⎯
H
⎯
z
Power Supply
VDD Supply Voltage ●2.7 5.5 V
IDD Supply Current, VDD Digital Inputs = 0V or VDD ●0.5 1 μA
VDD = 5V, VREF = 5V unless otherwise specifi ed. The ● denotes specifi cations that apply over the full operating temperature range,
otherwise specifi cations are at TA = 25°C.
LTC2751
4
2751f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Digital Inputs
VIH Digital Input High Voltage 3.3V ≤ VDD ≤ 5.5V
2.7V ≤ VDD < 3.3V
●
●
2.4
2
V
V
VIL Digital Input Low Voltage 4.5V < VDD ≤ 5.5V
2.7V ≤ VDD ≤ 4.5V
●
●
0.8
0.6
V
V
IIN Digital Input Current VIN = GND to VDD ●±1 µA
CIN Digital Input Capacitance VIN = 0V (Note 10) ●6pF
Digital Outputs
VOH IOH = 200µA ●VDD – 0.4 V
VOL IOL = 200µA ●0.4 V
TIMING CHARACTERISTICS
V
DD = 5V, VREF = 5V unless otherwise specifi ed. The ● denotes specifi cations that
apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD = 4.5V to 5.5V
Write and Update Timing
t1I/O Valid to
⎯
W
⎯
R Rising Edge Set-Up ●9ns
t2I/O Valid to
⎯
W
⎯
R Rising Edge Hold ●9ns
t3
⎯
W
⎯
R Pulse Width ●20 ns
t4UPD Pulse Width ●20 ns
t5UPD Falling Edge to
⎯
W
⎯
R Falling Edge No Data Shoot-Through ●0ns
t6
⎯
W
⎯
R Rising Edge to UPD Rising Edge (Note 10) ●0ns
t7
⎯
D/S Valid to
⎯
W
⎯
R Falling Edge Set-Up Time ●9ns
t8
⎯
W
⎯
R Rising Edge to
⎯
D/S Valid Hold Time ●9ns
Readback Timing
t13
⎯
W
⎯
R Rising Edge to READ Rising Edge ●9ns
t14 READ Falling Edge to
⎯
W
⎯
R Falling Edge (Note 10) ●20 ns
t15 READ Rising Edge to I/O Propagation Delay CL = 10pF ●30 ns
t17 UPD Valid to I/O Propagation Delay CL = 10pF ●30 ns
t18
⎯
D/S Valid to READ Rising Edge (Note 10) ●9ns
t19 READ Rising Edge to UPD Rising Edge No Update ●9ns
t20 UPD Falling Edge to READ Falling Edge No Update ●9ns
t22 READ Falling Edge to UPD Rising Edge (Note 10) ●9ns
t23 I/O Bus Hi-Z to READ Rising Edge (Note 10) ●0ns
t24 READ Falling Edge to I/O Bus Active (Note 10) ●20 ns
⎯
C
⎯
L
⎯
R Timing
t25
⎯
C
⎯
L
⎯
R Pulse Width Low ●20 ns
ELECTRICAL CHARACTERISTICS
V
DD = 5V, VREF = 5V unless otherwise specifi ed. The ● denotes the
specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C.
LTC2751
5
2751f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD = 2.7V to 3.3V
Write and Update Timing
t1I/O Valid to
⎯
W
⎯
R Rising Edge Set-Up ●18 ns
t2I/O Valid to
⎯
W
⎯
R Rising Edge Hold ●18 ns
t3
⎯
W
⎯
R Pulse Width ●30 ns
t4UPD Pulse Width ●30 ns
t5UPD Falling Edge to
⎯
W
⎯
R Falling Edge No Data Shoot-Through ●0ns
t6
⎯
W
⎯
R Rising Edge to UPD Rising Edge (Note 10) ●0ns
t7
⎯
D/S Valid to
⎯
W
⎯
R Falling Edge Set-Up Time ●18 ns
t8
⎯
W
⎯
R Rising Edge to
⎯
D/S Valid Hold Time ●18 ns
Readback Timing
t13
⎯
W
⎯
R Rising Edge to Read Rising Edge ●18 ns
t14 Read Falling Edge to
⎯
W
⎯
R Falling Edge (Note 10) ●40 ns
t15 Read Rising Edge to I/O Propagation Delay CL = 10pF ●40 ns
t17 UPD Valid to I/O Propagation Delay CL = 10pF ●40 ns
t18
⎯
D/S Valid to Read Rising Edge (Note 10) ●18 ns
t19 Read Rising Edge to UPD Rising Edge No Update ●9ns
t20 UPD Falling Edge to Read Falling Edge No Update ●9ns
t22 READ Falling Edge to UPD Rising Edge (Note 10) ●18 ns
t23 I/O Bus Hi-Z to Read Rising Edge (Note 10) ●0ns
t24 Read Falling Edge to I/O Bus Active (Note 10) ●40 ns
⎯
C
⎯
L
⎯
R Timing
t25
⎯
C
⎯
L
⎯
R Pulse Width Low ●30 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specifi ed maximum operating
junction temperature may impair device reliability.
Note 3: Because of the proprietary SoftSpan switching architecture, the
measured resistance looking into each of the specifi ed pins is constant for
all output ranges if the IOUT1 and IOUT2 pins are held at ground.
Note 4: R1 is measured from RIN to RCOM; R2 is measured from REF to
RCOM.
Note 5: Using LT1469 with CFEEDBACK = 15pF. A ±0.0015% settling time
of 1.7μs can be achieved by optimizing the time constant on an individual
TIMING CHARACTERISTICS
V
DD = 5V, VREF = 5V unless otherwise specifi ed. The ● denotes specifi cations that
apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C.
basis. See Application Note 74, “Component and Measurement Advances
Ensure 16-Bit DAC Settling Time.”
Note 6: Measured at the major carry transition, 0V to 5V range. Output
amplifi er: LT1469; CFB = 27pF.
Note 7. Full-scale transition; REF = 0V.
Note 8. REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output
amplifi er = LT1469.
Note 9. Calculation from Vn = √
⎯
4
⎯
k
⎯
T
⎯
R
⎯⎯⎯
B, where k = 1.38E-23 J/°K
(Boltzmann constant), R = resistance (Ω), T = temperature (°K), and B =
bandwidth (Hz).
Note 10. Guaranteed by design. Not production tested.
LTC2751
6
2751f
VREF (V)
–10 –8 0
44
–6 2
26810
2751 G09
VDD = 5V
±5V RANGE
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0.0
1.0
0.4
–0.6
0.6
0.8
0.2 +DNL
–DNL
+DNL
–DNL
CODE
0
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0.0
1.0
0.4
16384 32768
–0.6
0.6
0.8
0.2
49152 65535
2751 G01
VDD = 5V
VREF = 5V
±10V RANGE
CODE
0
–1.0
DNL (LSB)
–0.8
–0.4
–0.2
0.0
1.0
0.4
16384 32768
–0.6
0.6
0.8
0.2
49152 65535
2751 G02
VDD = 5V
VREF = 5V
±10V RANGE
TEMPERATURE (°C)
–40
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0.0
1.0
0.4
–20 20
040
–0.6
0.6
0.8
0.2
60 80
2751 G04
VDD = 5V
VREF = 5V
±10V RANGE
+INL
–INL
TEMPERATURE (°C)
–40
–1.0
DNL (LSB)
–0.8
–0.4
–0.2
0.0
1.0
0.4
–20 20
040
–0.6
0.6
0.8
0.2
60 80
2751 G05
VDD = 5V
VREF = 5V
±10V RANGE
+DNL
–DNL
TEMPERATURE (°C)
–40
BZE (LSB)
8
4
2
0
4
–20 20
040
6
6
8
2
60 80
2751 G06
VDD = 5V
VREF = 5V
±10V RANGE
0.5ppm/°C (TYP)
TEMPERATURE (°C)
–40
GE (LSB)
–16
–8
–4
0
8
–20 20
040
–12
12
16
4
60 80
2751 G07
VDD = 5V
VREF = 5V
±10V RANGE
0.6ppm/°C (TYP)
VREF (V)
–10 –8 0
44
–6 2
26810
2751 G08
VDD = 5V
±5V RANGE
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0.0
1.0
0.4
–0.6
0.6
0.8
0.2 +INL
–INL
+INL
–INL
INL vs Temperature DNL vs Temperature Bipolar Zero vs Temperature
Gain Error vs Temperature INL vs VREF DNL vs VREF
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
LTC2751-16
TA = 25°C, unless otherwise noted.
LTC2751
7
2751f
500ns/DIV
UPD
5V/DIV
GATED
SETTLING
WAVEFORM
250μV/DIV
2751 G10
USING LT1469 AMP
CFEEDBACK = 12pF
0V TO 10V STEP
CODE
0
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0.0
1.0
0.4
4096 8192
–0.6
0.6
0.8
0.2
12288 16383
2751 G11
VDD = 5V
VREF = 5V
±10V RANGE
CODE
0
–1.0
DNL (LSB)
–0.8
–0.4
–0.2
0.0
1.0
0.4
4096 8192
–0.6
0.6
0.8
0.2
12288 16383
2751 G12
VDD = 5V
VREF = 5V
±10V RANGE
CODE
0
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0.0
1.0
0.4
1024 2048
–0.6
0.6
0.8
0.2
3072 4095
2751 G13
VDD = 5V
VREF = 5V
±10V RANGE
CODE
0
DNL (LSB)
1024 2048 3072 4095
2751 G14
VDD = 5V
VREF = 5V
±10V RANGE
–1.0
–0.8
–0.4
–0.2
0.0
1.0
0.4
–0.6
0.6
0.8
0.2
TYPICAL PERFORMANCE CHARACTERISTICS
Settling 0V to 10V
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
LTC2751-12
LTC2751-16
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
LTC2751-14
VDD (V)
2.5
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0.0
1.0
0.4
34
3.5 4.5
–0.6
0.6
0.8
0.2
55.5
2751 G09b
+INL
–INL
INL vs VDD
TA = 25°C, unless otherwise noted.
LTC2751
8
2751f
500ns/DIV
UPD
5V/DIV
VOUT
2mV/DIV
2751 G15
USING AN LT1469
CFEEDBACK = 27pF
VDD = 5V
VREF = 5V
0V TO 5V RANGE
1nV•s (TYP)
LOGIC VOLTAGE (V)
01
0
IDD (mA)
2
4
6
8
10
12
2345
2751 G16
ALL DIGITAL PINS TIED TOGETHER
(EXCEPT READ TIED TO GND)
VDD = 5V
VDD = 3V
VDD (V)
2.5
0.5
LOGIC THRESHOLD (V)
0.75
1
1.25
1.5
2
33.5 4 4.5 5 5.5
1.75
2751 G17
RISING
FALLING
UPD FREQUENCY (Hz)
10
SUPPLY CURRENT (μA)
10
100
100k
1
0.1 100 1k 10k 1M
1000
2751 G18
VDD = 5V
VDD = 3V
ALTERNATING ZERO-SCALE/FULL-SCALE
(LTC2751-16)
Midscale Glitch
Logic Threshold
vs Supply Voltage
Supply Current vs
Logic Input Voltage
Supply Current
vs Update Frequency
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2751-12, LTC2751-14, LTC2751-16
TA = 25°C, unless otherwise noted.
LTC2751
9
2751f
PIN FUNCTIONS
RCOM (Pin 1): Center Tap Point of RIN and REF. Normally
tied to the negative input of the external reference invert-
ing amplifi er.
RIN (Pin 2): Input Resistor for External Reference Inverting
Amplifi er. Normally tied to the external reference voltage
VREF and to ROFS (Pin 37). Typically 5V; accepts up to
±15V.
S2 (Pin 3): Span I/O Bit 2. Pins S0, S1 and S2 are used to
program and to read back the output range of the DAC.
IOUT2 (Pin 4): DAC Current Output Complement. Tie IOUT2
to GND.
NC (Pin 5): No Connection. Must be tied to GND, provides
necessary shielding for IOUT2.
D3-D11 (Pins 6-14): LTC2751-12 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D11 is the MSB.
D5-D13 (Pins 6-14): LTC2751-14 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D13 is the MSB.
D7-D15 (Pins 6-14): LTC2751-16 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D15 is the MSB.
VDD (Pin 15): Positive Supply Input 2.7V ≤ VDD ≤ 5.5V.
Requires a 0.1µF bypass capacitor to GND.
GND (Pin 16): Ground. Tie to ground.
⎯
C
⎯
L
⎯
R (Pin 17): Asynchronous Clear. When
⎯
C
⎯
L
⎯
R is taken
to a logic low, the data registers are reset to the zero-volt
code for the present output range (VOUT = 0V).
MSPAN (Pin 18): Manual Span Control Pin. MSPAN is used
to confi gure the LTC2751 for operation in a single, fi xed
output range. When confi gured for single-span operation,
the output range is set via hardware pin strapping. The
span input and DAC registers are transparent and do not
respond to write or update commands.
To confi gure the part for single-span use, tie MSPAN
directly to VDD. If MSPAN is instead connected to GND
(SoftSpan confi guration), the output ranges are set and
verifi ed by using write, update and read operations. See
Manual Span Confi guration in the Operation section.
MSPAN must be connected either directly to GND (Soft-
Span confi guration) or VDD (single-span confi guration).
D0-D2 (Pins 19-21): LTC2751-12 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D0 is the LSB.
D0-D4 (Pins 19-23): LTC2751-14 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D0 is the LSB.
D0-D6 (Pins 19-25): LTC2751-16 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D0 is the LSB.
NC (Pins 22-27): LTC2751-12 Only. No Connection.
NC (Pins 24-27): LTC2751-14 Only. No Connection.
NC (Pins 26, 27): LTC2751-16 Only. No Connection.
⎯
D/S (Pin 28): Data/Span Select. This pin is used to select
activation of the data or span I/O pins (D0 to D15 or S0
to S2, respectively), along with their respective dedicated
registers, for write or read operations. Update operations
ignore
⎯
D/S, since all updates affect both data and span
registers. For single-span operation, tie
⎯
D/S to GND.
READ (Pin 29): Read Pin. When READ is asserted high,
the data I/O pins (D0-D15) or span I/O pins (S0-S2)
output the contents of the selected register (see Table 1).
For single-span operation, readback of the span I/O pins
is disabled.
UPD (Pin 30): Update and Buffer Select Pin. When READ
is held low and UPD is asserted high, the contents of the
input registers (both data and span) are copied into their
respective DAC registers. The output of the DAC is updated,
refl ecting the new DAC register values.
When READ is held high, the update function is disabled
and the UPD pin functions as a buffer selector—logic low
to select the input register, high for the DAC register. See
Readback in the Operation section.
⎯
W
⎯
R (Pin 31): Active Low Write Pin. A Write operation
copies the data present on the data or span I/O pins (D0-
D15 or S0-S2, respectively) into the input register. When
READ is high, the Write function is disabled.
S0 (Pin 32): Span I/O Bit 0. Pins S0, S1 and S2 are used to
program and to read back the output range of the DAC.
LTC2751
10
2751f
PIN FUNCTIONS
S1 (Pin 33): Span I/O Bit 1. Pins S0, S1 and S2 are used to
program and to read back the output range of the DAC.
RVOS (Pin 34): DAC Offset Adjust. Nominal input range is
±5V. If not used, RVOS should be shorted to IOUT2.
IOUT1 (Pin 35): DAC current output; normally tied to the
negative input of the I/V converter amplifi er.
RFB (Pin 36): DAC Feedback Resistor; normally tied to
the output of the I/V converter amplifi er. The DAC output
current from IOUT1 fl ows through the feedback resistor
to the RFB pin.
ROFS (Pin 37): Bipolar Offset Network. This pin provides
the translation of the output voltage range for bipolar
spans. Accepts up to ±15V; normally tied to the positive
reference voltage at RIN (Pin 2).
REF (Pin 38): Feedback Resistor for the Reference Inverting
Amplifi er, and Reference Input for the DAC. Normally tied
to the output of the reference inverting amplifi er. Typically
–5V. Accepts up to ±15V.
Exposed Pad (Pin 39): Ground. The Exposed Pad must
be soldered to the PCB.
LTC2751
11
2751f
BLOCK DIAGRAM
29
31
30
28
17
18
16-BIT DAC WITH SPAN SELECT
DAC
REGISTER
INPUT
REGISTER
RCOM
RIN R2R1
ROFS
REF RFB
IOUT1
IOUT2
READ
WR
UPD
D/S
CLR
MSPAN
2751 BD
CONTROL
LOGIC
3
3
3
I/O
PORT
DAC
REGISTER
INPUT
REGISTER
16
16
16
I/O
PORT
35
3637381
2
4
3, 32, 33
SPAN I/O
S2-S0
6-14, 19-25
DATA I/O
D15-D0
LTC2751
12
2751f
Output Ranges
The LTC2751 is a current-output, parallel-input precision
multiplying DAC with software-programmable output
ranges. SoftSpan provides two unipolar output ranges
(0V to 5V and 0V to 10V), and four bipolar ranges (±2.5V,
±5V, ±10V and –2.5V to 7.5V). These ranges are obtained
when an external precision 5V reference is used. When
a reference voltage of 2V is used, the SoftSpan ranges
become: 0V to 2V, 0V to 4V, ±1V, ±2V, ±4V and –1V to
3V. The output ranges are linearly scaled for references
other than 2V and 5V.
TIMING DIAGRAMS
OPERATION
Digital Section
The LTC2751 family has four internal interface registers
(see Block Diagram). Two of these—one input and one
DAC register—are dedicated to the data I/O port, and two
to the span I/O port. Each port is thus double-buffered. The
double-buffered feature provides the capability to simulta-
neously update the span and code, which allows smooth
voltage transitions when changing output ranges. It also
permits the simultaneous updating of multiple DACs.
CLR
WR
2751 TD01
t3
t6
t5
t7t8
t4
t2
t1
I/O
INPUT
UPD
D/S
t25
WR
2751 TD02
I/O
OUTPUT
I/O
INPUT
READ
UPD
D/S
t13
t23
t15
t19
t17
t20 t22
t18
t14
t24
Write, Update and Clear Timing
Readback Timing
LTC2751
13
2751f
OPERATION
Table 1 shows the functions of the LTC2751.
Table 1. Write, Update and Read Functions
READ
⎯
D/S
⎯
W
⎯
R UPD SPAN I/O DATA I/O
0 0 0 0 - Write to Input Register
0 0 0 1 - Write/Update
(Transparent)
00 10 - -
0 0 1 1 Update DAC Register Update DAC Register
0 1 0 0 Write to Input Register -
0 1 0 1 Write/Update
(Transparent)
-
01 10 - -
0 1 1 1 Update DAC register Update DAC Register
1 0 X 0 - Read Input Register
1 0 X 1 - Read DAC Register
1 1 X 0 Read Input Register -
1 1 X 1 Read DAC Register -
X = Don’t Care
Manual Span Confi guration
Multiple output ranges are not needed in some applications.
To confi gure the LTC2751 for single-span operation, tie the
MSPAN pin to VDD and the
⎯
D/S pin to GND. The desired
output range is then specifi ed by the span I/O pins (S0, S1
and S2) as usual, but the pins are programmed by tying
directly to GND or VDD (see Figure 1 and Table 2). In this
confi guration, the part will initialize to the chosen output
range at power-up, with VOUT = 0V.
When confi gured for manual span operation, span pin
readback is disabled.
Write and Update Operations
The data input register is loaded directly from a 16-bit
microprocessor bus by holding the
⎯
D/S pin low and then
pulsing the
⎯
W
⎯
R pin low. The second register (DAC regis-
ter) is loaded by pulsing the UPD pin high, which copies
the data held in the input register into the DAC register.
Note that updates always include both data and span; but
the DAC register values will not change unless the input
register values have been changed by writing.
Loading the span input register is accomplished in a similar
manner, by holding the
⎯
D/S pin high and then bringing the
⎯
W
⎯
R pin low. The span and data register structures are the
same except for the number of parallel bits—the span
registers have three bits, while the data registers have
12, 14, or 16 bits.
To make both registers transparent for fl owthrough
mode, tie
⎯
W
⎯
R low and UPD high. However, this defeats
the deglitcher operation and output glitch impulse may
increase. The deglitcher is activated on the rising edge
of the UPD pin.
The interface also allows the use of the input and DAC
registers in a master-slave, or edge-triggered, confi gura-
tion. This mode of operation occurs when
⎯
W
⎯
R and UPD
are tied together and driven by a single clock signal. The
data bits are loaded into the input register on the falling
edge of the clock and then loaded into the DAC register
on the rising edge.
The separation of data and span for write and read opera-
tions makes it possible to control both data and span on
one 16-bit wide data bus by allowing span pins S2 to S0
to share bus lines with the data LSBs (D2 to D0). Since
no write or read operation includes both span and data,
there cannot be a confl ict.
The asynchronous clear pin resets the LTC2751 to 0V
(zero-, half- or quarter-scale code) in any output range.
⎯
C
⎯
L
⎯
R resets both the input and DAC data registers, while
leaving the span registers undisturbed.
These devices also have a power-on reset. If confi gured
for SoftSpan operation, the part initializes to zero scale in
the 0V to 5V output range. If confi gured for single-span
operation, the part initializes to the zero-volt code in the
chosen output range.
Figure 1. Confi guring the LTC2751 for
Single-Span Operation (±10V Range)
LTC2751-16
MSPAN
S2
S1
S0
D/S
VDD
2751 F01
WR UPD READ
DATA I/O
16
VDD
LTC2751
14
2751f
OPERATION
is a two-function pin. The update function is disabled when
READ is high, and the UPD pin instead selects the input
or DAC register for readback. Table 1 shows the readback
functions for the LTC2751.
The most common readback task is to check the contents
of an input register after writing to it, before updating the
new data to the DAC register. To do this, bring READ high
while holding UPD low. The contents of the selected port’s
input register are output by the data or span I/O pins.
To read back the contents of a DAC register, bring READ
high, then bring UPD high. The contents of the selected
data or span DAC register are output by the data or span
I/O pins. Note: if no update is desired after the readback
operation, UPD must be returned low before bringing
READ low, otherwise the UPD pin will revert to its primary
function and update the DAC.
System Offset Adjustment
Many systems require compensation for overall system
offset. The RVOS offset adjustment pin is provided for this
purpose. For noise immunity and ease of adjustment, the
control voltage is attenuated to the DAC output:
V
OS = –0.01 • V(RVOS) [0V to 5V, ±2.5V spans]
V
OS = –0.02 • V(RVOS) [0V to 10V, ±5V,
–2.5V to 7.5V spans]
V
OS = –0.04 • V(RVOS) [±10V span]
The nominal input range of this pin is ±5V; other refer-
ence voltages of up to ±15V may be used if needed. The
RVOS pin has an input impedance of 1MΩ. To preserve the
settling performance of the LTC2751, this pin should be
driven with a Thevenin-equivalent impedance of 10kΩ or
less. If not used, RVOS should be shorted to IOUT2.
Table 2. Span Codes
S2 S1 S0 SPAN
0 0 0 Unipolar 0V to 5V
0 0 1 Unipolar 0V to 10V
0 1 0 Bipolar –5V to 5V
0 1 1 Bipolar –10V to 10V
1 0 0 Bipolar –2.5V to 2.5V
1 0 1 Bipolar –2.5V to 7.5V
Codes not shown are reserved and should not be used.
Readback
The contents of any one of the four interface registers can
be read back by using the READ pin in conjunction with
the
⎯
D/S and UPD pins.
A readback operation is initiated by bringing READ to logic
high. The I/O pins, which are high-impedance digital inputs
when READ is low, selectively change to low-impedance
logic outputs during readback.
The I/O pins comprise two ports, data and span. The data
I/O port consists of pins D0-D11, D0-D13 or D0-D15
(LTC2751-12, LTC2751-14 or LTC2751-16, respectively).
The span I/O port consists of pins S0, S1 and S2 for all
parts.
Each I/O port has one dedicated input register and one
dedicated DAC register. The register structure is shown
in the Block Diagram.
The
⎯
D/S pin is used to select which I/O port (data or span)
is confi gured to read back the contents of its registers.
The unselected I/O port’s pins remain high-impedance
inputs.
Once the I/O port is selected, its input or DAC register is
selected for readback by using the UPD pin. Note that UPD
LTC2751
15
2751f
OPERATION— EXAMPLES
WR
2751 TD03
SPAN I/O
INPUT
DATA I/O
INPUT
UPD
D/S
8000H
010
READ = LOW
UPDATE
(±5V RANGE, VOUT = 0V)
WR
2751 TD04
SPAN I/O
INPUT
DATA I/O
INPUT
READ = LOW
UPD
D/S
C000H4000H
011
UPDATE (5V) UPDATE (–5V)
WR
2751 TD05
DATA I/O
OUTPUT
DATA I/O
INPUT
READ
UPD
D/S
8000H
8000H0000H
HI-Z
INPUT REGISTER DAC REGISTER
HI-Z
UPDATE (2.5V)
1. Load ±5V range with the output at 0V. Note that since span and code are updated together, the output, if started at
0V, will stay there.
2. Load ±10V range with the output at 5V, changing to –5V.
3. Write and update midscale code in 0V to 5V range (VOUT = 2.5V) using readback to check the contents of the input
and DAC registers before updating.
LTC2751
16
2751f
Op Amp Selection
Because of the extremely high accuracy of the 16-bit
LTC2751-16, careful thought should be given to op amp
selection in order to achieve the exceptional performance
of which the part is capable. Fortunately, the sensitivity of
INL and DNL to op amp offset has been greatly reduced
compared to previous generations of multiplying DACs.
Tables 3 and 4 contain equations for evaluating the effects
of op amp parameters on the LTC2751’s accuracy when
APPLICATIONS INFORMATION
programmed in a unipolar or bipolar output range. These
are the changes the op amp can cause to the INL, DNL,
unipolar offset, unipolar gain error, bipolar zero and bipolar
gain error. Tables 3 and 4 can also be used to determine
the effects of op amp parameters on the LTC2751-14
and the LTC2751-12. However, the results obtained from
Tables 3 and 4 are in 16-bit LSBs. Divide these results
by 4 (LTC2751-14) and 16 (LTC2751-12) to obtain the
correct LSB sizing.
Table 5 contains a partial list of LTC precision op amps
recommended for use with the LTC2751. The easy-to-use
design equations simplify the selection of op amps to meet
the system’s specifi ed error budget. Select the amplifi er
from Table 5 and insert the specifi ed op amp parameters
in Table 4. Add up all the errors for each category to de-
termine the effect the op amp has on the accuracy of the
part. Arithmetic summation gives an (unlikely) worst-case
effect. A root-sum-square (RMS) summation produces a
more realistic estimate.
()
5V
VREF
()
5V
VREF
()
16.5k
AVOL1
OP AMP
VOS1 (mV)
IB1 (nA)
AVOL1 (V/V)
VOS2 (mV)
IB2 (mV)
AVOL2 (V/V)
VOS1 • 3.2 •
IB1 • 0.0003 •
A1 •
0
0
0
INL (LSB)
()
5V
VREF
()
5V
VREF
()
1.5k
AVOL1
()
66k
AVOL2
()
131k
AVOL1
()
131k
AVOL1
()
131k
AVOL2
()
131k
AVOL2
VOS1 • 0.82 •
IB1 • 0.00008 •
A2 •
0
0
0
DNL (LSB)
()
5V
VREF
()
5V
VREF
A3 • VOS1 • 13.2 •
IB1 • 0.13 •
0
0
0
0
UNIPOLAR
OFFSET (LSB)
()
5V
VREF
()
5V
VREF
()
5V
VREF
VOS1 • 13.2 •
IB1 • 0.0018 •
A5 •
VOS2 • 26.2 •
IB2 • 0.26 •
BIPOLAR GAIN
ERROR (LSB)
()
5V
VREF
()
5V
VREF
()
()
()
5V
VREF
()
5V
VREF
A3 • VOS1 • 19.8 •
IB1 • 0.13 •
0
A4 • VOS2 • 13.1 •
A4 • IB2 • 0.13 •
A4 •
BIPOLAR ZERO
ERROR (LSB)
UNIPOLAR GAIN
ERROR (LSB)
()
5V
VREF
()
5V
VREF
()
5V
VREF
()
5V
VREF
()
5V
VREF
VOS1 • 13.2 •
IB1 • 0.0018 •
A5 •
VOS2 • 26.2 •
IB2 • 0.26 •
Table 3. Variables for Each Output Range That Adjust the
Equations in Table 4
OUTPUT RANGE A1 A2 A3 A4 A5
5V 1.1 2 1 1
10V 2.2 3 0.5 1.5
±5V 22111.5
±10V 4 4 0.83 1 2.5
±2.5V 1 1 1.4 1 1
–2.5V to 7.5V 1.9 3 0.7 0.5 1.5
Table 5. Partial List of LTC Precision Amplifi ers Recommended for Use with the LTC2751 with Relevant Specifi cations
AMPLIFIER
AMPLIFIER SPECIFICATIONS
VOS
µV
IB
nA
AVOL
V/mV
VOLTAGE
NOISE
nV/√
⎯
H
⎯
z
CURRENT
NOISE
pA/√
⎯
H
⎯
z
SLEW
RATE
V/µs
GAIN BANDWIDTH
PRODUCT
MHz
tSETTLING
with LTC2751
µs
POWER
DISSIPATION
mW
LT1001 25 2 800 10 0.12 0.25 0.8 120 46
LT1097 50 0.35 1000 14 0.008 0.2 0.7 120 11
LT1112 (Dual) 60 0.25 1500 14 0.008 0.16 0.75 115 10.5/Op Amp
LT1124 (Dual) 70 20 4000 2.7 0.3 4.5 12.5 19 69/Op Amp
LT1468 75 10 5000 5 0.6 22 90 2 117
LT1469 (Dual) 125 10 2000 5 0.6 22 90 2 123/Op Amp
Table 4. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges (Circuit of Page 1). Subscript 1
Refers to Output Amp, Subscript 2 Refers to Reference Inverting Amp.
LTC2751
17
2751f
APPLICATIONS INFORMATION
Op amp offset will contribute mostly to output offset and
gain error and has minimal effect on INL and DNL. For
the LTC2751-16, a 250µV op amp offset will cause about
0.8LSB INL degradation and 0.2LSB DNL degradation
with a 5V reference. For the LTC2751 programmed in 5V
unipolar mode, the same 250µV op amp offset will cause
a 3.3LSB zero-scale error and a 3.3LSB gain error.
While not directly addressed by the simple equations in
Tables 3 and 4, temperature effects can be handled just as
easily for unipolar and bipolar applications. First, consult
an op amp’s data sheet to fi nd the worst-case VOS and IB
over temperature. Then, plug these numbers in the VOS
and IB equations from Table 4 and calculate the tempera-
ture-induced effects.
For applications where fast settling time is important,
Application Note 74, “Component and Measurement
Advances Ensure 16-Bit DAC Settling Time,” offers a
thorough discussion of 16-bit DAC settling time and op
amp selection.
Precision Voltage Reference Considerations
Much in the same way selecting an operational amplifi er
for use with the LTC2751 is critical to the performance
of the system, selecting a precision voltage reference
also requires due diligence. The output voltage of the
LTC2751 is directly affected by the voltage reference;
thus, any voltage reference error will appear as a DAC
output voltage error.
There are three primary error sources to consider when
selecting a precision voltage reference for 16-bit appli-
cations: output voltage initial tolerance, output voltage
temperature coeffi cient and output voltage noise.
Initial reference output voltage tolerance, if uncorrected,
generates a full-scale error term. Choosing a reference
with low output voltage initial tolerance, like the LT1236
(±0.05%), minimizes the gain error caused by the reference;
however, a calibration sequence that corrects for system
zero- and full-scale error is always recommended.
A reference’s output voltage temperature coeffi cient affects
not only the full-scale error, but can also affect the circuit’s
INL and DNL performance. If a reference is chosen with
a loose output voltage temperature coeffi cient, then the
DAC output voltage along its transfer characteristic will
be very dependent on ambient conditions. Minimizing
the error due to reference temperature coeffi cient can be
achieved by choosing a precision reference with a low
output voltage temperature coeffi cient and/or tightly con-
trolling the ambient temperature of the circuit to minimize
temperature gradients.
As precision DAC applications move to 16-bit and higher
performance, reference output voltage noise may contrib-
ute a dominant share of the system’s noise fl oor. This in
turn can degrade system dynamic range and signal-to-
noise ratio. Care should be exercised in selecting a voltage
reference with as low an output noise voltage as practi-
cal for the system resolution desired. Precision voltage
references, like the LT1236, produce low output noise in
the 0.1Hz to 10Hz region, well below the 16-bit LSB level
in 5V or 10V full-scale systems. However, as the circuit
bandwidths increase, fi ltering the output of the reference
may be required to minimize output noise.
Table 6. Partial List of LTC Precision References Recommended
for Use with the LTC2751 with Relevant Specifi cations
REFERENCE
INITIAL
TOLERANCE
TEMPERATURE
DRIFT
0.1Hz to 10Hz
NOISE
LT1019A-5,
LT1019A-10
±0.05% 5ppm/°C 12µVP-P
LT1236A-5,
LT1236A-10
±0.05% 5ppm/°C 3µVP-P
LT1460A-5,
LT1460A-10
±0.075% 10ppm/°C 20µVP-P
LT1790A-2.5 ±0.05% 10ppm/°C 12µVP-P
Grounding
As with any high resolution converter, clean grounding is
important. A low impedance analog ground plane and star
grounding techniques should be used. IOUT2 must be tied
to the star ground with as low a resistance as possible.
When it is not possible to locate star ground close to
IOUT2, a low resistance trace should be used to route this
pin to star ground. This minimizes the voltage drop from
this pin to ground caused by the code dependent current
fl owing to ground. When the resistance of this circuit
board trace becomes greater than 1Ω, a force/sense am-
plifi ed confi guration should be used to drive this pin (see
Figure 2). This preserves the excellent accuracy (1LSB
INL and DNL) of the LTC2751-16.
LTC2751
18
2751f
APPLICATIONS INFORMATION
7
5
6
1
2
3
C2**
150pF
15V
–15V
8
4
0.1F
0.1F
–
+
1/2 LT1469
–
+
1/2 LT1469
16-BIT DAC WITH SPAN SELECT
LTC2751-16
RVOS
RCOM
1
RIN
2
R2
R1
38
ROFS
37
REF
5V
5V
REF RFB
IOUT1
VOUT
36
35
IOUT2
GND
WR
UPD
READ
D/S
CLR
MSPAN
4
16
31
30
29
28
17
18
3, 33, 32
SPAN I/O
S2-S0
C1
15pF
VDD
15
2751 TA02
WR
UPD
READ
D/S
CLR
C3
0.1F
3
6-14, 19-25 34
DATA I/O
D15-D0
16
**FOR MULTIPLYING APPLICATIONS C2 = 15pF
16-Bit DAC with Software-Selectable Ranges
TYPICAL APPLICATIONS
–
+
1/2 LT®1469
–
+
1/2 LT1469
16-BIT DAC WITH SPAN SELECT
LTC2751-16
RVOS
RCOM
1
RIN
2
5
7
6
2
8
1
3
4
R2
R1
38
ROFS
37
REF
5V
5V
15V
REF RFB
IOUT1
VOUT
36
35
IOUT2
GND
WR
UPD
READ
D/S
CLR
MSPAN
4
16
31
30
29
28
17
18
3, 33, 32
C2**
150pF
SPAN I/O
S2-S0
C1
15pF
VDD
15
WR
UPD
READ
D/S
CLR
C3
0.1F
0.1F
3
6-14, 19-25 34
DATA I/O
D15-D0
16
–
+
6
1
23
IOUT2
2
3
*SCHOTTKY BARRIER DIODE
**FOR MULTIPLYING APPLICATIONS C2 = 15pF
ZETEX*
BAT54S
LT1001
2751 F02
1000pF
ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE
6
1
23
6
–
+
LT1468
3
ZETEX
BAT54S
2
200
200
IOUT2
–15V
0.1F
Figure 2. Basic Connections for SoftSpan VOUT DAC with Two Optional Circuits
for Driving IOUT2 from GND with a Force/Sense Amplifi er
LTC2751
19
2751f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701)
5.00 ± 0.10
(2 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
PIN 1
TOP MARK
(SEE NOTE 6)
0.40 ± 0.10
37
1
2
38
BOTTOM VIEW—EXPOSED PAD
5.15 ± 0.10
(2 SIDES)
7.00 ± 0.10
(2 SIDES)
0.75 ± 0.05
R = 0.115
TYP
0.25 ± 0.05
(UH) QFN 0205
0.50 BSC
0.200 REF
0.200 REF
0.00 – 0.05
RECOMMENDED SOLDER PAD LAYOUT
3.15 ± 0.10
(2 SIDES)
0.40 ±0.10
0.00 – 0.05
0.75 ± 0.05
0.70 ± 0.05
0.50 BSC
5.15 ± 0.05 (2 SIDES)
3.15 ± 0.05
(2 SIDES)
4.10 ± 0.05
(2 SIDES)
5.50 ± 0.05
(2 SIDES)
6.10 ± 0.05 (2 SIDES)
7.50 ± 0.05 (2 SIDES)
0.25 ± 0.05
PACKAGE
OUTLINE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45° CHAMFER
LTC2751
20
2751f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2007
LT 0907 • PRINTED IN USA
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LT1027 Precision Reference 1ppm/°C Maximum Drift
LT1236A-5 Precision Reference 0.05% Maximum Tolerance, 1ppm 0.1Hz to 10Hz Noise
LT1468 16-Bit Accurate Op-Amp 90MHz GBW, 22V/µs Slew Rate
LT1469 Dual 16-Bit Accurate Op-Amp 90MHz GBW, 22V/µs Slew Rate
LTC1588/LTC1589/
LTC1592
Serial 12-/14-/16-Bit IOUT Single DACs Software-Selectable (SoftSpan) Ranges, ±1LSB INL, DNL, 16-Lead SSOP Package
LTC1591/LTC1597 Parallel 14-/16-Bit IOUT Single DAC Integrated 4-Quadrant Resistors
LTC1821 Parallel 16-Bit VOUT Single DAC ±1LSB INL, DNL, 0V to 10V, 0V to –10V, ±10V Output Ranges
LTC2601/LTC2611/
LTC2621
Serial 12-/14-/16-Bit VOUT Single DACs Single DACs, SPI-Compatible, Single Supply, 0V to 5V Outputs in 3mm × 3mm
DFN-10 Package
LTC2606/LTC2616/
LTC2626
Serial 12-/14-/16-Bit VOUT Single DACs Single DACs, I2C-Compatible, Single Supply, 0V to 5V Outputs in 3mm × 3mm
DFN-10 Package
LTC2641/LTC2642 Serial 12-/14-/16-Bit Unbuffered VOUT Single
DACs
±2LSB INL, ±1LSB DNL, 1µs Settling, Tiny MSOP-10, 3mm × 3mm DFN-10
Packages
LTC2704 Serial 12-/14-/16-Bit VOUT Quad DACs Software-Selectable (SoftSpan) Ranges, Integrated Amplifi ers
–
+
U2A
LT®1469
–
+
U2B
LT1469
LTC2751-16
U1
LT1027
U3
RVOS
RCOM
RIN
2
1
3
8
3
4
2
1
6
7
5
IN OUT
TRIM
GND
ROFS
37
V+
V+
V–
REF RFB
IOUT1
VOUT
36
35
IOUT2
DATA I/O
SPAN I/O
GND
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
S2
S1
S0
4
34
6
7
8
9
10
11
12
13
14
19
20
21
22
23
24
25
3
33
32
4
22
1
6
5
C22
0.001F
C1
30pF
VDD
2751 TA03
R1
10k
WRUPDREADD/S CLR MSPAN
28 29 30 31 17 18
WRUPDREADD/S CLR
GNDGNDNC
51639
15 2 1 38
GND
GND
GND
C23
0.1F
C20
10F
C13
10F
GND
GND
R2
10k
Offset and Gain Trim Circuits. Powering VDD from LT1027 Ensures Quiet Supply
