INTEGRATED CIRCUITS DATA Sil 74LV32 = = | Quad 2-input OR gate Product specification Supersedes data of 1997 Feb 03 IC24 Data Handbook Philips Semiconductors PHILIPS Q 1998 Apr 20 PHILIPSPhilips Semiconductors Product specification ee Quad 2-input OR gate 74LV32 DESCRIPTION The 74LV32 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT32. The 74LV32 provides the 2-input OR function. FEATURES Wide operating voltage: 1.0 to 5.5 V Optimized for Low Voltage applications: 1.0 to 3.6 V Accepts TTL input levels between Voc = 2.7 V and Voc = 3.6 V Typical Vo_p (output ground bounce) < 0.8 V at Voc = 3.3 V, Tamb = 25C. Typical Voyy (output Voy undershoot) > 2 V at Voc = 3.3 V, Tams = 25C. Output capability: standard loc category: SSI QUICK REFERENCE DATA GND = 0 V; Tamb = 25C; tp =t}< 2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT Propagation delay CL = 15 pF; teHU/tPLH nA, nB to nY Veo =33V 6 ns Cc; Input capacitance 3.5 pF Cpp Power dissipation capacitance per gate V| = GND to Vec! 16 pF NOTES: 1. Cpp is used to determine the dynamic power dissipation (Pp in uW) Pp = Cpp x Voc? x fi + (CL x Voc? x fo) where: f, = input frequency in MHz; C, = output load capacitance in pF; fy = output frequency in MHz; Vcc = supply voltage in V; (CL x Voc? x fo) = sum of the outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE | OUTSIDE NORTH AMERICA | NORTH AMERICA PKG. DWG. # 14-Pin Plastic DIL 40C to +125C 7ALV32 N 74LV32 N SOT27-1 14-Pin Plastic SO 40C to +125C 74LV32 D 74LV32 D SOT108-1 14-Pin Plastic SSOP Type II 40C to +125C 74LV32 DB 74LV32 DB SOT337-1 14-Pin Plastic TSSOP Type | 40C to +125C 74LV32 PW 74LV32PW DH SOT402-1 PIN DESCRIPTION FUNCTION TABLE PIN NUMBER SYMBOL NAME AND FUNCTION INPUTS OUTPUTS 1,4,9,12 1A-4A Data inputs nA nB ny 2, 5, 10, 13 1B-4B Data inputs L L L 3, 6, 8, 11 1Y -4Y Data Outputs L H H 7 GND Ground (0 V) H L H 14 Vv Positive supply voltage cc Pply g H H H 1998 Apr 20 H = HIGH voltage level L = LOW voltage level 853-1897 19258Philips Semiconductors Product specification Quad 2-input OR gate 74LV32 PIN CONFIGURATION LOGIC SYMBOL VY 1A | 4 14 | Vog 1 1B [2 13 | 4B 2 v3 12 | 4A 4 2a [ 4 1 | 4y 5 2B [5 10 | 3B 9 ay [6 9 | 3A Zz ey 7 GND [7 | | 3Y 12 " Sv00450 13 LOGIC SYMBOL (IEEE/IEC) SVvo00452 1 24 3 LOGIC DIAGRAM (ONE GATE) 2 | A 21 5 Y 5 B SV00454 8 > 3 10 12 a 7 13 - SV00453 RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT Voc DC supply voltage See Note1 1.0 3.3 5.5 Vv V| Input voltage 0 - Voc Vv Vo Output voltage 0 - Voc Vv Tamb Operating ambient temperature range in free air See pe ane RC to es C Voc = 1.0V to 2.0V _ - 500 : : Voc = 2.0V to 2.7V - 200 tht Input rise and fall times Veo =27V to36V 7 _ 100 ns/V Voc = 3.6V to 5.5V - 50 NOTE: 1. The LV is guaranteed to function down to Voc = 1.0V (input levels GND or Voc); DC characteristics are guaranteed from Voc = 1.2V to Voc = 5.5V. 1998 Apr 20 3Philips Semiconductors Product specification Quad 2-input OR gate 74LV32 ABSOLUTE MAXIMUM RATINGS": 2 In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = OV) SYMBOL PARAMETER CONDITIONS RATING UNIT Voc DC supply voltage 0.5 to +7.0 Vv +I\k DC input diode current V, <-0.5 or Vi > Voc + 0.5V 20 mA tlok DC output diode current Vo < 0.5 or Vo > Veco + 0.5V 50 mA DC output source or sink current 4 tlo standard outputs 0.5V <Vo < Voc + 0.5V 25 mA DC Vcc or GND current for types with HNGND: standard outputs 50 mA Tstg Storage temperature range 65 to +150 C Power dissipation per package for temperature range: 40 to +125C P plastic DIL above +70C derate linearly with 12mW/K 750 Ww TOT plastic mini-pack (SO) above +70C derate linearly with 8 mW/K 500 m plastic shrink mini-pack (SSOP and TSSOP) above +60C derate linearly with 5.5 mW/K 400 NOTE: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions voltages are referenced to GND (ground = OV) LIMITS SYMBOL PARAMETER TEST CONDITIONS -40C to +85C -40C to +125C UNIT MIN TYP! MAX MIN MAX Veo = 1.2V Voc 0.6 Voc Vv HIGH level Input = | Voc = 2.0V 1.4 1.4 V IH | voltage Voc =2.7 to 3.6V 2.0 2.0 Voc = 4.5 to 5.5V 0.7* Voc 0.7* Voc Veo = 1.2V 0.4 GND GND Vib LOW level Input Voc = 2.0V 0.6 0.6 V voltage Voc = 2.7 to 3.6V 0.8 0.8 Voc = 4.5 to 5.5 0.3* Voc 0.3 * Voc Vec = 1.2V; V| = Vin or VIL; -lo = 100A 1.2 Vec = 2.0V; V| = Vin or VIL; -lo = 100A 1.8 2.0 18 HIGH level output ve 7 Vou voltage: all outputs Voc =2.7V; V| = Vin or VIL; lo = 100A 2.5 2.7 2.5 Vv Vec = 3.0V; Vv; = Vin or ViL; -lo = 100A 2.8 3.0 2.8 Vec = 4.5V;V| = Vin or VIL; -lo = 100A 43 45 43 voltage. output | Viog = 3.0V;V) = Viq oF Vip:-lo = 6mA 240 | 282 2.20 VoH | STANDARD V outputs Vec = 4.5V;V| = Vin or VIL; -lo =12mA 3.60 4.20 3.50 Vec = 1.2V; V| = Vin or VIL; lo = 100A 0 Vec = 2.0V; V| = Vin or VIL; lo = 100A 0 0.2 0.2 LOW level output ve VoL voltage: all outputs Vec = 2.7V; Vv; = Vin or ViL; lo = 100A 0 0.2 0.2 Vv Vec = 3.0V;V| = Vin or VIL; lo = 100A 0 0.2 0.2 Vec = 4.5V;V| = Vin or VIL; lo = 100A 0 0.2 0.2 LOW level output _ ay _ voltage; Vec = 3.0V;V, = Vin or VIL; lo =6mA 0.25 0.40 0.50 Vol | STANDARD V outputs Vec = 4.5V;V| = Vin or VIL; lo = 12mA 0.35 0.55 0.65 I Input leakage Voc = 5.5V; V = Voo or GND 1.0 1.0 LA 1998 Apr 20Philips Semiconductors Product specification Quad 2-input OR gate 74LV32 DC ELECTRICAL CHARACTERISTICS (Continued) Over recommended operating conditions voltages are referenced to GND (ground = OV) LIMITS SYMBOL PARAMETER TEST CONDITIONS -40C to +85C -40C to +125C UNIT MIN TYP! MAX MIN MAX Quiescent supply _ Vie a loc current: ssl Vec = 5.5V; V| = Vec or GND; lo =0 20.0 40 pA Additional Alec quiescent supply Voc = 2.7V to 3.6V; V| = Voc 0.6V 500 850 pA current NOTES: 1. All typical values are measured at Tamp = 25C. AC CHARACTERISTICS GND = OV; t, = t = 2.5ns; CL = 50pF; R, = 5002 LIMITS LIMITS CONDITION 6 6 SYMBOL PARAMETER WAVEFORM A0 to +85 C 740 to +125 C | UNIT Vec(V) MIN TYP! MAX MIN MAX 1.2 40 ; 2.0 14 22 28 tpuupin | Pychagationdelay | Figures 1, 2 27 10 16 20 ns 3.01036 82 13 16 4.510 5.5 10 13 NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25C 2. Typical values are measured at Voc = 3.3 V. AC WAVEFORMS TEST CIRCUIT Vu = 1.5 V at Voc 2 2.7 V and < 3.6 V; Vu = 0.5 Vx Voc at Voc < 2.7 V and 24.5 V; Voe VoL and Voy are the typical output voltage drop that occur with the output load. V, VI Vo PULSE nA, nB INPUT GENERATOR D.U.T. GND -__- Rr T oy LEPF AL= 1k Vou = = = = = = nY OUTPUT Test Circuit for Outputs VoL DEFINITIONS Svo04di4 R_ = Load resistor Figure 1. Input (nA, nB) to output (nY) propagation delays C, = Load capacitance includes jig and probe capacitiance and output transition times. Ry = Termination resistance should be equal to Zour of pulse generators. TEST Vec 7 teLHAPHL <2.7V Voc 2.7-3.6V 27V 24.5V Voc Sv00902 Figure 2. Load circuitry for switching times. 1998 Apr 20 5Philips Semiconductors Quad 2-input OR gate Product specification 74LV32 DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 oO c Sg Qa D & S oD a 0 5 10 mm De scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A Ay Ao (1) (1) z (1) UNIT | max. | min. | max. b by D E e al L Me MH w max. 1.73 0.53 0.36 19.50 6.48 3.60 8.25 10.0 mm 42 0.51 32 1.13 0.38 0.23 18.55 6.20 2.54 7.62 3.05 7.80 8.3 0.254 22 . 0.068 | 0.021 0.014 0.77 0.26 0.14 0.32 0.39 inches 0.17 0.020 0.13 0.044 | 0015 0.009 0.73 0.24 0.10 0.30 0.12 0.31 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES VERSION PROJECTION | SUE DATE IEC JEDEC EIAJ 02-44-44 sot27-1 050G04 MO-001AA nt oeont 1 1998 Apr 20Philips Semiconductors Quad 2-input OR gate Product specification 74LV32 $014: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 Zpre RAAB AA A | | t {Ne Ao - __ - __ - _} -- _ - ___-_}_ f A Ay \\ 4 As) pin 1 index ' | t } } - f Fe I ain Lp [e] _ detail X 0 2.5 5mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT | max. | 41 | Az | As bp c Dp) | EY | e HE L Lp Q v w y z | 6 0.25 | 1.45 0.49 | 0.25 | 8.75 | 4.0 6.2 10 | 07 0.7 mm 11-75) o40 | 1.25 | 975 | 036 | 019 | 355] 38} 127] 5a} 1] o4 | oe | 279] 275] Ot | og | go . 0.0098] 0.057 0.019 |0.0098] 0.35 | 0.16 0.24 0.039 | 0.028 0.028| 0 inches | 0.069 |q 9939] 0.049 | 9-91 | 0.014 {0.0075} 0.34 | 0.15 | %9} 0.23 | %41 | 0.016 | 0.024 | 201 | 2-1 | 9-004 | 9 40 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION PROJECTION ISSUE DATE IEC JEDEC EIAJ 94+08-+13- SOT108-1 076E06S MS-012AB on 95.01.33 1998 Apr 20Philips Semiconductors Product specification Quad 2-input OR gate 74LV32 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 D E [A] a [ \ ! . T | LUA tS aT | = oy] le He +l SOA <a- 7 | 14 8 v 1 | | ! ! tf 0 Ao sp ---+---++ Ay mn 4 As) a I pin 1 index { Cy! i I | we T <<_ | r| yi U : | p 0 2.5 5mm be scale DIMENSIONS (mm are the original dimensions) UNIT mex. A, | As | Az | bp e | DM) EM) e | HE L Lp | @ v w y | 2] 6 0.21 | 1.80 0.38 | 0.20] 64 | 54 7.9 1.03 | 0.9 1.4 | 8 mm | 20 | 905 | 1.65 | 25 | 025] 0.09] 60 | 52 | 2] 76 | 125] 063} 07 | 9% | 21] OT] Og | Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC EIAJ PROJECTION $OT337-1 MO-150AB a } coor ta 1998 Apr 20Philips Semiconductors Product specification Quad 2-input OR gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A Pal | NN + f \ - cle -________J wy } : | \~ | Oy - He eles *| Z 14 8 I l | { | Q \ A (Az) 4-4, an j A pin 1 index | x 1 t | f re 1 Lp }< |_+] 1 7 [detail x] ae 0 2.5 5mm scale DIMENSIONS (mm are the original dimensions) A UNIT | ax | At | A2 | As | bp c pM) | EQ] e HE L Lp Q v w y Zz] 6 0.15 | 0.95 0.30 0.2 5.1 4.5 6.6 0.75 0.4 0.72 8 mm | 1-19 | o05 | 0.80] %? | 019] 0.1 | 49 | 43 1] 62 | 1 |oso] o3 | 2? | 218] O71 | o38 } 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC EIAJ PROJECTION $OT402-1 MO-153 a oe nog 1998 Apr 20 9Philips Semiconductors Product specification Quad 2-input OR gate 74LV32 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published ata later date. Philips Preliminary Specification Preproduction Product Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. seine, . This data sheet contains Final Specifications. Philips Semiconductors reserves the rightto make changes Product Specification Full Production . . oo | | F at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors Copyright Philips Electronics North America Corporation 1998 811 East Arques Avenue All rights reserved. Printed in U.S.A. P.O. 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