Aug. 2006 HYS72D 64301H B R- [ 5 / 6 ] - C HYS72D128x00HBR-[5/6]-C HYS72D 128321 H BR- [ 5 / 6 ] - C HYS72D256x20HBR-[5/6]-C 1 8 4 - P i n R e g i s t e r e d D o u b l e - D a t a - R a t e SD R A M M o d u l e RDIMM DDR SDRAM RoHS Compliant Internet Data Sheet Rev. 1.21 Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module HYS72D64301HBR-[5/6]-C, HYS72D128x00HBR-[5/6]-C, HYS72D128321HBR-[5/6]-C, HYS72D256x20HBR-[5/6]-C Revision History: 2006-08, Rev. 1.21 Page Subjects (major changes since last revision) All Qimonda update All Adapted Internet Edition Previous Revision: 2006-03, Rev. 1.2 Page Subjects (major changes since last revision) 8 Added product types to PC2700R Previous Revision: 2005-12, Rev. 1.1 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com qag_techdoc_rev400 / 3.2 QAG / 2006-08-01 03292006-6N25-8R3I 2 Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module 1 Overview 1.1 Features * 184-Pin Registered 8-Byte Dual-In-Line DDR SDRAM Module for PC, Workstation and Server main memory applications * One rank 64M x72, 128M x72 organization , and two ranks 256M x72 organization * Standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single + 2.5 V ( 0.2 V) power supply and +2.6 ( 0.1 V) power supply for DDR400 * Built with DDR SDRAMs in FBGA 60 package * Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) * Auto Refresh (CBR) and Self Refresh * RAS-lockout supported tRAP= tRCD * All inputs and outputs SSTL_2 compatible * Re-drive for all input signals using register and PLL devices. * Serial Presence Detect with E2PROM * Low Profile Modules form factor: 133.35 mm x 28.58 mm (1.1") x 4.00 mm and 133.35 mm x 30.48 mm (1.2") * Standard reference card layout Raw Card A, B, C and F * Gold plated contacts * RoHS Compliant Product1) TABLE 1 Performance Part Number Speed Code Speed Grade Component Module max. Clock Frequency @CL3 @CL2.5 @CL2 fCK3 fCK2.5 fCK2 -5 -6 Unit DDR400B DDR333B -- PC3200-3033 PC2700-2533 -- 200 166 MHz 166 166 MHz 133 133 MHz 1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. Rev. 1.21, 2006-08 03292006-6N25-8R3I 3 Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module 1.2 Description The HYS72D[64/128/256]xxxHBR-[5/6]-C are low-profile versions of the standard Registered DIMM modules with 1.1inch (28.58 mm) and 1.2-inch (30.40 mm) height for Server Applications. The low-profile DIMM versions are available as 64M x72, 128M x72 (1 GB), and 256M x72 (2 GB). The memory array is designed with Double-Data-Rate Synchronous DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes contain factory programmed configuration data and the second 128 bytes are made available to the customer. TABLE 2 Ordering Information Product Type1) Compliance Code2) Description SDRAM Technology PC3200 (CL=3) HYS72D64301HBR-5-C PC3200R-30331-A0 one rank 512 MByte Reg. ECC DIMM 512 MBit (x8) HYS72D128300HBR-5-C PC3200R-30331-C0 one rank 1 GByte Reg. ECC DIMM 512 MBit (x4) HYS72D128321HBR-5-C PC3200R-30331-B0 two ranks 1 GByte Reg. ECC DIMM 512 MBit (x8) HYS72D256320HBR-5-C PC3200R-30331-F0 two ranks 2 GByte Reg. ECC DIMM 512 MBit (x4) PC2700 (CL=2.5) HYS72D64301HBR-6-C PC2700R-25331-A0 one rank 512 MByte Reg. ECC DIMM 512 MBit (x8) HYS72D128300HBR-6-C PC2700R-25331-C0 one rank 1 GByte Reg. ECC DIMM 512 MBit (x4) HYS72D128900HBR-6-C PC2700R-25331-C0 one rank 1 GByte Reg. ECC DIMM 512 MBit (x4) HYS72D128321HBR-6-C PC2700R-25331-B0 two ranks 1 GByte Reg. ECC DIMM 512 MBit (x8) HYS72D256320HBR-6-C PC2700R-25331-F0 two ranks 2 GByte Reg. ECC DIMM 512 MBit (x4) HYS72D256920HBR-6-C PC2700R-25331-F0 two ranks 2 GByte Reg. ECC DIMM 512 MBit (x4) 1) All product types end with a place code designating the silicon-die revision. Reference information available on request. Example: HYS72D256320HBR-5-C, indicating Rev.C die are used for SDRAM components. 2) The Compliance Code is printed on the module labels and describes the speed sort (for example "PC2700R"), the latencies (for example "25331" means CAS latency of 2.5 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Precharge latency of 3 clocks), SPD code definition version 1, and the Raw Card used for this module. TABLE 3 Address Format Density Organization Memory Ranks SDRAMs # of SDRAMs # of row/bank/ column bits Refresh Period Interval 512 MB 64M x72 1 64M x8 9 13/2/12 8K 64 ms 7.8 ms 1 GB 128M x72 1 128M x4 18 13/2/12 8K 64 ms 7.8 ms 1 GB 128M x72 2 64M x8 18 13/2/11 8K 64 ms 7.8 ms 2 GB 256M x72 2 128M x4 36 13/2/12 8K 64 ms 7.8 ms Rev. 1.21, 2006-08 03292006-6N25-8R3I 4 Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module 2 Pin Configuration The pin configuration of the Registered DDR SDRAM DIMM is listed by function in Table 4 (184 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 5 and Table 6 respectively. The pin numbering is depicted in Chapter 1. TABLE 4 Pin Configuration of RDIMM Pin # Name Pin Type Buffer Type Function Clock Signals 137 CK0 I SSTL Clock Signal 138 CK0 I SSTL Complement Clock 21 CKE0 I SSTL Clock Enable Rank 0 111 CKE1 I SSTL Clock Enable Rank 1 2-rank module NC NC SSTL Note: 1-rank module S0 I SSTL Chip Select of Rank 0 158 S1 I SSTL Chip Select of Rank 1 Note: 2-ranks module NC NC - Note: 1-rank module 154 RAS I SSTL Row Address Strobe 65 CAS I SSTL Column Address Strobe 63 WE I SSTL Write Enable 10 RESET I LVCMOS Register Reset Bank Address Bus 1:0 BA0 I SSTL 52 BA1 I SSTL 48 A0 I SSTL 43 A1 I SSTL 41 A2 I SSTL 130 A3 I SSTL Rev. 1.21, 2006-08 03292006-6N25-8R3I Pin Type Buffer Type Function 37 A4 I SSTL Address Bus 11:0 32 A5 I SSTL 125 A6 I SSTL 29 A7 I SSTL 122 A8 I SSTL 27 A9 I SSTL A10 I SSTL AP I SSTL 118 A11 I SSTL 115 A12 I SSTL Address Signal 12 Note: Module based on 256 Mbit or larger dies NC NC - Note: 128 Mbit based module A13 I SSTL Address Signal 13 Note: 1 Gbit based module NC NC - Note: Module based on 512 Mbit or smaller dies Data Bus 63:0 167 Address Signals 59 Name 141 Control Signals 157 Pin # Data Signals Address Bus 11:0 5 2 DQ0 I/O SSTL 4 DQ1 I/O SSTL 6 DQ2 I/O SSTL 8 DQ3 I/O SSTL 94 DQ4 I/O SSTL 95 DQ5 I/O SSTL 98 DQ6 I/O SSTL 99 DQ7 I/O SSTL 12 DQ8 I/O SSTL 13 DQ9 I/O SSTL 19 DQ10 I/O SSTL 20 DQ11 I/O SSTL 105 DQ12 I/O SSTL Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module Pin # Name Pin Type Buffer Type Function Pin # Name Pin Type Buffer Type Function 106 DQ13 I/O SSTL Data Bus 63:0 166 DQ53 I/O SSTL Data Bus 63:0 109 DQ14 I/O SSTL 170 DQ54 I/O SSTL 110 DQ15 I/O SSTL 171 DQ55 I/O SSTL 23 DQ16 I/O SSTL 83 DQ56 I/O SSTL 24 DQ17 I/O SSTL 84 DQ57 I/O SSTL 28 DQ18 I/O SSTL 87 DQ58 I/O SSTL 31 DQ19 I/O SSTL 88 DQ59 I/O SSTL 114 DQ20 I/O SSTL 174 DQ60 I/O SSTL 117 DQ21 I/O SSTL 175 DQ61 I/O SSTL 121 DQ22 I/O SSTL 178 DQ62 I/O SSTL 123 DQ23 I/O SSTL 179 DQ63 I/O SSTL 33 DQ24 I/O SSTL 44 CB0 I/O SSTL 35 DQ25 I/O SSTL 45 CB1 I/O SSTL 39 DQ26 I/O SSTL 49 CB2 I/O SSTL 40 DQ27 I/O SSTL 51 CB3 I/O SSTL 126 DQ28 I/O SSTL 134 CB4 I/O SSTL 127 DQ29 I/O SSTL 135 CB5 I/O SSTL 131 DQ30 I/O SSTL 142 CB6 I/O SSTL 133 DQ31 I/O SSTL 144 CB7 I/O SSTL 53 DQ32 I/O SSTL 5 DQS0 I/O SSTL 55 DQ33 I/O SSTL 14 DQS1 I/O SSTL 57 DQ34 I/O SSTL 25 DQS2 I/O SSTL 60 DQ35 I/O SSTL 36 DQS3 I/O SSTL 146 DQ36 I/O SSTL 56 DQS4 I/O SSTL 147 DQ37 I/O SSTL 67 DQS5 I/O SSTL 150 DQ38 I/O SSTL 78 DQS6 I/O SSTL 151 DQ39 I/O SSTL 86 DQS7 I/O SSTL 61 DQ40 I/O SSTL 47 DQS8 I/O SSTL 64 DQ41 I/O SSTL 97 DM0 I SSTL 68 DQ42 I/O SSTL Data Mask 0 Note: x8 based module 69 DQ43 I/O SSTL DQS9 I/O SSTL 153 DQ44 I/O SSTL Data Strobe 9 Note: x4 based module 155 DQ45 I/O SSTL DM1 I SSTL 161 DQ46 I/O SSTL Data Mask 1 Note: x8 based module 162 DQ47 I/O SSTL DQS10 I/O SSTL 72 DQ48 I/O SSTL Data Strobe 10 Note: x4 based module 73 DQ49 I/O SSTL DM2 I SSTL 79 DQ50 I/O SSTL Data Mask 2 Note: x8 based module 80 DQ51 I/O SSTL DQS11 I/O SSTL 165 DQ52 I/O SSTL Data Strobe 11 Note: x4 based module Rev. 1.21, 2006-08 03292006-6N25-8R3I 107 119 6 Check Bits 7:0 Data Strobes 8:0 Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module Pin # Name Pin Type Buffer Type Function Pin # 129 DM3 I SSTL Data Mask 3 Note: x8 based module DQS12 I/O SSTL Data Strobe 12 Note: x4 based module DM4 I SSTL Data Mask 4 Note: x8 based module DQS13 I/O SSTL Data Strobe 13 Note: x4 based module DM5 I SSTL Data Mask 5 Note: x8 based module DQS14 I/O SSTL Data Strobe 14 Note: x4 based module DM6 I SSTL Data Mask 6 Note: x8 based module DQS15 I/O SSTL Data Strobe 15 Note: x4 based module DM7 I SSTL Data Mask 7 Note: x8 based module DQS16 I/O SSTL Data Strobe 16 Note: x4 based module DM8 I SSTL Data Mask 8 Note: x8 based module 149 159 169 177 140 DQS17 I/O SSTL Pin Type Buffer Type Function 15, VDDQ 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 PWR - I/O Driver Power Supply 7, VDD 38, 46, 70, 85, 108, 120, 148, 168 PWR - Power Supply 3 GND - Ground Plane 11 Data Strobe 17 Note: x4 based module 18 26 EEPROM 92 SCL I CMOS Serial Bus Clock 34 91 SDA I/O OD Serial Bus Data 42 181 SA0 I CMOS 50 182 SA1 I CMOS Slave Address Select Bus 2:0 183 SA2 I CMOS 58 66 74 Power Supplies 1 VREF AI - I/O Reference Voltage 81 184 VDDSPD PWR - EEPROM Power Supply 89 93 100 Rev. 1.21, 2006-08 03292006-6N25-8R3I 7 Name VSS Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module Pin # Name 116 VSS Pin Type Buffer Type Function GND - Ground Plane TABLE 5 Abbreviations for Pin Type Abbreviation Description 124 132 I Standard input-only pin. Digital levels. 139 O Output. Digital levels. 145 I/O I/O is a bidirectional input/output signal. 152 AI Input. Analog levels. 160 PWR Power 176 GND Ground Other Pins NU Not Usable (JEDEC Standard) NC Not Connected (JEDEC Standard) 82 VDDID 9, NC 16, 17, 71, 75, 76, 90, 101, 102, 103, 113, 163, 173 O OD VDD Identification NC - Not connected Rev. 1.21, 2006-08 03292006-6N25-8R3I TABLE 6 Abbreviations for Buffer Type Abbreviation Description 8 SSTL Serial Stub Terminalted Logic (SSTL2) LV-CMOS Low Voltage CMOS CMOS CMOS Levels OD Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR. Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module FIGURE 1 Pin Configuration 184 Pins, Registered VREF VSS DQS0 VDD NC VSS DQ09 VDDQ NC DQ10 CKE0 DQ16 DQS2 A9 A7 DQ19 DQ24 DQ25 A4 DQ26 A2 A1 CB01 DQS8 CB02 CB03 - Pin 001 Pin 003 Pin 005 Pin 007 Pin 009 Pin 011 Pin 013 Pin 015 Pin 017 Pin 019 Pin 021 Pin 023 Pin 025 Pin 027 Pin 029 Pin 031 Pin 033 Pin 035 Pin 037 Pin 039 Pin 041 Pin 043 Pin 045 Pin 047 Pin 049 Pin 051 DQ32 DQ33 DQ34 BA0 DQ40 WE CAS DQS5 DQ43 NC DQ49 NC VDDQ DQ50 VSS DQ56 VDD DQ58 VSS SDA - Pin 053 Pin 055 Pin 057 Pin 059 Pin 061 Pin 063 Pin 065 Pin 067 Pin 069 Pin 071 Pin 073 Pin 075 Pin 077 Pin 079 Pin 081 Pin 083 Pin 085 Pin 087 Pin 089 Pin 091 Pin 002 Pin 004 Pin 006 Pin 008 Pin 010 Pin 012 Pin 014 Pin 016 Pin 018 Pin 020 Pin 022 Pin 024 Pin 026 Pin 028 Pin 030 Pin 032 Pin 034 Pin 036 Pin 038 Pin 040 Pin 042 Pin 044 Pin 046 Pin 048 Pin 050 Pin 052 Pin 094 - DQ04 Pin 096 - VDDQ Pin 098 - DQ06 Pin 100 - VSS Pin 102 - NC Pin 104 - VDDQ Pin 106 - DQ13 Pin 108 - VDD Pin 110 - DQ15 Pin 112 - VDDQ Pin 114 - DQ20 Pin 116 - VSS Pin 118 - A11 Pin 120 - VDD VDDQ - Pin 054 DQS4 - Pin 056 VSS - Pin 058 DQ35 - Pin 060 VDDQ - Pin 062 DQ41 - Pin 064 VSS - Pin 066 DQ42 - Pin 068 VDD - Pin 070 DQ48 - Pin 072 VSS - Pin 074 NC - Pin 076 DQS6 - Pin 078 DQ51 - Pin 080 VDDID - Pin 082 DQ57 - Pin 084 DQS7 - Pin 086 DQ59 - Pin 088 NC - Pin 090 SCL - Pin 092 Pin 146 - DQ36 Pin 148 - VDD Pin 150 - DQ38 Pin 152 - VSS Pin 154 - RAS Pin 156 - VDDQ Pin 158 - S1/NC Pin 160 - VSS Pin 162 - DQ47 Pin 164 - VDDQ Pin 166 - DQ53 Pin 168 - VDD Pin 170 - DQ54 Pin 172 - VDDQ Pin 174 - DQ60 Pin 176 - VSS Pin 178 - DQ62 Pin 180 - VDDQ Pin 182 - SA1 Pin 184 - VDDSPD DQ00 DQ01 DQ02 DQ03 RESET DQ08 DQS1 NC VSS DQ11 VDDQ DQ17 VSS DQ18 VDDQ A5 VSS DQS3 VDD DQ27 VSS CB00 VDD A0 VSS BA1 - Pin 122 Pin 124 Pin 126 Pin 128 Pin 130 Pin 132 Pin 134 Pin 136 Pin 138 Pin 140 Pin 142 Pin 144 - A8 VSS DQ28 VDDQ A3 VSS DQ04 VDDQ CK0 DM8/DQS17 CB06 CB07 VSS Pin 093 Pin 095 Pin 097 Pin 099 Pin 101 Pin 103 Pin 105 Pin 107 Pin 109 Pin 111 Pin 113 Pin 115 Pin 117 Pin 119 Pin 121 Pin 123 Pin 125 Pin 127 Pin 129 Pin 131 Pin 133 Pin 135 Pin 137 Pin 139 Pin 141 Pin 143 - DQ05 DQ00/DQS9 DQ07 NC NC DQ15 DM1/DQS10 DQ14 CKE1/NC NC A12/NC DQ21 DM2/DQS11 DQ22 DQ23 A6 DQ29 DM3/DQS12 DQ30 DQ31 CB5 CK0 VSS A10/AP VDDQ Pin 145 Pin 147 Pin 149 Pin 151 Pin 153 Pin 155 Pin 157 Pin 159 Pin 161 Pin 163 Pin 165 Pin 167 Pin 169 Pin 171 Pin 173 Pin 175 Pin 177 Pin 179 Pin 181 Pin 183 - DQ37 DM4/DQS13 DQ39 DQ44 DQ45 S0 DM5/DQS14 DQ46 NC DQ52 A13/NC DM6/DQS15 DQ55 NC DQ61 DM7/DQS16 DQ63 SA0 SA2 VSS MPPD0020 Rev. 1.21, 2006-08 03292006-6N25-8R3I 9 Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module 3 Electrical Characteristics 3.1 Operating Conditions TABLE 7 Absolute Maximum Ratings Parameter Symbol Values Unit Note/ Test Condition min. typ. max. -0.5 - VDDQ + 0.5 V - -1 - +3.6 V - -1 - +3.6 V - Storage temperature (plastic) VIN, VOUT VIN VDD VDDQ TA TSTG Power dissipation (per SDRAM component) Short circuit output current Voltage on I/O pins relative to VSS Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient) -1 - +3.6 V - 0 - +70 C - -55 - +150 C - PD - 1 - W - IOUT - 50 - mA - Attention: Permanent damage to the device may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. Rev. 1.21, 2006-08 03292006-6N25-8R3I 10 Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module TABLE 8 Electrical Characteristics and DC Operating Conditions Parameter Device Supply Voltage Device Supply Voltage Output Supply Voltage Output Supply Voltage EEPROM supply voltage Supply Voltage, I/O Supply Voltage Input Reference Voltage I/O Termination Voltage (System) Symbol Unit Note/Test Condition1) Values Min. Typ. Max. VDD VDD VDDQ VDDQ VDDSPD VSS, VSSQ 2.3 2.5 2.7 V 2.5 2.6 2.7 V 2.3 2.5 2.7 V 2.5 2.6 2.7 V fCK 166 MHz fCK > 166 MHz 2) fCK 166 MHz 3) fCK > 166 MHz 2)3) 2.3 2.5 3.6 V -- 0 V -- VREF VTT 0.49 x VDDQ 0.51 x VDDQ V 4) VREF - 0.04 VREF + 0.04 V 5) VREF + 0.15 VDDQ + 0.3 V 6) -0.3 VREF - 0.15 V 6) -0.3 VDDQ + 0.3 V 6) VIH(DC) Input Low (Logic0) Voltage VIL(DC) Input Voltage Level, CK and VIN(DC) Input High (Logic1) Voltage 0 0.5 x VDDQ CK Inputs Input Differential Voltage, CK and CK Inputs VID(DC) 0.36 VDDQ + 0.6 V 6)7) VI-Matching Pull-up Current to Pull-down Current VIRatio 0.71 1.4 -- 8) Input Leakage Current II -2 2 A Any input 0 V VIN VDD; All other pins not under test = 0 V9) Output Leakage Current IOZ -5 5 A DQs are disabled; 0 V VOUT VDDQ 9) Output High Current, Normal IOH Strength Driver -- -16.2 mA VOUT = 1.95 V Output Low Current, Normal IOL Strength Driver 16.2 -- mA VOUT = 0.35 V 1) 2) 3) 4) 5) 6) 7) 8) 9) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V; DDR400 conditions apply for all clock frequencies above 166 MHz Under all conditions, VDDQ must be less than or equal to VDD. Peak to peak AC noise on VREF may not exceed 2% VREF.DC. VREF is also expected to track noise variations in VDDQ. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. Inputs are not recognized as valid until VREF stabilizes. VID is the magnitude of the difference between the input level on CK and the input level on CK. The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. Values are shown per pin. Rev. 1.21, 2006-08 03292006-6N25-8R3I 11 Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module TABLE 9 IDD Conditions Parameter Symbol Operating Current 0 one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. IDD0 Operating Current 1 one bank; active/read/precharge; Burst Length = 4; see component data sheet. IDD1 Precharge Power-Down Standby Current all banks idle; power-down mode; CKE VIL,MAX IDD2P Precharge Floating Standby Current CS VIH,,MIN, all banks idle; CKE VIH,MIN; address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM. IDD2F Precharge Quiet Standby Current CS VIHMIN, all banks idle; CKE VIH,MIN; VIN = VREF for DQ, DQS and DM; address and other control inputs stable at VIH,MIN or VIL,MAX. IDD2Q Active Power-Down Standby Current one bank active; power-down mode; CKE VILMAX; VIN = VREF for DQ, DQS and DM. IDD3P Active Standby Current one bank active; CS VIH,MIN; CKE VIH,MIN; tRC = tRAS,MAX; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. IDD3N Operating Current Read one bank active; Burst Length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA IDD4R Operating Current Write one bank active; Burst Length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B IDD4W Auto-Refresh Current tRC = tRFCMIN, burst refresh IDD5 Self-Refresh Current CKE 0.2 V; external clock on IDD6 Operating Current 7 four bank interleaving with Burst Length = 4; see component data sheet. IDD7 Rev. 1.21, 2006-08 03292006-6N25-8R3I 12 Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module TABLE 10 Product Type HYS72D64301HBR-5-C HYS72D128300HBR-5-C HYS72D128321HBR-5-C HYS72D256320HBR-5-C IDD Specification for HYS72D[64/128/256]xxxHBR-5-C Organization 512 MB 1 GB 1 GB 2 GB x72 x72 x72 x72 1 Rank 1 Rank 2 Ranks 2 Ranks -5 -5 -5 -5 Unit Note 1)2) Symbol Typ. Max. Typ. Max. Typ. Max. Typ. Max. IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 1050 1240 1890 2210 1660 1910 3120 3570 mA 3) 1270 1470 2200 2530 1880 2140 3430 3890 mA 3)4) 360 440 670 780 670 780 1290 1460 mA 5) 830 940 1360 1510 1360 1510 2410 2650 mA 5) 510 600 960 1120 960 1120 1870 2140 mA 5) 460 530 860 970 870 970 1670 1850 mA 5) 920 1050 1540 1730 1540 1730 2770 3090 mA 5) 1360 1510 2380 2620 1970 2190 3610 3980 mA 3)4) 1400 1560 2470 2710 2020 2240 3700 4070 mA 3) 1670 2120 3280 4130 2290 2800 4510 5490 mA 3) 330 390 640 740 640 740 1270 1430 mA 5) 2390 2770 4450 5140 3010 3450 5680 6500 mA 3)4) 1) Module IDD is calculated on the basis of component IDD and includes Register and PLL currents 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component] Rev. 1.21, 2006-08 03292006-6N25-8R3I 13 Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module TABLE 11 Product Type HYS72D64301HBR-6-C HYS72D128300HBR-6-C HYS72D128900HBR-6-C HYS72D128321HBR-6-C HYS72D256320HBR-6-C HYS72D256920HBR-6-C IDD Specification for HYS72D[64/128/256]xxxHBR-6-C Organization 512 MB 1 GB 1 GB 2 GB x72 x72 x72 x72 1 Rank 1 Rank 2 Ranks 2 Ranks -6 -6 -6 -6 Unit Note1)2) Symbol Typ. Max. Typ. Max. Typ. Max. Typ. Max. IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7 1000 1140 1790 2020 1530 1720 2860 3180 mA 3) 1160 1360 2000 2330 1700 1940 3060 3490 mA 3)4) 340 410 600 700 600 700 1120 1280 mA 5) 740 840 1180 1310 1180 1310 2060 2260 mA 5) 470 560 860 1000 860 1000 1630 1890 mA 5) 430 500 770 880 770 880 1460 1640 mA 5) 830 940 1370 1520 1370 1520 2440 2690 mA 5) 1210 1410 2090 2420 1740 1990 3150 3580 mA 3)4) 1250 1450 2180 2510 1790 2030 3240 3670 mA 3) 1510 1950 2930 3780 2040 2530 4000 4940 mA 3) 320 390 580 680 580 680 1110 1270 mA 5) 2150 2490 3980 4580 2690 3070 5040 5750 mA 3)4) 1) Module IDD is calculated on the basis of component IDD and includes Register and PLL currents 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the component IDDx data sheet values as: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component] Rev. 1.21, 2006-08 03292006-6N25-8R3I 14 Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module 3.2 A.C. Timing Parameters TABLE 12 AC Timing - Absolute Specifications for PC3200 and PC2700 Parameter Symbol -5 -6 DDR400B DDR333 Min. Max. Min. Max. Unit Note/ Test Condition 1) DQ output access time from CK/CK tAC -0.5 +0.5 -0.7 +0.7 ns 2)3)4)5) CK high-level width tCH 0.45 0.55 0.45 0.55 tCK 2)3)4)5) Clock cycle time tCK 5 8 6 12 ns CL = 3.0 2)3)4)5) 6 12 6 12 ns CL = 2.5 2)3)4)5) 7.5 12 7.5 12 ns CL = 2.0 2)3)4)5) 0.55 0.45 0.55 tCK 2)3)4)5) tCK 2)3)4)5)6) CK low-level width tCL 0.45 Auto precharge write recovery + precharge time tDAL (tWR/tCK)+(tRP/tCK) DQ and DM input hold time tDH 0.4 -- 0.45 -- ns 2)3)4)5) DQ and DM input pulse width (each input) tDIPW 1.75 -- 1.75 -- ns 2)3)4)5)6) DQS output access time from CK/CK tDQSCK -0.6 +0.6 -0.6 +0.6 ns 2)3)4)5) DQS input low (high) pulse width tDQSL,H (write cycle) 0.35 -- 0.35 -- tCK 2)3)4)5) DQS-DQ skew (DQS and associated DQ signals) tDQSQ -- +0.40 -- +0.40 ns TFBGA Write command to 1 DQS latching transition tDQSS 0.72 1.25 0.75 1.25 tCK 2)3)4)5) DQ and DM input setup time tDS 0.4 -- 0.45 -- ns 2)3)4)5) DQS falling edge hold time from CK (write cycle) tDSH 0.2 -- 0.2 -- tCK 2)3)4)5) DQS falling edge to CK setup time (write cycle) tDSS 0.2 -- 0.2 -- tCK 2)3)4)5) Clock Half Period tHP min. (tCL, tCH) -- min. (tCL, tCH) -- ns 2)3)4)5) Data-out high-impedance time from CK/CK tHZ -- +0.7 -0.7 +0.7 ns 2)3)4)5)7) Address and control input hold time tIH 0.6 -- 0.75 -- ns fast slew rate st 2)3)4)5) 3)4)5)6)8) 0.7 -- 0.8 -- ns slow slew rate 3)4)5)6)8) Control and Addr. input pulse width (each input) Rev. 1.21, 2006-08 03292006-6N25-8R3I tIPW 2.2 -- 15 2.2 -- ns 2)3)4)5)9) Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module Parameter Address and control input setup time Symbol tIS -5 -6 DDR400B DDR333 Min. Max. Min. Max. 0.6 -- 0.75 -- Unit Note/ Test Condition 1) ns fast slew rate 3)4)5)6)8) 0.7 -- 0.8 -- ns slow slew rate 3)4)5)6)8) Data-out low-impedance time from CK/CK tLZ -0.7 +0.7 -0.7 +0.7 ns 2)3)4)5)7) Mode register set command cycle time tMRD 2 -- 2 -- tCK 2)3)4)5) DQ/DQS output hold time tQH tHP -tQHS -- tHP -tQHS -- ns 2)3)4)5) Data hold skew factor tQHS -- +0.50 -- +0.50 ns TFBGA 2)3)4)5) Active to Autoprecharge delay tRAP tRCD -- tRCD -- ns 2)3)4)5) Active to Precharge command tRAS 40 70E+3 42 70E+3 ns 2)3)4)5) Active to Active/Auto-refresh command period tRC 55 -- 60 -- ns 2)3)4)5) Active to Read or Write delay tRCD 15 -- 18 -- ns 2)3)4)5) Average Periodic Refresh Interval tREFI -- 7.8 -- 7.8 s 2)3)4)5)10) Auto-refresh to Active/Autorefresh command period tRFC 65 -- 72 -- ns 2)3)4)5) Precharge command period tRP 15 -- 18 -- ns 2)3)4)5) Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK 2)3)4)5) Read postamble tRPST 0.40 0.60 0.40 0.60 tCK 2)3)4)5) 2)3)4)5) Active bank A to Active bank B command tRRD 10 -- 12 -- ns Write preamble tWPRE 0.25 -- 0.25 -- tCK 2)3)4)5) Write preamble setup time tWPRES 0 -- 0 -- ns 2)3)4)5)11) Write postamble tWPST 0.40 0.60 0.40 0.60 tCK 2)3)4)5)12) Write recovery time tWR 15 -- 15 -- ns 2)3)4)5) Internal write to read command delay tWTR 2 -- 1 -- tCK 2)3)4)5) Exit self-refresh to non-read command tXSNR 75 -- 75 -- ns 2)3)4)5) Exit self-refresh to read command tXSRD 200 -- 200 -- tCK 2)3)4)5) 1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR333); DDQ = 2.6 V 0.1 V, DD = +2.6 V 0.1 V (DDR400) 2) Input slew rate 1 V/ns for DDR400, DDR333 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). Rev. 1.21, 2006-08 03292006-6N25-8R3I 16 Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module 8) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VIH(ac) and VIL(ac). 9) These parameters guarantee device timing, but they are not necessarily tested on each device. 10) A maximun of eight Autorefresh commands can be posted to any given DDR SDRAM device 11) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW at this time, depending on tDQSS. 12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. Rev. 1.21, 2006-08 03292006-6N25-8R3I 17 Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module 4 SPD Codes TABLE 13 Product Type HYS72D64301HBR-5-C HYS72D128321HBR-5-C HYS72D128300HBR-5-C HYS72D256320HBR-5-C SPD Codes for HYS72D[64/128/256]3[00/01/20/21]HBR-5-C Organization 512 MB 1 GByte 1 GByte 2 GByte x72 x72 x72 x72 1 Rank (x8) 2 Ranks (x8) 1 Rank (x4) 2 Ranks (x4) PC3200R- 30331 PC3200R-30331 PC3200R- 30331 PC3200R- 30331 JEDEC SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Rev 1.0 Description HEX HEX HEX HEX 0 Programmed SPD Bytes in E2PROM 80 80 80 80 1 Total number of Bytes in E2PROM 08 08 08 08 2 Memory Type (DDR = 07h) 07 07 07 07 3 Number of Row Addresses 0D 0D 0D 0D 4 Number of Column Addresses 0B 0B 0C 0C Label Code Byte# 5 Number of DIMM Ranks 01 02 01 02 6 Data Width (LSB) 48 48 48 48 7 Data Width (MSB) 00 00 00 00 8 Interface Voltage Levels 04 04 04 04 9 tCK @ CLmax (Byte 18) [ns] 50 50 50 50 10 tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 70 70 11 Error Correction Support 02 02 02 02 12 Refresh Rate 82 82 82 82 13 Primary SDRAM Width 08 08 04 04 14 Error Checking SDRAM Width 08 08 04 04 15 tCCD [cycles] 01 01 01 01 16 Burst Length Supported 0E 0E 0E 0E 17 Number of Banks on SDRAM Device 04 04 04 04 Rev. 1.21, 2006-08 03292006-6N25-8R3I 18 Internet Data Sheet Product Type HYS72D64301HBR-5-C HYS72D128321HBR-5-C HYS72D128300HBR-5-C HYS72D256320HBR-5-C HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module Organization 512 MB 1 GByte 1 GByte 2 GByte x72 x72 x72 x72 1 Rank (x8) 2 Ranks (x8) 1 Rank (x4) 2 Ranks (x4) PC3200R- 30331 PC3200R-30331 PC3200R- 30331 PC3200R- 30331 JEDEC SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Rev 1.0 Byte# Description HEX HEX HEX HEX 18 CAS Latency 1C 1C 1C 1C 19 CS Latency 01 01 01 01 20 Write Latency 02 02 02 02 21 DIMM Attributes 26 26 26 26 22 Component Attributes C1 C1 C1 C1 23 tCK @ CLmax -0.5 (Byte 18) [ns] 60 60 60 60 24 tAC SDRAM @ CLmax -0.5 [ns] 70 70 70 70 25 tCK @ CLmax -1 (Byte 18) [ns] 75 75 75 75 26 tAC SDRAM @ CLmax -1 [ns] 70 70 70 70 27 tRPmin [ns] 3C 3C 3C 3C Label Code 28 tRRDmin [ns] 28 28 28 28 29 tRCDmin [ns] 3C 3C 3C 3C 30 tRASmin [ns] 28 28 28 28 31 Module Density per Rank 80 80 01 01 32 tAS, tCS [ns] 60 60 60 60 33 tAH, tCH [ns] 60 60 60 60 34 tDS [ns] 40 40 40 40 35 tDH [ns] 40 40 40 40 36 - 40 not used 00 00 00 00 41 tRCmin [ns] 37 37 37 37 42 tRFCmin [ns] 41 41 41 41 43 tCKmax [ns] 28 28 28 28 44 tDQSQmax [ns] 28 28 28 28 45 tQHSmax [ns] 50 50 50 50 46 not used 00 00 00 00 47 DIMM PCB Height 01 01 01 01 Rev. 1.21, 2006-08 03292006-6N25-8R3I 19 Internet Data Sheet Product Type HYS72D64301HBR-5-C HYS72D128321HBR-5-C HYS72D128300HBR-5-C HYS72D256320HBR-5-C HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module Organization 512 MB 1 GByte 1 GByte 2 GByte x72 x72 x72 x72 1 Rank (x8) 2 Ranks (x8) 1 Rank (x4) 2 Ranks (x4) PC3200R- 30331 PC3200R-30331 PC3200R- 30331 PC3200R- 30331 JEDEC SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Rev 1.0 Byte# Description HEX HEX HEX HEX 48 - 61 not used 00 00 00 00 62 SPD Revision 10 10 10 10 Label Code 63 Checksum of Byte 0-62 C7 C8 41 42 64 Manufacturer's JEDEC ID Code (1) 7F 7F 7F 7F 65 Manufacturer's JEDEC ID Code (2) 7F 7F 7F 7F 66 Manufacturer's JEDEC ID Code (3) 7F 7F 7F 7F 67 Manufacturer's JEDEC ID Code (4) 7F 7F 7F 7F 68 Manufacturer's JEDEC ID Code (5) 7F 7F 7F 7F 69 Manufacturer's JEDEC ID Code (6) 51 51 51 51 70 Manufacturer's JEDEC ID Code (7) 00 00 00 00 71 Manufacturer's JEDEC ID Code (8) 00 00 00 00 72 Module Manufacturer Location xx xx xx xx 73 Part Number, Char 1 37 37 37 37 74 Part Number, Char 2 32 32 32 32 75 Part Number, Char 3 44 44 44 44 76 Part Number, Char 4 36 31 31 32 77 Part Number, Char 5 34 32 32 35 78 Part Number, Char 6 33 38 38 36 79 Part Number, Char 7 30 33 33 33 80 Part Number, Char 8 31 32 30 32 81 Part Number, Char 9 48 31 30 30 82 Part Number, Char 10 42 48 48 48 83 Part Number, Char 11 52 42 42 42 84 Part Number, Char 12 35 52 52 52 85 Part Number, Char 13 43 35 35 35 86 Part Number, Char 14 20 43 43 43 Rev. 1.21, 2006-08 03292006-6N25-8R3I 20 Internet Data Sheet Product Type HYS72D64301HBR-5-C HYS72D128321HBR-5-C HYS72D128300HBR-5-C HYS72D256320HBR-5-C HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module Organization 512 MB 1 GByte 1 GByte 2 GByte x72 x72 x72 x72 1 Rank (x8) 2 Ranks (x8) 1 Rank (x4) 2 Ranks (x4) PC3200R- 30331 PC3200R-30331 PC3200R- 30331 PC3200R- 30331 JEDEC SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Rev 1.0 Byte# Description HEX HEX HEX HEX 87 Part Number, Char 15 20 20 20 20 88 Part Number, Char 16 20 20 20 20 89 Part Number, Char 17 20 20 20 20 90 Part Number, Char 18 20 20 20 20 91 Module Revision Code 1x 1x 1x 1x Label Code 92 Test Program Revision Code xx xx xx xx 93 Module Manufacturing Date Year xx xx xx xx 94 Module Manufacturing Date Week xx xx xx xx 95 - 98 Module Serial Number (1 - 4) xx xx xx xx 00 00 00 00 99 - 127 not used Rev. 1.21, 2006-08 03292006-6N25-8R3I 21 Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module TABLE 14 Product Type HYS72D64301HBR-6-C HYS72D128321HBR-6-C HYS72D128300HBR-6-C HYS72D256320HBR-6-C SPD Codes for HYS72D[64/128/256]3[00/01/20/21]HBR-6-C Organization 512 MB 1 GByte 1 GByte 2 GByte x72 x72 x72 x72 1 Rank (x8) 2 Ranks (x8) 1 Rank (x4) 2 Ranks (x4) PC2700R- 25331 PC2700R- 25331 PC2700R- 25331 PC2700R- 25331 JEDEC SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Rev 1.0 Byte# Description HEX HEX HEX HEX 0 Programmed SPD Bytes in E2PROM 80 80 80 80 1 Total number of Bytes in E2PROM 08 08 08 08 2 Memory Type (DDR = 07h) 07 07 07 07 Label Code 3 Number of Row Addresses 0D 0D 0D 0D 4 Number of Column Addresses 0B 0B 0C 0C 5 Number of DIMM Ranks 01 02 01 02 6 Data Width (LSB) 48 48 48 48 7 Data Width (MSB) 00 00 00 00 8 Interface Voltage Levels 04 04 04 04 9 tCK @ CLmax (Byte 18) [ns] 60 60 60 60 10 tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 70 70 11 Error Correction Support 02 02 02 02 12 Refresh Rate 82 82 82 82 13 Primary SDRAM Width 08 08 04 04 14 Error Checking SDRAM Width 08 08 04 04 15 tCCD [cycles] 01 01 01 01 16 Burst Length Supported 0E 0E 0E 0E 17 Number of Banks on SDRAM Device 04 04 04 04 18 CAS Latency 0C 0C 0C 0C 19 CS Latency 01 01 01 01 20 Write Latency 02 02 02 02 21 DIMM Attributes 26 26 26 26 22 Component Attributes C1 C1 C1 C1 Rev. 1.21, 2006-08 03292006-6N25-8R3I 22 Internet Data Sheet Product Type HYS72D64301HBR-6-C HYS72D128321HBR-6-C HYS72D128300HBR-6-C HYS72D256320HBR-6-C HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module Organization 512 MB 1 GByte 1 GByte 2 GByte x72 x72 x72 x72 1 Rank (x8) 2 Ranks (x8) 1 Rank (x4) 2 Ranks (x4) PC2700R- 25331 PC2700R- 25331 PC2700R- 25331 PC2700R- 25331 JEDEC SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Rev 1.0 Byte# Description HEX HEX HEX HEX 23 tCK @ CLmax -0.5 (Byte 18) [ns] 75 75 75 75 24 tAC SDRAM @ CLmax -0.5 [ns] 70 70 70 70 25 tCK @ CLmax -1 (Byte 18) [ns] 00 00 00 00 26 tAC SDRAM @ CLmax -1 [ns] 00 00 00 00 27 tRPmin [ns] 48 48 48 48 28 tRRDmin [ns] 30 30 30 30 29 tRCDmin [ns] 48 48 48 48 30 tRASmin [ns] 2A 2A 2A 2A Label Code 31 Module Density per Rank 80 80 01 01 32 tAS, tCS [ns] 75 75 75 75 33 tAH, tCH [ns] 75 75 75 75 34 tDS [ns] 45 45 45 45 35 tDH [ns] 45 45 45 45 36 - 40 not used 00 00 00 00 41 tRCmin [ns] 3C 3C 3C 3C 42 tRFCmin [ns] 48 48 48 48 43 tCKmax [ns] 30 30 30 30 44 tDQSQmax [ns] 28 28 28 28 45 tQHSmax [ns] 50 50 50 50 46 not used 00 00 00 00 47 DIMM PCB Height 01 01 01 01 48 - 61 not used 00 00 00 00 62 SPD Revision 10 10 10 10 63 Checksum of Byte 0-62 61 62 DB DC 64 Manufacturer's JEDEC ID Code (1) 7F 7F 7F 7F 65 Manufacturer's JEDEC ID Code (2) 7F 7F 7F 7F Rev. 1.21, 2006-08 03292006-6N25-8R3I 23 Internet Data Sheet Product Type HYS72D64301HBR-6-C HYS72D128321HBR-6-C HYS72D128300HBR-6-C HYS72D256320HBR-6-C HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module Organization 512 MB 1 GByte 1 GByte 2 GByte x72 x72 x72 x72 1 Rank (x8) 2 Ranks (x8) 1 Rank (x4) 2 Ranks (x4) PC2700R- 25331 PC2700R- 25331 PC2700R- 25331 PC2700R- 25331 JEDEC SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Rev 1.0 Byte# Description HEX HEX HEX HEX 66 Manufacturer's JEDEC ID Code (3) 7F 7F 7F 7F 67 Manufacturer's JEDEC ID Code (4) 7F 7F 7F 7F 68 Manufacturer's JEDEC ID Code (5) 7F 7F 7F 7F 69 Manufacturer's JEDEC ID Code (6) 51 51 51 51 70 Manufacturer's JEDEC ID Code (7) 00 00 00 00 71 Manufacturer's JEDEC ID Code (8) 00 00 00 00 72 Module Manufacturer Location xx xx xx xx 73 Part Number, Char 1 37 37 37 37 74 Part Number, Char 2 32 32 32 32 75 Part Number, Char 3 44 44 44 44 76 Part Number, Char 4 36 31 31 32 77 Part Number, Char 5 34 32 32 35 78 Part Number, Char 6 33 38 38 36 79 Part Number, Char 7 30 33 33 33 80 Part Number, Char 8 31 32 30 32 81 Part Number, Char 9 48 31 30 30 82 Part Number, Char 10 42 48 48 48 83 Part Number, Char 11 52 42 42 42 84 Part Number, Char 12 36 52 52 52 85 Part Number, Char 13 43 36 36 36 86 Part Number, Char 14 20 43 43 43 87 Part Number, Char 15 20 20 20 20 88 Part Number, Char 16 20 20 20 20 89 Part Number, Char 17 20 20 20 20 90 Part Number, Char 18 20 20 20 20 91 Module Revision Code 1x 1x 1x 1x Label Code Rev. 1.21, 2006-08 03292006-6N25-8R3I 24 Internet Data Sheet Product Type HYS72D64301HBR-6-C HYS72D128321HBR-6-C HYS72D128300HBR-6-C HYS72D256320HBR-6-C HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module Organization 512 MB 1 GByte 1 GByte 2 GByte x72 x72 x72 x72 1 Rank (x8) 2 Ranks (x8) 1 Rank (x4) 2 Ranks (x4) PC2700R- 25331 PC2700R- 25331 PC2700R- 25331 PC2700R- 25331 JEDEC SPD Revision Rev 1.0 Rev 1.0 Rev 1.0 Rev 1.0 Description HEX HEX HEX HEX Label Code Byte# 92 Test Program Revision Code xx xx xx xx 93 Module Manufacturing Date Year xx xx xx xx 94 Module Manufacturing Date Week xx xx xx xx 95 - 98 Module Serial Number (1 - 4) xx xx xx xx 00 00 00 00 99 - 127 not used Rev. 1.21, 2006-08 03292006-6N25-8R3I 25 Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module TABLE 15 Product Type HYS72D128900HBR-6-C HYS72D256920HBR-6-C SPD Codes for HYS72D[128/256]90x0HBR-6-C Organization 1 GByte 2 GByte x72 x72 1 Rank (x4) 2 Ranks (x4) PC2700R-25331 PC2700R-25331 JEDEC SPD Revision Rev 1.0 Rev 1.0 Byte# Description HEX HEX 0 Programmed SPD Bytes in E2PROM 80 80 Label Code 1 Total number of Bytes in E2PROM 08 08 2 Memory Type (DDR = 07h) 07 07 3 Number of Row Addresses 0D 0D 4 Number of Column Addresses 0C 0C 5 Number of DIMM Ranks 01 02 6 Data Width (LSB) 48 48 7 Data Width (MSB) 00 00 8 Interface Voltage Levels 04 04 9 tCK @ CLmax (Byte 18) [ns] 60 60 10 tAC SDRAM @ CLmax (Byte 18) [ns] 70 70 11 Error Correction Support 02 02 12 Refresh Rate 82 82 13 Primary SDRAM Width 04 04 14 Error Checking SDRAM Width 04 04 15 tCCD [cycles] 01 01 16 Burst Length Supported 0E 0E 17 Number of Banks on SDRAM Device 04 04 18 CAS Latency 0C 0C 19 CS Latency 01 01 20 Write Latency 02 02 21 DIMM Attributes 26 26 22 Component Attributes C1 C1 23 tCK @ CLmax -0.5 (Byte 18) [ns] 75 75 Rev. 1.21, 2006-08 03292006-6N25-8R3I 26 Internet Data Sheet Product Type HYS72D128900HBR-6-C HYS72D256920HBR-6-C HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module Organization 1 GByte 2 GByte x72 x72 1 Rank (x4) 2 Ranks (x4) PC2700R-25331 PC2700R-25331 JEDEC SPD Revision Rev 1.0 Rev 1.0 Description HEX HEX Label Code Byte# 24 tAC SDRAM @ CLmax -0.5 [ns] 70 70 25 tCK @ CLmax -1 (Byte 18) [ns] 00 00 26 tAC SDRAM @ CLmax -1 [ns] 00 00 27 tRPmin [ns] 48 48 28 tRRDmin [ns] 30 30 29 tRCDmin [ns] 48 48 30 tRASmin [ns] 2A 2A 31 Module Density per Rank 01 01 32 tAS, tCS [ns] 75 75 33 tAH, tCH [ns] 75 75 34 tDS [ns] 45 45 35 tDH [ns] 45 45 36 - 40 not used 00 00 41 tRCmin [ns] 3C 3C 42 tRFCmin [ns] 48 48 43 tCKmax [ns] 30 30 44 tDQSQmax [ns] 28 28 45 tQHSmax [ns] 50 50 46 not used 00 00 47 DIMM PCB Height 01 01 48 - 61 not used 00 00 62 SPD Revision 10 10 63 Checksum of Byte 0-62 DB DC 64 Manufacturer's JEDEC ID Code (1) 7F 7F 65 Manufacturer's JEDEC ID Code (2) 7F 7F 66 Manufacturer's JEDEC ID Code (3) 7F 7F Rev. 1.21, 2006-08 03292006-6N25-8R3I 27 Internet Data Sheet Product Type HYS72D128900HBR-6-C HYS72D256920HBR-6-C HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module Organization 1 GByte 2 GByte x72 x72 1 Rank (x4) 2 Ranks (x4) PC2700R-25331 PC2700R-25331 JEDEC SPD Revision Rev 1.0 Rev 1.0 Byte# Description HEX HEX 67 Manufacturer's JEDEC ID Code (4) 7F 7F 68 Manufacturer's JEDEC ID Code (5) 7F 7F 69 Manufacturer's JEDEC ID Code (6) 51 51 70 Manufacturer's JEDEC ID Code (7) 00 00 71 Manufacturer's JEDEC ID Code (8) 00 00 Label Code 72 Module Manufacturer Location xx xx 73 Part Number, Char 1 37 37 74 Part Number, Char 2 32 32 75 Part Number, Char 3 44 44 76 Part Number, Char 4 31 32 77 Part Number, Char 5 32 35 78 Part Number, Char 6 38 36 79 Part Number, Char 7 39 39 80 Part Number, Char 8 30 32 81 Part Number, Char 9 30 30 82 Part Number, Char 10 48 48 83 Part Number, Char 11 42 42 84 Part Number, Char 12 52 52 85 Part Number, Char 13 36 36 86 Part Number, Char 14 43 43 87 Part Number, Char 15 20 20 88 Part Number, Char 16 20 20 89 Part Number, Char 17 20 20 90 Part Number, Char 18 20 20 91 Module Revision Code 1x 1x 92 Test Program Revision Code xx xx Rev. 1.21, 2006-08 03292006-6N25-8R3I 28 Internet Data Sheet Product Type HYS72D128900HBR-6-C HYS72D256920HBR-6-C HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module Organization 1 GByte 2 GByte x72 x72 1 Rank (x4) 2 Ranks (x4) PC2700R-25331 PC2700R-25331 JEDEC SPD Revision Rev 1.0 Rev 1.0 Description HEX HEX 93 Module Manufacturing Date Year xx xx 94 Module Manufacturing Date Week xx xx 95 - 98 Module Serial Number (1 - 4) xx xx 99 - 127 not used 00 00 Label Code Byte# Rev. 1.21, 2006-08 03292006-6N25-8R3I 29 Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module 5 Package Outlines FIGURE 2 $ %& Package Outline Raw Card A - L-DIM-184-21-3 $%& 0 $; $ $ %& % & $ %& 0 ,1 'HWDLORIFRQWDF WV $ %& %XUU PD [ DOORZ HG Notes 1. General tolerances +/- 0.15 2. Drawing according to ISO 8015 Rev. 1.21, 2006-08 03292006-6N25-8R3I 30 [ Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module FIGURE 3 $ % & Package Outline Raw Card C - L-DIM-184-22-2 $ % & 0$ ; $ $ %& % & $ % & 0 ,1 'HWDLOR IFRQWDF WV $ %& %XUUPD [DOORZH G Notes 1. General tolerances +/- 0.15 2. Drawing according to ISO 8015 Rev. 1.21, 2006-08 03292006-6N25-8R3I 31 [ Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module FIGURE 4 $ %& Package Outline Raw Card B - L-DIM-184-23-2 $ % & 0 $ ; $ $ % & % & $ %& 0 ,1 'HWDLOR IFRQWDF WV $ %& %XU UPD [ DOORZ HG Notes 1. General tolerances +/- 0.15 2. Drawing according to ISO 8015 Rev. 1.21, 2006-08 03292006-6N25-8R3I 32 [ Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module FIGURE 5 Package Outline Raw Card F - L-DIM-184-25 $ % & $ %& 0 $; $ $ % & % & $ % & 0 ,1 'HWDLORIFRQWDFWV $ %& /' ,0 %XUU PD [ DOORZ HG Notes 1. General tolerances +/- 0.15 2. Drawing according to ISO 8015 Rev. 1.21, 2006-08 03292006-6N25-8R3I 33 Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module 6 Application Note Power Up and Power Management on DDR Registered DIMMs (according to JEDEC ballot JC-42.5 Item 1173) 184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and to minimize power consumption during low power mode. One feature is externally controlled via a system-generated RESET signal; the second is based on module detection of the input clocks. These enhancements permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipations and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-Locked Loop) when the memory is in Self-Refresh mode. The new RESET pin controls power dissipation on the module's registers and ensures that CKE and other SDRAM inputs are maintained at a valid `low' level during power-up and self refresh. When RESET is at a low level, all the register outputs are forced to a low level, and all differential register input receivers are powered down, resulting in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven from the system as an asynchronous signal according to the attached details. Using this function also permits the system and DIMM clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs stay in Self Refresh mode. TABLE 16 Function for RESET Register Outputs1) Register Inputs RESET CK CK Data in (D) Data out (Q) H Rising Falling H H H Rising Falling L L H L or H L or H X Qo H High Z High Z X Illegal input conditions L X or Hi-Z X or Hi-Z X or Hi-Z L 1) X : Don't care, Hi-Z : High Impedance, Qo: Data latched at the previous of CK risning and CK falling As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are maintained low at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low maintains a high impedance state on the SDRAM DQ, DQS and DM outputs -- where they will remain until activated by a valid `read' cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable. The DDR PLL devices automatically detect clock activity above 20MHz. When an input clock frequency of 20MHz or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operating frequency at which all specifications will be met is 95MHz). If the clock input frequency drops below 20MHz (actual detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are made High-Z, and the differential inputs are powered down -- resulting in a total PLL current consumption of less than 1mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it is tied inactive on the DIMM. This application note describes the required and optional system sequences associated with the DDR Registered DIMM 'RESET' function. It is important to note that all references to CKE refer to both CKE0 and CKE1 for a 2-bank DIMM. Because RESET applies to all DIMM register devices, it is therefore not possible to uniquely control CKE to one physical DIMM bank through the use of the RESET pin. Rev. 1.21, 2006-08 03292006-6N25-8R3I 34 Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module Power-Up Sequence with RESET -- Required 1. The system sets RESET at a valid low level. This is the preferred default state during power-up. This input condition forces all register outputs to a low state independent of the condition on the register inputs (data and clock), ensuring that CKE is at a stable low-level at the DDR SDRAMs. 2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR SDRAMs. 3. Stabilization of Clocks to the SDRAM The system must drive clocks to the application frequency (PLL operation is not assured until the input clock reaches 20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. When a stable clock is present at the SDRAM input (driven from the PLL), the DDR SDRAM requires 200 sec prior to SDRAM operation. 4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 5. The system switches RESET to a logic `high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, setting the RESET timing in relation to a specific clock edge is not required (during this period, register inputs must remain stable). 6. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows their clock receivers, data input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in step 5. It is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input signal, is specified in the register and DIMM do-umentation. 7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDEC-pproved initialization sequence). Self Refresh Entry (RESET low, clocks powered off) -- Optional Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking. Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption (RESET low deactivates register CK and CK, data input receivers, and data output drivers). * The system applies Self Refresh entry command. (CKEAELow, CSAELow, RAS AE Low, CASAE Low, WEAE High) Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input conditions to the SDRAM are Don't Cares-- with the exception of CKE. * The system sets RESET at a valid low level. This input condition forces all register outputs to a low state, independent of the condition on the registerm inputs (data and clock), and ensures that CKE, and all other control and address signals, are a stable low-level at the DDR SDRAMs. Since the RESET signal is asynchronous, setting the RESET timing in relation to a specific clock edge is not required. * The system turns off clock inputs to the DIMM. (Optional) a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Z clock inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time defines the time in which the clocks and the control and address signals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM documentation. b. The system may release DIMM address and control inputs to High-Z. This can be done after the RESET deactivate time of the register. The deactivate time defines the time in which the clocks and the control and the address signals must maintain valid levels after RESET low has been applied. It is highly recommended that CKE continue to remain low during this operation. Rev. 1.21, 2006-08 03292006-6N25-8R3I 35 Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module * The DIMM is in lowest power Self Refresh mode. Self Refresh Exit (RESET low, clocks powered off) -- Optional 1. Stabilization of Clocks to the SDRAM. The system must drive clocks to the application frequency (PLL operation is not assured until the input clock reaches ~20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. 2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the JEDEC Self Refresh Exit sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs, to be consistent with the state of the register outputs. 3. The system switches RESET to a logic `high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, RESET timing relationship to a specific clock edge is not required (during this period, register inputs must remain stable). 4. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in Step 2. It is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input signal, is specified in the register and DIMM do-umentation. 5. System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure. Self Refresh Entry (RESET low, clocks running) -- Optional Although keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh, this is an alternate operating mode for these DIMMs. 1. System enters Self Refresh entry command. (CKEAE Low, CSAE Low, RASAE Low, CASAE Low, WEAE High) Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input conditions to the SDRAM are Don't Cares -- with the exception of CKE. * The system sets RESET at a valid low level. This input condition forces all register outputs to a low state, independent of the condition on the data and clock register inputs, and ensures that CKE is a stable low-level at the DDR SDRAMs. * The system may release DIMM address and control inputs to High-Z. This can be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time describes the time in which the clocks and the control and the address signals must maintain valid levels after RESET low has been applied. It is highly recommended that CKE continue to remain low during the operation. * The DIMM is in a low power, Self Refresh mode. Self Refresh Exit (RESET low, clocks running) -- Optional 1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the Self Refresh Exit sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. Rev. 1.21, 2006-08 03292006-6N25-8R3I 36 Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module 2. The system switches RESET to a logic 'high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, it does not need to be tied to a particular clock edge (during this period, register inputs must continue to remain stable). 3. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in Step 1. It is also a functional requirement that the registers maintain a low state at the CKE outputs in order to guarantee that the DDR SDRAMs continue to receive a low level on CKE. This activation time, from asynchronous switching of RESET from low to high, until the registers are stable and ready to accept an input signal, is t (ACT ) as specified in the register and DIMM documentation. 4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure. Self Refresh Entry/Exit (RESET high, clocks running) -- Optional As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification explains in detail the method for entering and exiting Self Refresh for this case. Self Refresh Entry (RESET high, clocks powered off) -- Not Permissible In order to maintain a valid low level on the register output, it is required that either the clocks be running and the system drive a low level on CKE, or the clocks are powered off and RESET is asserted low according to the sequence defined in this application note. In the case where RESET remains high and the clocks are powered off, the PLL drives a High-Z clock input into the register clock input. Without the low level on RESET an unknown DIMM state will result. Rev. 1.21, 2006-08 03292006-6N25-8R3I 37 Internet Data Sheet HYS72D[64/128/256]xxxHBR-[5/6]-C Registered Double-Data-Rate SDRAM Module Table of Contents 1 1.1 1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 3.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 A.C. Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Rev. 1.21, 2006-08 03292006-6N25-8R3I 38 Internet Data Sheet Edition 2006-08 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2006. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. 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