FAN3852UC16X - ON SEMICONDUCTOR

June, 2019 − Rev. 3

1Publication Order Number:

FAN3852/D

FAN3852

Microphone Pre-Amplifier

with Digital Output

Description

The FAN3852 integrates a pre−amplifier, LDO, and ADC that

converts Electret Condenser Microphone (ECM) outputs to digital

Pulse Density Modulation (PDM) data streams. The pre−amplifier

accepts analog signals from the ECM and drives an over−sampled

sigma delta Analog−to−Digital Converter (ADC) and outputs PDM

data. The PDM digital audio has the advantage of noise rejection and

easy interface to mobile handset processors.

The FAN3852 features an integrated LDO and is powered from the

system supply rails up to 3.63 V, with low power consumption of only

0.85 mW and less than 20 mW in Power−Down Mode.

Features

•Optimized for Mobile Handset and Notebook PC Microphone

Applications

•Accepts Input from Electret Condenser Microphones (ECM)

•Pulse Density Modulation (PDM) Output

•Standard 5−Wire Digital Interface

•Low Input Capacitance, High PSR, 20 kHz Pre−Amplifier

•Low−Power 1.5 mA Sleep Mode

•Typical 420 mA Supply Current

•SNR of 62 dB (A) for 16 dB Gain

•Total Harmonic Distortion 0.02%

•Input Clock Frequency Range of 1−4 MHz

•Integrated Low Drop−Out Regulator (LDO)

•Small 1.242 mm × 0.842 mm 6−Ball, 0.400 mm pitch standard

WLCSP Package

•1.5 kV HBM ESD on MIC Input

Typical Applications

•Electret Condenser Microphones with Digital Output

•Mobile Handset

•Headset Accessories

•Personal Computer (PC)

WLCSP−6

CASE 567TS

See detailed ordering and shipping information on page 2

of this data sheet.

ORDERING INFORMATION

www.onsemi.com

MARKING DIAGRAM

VK = Device Identifier

K = Lot Run Code

. = Pin A1 Mark

2 = Date Code

Z = Plant Code

PIN CONFIGURATION

VK&K

&.&2&Z

Pin A1

CLOCK

GND

DATA

SELECT

INPUT

VDD

Top View

A1 A2

B1 B2

C1 C2

FAN3852

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ORDERING INFORMATION

Part Number Operating Temperature Range Package Packing Method†

FAN3852UC16X −40°C to 85°C6 Ball, Wafer−Level

Chip−Scale Package (WLCSP)

3000 Units/Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

INTERNAL BLOCK DIAGRAM

Figure 1. Block Diagram

LDO

Pre*Amp

LDO

INPUT

CLOCK

DATA

SELECT

GND

VDD

Sleep

Mode Ctrl

S−D

ADC

Table 1. PIN DEFINITIONS

Pin # Name Type Description

A1 CLOCK Input Clock Input

B1 GND Input Ground Pin

C1 DATA Output PDM Output − 1 Bit ADC

A2 SELECT Input Rising or Falling Clock Edge Select

B2 INPUT Input Microphone Input

C2 VDD Input Device Power Pin

Table 2. ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Min. Max. Unit

VDD DC Supply Voltage −0.3 4.0 V

VIO Digital I/O −0.3 VDD + 0.3 V

Microphone Input −0.3 2.2

ESD Human Body Model, JESD22−A114, All Pins Except Microphone

Input

±8kV

Human Body Model, JESD2−A114 − Microphone Input ±1.5

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. This device is fabricated using CMOS technology and is therefore susceptible to damage from electrostatic discharges. Appropriate

precautions must be taken during handling and storage of this device to prevent exposure to ESD.

FAN3852

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Table 3. RELIABILITY INFORMATION

Symbol Rating Min. Typ. Max. Unit

TJJunction Temperature +150 °C

TSTG Storage Temperature Range −65 +125 °C

TRFLW Peak Reflow Temperature +260 °C

qJA Thermal Resistance, JEDEC Standard, Multilayer

Test Boards, Still Air

90 °C/W

2. TA = 25°C unless otherwise specified

Table 4. RECOMMENDED OPERATING CONDITIONS

Symbol Rating Min. Typ. Max. Unit

TAOperating Temperature Range −400 +85 °C

VDD Supply Voltage Range 1.64 1.80 3.63 V

TRF−CLK Clock Rise and Fall Time 10 ns

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

Table 5. DEVICE SPECIFIC ELECTRICAL CHARACTERISTICS

Symbol Value

FAN3852UC16X

Unit

Min. Typ. Max.

SNR Signal−to−Noise Ratio

fIN = 1 kHz (1 Pa), A−Weighted

62 dB (A)

eNTotal Input RMS Noise

20 Hz to 20 kHz, A−Weighted

5.74 6.80 mVRMS

VIN Maximum Input Signal

fIN = 1 kHz, THD + N < 10%, Level = 0 V

448 mVPP

3. Guaranteed by characterization and/or design. Not production tested.

Table 6. ELECTRICAL CHARACTERISTICS

Unless otherwise specified, al limits are guaranteed for TA = 25°C, VDD = 1.8 V, VIN = 94 dB (SPL) and fCLK = 2.4 MHz.

Duty Cycle = 50% and CMIC = 15 pF

Symbol Parameter Condition Min. Typ. Max. Unit

VDD Supply Voltage Range 1.64 1.80 3.63 V

IDD Supply Current INPUT = AC Coupled to GND,

CLOCK = On, No Load

420 mA

ISLEEP Sleep Mode Current fCLK = GND 1.50 8.0 mA

PSR Power Supply Rejection (Note 5) INPUT = AC Coupled to GND,

Test Signal on VDD = 217 Hz,

Square Wave and Broadband

Noise (Note 4), Both 100 mVP−P

−74 dBFS

INNOM Nominal Sensitivity (Note 6) INPUT = 94 dBSPL (1 Pa) −26 dBFS

THD Total Harmonic Distortion (Note 7) fIN = 1 KHz, INPUT = −26 dBFS 0.02 0.20 %

THD+N THD and Noise (Note 5) 50 Hz ≤ fIN ≤ 1 kHz,

INPUT = −20 dBFS

0.2 1.0 %

fIN = 1 KHz, INPUT = −5 dBFS 1.0 5.0

fIN = 1 KHz, INPUT = 0 dBFS 5.0 10.0

CIN Input Capacitance (Note 8) INPUT 1.3 pF

RIN Input Resistance (Note 8) INPUT >10 GW

VIL CLOCK & SELECT Input Logic

LOW Level

0.3 V

FAN3852

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Table 6. ELECTRICAL CHARACTERISTICS (continued)

Unless otherwise specified, al limits are guaranteed for TA = 25°C, VDD = 1.8 V, VIN = 94 dB (SPL) and fCLK = 2.4 MHz.

Duty Cycle = 50% and CMIC = 15 pF

Symbol UnitMax.Typ.Min.ConditionParameter

VIH CLOCK & SELECT Input Logic

HIGH Level

1.5 VDD+0.3 V

VOL Data Output Logic LOW Level 0.35*VDD V

VOH Data Output Logic HIGH Level 0.65*VDD V

VOUT Acoustic Overload Point (Note 8) THD+N < 10% 120 dBSPL

tATime from CLOCK Transition to

Data becoming Valid

On Falling Edge of CLOCK,

SELECT = GND, CLOAD = 15 pF

18 43 ns

tBTime from CLOCK Transition to

Data becoming HIGH−Z

On Rising Edge of CLOCK,

SELECT = GND, CLOAD = 15 pF

0 5 16 ns

tATime from CLOCK Transition to

Data becoming Valid

On Rising Edge of CLOCK,

SELECT = VDD, CLOAD = 15 pF

18 58 ns

tBTime from CLOCK Transition to

Data becoming HIGH−Z

On Falling Edge of CLOCK,

SELECT = VDD, CLOAD = 15 pF

0 5 16 ns

fCLK Input CLOCK Frequency (Note 9) Active Mode 1.0 2.4 4.0 MHz

CLKdc CLOCK Duty Cycle (Note 5) 40 50 60 %

tWAKEUP Wake−Up Time (Note 10) fCLK = 2.4 MHz 0.35 2.00 ms

tFALLASLEAP Fall−Asleep Time (Note 11) fCLK = 2.4 MHz 0 0.01 1.00 ms

CLOAD Load Capacitance on Data 100 pF

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. Pseudo−random noise with triangular probability density function. Bandwidth up to 10 MHz.

5. Guaranteed by characterization. Not production tested.

6. Assuming that 120 dB (SPL) is mapped to 0 dBFS.

7. Assuming an input of −45 dBV.

8. Guaranteed by design. Not production tested.

9. All parameters are tested at 2.4 MHz. Frequency range guaranteed by characterization.

10.Device wakes up when fCLK ≥ 300 kHz.

11. Device falls asleep when fCLK ≤ 70 kHz.

Figure 2. Interface Timing

tA − Microphone delay from clock edge to data assertion.

tB − Microphone delay from clock edge to high−impedance state.

tA > tB to have interim HIGH−Z state in both signals.

CLK

DATA1

DATA2

(For possible 2nd Mic)

Data

Valid HIGH−Z

Data

Valid HIGH−Z

FAN3852

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TYPICAL PERFORMANCE CHARACTERISTICS

Unless otherwise specified, all limits are guaranteed for TA = 25°C, VDD = 1.8 V, VIN = 94 dB (SPL), fCLK = 2.4 MHz and duty Cycle = 50%.

Figure 3. Noise vs. Frequency

10110210

310410

5106

−160

−140

−120

−100

−80

−60

−40

−20

Frequency [Hz]

Amplitude [dBFS]

Amplitude Spectrum [dBFS], Fo = 1000.2135 Hz, Fs = 2.400000 MHz, SNR = 56.89 dB, SNR = 60.88 dB(A), THD = 0.008 %

← Fo(0)= −26.15 dBFS

← Fo(1)= −110.28 dBFS

← Fo(2)= −116.40 dBFS

← Fo(3)= −120.45 dBFS

← Fo(4)= −125.03 dBFS

THD = 81.95 dB

SNR = 60.88 dBc(A)

SINAD = 56.87 dB

ENOB = 13.50

N = 2097152 pts

Blackman Window

↓ Integrated Noise = −87.03 dBFS(A)

Spur = −101.34 dBFS, SFDR = 75.19 dBc

Noise

Noise(A)

Signal

↓

Figure 4. THD, SINDA, and SNR vs. Input Amplitude

FAN3852

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TYPICAL PERFORMANCE CHARACTERISTICS (continued)

Unless otherwise specified, all limits are guaranteed for TA = 25°C, VDD = 1.8 V, VIN = 94 dB (SPL), fCLK = 2.4 MHz and duty Cycle = 50%.

Figure 5. THD, SINAD and SNR vs. Output Level

Figure 6.  Gain vs. Temperature (Nominal Temperature = 255C)

-4

-3

-2

-1

Tj ˚CJunction Temperature-

ΔGain (dB)

-40 40 800-30 -20 -10 10 20 30 50 60 70

−40

−30

−20

−10

Temp (°C) Delta (dB)

0.1971

0.1644

0.1260

0.0954

0.0657

0.0359

0.0139

−0.0097

−0.0344

−0.0514

−0.0739

−0.0998

−0.1183

−0.1271

0.0000

FAN3852

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APPLICATIONS INFORMATION

Figure 7. Mono Microphone Application Circuit

Decimation

Noise Shaper

Low Pass Filter

INPUT

Serial PortCLK

Pre *

Amp

Applications Software

ADC

Interpolation

CLOCK

SDI

DATA

SPEAKER

VDD

SELECT

Audio

Output

L/R

SDO

Figure 8. Stereo Microphone Application Circuit

INPUT

Pre

Amp ADC

DATA

VDD

SELECT

CLOCK

SPEAKER

Audio

Output

Serial Port

CLK SDI L/R

SDO

Decimation

Noise Shaper

Low Pass Filter

Interpolation

Applications Software

INPUT

ADC

DATA

SELECT

CLOCK

Pre

Amp

VDD

FAN3852

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APPLICATIONS INFORMATION (continued)

Figure 9. MIC Element Drawing

Diaphragm

Backplate

Airgap

Electret

FAN3852

INPUT

CLOCK

DATA

VDD

SELECT

GND

A 0.1 mF decoupling capacitor is required for VDD. It can

be located inside the microphone or on the PCB very close

to the VDD pin.

Due to high input impedance, care should be taken to

remove all flux used during the reflow soldering process.

A 100 W resistance is recommended on the clock output

of the device driving the FAN3852 to minimize ringing and

improve signal integrity.

For optimal PSR, route a trace to the VDD pin. Do not

place a VDD plane under the device.

Figure 10. Example Hardware Implementation

PDM Clock

1.64 V − 3.63 V

C2 C3

VDD

INPUT

SELECT

CLOCK

FAN3852

C1 PDM Data

ECM

RBIAS

2.2 k

1−4 MHz

DATA

PDM

Codec

GND

Table 7. RECOMMENDED COMPONENTS

Ref Des Qty Description of Options Package Manufacturer Mfg PIN

U1 1 FAN3852 Microphone Pre−Amplifier

with Digital Output

WLCSP6 ON

Semiconductor

FAN3852UC16X

C1 1 Input AC Coupling Capacitor;

1 nF/1000 pF, ≥ 6.3 V, low−leakage

0402 Johansen

Dielectrics

500R07W102KV4T

0402 Murata GCM155R71H102KA37D

0603 Taiyo Yuden UMK107SD102KA−T

C2 1 Primary VDD Decoupling Capacitor;

0.1 mF, MLCC, ≥ 6.3 V

0402 Samsung CL05B104KO5NNNC

0402 Yageo CC0402KRX7R7BB104

0603 AVX 06033C104KAT4A

C3 1 Optional VDD Decoupling Capacitor;

0.01 mF, MLCC, ≥ 6.3 V

0402 Samsung CL05B103KB5VPNC

0402 Murata GCM155R71H103KA55J

0603 Yageo CC0603KRX7R7BB103

FAN3852

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PACKAGE DIMENSIONS

WLCSP6 1.242x0.842x0.457

CASE 567TS

ISSUE A

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FAN3852/D

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